1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2011-2018 Magewell Electronics Co., Ltd. (Nanjing)
4 * All rights reserved.
5 * Author: Yong Deng <yong.deng@magewell.com>
6 */
7
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/err.h>
12 #include <linux/fs.h>
13 #include <linux/interrupt.h>
14 #include <linux/io.h>
15 #include <linux/ioctl.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/regmap.h>
22 #include <linux/reset.h>
23 #include <linux/sched.h>
24 #include <linux/sizes.h>
25 #include <linux/slab.h>
26 #include <media/v4l2-mc.h>
27
28 #include "sun6i_csi.h"
29 #include "sun6i_csi_reg.h"
30
31 /* Helpers */
32
33 /* TODO add 10&12 bit YUV, RGB support */
sun6i_csi_is_format_supported(struct sun6i_csi_device * csi_dev,u32 pixformat,u32 mbus_code)34 bool sun6i_csi_is_format_supported(struct sun6i_csi_device *csi_dev,
35 u32 pixformat, u32 mbus_code)
36 {
37 struct sun6i_csi_v4l2 *v4l2 = &csi_dev->v4l2;
38
39 /*
40 * Some video receivers have the ability to be compatible with
41 * 8bit and 16bit bus width.
42 * Identify the media bus format from device tree.
43 */
44 if ((v4l2->v4l2_ep.bus_type == V4L2_MBUS_PARALLEL
45 || v4l2->v4l2_ep.bus_type == V4L2_MBUS_BT656)
46 && v4l2->v4l2_ep.bus.parallel.bus_width == 16) {
47 switch (pixformat) {
48 case V4L2_PIX_FMT_NV12_16L16:
49 case V4L2_PIX_FMT_NV12:
50 case V4L2_PIX_FMT_NV21:
51 case V4L2_PIX_FMT_NV16:
52 case V4L2_PIX_FMT_NV61:
53 case V4L2_PIX_FMT_YUV420:
54 case V4L2_PIX_FMT_YVU420:
55 case V4L2_PIX_FMT_YUV422P:
56 switch (mbus_code) {
57 case MEDIA_BUS_FMT_UYVY8_1X16:
58 case MEDIA_BUS_FMT_VYUY8_1X16:
59 case MEDIA_BUS_FMT_YUYV8_1X16:
60 case MEDIA_BUS_FMT_YVYU8_1X16:
61 return true;
62 default:
63 dev_dbg(csi_dev->dev,
64 "Unsupported mbus code: 0x%x\n",
65 mbus_code);
66 break;
67 }
68 break;
69 default:
70 dev_dbg(csi_dev->dev, "Unsupported pixformat: 0x%x\n",
71 pixformat);
72 break;
73 }
74 return false;
75 }
76
77 switch (pixformat) {
78 case V4L2_PIX_FMT_SBGGR8:
79 return (mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8);
80 case V4L2_PIX_FMT_SGBRG8:
81 return (mbus_code == MEDIA_BUS_FMT_SGBRG8_1X8);
82 case V4L2_PIX_FMT_SGRBG8:
83 return (mbus_code == MEDIA_BUS_FMT_SGRBG8_1X8);
84 case V4L2_PIX_FMT_SRGGB8:
85 return (mbus_code == MEDIA_BUS_FMT_SRGGB8_1X8);
86 case V4L2_PIX_FMT_SBGGR10:
87 return (mbus_code == MEDIA_BUS_FMT_SBGGR10_1X10);
88 case V4L2_PIX_FMT_SGBRG10:
89 return (mbus_code == MEDIA_BUS_FMT_SGBRG10_1X10);
90 case V4L2_PIX_FMT_SGRBG10:
91 return (mbus_code == MEDIA_BUS_FMT_SGRBG10_1X10);
92 case V4L2_PIX_FMT_SRGGB10:
93 return (mbus_code == MEDIA_BUS_FMT_SRGGB10_1X10);
94 case V4L2_PIX_FMT_SBGGR12:
95 return (mbus_code == MEDIA_BUS_FMT_SBGGR12_1X12);
96 case V4L2_PIX_FMT_SGBRG12:
97 return (mbus_code == MEDIA_BUS_FMT_SGBRG12_1X12);
98 case V4L2_PIX_FMT_SGRBG12:
99 return (mbus_code == MEDIA_BUS_FMT_SGRBG12_1X12);
100 case V4L2_PIX_FMT_SRGGB12:
101 return (mbus_code == MEDIA_BUS_FMT_SRGGB12_1X12);
102
103 case V4L2_PIX_FMT_YUYV:
104 return (mbus_code == MEDIA_BUS_FMT_YUYV8_2X8);
105 case V4L2_PIX_FMT_YVYU:
106 return (mbus_code == MEDIA_BUS_FMT_YVYU8_2X8);
107 case V4L2_PIX_FMT_UYVY:
108 return (mbus_code == MEDIA_BUS_FMT_UYVY8_2X8);
109 case V4L2_PIX_FMT_VYUY:
110 return (mbus_code == MEDIA_BUS_FMT_VYUY8_2X8);
111
112 case V4L2_PIX_FMT_NV12_16L16:
113 case V4L2_PIX_FMT_NV12:
114 case V4L2_PIX_FMT_NV21:
115 case V4L2_PIX_FMT_NV16:
116 case V4L2_PIX_FMT_NV61:
117 case V4L2_PIX_FMT_YUV420:
118 case V4L2_PIX_FMT_YVU420:
119 case V4L2_PIX_FMT_YUV422P:
120 switch (mbus_code) {
121 case MEDIA_BUS_FMT_UYVY8_2X8:
122 case MEDIA_BUS_FMT_VYUY8_2X8:
123 case MEDIA_BUS_FMT_YUYV8_2X8:
124 case MEDIA_BUS_FMT_YVYU8_2X8:
125 return true;
126 default:
127 dev_dbg(csi_dev->dev, "Unsupported mbus code: 0x%x\n",
128 mbus_code);
129 break;
130 }
131 break;
132
133 case V4L2_PIX_FMT_RGB565:
134 return (mbus_code == MEDIA_BUS_FMT_RGB565_2X8_LE);
135 case V4L2_PIX_FMT_RGB565X:
136 return (mbus_code == MEDIA_BUS_FMT_RGB565_2X8_BE);
137
138 case V4L2_PIX_FMT_JPEG:
139 return (mbus_code == MEDIA_BUS_FMT_JPEG_1X8);
140
141 default:
142 dev_dbg(csi_dev->dev, "Unsupported pixformat: 0x%x\n",
143 pixformat);
144 break;
145 }
146
147 return false;
148 }
149
sun6i_csi_set_power(struct sun6i_csi_device * csi_dev,bool enable)150 int sun6i_csi_set_power(struct sun6i_csi_device *csi_dev, bool enable)
151 {
152 struct device *dev = csi_dev->dev;
153 struct regmap *regmap = csi_dev->regmap;
154 int ret;
155
156 if (!enable) {
157 regmap_update_bits(regmap, CSI_EN_REG, CSI_EN_CSI_EN, 0);
158 pm_runtime_put(dev);
159
160 return 0;
161 }
162
163 ret = pm_runtime_resume_and_get(dev);
164 if (ret < 0)
165 return ret;
166
167 regmap_update_bits(regmap, CSI_EN_REG, CSI_EN_CSI_EN, CSI_EN_CSI_EN);
168
169 return 0;
170 }
171
get_csi_input_format(struct sun6i_csi_device * csi_dev,u32 mbus_code,u32 pixformat)172 static enum csi_input_fmt get_csi_input_format(struct sun6i_csi_device *csi_dev,
173 u32 mbus_code, u32 pixformat)
174 {
175 /* non-YUV */
176 if ((mbus_code & 0xF000) != 0x2000)
177 return CSI_INPUT_FORMAT_RAW;
178
179 switch (pixformat) {
180 case V4L2_PIX_FMT_YUYV:
181 case V4L2_PIX_FMT_YVYU:
182 case V4L2_PIX_FMT_UYVY:
183 case V4L2_PIX_FMT_VYUY:
184 return CSI_INPUT_FORMAT_RAW;
185 default:
186 break;
187 }
188
189 /* not support YUV420 input format yet */
190 dev_dbg(csi_dev->dev, "Select YUV422 as default input format of CSI.\n");
191 return CSI_INPUT_FORMAT_YUV422;
192 }
193
194 static enum csi_output_fmt
get_csi_output_format(struct sun6i_csi_device * csi_dev,u32 pixformat,u32 field)195 get_csi_output_format(struct sun6i_csi_device *csi_dev, u32 pixformat,
196 u32 field)
197 {
198 bool buf_interlaced = false;
199
200 if (field == V4L2_FIELD_INTERLACED
201 || field == V4L2_FIELD_INTERLACED_TB
202 || field == V4L2_FIELD_INTERLACED_BT)
203 buf_interlaced = true;
204
205 switch (pixformat) {
206 case V4L2_PIX_FMT_SBGGR8:
207 case V4L2_PIX_FMT_SGBRG8:
208 case V4L2_PIX_FMT_SGRBG8:
209 case V4L2_PIX_FMT_SRGGB8:
210 return buf_interlaced ? CSI_FRAME_RAW_8 : CSI_FIELD_RAW_8;
211 case V4L2_PIX_FMT_SBGGR10:
212 case V4L2_PIX_FMT_SGBRG10:
213 case V4L2_PIX_FMT_SGRBG10:
214 case V4L2_PIX_FMT_SRGGB10:
215 return buf_interlaced ? CSI_FRAME_RAW_10 : CSI_FIELD_RAW_10;
216 case V4L2_PIX_FMT_SBGGR12:
217 case V4L2_PIX_FMT_SGBRG12:
218 case V4L2_PIX_FMT_SGRBG12:
219 case V4L2_PIX_FMT_SRGGB12:
220 return buf_interlaced ? CSI_FRAME_RAW_12 : CSI_FIELD_RAW_12;
221
222 case V4L2_PIX_FMT_YUYV:
223 case V4L2_PIX_FMT_YVYU:
224 case V4L2_PIX_FMT_UYVY:
225 case V4L2_PIX_FMT_VYUY:
226 return buf_interlaced ? CSI_FRAME_RAW_8 : CSI_FIELD_RAW_8;
227
228 case V4L2_PIX_FMT_NV12_16L16:
229 return buf_interlaced ? CSI_FRAME_MB_YUV420 :
230 CSI_FIELD_MB_YUV420;
231 case V4L2_PIX_FMT_NV12:
232 case V4L2_PIX_FMT_NV21:
233 return buf_interlaced ? CSI_FRAME_UV_CB_YUV420 :
234 CSI_FIELD_UV_CB_YUV420;
235 case V4L2_PIX_FMT_YUV420:
236 case V4L2_PIX_FMT_YVU420:
237 return buf_interlaced ? CSI_FRAME_PLANAR_YUV420 :
238 CSI_FIELD_PLANAR_YUV420;
239 case V4L2_PIX_FMT_NV16:
240 case V4L2_PIX_FMT_NV61:
241 return buf_interlaced ? CSI_FRAME_UV_CB_YUV422 :
242 CSI_FIELD_UV_CB_YUV422;
243 case V4L2_PIX_FMT_YUV422P:
244 return buf_interlaced ? CSI_FRAME_PLANAR_YUV422 :
245 CSI_FIELD_PLANAR_YUV422;
246
247 case V4L2_PIX_FMT_RGB565:
248 case V4L2_PIX_FMT_RGB565X:
249 return buf_interlaced ? CSI_FRAME_RGB565 : CSI_FIELD_RGB565;
250
251 case V4L2_PIX_FMT_JPEG:
252 return buf_interlaced ? CSI_FRAME_RAW_8 : CSI_FIELD_RAW_8;
253
254 default:
255 dev_warn(csi_dev->dev, "Unsupported pixformat: 0x%x\n", pixformat);
256 break;
257 }
258
259 return CSI_FIELD_RAW_8;
260 }
261
get_csi_input_seq(struct sun6i_csi_device * csi_dev,u32 mbus_code,u32 pixformat)262 static enum csi_input_seq get_csi_input_seq(struct sun6i_csi_device *csi_dev,
263 u32 mbus_code, u32 pixformat)
264 {
265 /* Input sequence does not apply to non-YUV formats */
266 if ((mbus_code & 0xF000) != 0x2000)
267 return 0;
268
269 switch (pixformat) {
270 case V4L2_PIX_FMT_NV12_16L16:
271 case V4L2_PIX_FMT_NV12:
272 case V4L2_PIX_FMT_NV16:
273 case V4L2_PIX_FMT_YUV420:
274 case V4L2_PIX_FMT_YUV422P:
275 switch (mbus_code) {
276 case MEDIA_BUS_FMT_UYVY8_2X8:
277 case MEDIA_BUS_FMT_UYVY8_1X16:
278 return CSI_INPUT_SEQ_UYVY;
279 case MEDIA_BUS_FMT_VYUY8_2X8:
280 case MEDIA_BUS_FMT_VYUY8_1X16:
281 return CSI_INPUT_SEQ_VYUY;
282 case MEDIA_BUS_FMT_YUYV8_2X8:
283 case MEDIA_BUS_FMT_YUYV8_1X16:
284 return CSI_INPUT_SEQ_YUYV;
285 case MEDIA_BUS_FMT_YVYU8_1X16:
286 case MEDIA_BUS_FMT_YVYU8_2X8:
287 return CSI_INPUT_SEQ_YVYU;
288 default:
289 dev_warn(csi_dev->dev, "Unsupported mbus code: 0x%x\n",
290 mbus_code);
291 break;
292 }
293 break;
294 case V4L2_PIX_FMT_NV21:
295 case V4L2_PIX_FMT_NV61:
296 case V4L2_PIX_FMT_YVU420:
297 switch (mbus_code) {
298 case MEDIA_BUS_FMT_UYVY8_2X8:
299 case MEDIA_BUS_FMT_UYVY8_1X16:
300 return CSI_INPUT_SEQ_VYUY;
301 case MEDIA_BUS_FMT_VYUY8_2X8:
302 case MEDIA_BUS_FMT_VYUY8_1X16:
303 return CSI_INPUT_SEQ_UYVY;
304 case MEDIA_BUS_FMT_YUYV8_2X8:
305 case MEDIA_BUS_FMT_YUYV8_1X16:
306 return CSI_INPUT_SEQ_YVYU;
307 case MEDIA_BUS_FMT_YVYU8_1X16:
308 case MEDIA_BUS_FMT_YVYU8_2X8:
309 return CSI_INPUT_SEQ_YUYV;
310 default:
311 dev_warn(csi_dev->dev, "Unsupported mbus code: 0x%x\n",
312 mbus_code);
313 break;
314 }
315 break;
316
317 case V4L2_PIX_FMT_YUYV:
318 return CSI_INPUT_SEQ_YUYV;
319
320 default:
321 dev_warn(csi_dev->dev, "Unsupported pixformat: 0x%x, defaulting to YUYV\n",
322 pixformat);
323 break;
324 }
325
326 return CSI_INPUT_SEQ_YUYV;
327 }
328
sun6i_csi_setup_bus(struct sun6i_csi_device * csi_dev)329 static void sun6i_csi_setup_bus(struct sun6i_csi_device *csi_dev)
330 {
331 struct v4l2_fwnode_endpoint *endpoint = &csi_dev->v4l2.v4l2_ep;
332 struct sun6i_csi_config *config = &csi_dev->config;
333 unsigned char bus_width;
334 u32 flags;
335 u32 cfg;
336 bool input_interlaced = false;
337
338 if (config->field == V4L2_FIELD_INTERLACED
339 || config->field == V4L2_FIELD_INTERLACED_TB
340 || config->field == V4L2_FIELD_INTERLACED_BT)
341 input_interlaced = true;
342
343 bus_width = endpoint->bus.parallel.bus_width;
344
345 regmap_read(csi_dev->regmap, CSI_IF_CFG_REG, &cfg);
346
347 cfg &= ~(CSI_IF_CFG_CSI_IF_MASK | CSI_IF_CFG_MIPI_IF_MASK |
348 CSI_IF_CFG_IF_DATA_WIDTH_MASK |
349 CSI_IF_CFG_CLK_POL_MASK | CSI_IF_CFG_VREF_POL_MASK |
350 CSI_IF_CFG_HREF_POL_MASK | CSI_IF_CFG_FIELD_MASK |
351 CSI_IF_CFG_SRC_TYPE_MASK);
352
353 if (input_interlaced)
354 cfg |= CSI_IF_CFG_SRC_TYPE_INTERLACED;
355 else
356 cfg |= CSI_IF_CFG_SRC_TYPE_PROGRESSED;
357
358 switch (endpoint->bus_type) {
359 case V4L2_MBUS_PARALLEL:
360 cfg |= CSI_IF_CFG_MIPI_IF_CSI;
361
362 flags = endpoint->bus.parallel.flags;
363
364 cfg |= (bus_width == 16) ? CSI_IF_CFG_CSI_IF_YUV422_16BIT :
365 CSI_IF_CFG_CSI_IF_YUV422_INTLV;
366
367 if (flags & V4L2_MBUS_FIELD_EVEN_LOW)
368 cfg |= CSI_IF_CFG_FIELD_POSITIVE;
369
370 if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
371 cfg |= CSI_IF_CFG_VREF_POL_POSITIVE;
372 if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
373 cfg |= CSI_IF_CFG_HREF_POL_POSITIVE;
374
375 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
376 cfg |= CSI_IF_CFG_CLK_POL_FALLING_EDGE;
377 break;
378 case V4L2_MBUS_BT656:
379 cfg |= CSI_IF_CFG_MIPI_IF_CSI;
380
381 flags = endpoint->bus.parallel.flags;
382
383 cfg |= (bus_width == 16) ? CSI_IF_CFG_CSI_IF_BT1120 :
384 CSI_IF_CFG_CSI_IF_BT656;
385
386 if (flags & V4L2_MBUS_FIELD_EVEN_LOW)
387 cfg |= CSI_IF_CFG_FIELD_POSITIVE;
388
389 if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
390 cfg |= CSI_IF_CFG_CLK_POL_FALLING_EDGE;
391 break;
392 default:
393 dev_warn(csi_dev->dev, "Unsupported bus type: %d\n",
394 endpoint->bus_type);
395 break;
396 }
397
398 switch (bus_width) {
399 case 8:
400 cfg |= CSI_IF_CFG_IF_DATA_WIDTH_8BIT;
401 break;
402 case 10:
403 cfg |= CSI_IF_CFG_IF_DATA_WIDTH_10BIT;
404 break;
405 case 12:
406 cfg |= CSI_IF_CFG_IF_DATA_WIDTH_12BIT;
407 break;
408 case 16: /* No need to configure DATA_WIDTH for 16bit */
409 break;
410 default:
411 dev_warn(csi_dev->dev, "Unsupported bus width: %u\n", bus_width);
412 break;
413 }
414
415 regmap_write(csi_dev->regmap, CSI_IF_CFG_REG, cfg);
416 }
417
sun6i_csi_set_format(struct sun6i_csi_device * csi_dev)418 static void sun6i_csi_set_format(struct sun6i_csi_device *csi_dev)
419 {
420 struct sun6i_csi_config *config = &csi_dev->config;
421 u32 cfg;
422 u32 val;
423
424 regmap_read(csi_dev->regmap, CSI_CH_CFG_REG, &cfg);
425
426 cfg &= ~(CSI_CH_CFG_INPUT_FMT_MASK |
427 CSI_CH_CFG_OUTPUT_FMT_MASK | CSI_CH_CFG_VFLIP_EN |
428 CSI_CH_CFG_HFLIP_EN | CSI_CH_CFG_FIELD_SEL_MASK |
429 CSI_CH_CFG_INPUT_SEQ_MASK);
430
431 val = get_csi_input_format(csi_dev, config->code,
432 config->pixelformat);
433 cfg |= CSI_CH_CFG_INPUT_FMT(val);
434
435 val = get_csi_output_format(csi_dev, config->pixelformat,
436 config->field);
437 cfg |= CSI_CH_CFG_OUTPUT_FMT(val);
438
439 val = get_csi_input_seq(csi_dev, config->code,
440 config->pixelformat);
441 cfg |= CSI_CH_CFG_INPUT_SEQ(val);
442
443 if (config->field == V4L2_FIELD_TOP)
444 cfg |= CSI_CH_CFG_FIELD_SEL_FIELD0;
445 else if (config->field == V4L2_FIELD_BOTTOM)
446 cfg |= CSI_CH_CFG_FIELD_SEL_FIELD1;
447 else
448 cfg |= CSI_CH_CFG_FIELD_SEL_BOTH;
449
450 regmap_write(csi_dev->regmap, CSI_CH_CFG_REG, cfg);
451 }
452
sun6i_csi_set_window(struct sun6i_csi_device * csi_dev)453 static void sun6i_csi_set_window(struct sun6i_csi_device *csi_dev)
454 {
455 struct sun6i_csi_config *config = &csi_dev->config;
456 u32 bytesperline_y;
457 u32 bytesperline_c;
458 int *planar_offset = csi_dev->planar_offset;
459 u32 width = config->width;
460 u32 height = config->height;
461 u32 hor_len = width;
462
463 switch (config->pixelformat) {
464 case V4L2_PIX_FMT_YUYV:
465 case V4L2_PIX_FMT_YVYU:
466 case V4L2_PIX_FMT_UYVY:
467 case V4L2_PIX_FMT_VYUY:
468 dev_dbg(csi_dev->dev,
469 "Horizontal length should be 2 times of width for packed YUV formats!\n");
470 hor_len = width * 2;
471 break;
472 default:
473 break;
474 }
475
476 regmap_write(csi_dev->regmap, CSI_CH_HSIZE_REG,
477 CSI_CH_HSIZE_HOR_LEN(hor_len) |
478 CSI_CH_HSIZE_HOR_START(0));
479 regmap_write(csi_dev->regmap, CSI_CH_VSIZE_REG,
480 CSI_CH_VSIZE_VER_LEN(height) |
481 CSI_CH_VSIZE_VER_START(0));
482
483 planar_offset[0] = 0;
484 switch (config->pixelformat) {
485 case V4L2_PIX_FMT_NV12_16L16:
486 case V4L2_PIX_FMT_NV12:
487 case V4L2_PIX_FMT_NV21:
488 case V4L2_PIX_FMT_NV16:
489 case V4L2_PIX_FMT_NV61:
490 bytesperline_y = width;
491 bytesperline_c = width;
492 planar_offset[1] = bytesperline_y * height;
493 planar_offset[2] = -1;
494 break;
495 case V4L2_PIX_FMT_YUV420:
496 case V4L2_PIX_FMT_YVU420:
497 bytesperline_y = width;
498 bytesperline_c = width / 2;
499 planar_offset[1] = bytesperline_y * height;
500 planar_offset[2] = planar_offset[1] +
501 bytesperline_c * height / 2;
502 break;
503 case V4L2_PIX_FMT_YUV422P:
504 bytesperline_y = width;
505 bytesperline_c = width / 2;
506 planar_offset[1] = bytesperline_y * height;
507 planar_offset[2] = planar_offset[1] +
508 bytesperline_c * height;
509 break;
510 default: /* raw */
511 dev_dbg(csi_dev->dev,
512 "Calculating pixelformat(0x%x)'s bytesperline as a packed format\n",
513 config->pixelformat);
514 bytesperline_y = (sun6i_csi_get_bpp(config->pixelformat) *
515 config->width) / 8;
516 bytesperline_c = 0;
517 planar_offset[1] = -1;
518 planar_offset[2] = -1;
519 break;
520 }
521
522 regmap_write(csi_dev->regmap, CSI_CH_BUF_LEN_REG,
523 CSI_CH_BUF_LEN_BUF_LEN_C(bytesperline_c) |
524 CSI_CH_BUF_LEN_BUF_LEN_Y(bytesperline_y));
525 }
526
sun6i_csi_update_config(struct sun6i_csi_device * csi_dev,struct sun6i_csi_config * config)527 int sun6i_csi_update_config(struct sun6i_csi_device *csi_dev,
528 struct sun6i_csi_config *config)
529 {
530 if (!config)
531 return -EINVAL;
532
533 memcpy(&csi_dev->config, config, sizeof(csi_dev->config));
534
535 sun6i_csi_setup_bus(csi_dev);
536 sun6i_csi_set_format(csi_dev);
537 sun6i_csi_set_window(csi_dev);
538
539 return 0;
540 }
541
sun6i_csi_update_buf_addr(struct sun6i_csi_device * csi_dev,dma_addr_t addr)542 void sun6i_csi_update_buf_addr(struct sun6i_csi_device *csi_dev,
543 dma_addr_t addr)
544 {
545 regmap_write(csi_dev->regmap, CSI_CH_F0_BUFA_REG,
546 (addr + csi_dev->planar_offset[0]) >> 2);
547 if (csi_dev->planar_offset[1] != -1)
548 regmap_write(csi_dev->regmap, CSI_CH_F1_BUFA_REG,
549 (addr + csi_dev->planar_offset[1]) >> 2);
550 if (csi_dev->planar_offset[2] != -1)
551 regmap_write(csi_dev->regmap, CSI_CH_F2_BUFA_REG,
552 (addr + csi_dev->planar_offset[2]) >> 2);
553 }
554
sun6i_csi_set_stream(struct sun6i_csi_device * csi_dev,bool enable)555 void sun6i_csi_set_stream(struct sun6i_csi_device *csi_dev, bool enable)
556 {
557 struct regmap *regmap = csi_dev->regmap;
558
559 if (!enable) {
560 regmap_update_bits(regmap, CSI_CAP_REG, CSI_CAP_CH0_VCAP_ON, 0);
561 regmap_write(regmap, CSI_CH_INT_EN_REG, 0);
562 return;
563 }
564
565 regmap_write(regmap, CSI_CH_INT_STA_REG, 0xFF);
566 regmap_write(regmap, CSI_CH_INT_EN_REG,
567 CSI_CH_INT_EN_HB_OF_INT_EN |
568 CSI_CH_INT_EN_FIFO2_OF_INT_EN |
569 CSI_CH_INT_EN_FIFO1_OF_INT_EN |
570 CSI_CH_INT_EN_FIFO0_OF_INT_EN |
571 CSI_CH_INT_EN_FD_INT_EN |
572 CSI_CH_INT_EN_CD_INT_EN);
573
574 regmap_update_bits(regmap, CSI_CAP_REG, CSI_CAP_CH0_VCAP_ON,
575 CSI_CAP_CH0_VCAP_ON);
576 }
577
578 /* Media */
579
580 static const struct media_device_ops sun6i_csi_media_ops = {
581 .link_notify = v4l2_pipeline_link_notify,
582 };
583
584 /* V4L2 */
585
sun6i_csi_link_entity(struct sun6i_csi_device * csi_dev,struct media_entity * entity,struct fwnode_handle * fwnode)586 static int sun6i_csi_link_entity(struct sun6i_csi_device *csi_dev,
587 struct media_entity *entity,
588 struct fwnode_handle *fwnode)
589 {
590 struct media_entity *sink;
591 struct media_pad *sink_pad;
592 int src_pad_index;
593 int ret;
594
595 ret = media_entity_get_fwnode_pad(entity, fwnode, MEDIA_PAD_FL_SOURCE);
596 if (ret < 0) {
597 dev_err(csi_dev->dev,
598 "%s: no source pad in external entity %s\n", __func__,
599 entity->name);
600 return -EINVAL;
601 }
602
603 src_pad_index = ret;
604
605 sink = &csi_dev->video.video_dev.entity;
606 sink_pad = &csi_dev->video.pad;
607
608 dev_dbg(csi_dev->dev, "creating %s:%u -> %s:%u link\n",
609 entity->name, src_pad_index, sink->name, sink_pad->index);
610 ret = media_create_pad_link(entity, src_pad_index, sink,
611 sink_pad->index,
612 MEDIA_LNK_FL_ENABLED |
613 MEDIA_LNK_FL_IMMUTABLE);
614 if (ret < 0) {
615 dev_err(csi_dev->dev, "failed to create %s:%u -> %s:%u link\n",
616 entity->name, src_pad_index,
617 sink->name, sink_pad->index);
618 return ret;
619 }
620
621 return 0;
622 }
623
sun6i_subdev_notify_complete(struct v4l2_async_notifier * notifier)624 static int sun6i_subdev_notify_complete(struct v4l2_async_notifier *notifier)
625 {
626 struct sun6i_csi_device *csi_dev =
627 container_of(notifier, struct sun6i_csi_device,
628 v4l2.notifier);
629 struct sun6i_csi_v4l2 *v4l2 = &csi_dev->v4l2;
630 struct v4l2_device *v4l2_dev = &v4l2->v4l2_dev;
631 struct v4l2_subdev *sd;
632 int ret;
633
634 dev_dbg(csi_dev->dev, "notify complete, all subdevs registered\n");
635
636 sd = list_first_entry(&v4l2_dev->subdevs, struct v4l2_subdev, list);
637 if (!sd)
638 return -EINVAL;
639
640 ret = sun6i_csi_link_entity(csi_dev, &sd->entity, sd->fwnode);
641 if (ret < 0)
642 return ret;
643
644 ret = v4l2_device_register_subdev_nodes(v4l2_dev);
645 if (ret < 0)
646 return ret;
647
648 return 0;
649 }
650
651 static const struct v4l2_async_notifier_operations sun6i_csi_async_ops = {
652 .complete = sun6i_subdev_notify_complete,
653 };
654
sun6i_csi_fwnode_parse(struct device * dev,struct v4l2_fwnode_endpoint * vep,struct v4l2_async_subdev * asd)655 static int sun6i_csi_fwnode_parse(struct device *dev,
656 struct v4l2_fwnode_endpoint *vep,
657 struct v4l2_async_subdev *asd)
658 {
659 struct sun6i_csi_device *csi_dev = dev_get_drvdata(dev);
660
661 if (vep->base.port || vep->base.id) {
662 dev_warn(dev, "Only support a single port with one endpoint\n");
663 return -ENOTCONN;
664 }
665
666 switch (vep->bus_type) {
667 case V4L2_MBUS_PARALLEL:
668 case V4L2_MBUS_BT656:
669 csi_dev->v4l2.v4l2_ep = *vep;
670 return 0;
671 default:
672 dev_err(dev, "Unsupported media bus type\n");
673 return -ENOTCONN;
674 }
675 }
676
sun6i_csi_v4l2_setup(struct sun6i_csi_device * csi_dev)677 static int sun6i_csi_v4l2_setup(struct sun6i_csi_device *csi_dev)
678 {
679 struct sun6i_csi_v4l2 *v4l2 = &csi_dev->v4l2;
680 struct media_device *media_dev = &v4l2->media_dev;
681 struct v4l2_device *v4l2_dev = &v4l2->v4l2_dev;
682 struct v4l2_async_notifier *notifier = &v4l2->notifier;
683 struct device *dev = csi_dev->dev;
684 int ret;
685
686 /* Media Device */
687
688 strscpy(media_dev->model, SUN6I_CSI_DESCRIPTION,
689 sizeof(media_dev->model));
690 media_dev->hw_revision = 0;
691 media_dev->ops = &sun6i_csi_media_ops;
692 media_dev->dev = dev;
693
694 media_device_init(media_dev);
695
696 ret = media_device_register(media_dev);
697 if (ret) {
698 dev_err(dev, "failed to register media device: %d\n", ret);
699 goto error_media;
700 }
701
702 /* V4L2 Device */
703
704 v4l2_dev->mdev = media_dev;
705
706 ret = v4l2_device_register(dev, v4l2_dev);
707 if (ret) {
708 dev_err(dev, "failed to register v4l2 device: %d\n", ret);
709 goto error_media;
710 }
711
712 /* Video */
713
714 ret = sun6i_video_setup(csi_dev);
715 if (ret)
716 goto error_v4l2_device;
717
718 /* V4L2 Async */
719
720 v4l2_async_nf_init(notifier);
721 notifier->ops = &sun6i_csi_async_ops;
722
723 ret = v4l2_async_nf_parse_fwnode_endpoints(dev, notifier,
724 sizeof(struct
725 v4l2_async_subdev),
726 sun6i_csi_fwnode_parse);
727 if (ret)
728 goto error_video;
729
730 ret = v4l2_async_nf_register(v4l2_dev, notifier);
731 if (ret) {
732 dev_err(dev, "failed to register v4l2 async notifier: %d\n",
733 ret);
734 goto error_v4l2_async_notifier;
735 }
736
737 return 0;
738
739 error_v4l2_async_notifier:
740 v4l2_async_nf_cleanup(notifier);
741
742 error_video:
743 sun6i_video_cleanup(csi_dev);
744
745 error_v4l2_device:
746 v4l2_device_unregister(&v4l2->v4l2_dev);
747
748 error_media:
749 media_device_unregister(media_dev);
750 media_device_cleanup(media_dev);
751
752 return ret;
753 }
754
sun6i_csi_v4l2_cleanup(struct sun6i_csi_device * csi_dev)755 static void sun6i_csi_v4l2_cleanup(struct sun6i_csi_device *csi_dev)
756 {
757 struct sun6i_csi_v4l2 *v4l2 = &csi_dev->v4l2;
758
759 media_device_unregister(&v4l2->media_dev);
760 v4l2_async_nf_unregister(&v4l2->notifier);
761 v4l2_async_nf_cleanup(&v4l2->notifier);
762 sun6i_video_cleanup(csi_dev);
763 v4l2_device_unregister(&v4l2->v4l2_dev);
764 media_device_cleanup(&v4l2->media_dev);
765 }
766
767 /* Platform */
768
sun6i_csi_interrupt(int irq,void * private)769 static irqreturn_t sun6i_csi_interrupt(int irq, void *private)
770 {
771 struct sun6i_csi_device *csi_dev = private;
772 struct regmap *regmap = csi_dev->regmap;
773 u32 status;
774
775 regmap_read(regmap, CSI_CH_INT_STA_REG, &status);
776
777 if (!(status & 0xFF))
778 return IRQ_NONE;
779
780 if ((status & CSI_CH_INT_STA_FIFO0_OF_PD) ||
781 (status & CSI_CH_INT_STA_FIFO1_OF_PD) ||
782 (status & CSI_CH_INT_STA_FIFO2_OF_PD) ||
783 (status & CSI_CH_INT_STA_HB_OF_PD)) {
784 regmap_write(regmap, CSI_CH_INT_STA_REG, status);
785 regmap_update_bits(regmap, CSI_EN_REG, CSI_EN_CSI_EN, 0);
786 regmap_update_bits(regmap, CSI_EN_REG, CSI_EN_CSI_EN,
787 CSI_EN_CSI_EN);
788 return IRQ_HANDLED;
789 }
790
791 if (status & CSI_CH_INT_STA_FD_PD)
792 sun6i_video_frame_done(csi_dev);
793
794 regmap_write(regmap, CSI_CH_INT_STA_REG, status);
795
796 return IRQ_HANDLED;
797 }
798
sun6i_csi_suspend(struct device * dev)799 static int sun6i_csi_suspend(struct device *dev)
800 {
801 struct sun6i_csi_device *csi_dev = dev_get_drvdata(dev);
802
803 reset_control_assert(csi_dev->reset);
804 clk_disable_unprepare(csi_dev->clock_ram);
805 clk_disable_unprepare(csi_dev->clock_mod);
806
807 return 0;
808 }
809
sun6i_csi_resume(struct device * dev)810 static int sun6i_csi_resume(struct device *dev)
811 {
812 struct sun6i_csi_device *csi_dev = dev_get_drvdata(dev);
813 int ret;
814
815 ret = reset_control_deassert(csi_dev->reset);
816 if (ret) {
817 dev_err(dev, "failed to deassert reset\n");
818 return ret;
819 }
820
821 ret = clk_prepare_enable(csi_dev->clock_mod);
822 if (ret) {
823 dev_err(dev, "failed to enable module clock\n");
824 goto error_reset;
825 }
826
827 ret = clk_prepare_enable(csi_dev->clock_ram);
828 if (ret) {
829 dev_err(dev, "failed to enable ram clock\n");
830 goto error_clock_mod;
831 }
832
833 return 0;
834
835 error_clock_mod:
836 clk_disable_unprepare(csi_dev->clock_mod);
837
838 error_reset:
839 reset_control_assert(csi_dev->reset);
840
841 return ret;
842 }
843
844 static const struct dev_pm_ops sun6i_csi_pm_ops = {
845 .runtime_suspend = sun6i_csi_suspend,
846 .runtime_resume = sun6i_csi_resume,
847 };
848
849 static const struct regmap_config sun6i_csi_regmap_config = {
850 .reg_bits = 32,
851 .reg_stride = 4,
852 .val_bits = 32,
853 .max_register = 0x9c,
854 };
855
sun6i_csi_resources_setup(struct sun6i_csi_device * csi_dev,struct platform_device * platform_dev)856 static int sun6i_csi_resources_setup(struct sun6i_csi_device *csi_dev,
857 struct platform_device *platform_dev)
858 {
859 struct device *dev = csi_dev->dev;
860 const struct sun6i_csi_variant *variant;
861 void __iomem *io_base;
862 int ret;
863 int irq;
864
865 variant = of_device_get_match_data(dev);
866 if (!variant)
867 return -EINVAL;
868
869 /* Registers */
870
871 io_base = devm_platform_ioremap_resource(platform_dev, 0);
872 if (IS_ERR(io_base))
873 return PTR_ERR(io_base);
874
875 csi_dev->regmap = devm_regmap_init_mmio_clk(dev, "bus", io_base,
876 &sun6i_csi_regmap_config);
877 if (IS_ERR(csi_dev->regmap)) {
878 dev_err(dev, "failed to init register map\n");
879 return PTR_ERR(csi_dev->regmap);
880 }
881
882 /* Clocks */
883
884 csi_dev->clock_mod = devm_clk_get(dev, "mod");
885 if (IS_ERR(csi_dev->clock_mod)) {
886 dev_err(dev, "failed to acquire module clock\n");
887 return PTR_ERR(csi_dev->clock_mod);
888 }
889
890 csi_dev->clock_ram = devm_clk_get(dev, "ram");
891 if (IS_ERR(csi_dev->clock_ram)) {
892 dev_err(dev, "failed to acquire ram clock\n");
893 return PTR_ERR(csi_dev->clock_ram);
894 }
895
896 ret = clk_set_rate_exclusive(csi_dev->clock_mod,
897 variant->clock_mod_rate);
898 if (ret) {
899 dev_err(dev, "failed to set mod clock rate\n");
900 return ret;
901 }
902
903 /* Reset */
904
905 csi_dev->reset = devm_reset_control_get_shared(dev, NULL);
906 if (IS_ERR(csi_dev->reset)) {
907 dev_err(dev, "failed to acquire reset\n");
908 ret = PTR_ERR(csi_dev->reset);
909 goto error_clock_rate_exclusive;
910 }
911
912 /* Interrupt */
913
914 irq = platform_get_irq(platform_dev, 0);
915 if (irq < 0) {
916 dev_err(dev, "failed to get interrupt\n");
917 ret = -ENXIO;
918 goto error_clock_rate_exclusive;
919 }
920
921 ret = devm_request_irq(dev, irq, sun6i_csi_interrupt, 0, SUN6I_CSI_NAME,
922 csi_dev);
923 if (ret) {
924 dev_err(dev, "failed to request interrupt\n");
925 goto error_clock_rate_exclusive;
926 }
927
928 /* Runtime PM */
929
930 pm_runtime_enable(dev);
931
932 return 0;
933
934 error_clock_rate_exclusive:
935 clk_rate_exclusive_put(csi_dev->clock_mod);
936
937 return ret;
938 }
939
sun6i_csi_resources_cleanup(struct sun6i_csi_device * csi_dev)940 static void sun6i_csi_resources_cleanup(struct sun6i_csi_device *csi_dev)
941 {
942 pm_runtime_disable(csi_dev->dev);
943 clk_rate_exclusive_put(csi_dev->clock_mod);
944 }
945
sun6i_csi_probe(struct platform_device * platform_dev)946 static int sun6i_csi_probe(struct platform_device *platform_dev)
947 {
948 struct sun6i_csi_device *csi_dev;
949 struct device *dev = &platform_dev->dev;
950 int ret;
951
952 csi_dev = devm_kzalloc(dev, sizeof(*csi_dev), GFP_KERNEL);
953 if (!csi_dev)
954 return -ENOMEM;
955
956 csi_dev->dev = &platform_dev->dev;
957 platform_set_drvdata(platform_dev, csi_dev);
958
959 ret = sun6i_csi_resources_setup(csi_dev, platform_dev);
960 if (ret)
961 return ret;
962
963 ret = sun6i_csi_v4l2_setup(csi_dev);
964 if (ret)
965 goto error_resources;
966
967 return 0;
968
969 error_resources:
970 sun6i_csi_resources_cleanup(csi_dev);
971
972 return ret;
973 }
974
sun6i_csi_remove(struct platform_device * pdev)975 static int sun6i_csi_remove(struct platform_device *pdev)
976 {
977 struct sun6i_csi_device *csi_dev = platform_get_drvdata(pdev);
978
979 sun6i_csi_v4l2_cleanup(csi_dev);
980 sun6i_csi_resources_cleanup(csi_dev);
981
982 return 0;
983 }
984
985 static const struct sun6i_csi_variant sun6i_a31_csi_variant = {
986 .clock_mod_rate = 297000000,
987 };
988
989 static const struct sun6i_csi_variant sun50i_a64_csi_variant = {
990 .clock_mod_rate = 300000000,
991 };
992
993 static const struct of_device_id sun6i_csi_of_match[] = {
994 {
995 .compatible = "allwinner,sun6i-a31-csi",
996 .data = &sun6i_a31_csi_variant,
997 },
998 {
999 .compatible = "allwinner,sun8i-a83t-csi",
1000 .data = &sun6i_a31_csi_variant,
1001 },
1002 {
1003 .compatible = "allwinner,sun8i-h3-csi",
1004 .data = &sun6i_a31_csi_variant,
1005 },
1006 {
1007 .compatible = "allwinner,sun8i-v3s-csi",
1008 .data = &sun6i_a31_csi_variant,
1009 },
1010 {
1011 .compatible = "allwinner,sun50i-a64-csi",
1012 .data = &sun50i_a64_csi_variant,
1013 },
1014 {},
1015 };
1016
1017 MODULE_DEVICE_TABLE(of, sun6i_csi_of_match);
1018
1019 static struct platform_driver sun6i_csi_platform_driver = {
1020 .probe = sun6i_csi_probe,
1021 .remove = sun6i_csi_remove,
1022 .driver = {
1023 .name = SUN6I_CSI_NAME,
1024 .of_match_table = of_match_ptr(sun6i_csi_of_match),
1025 .pm = &sun6i_csi_pm_ops,
1026 },
1027 };
1028
1029 module_platform_driver(sun6i_csi_platform_driver);
1030
1031 MODULE_DESCRIPTION("Allwinner A31 Camera Sensor Interface driver");
1032 MODULE_AUTHOR("Yong Deng <yong.deng@magewell.com>");
1033 MODULE_LICENSE("GPL");
1034
