1 /*
2 * Copyright (C) 2015 Free Electrons
3 * Copyright (C) 2015 NextThing Co
4 *
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 */
12
13 #include <drm/drmP.h>
14 #include <drm/drm_atomic.h>
15 #include <drm/drm_atomic_helper.h>
16 #include <drm/drm_crtc.h>
17 #include <drm/drm_crtc_helper.h>
18 #include <drm/drm_fb_cma_helper.h>
19 #include <drm/drm_gem_cma_helper.h>
20 #include <drm/drm_plane_helper.h>
21
22 #include <linux/component.h>
23 #include <linux/list.h>
24 #include <linux/of_device.h>
25 #include <linux/of_graph.h>
26 #include <linux/reset.h>
27
28 #include "sun4i_backend.h"
29 #include "sun4i_drv.h"
30 #include "sun4i_frontend.h"
31 #include "sun4i_layer.h"
32 #include "sunxi_engine.h"
33
34 struct sun4i_backend_quirks {
35 /* backend <-> TCON muxing selection done in backend */
36 bool needs_output_muxing;
37 };
38
39 static const u32 sunxi_rgb2yuv_coef[12] = {
40 0x00000107, 0x00000204, 0x00000064, 0x00000108,
41 0x00003f69, 0x00003ed6, 0x000001c1, 0x00000808,
42 0x000001c1, 0x00003e88, 0x00003fb8, 0x00000808
43 };
44
45 /*
46 * These coefficients are taken from the A33 BSP from Allwinner.
47 *
48 * The formula is for each component, each coefficient being multiplied by
49 * 1024 and each constant being multiplied by 16:
50 * G = 1.164 * Y - 0.391 * U - 0.813 * V + 135
51 * R = 1.164 * Y + 1.596 * V - 222
52 * B = 1.164 * Y + 2.018 * U + 276
53 *
54 * This seems to be a conversion from Y[16:235] UV[16:240] to RGB[0:255],
55 * following the BT601 spec.
56 */
57 static const u32 sunxi_bt601_yuv2rgb_coef[12] = {
58 0x000004a7, 0x00001e6f, 0x00001cbf, 0x00000877,
59 0x000004a7, 0x00000000, 0x00000662, 0x00003211,
60 0x000004a7, 0x00000812, 0x00000000, 0x00002eb1,
61 };
62
sun4i_backend_format_is_planar_yuv(uint32_t format)63 static inline bool sun4i_backend_format_is_planar_yuv(uint32_t format)
64 {
65 switch (format) {
66 case DRM_FORMAT_YUV411:
67 case DRM_FORMAT_YUV422:
68 case DRM_FORMAT_YUV444:
69 return true;
70 default:
71 return false;
72 }
73 }
74
sun4i_backend_format_is_packed_yuv422(uint32_t format)75 static inline bool sun4i_backend_format_is_packed_yuv422(uint32_t format)
76 {
77 switch (format) {
78 case DRM_FORMAT_YUYV:
79 case DRM_FORMAT_YVYU:
80 case DRM_FORMAT_UYVY:
81 case DRM_FORMAT_VYUY:
82 return true;
83
84 default:
85 return false;
86 }
87 }
88
sun4i_backend_apply_color_correction(struct sunxi_engine * engine)89 static void sun4i_backend_apply_color_correction(struct sunxi_engine *engine)
90 {
91 int i;
92
93 DRM_DEBUG_DRIVER("Applying RGB to YUV color correction\n");
94
95 /* Set color correction */
96 regmap_write(engine->regs, SUN4I_BACKEND_OCCTL_REG,
97 SUN4I_BACKEND_OCCTL_ENABLE);
98
99 for (i = 0; i < 12; i++)
100 regmap_write(engine->regs, SUN4I_BACKEND_OCRCOEF_REG(i),
101 sunxi_rgb2yuv_coef[i]);
102 }
103
sun4i_backend_disable_color_correction(struct sunxi_engine * engine)104 static void sun4i_backend_disable_color_correction(struct sunxi_engine *engine)
105 {
106 DRM_DEBUG_DRIVER("Disabling color correction\n");
107
108 /* Disable color correction */
109 regmap_update_bits(engine->regs, SUN4I_BACKEND_OCCTL_REG,
110 SUN4I_BACKEND_OCCTL_ENABLE, 0);
111 }
112
sun4i_backend_commit(struct sunxi_engine * engine)113 static void sun4i_backend_commit(struct sunxi_engine *engine)
114 {
115 DRM_DEBUG_DRIVER("Committing changes\n");
116
117 regmap_write(engine->regs, SUN4I_BACKEND_REGBUFFCTL_REG,
118 SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS |
119 SUN4I_BACKEND_REGBUFFCTL_LOADCTL);
120 }
121
sun4i_backend_layer_enable(struct sun4i_backend * backend,int layer,bool enable)122 void sun4i_backend_layer_enable(struct sun4i_backend *backend,
123 int layer, bool enable)
124 {
125 u32 val;
126
127 DRM_DEBUG_DRIVER("%sabling layer %d\n", enable ? "En" : "Dis",
128 layer);
129
130 if (enable)
131 val = SUN4I_BACKEND_MODCTL_LAY_EN(layer);
132 else
133 val = 0;
134
135 regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
136 SUN4I_BACKEND_MODCTL_LAY_EN(layer), val);
137 }
138
sun4i_backend_drm_format_to_layer(u32 format,u32 * mode)139 static int sun4i_backend_drm_format_to_layer(u32 format, u32 *mode)
140 {
141 switch (format) {
142 case DRM_FORMAT_ARGB8888:
143 *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB8888;
144 break;
145
146 case DRM_FORMAT_ARGB4444:
147 *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB4444;
148 break;
149
150 case DRM_FORMAT_ARGB1555:
151 *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB1555;
152 break;
153
154 case DRM_FORMAT_RGBA5551:
155 *mode = SUN4I_BACKEND_LAY_FBFMT_RGBA5551;
156 break;
157
158 case DRM_FORMAT_RGBA4444:
159 *mode = SUN4I_BACKEND_LAY_FBFMT_RGBA4444;
160 break;
161
162 case DRM_FORMAT_XRGB8888:
163 *mode = SUN4I_BACKEND_LAY_FBFMT_XRGB8888;
164 break;
165
166 case DRM_FORMAT_RGB888:
167 *mode = SUN4I_BACKEND_LAY_FBFMT_RGB888;
168 break;
169
170 case DRM_FORMAT_RGB565:
171 *mode = SUN4I_BACKEND_LAY_FBFMT_RGB565;
172 break;
173
174 default:
175 return -EINVAL;
176 }
177
178 return 0;
179 }
180
sun4i_backend_update_layer_coord(struct sun4i_backend * backend,int layer,struct drm_plane * plane)181 int sun4i_backend_update_layer_coord(struct sun4i_backend *backend,
182 int layer, struct drm_plane *plane)
183 {
184 struct drm_plane_state *state = plane->state;
185
186 DRM_DEBUG_DRIVER("Updating layer %d\n", layer);
187
188 if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
189 DRM_DEBUG_DRIVER("Primary layer, updating global size W: %u H: %u\n",
190 state->crtc_w, state->crtc_h);
191 regmap_write(backend->engine.regs, SUN4I_BACKEND_DISSIZE_REG,
192 SUN4I_BACKEND_DISSIZE(state->crtc_w,
193 state->crtc_h));
194 }
195
196 /* Set height and width */
197 DRM_DEBUG_DRIVER("Layer size W: %u H: %u\n",
198 state->crtc_w, state->crtc_h);
199 regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYSIZE_REG(layer),
200 SUN4I_BACKEND_LAYSIZE(state->crtc_w,
201 state->crtc_h));
202
203 /* Set base coordinates */
204 DRM_DEBUG_DRIVER("Layer coordinates X: %d Y: %d\n",
205 state->crtc_x, state->crtc_y);
206 regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYCOOR_REG(layer),
207 SUN4I_BACKEND_LAYCOOR(state->crtc_x,
208 state->crtc_y));
209
210 return 0;
211 }
212
sun4i_backend_update_yuv_format(struct sun4i_backend * backend,int layer,struct drm_plane * plane)213 static int sun4i_backend_update_yuv_format(struct sun4i_backend *backend,
214 int layer, struct drm_plane *plane)
215 {
216 struct drm_plane_state *state = plane->state;
217 struct drm_framebuffer *fb = state->fb;
218 uint32_t format = fb->format->format;
219 u32 val = SUN4I_BACKEND_IYUVCTL_EN;
220 int i;
221
222 for (i = 0; i < ARRAY_SIZE(sunxi_bt601_yuv2rgb_coef); i++)
223 regmap_write(backend->engine.regs,
224 SUN4I_BACKEND_YGCOEF_REG(i),
225 sunxi_bt601_yuv2rgb_coef[i]);
226
227 /*
228 * We should do that only for a single plane, but the
229 * framebuffer's atomic_check has our back on this.
230 */
231 regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
232 SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN,
233 SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN);
234
235 /* TODO: Add support for the multi-planar YUV formats */
236 if (sun4i_backend_format_is_packed_yuv422(format))
237 val |= SUN4I_BACKEND_IYUVCTL_FBFMT_PACKED_YUV422;
238 else
239 DRM_DEBUG_DRIVER("Unsupported YUV format (0x%x)\n", format);
240
241 /*
242 * Allwinner seems to list the pixel sequence from right to left, while
243 * DRM lists it from left to right.
244 */
245 switch (format) {
246 case DRM_FORMAT_YUYV:
247 val |= SUN4I_BACKEND_IYUVCTL_FBPS_VYUY;
248 break;
249 case DRM_FORMAT_YVYU:
250 val |= SUN4I_BACKEND_IYUVCTL_FBPS_UYVY;
251 break;
252 case DRM_FORMAT_UYVY:
253 val |= SUN4I_BACKEND_IYUVCTL_FBPS_YVYU;
254 break;
255 case DRM_FORMAT_VYUY:
256 val |= SUN4I_BACKEND_IYUVCTL_FBPS_YUYV;
257 break;
258 default:
259 DRM_DEBUG_DRIVER("Unsupported YUV pixel sequence (0x%x)\n",
260 format);
261 }
262
263 regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVCTL_REG, val);
264
265 return 0;
266 }
267
sun4i_backend_update_layer_formats(struct sun4i_backend * backend,int layer,struct drm_plane * plane)268 int sun4i_backend_update_layer_formats(struct sun4i_backend *backend,
269 int layer, struct drm_plane *plane)
270 {
271 struct drm_plane_state *state = plane->state;
272 struct drm_framebuffer *fb = state->fb;
273 bool interlaced = false;
274 u32 val;
275 int ret;
276
277 /* Clear the YUV mode */
278 regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
279 SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN, 0);
280
281 if (plane->state->crtc)
282 interlaced = plane->state->crtc->state->adjusted_mode.flags
283 & DRM_MODE_FLAG_INTERLACE;
284
285 regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
286 SUN4I_BACKEND_MODCTL_ITLMOD_EN,
287 interlaced ? SUN4I_BACKEND_MODCTL_ITLMOD_EN : 0);
288
289 DRM_DEBUG_DRIVER("Switching display backend interlaced mode %s\n",
290 interlaced ? "on" : "off");
291
292 val = SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA(state->alpha >> 8);
293 if (state->alpha != DRM_BLEND_ALPHA_OPAQUE)
294 val |= SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_EN;
295 regmap_update_bits(backend->engine.regs,
296 SUN4I_BACKEND_ATTCTL_REG0(layer),
297 SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_MASK |
298 SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_EN,
299 val);
300
301 if (fb->format->is_yuv)
302 return sun4i_backend_update_yuv_format(backend, layer, plane);
303
304 ret = sun4i_backend_drm_format_to_layer(fb->format->format, &val);
305 if (ret) {
306 DRM_DEBUG_DRIVER("Invalid format\n");
307 return ret;
308 }
309
310 regmap_update_bits(backend->engine.regs,
311 SUN4I_BACKEND_ATTCTL_REG1(layer),
312 SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val);
313
314 return 0;
315 }
316
sun4i_backend_update_layer_frontend(struct sun4i_backend * backend,int layer,uint32_t fmt)317 int sun4i_backend_update_layer_frontend(struct sun4i_backend *backend,
318 int layer, uint32_t fmt)
319 {
320 u32 val;
321 int ret;
322
323 ret = sun4i_backend_drm_format_to_layer(fmt, &val);
324 if (ret) {
325 DRM_DEBUG_DRIVER("Invalid format\n");
326 return ret;
327 }
328
329 regmap_update_bits(backend->engine.regs,
330 SUN4I_BACKEND_ATTCTL_REG0(layer),
331 SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN,
332 SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN);
333
334 regmap_update_bits(backend->engine.regs,
335 SUN4I_BACKEND_ATTCTL_REG1(layer),
336 SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val);
337
338 return 0;
339 }
340
sun4i_backend_update_yuv_buffer(struct sun4i_backend * backend,struct drm_framebuffer * fb,dma_addr_t paddr)341 static int sun4i_backend_update_yuv_buffer(struct sun4i_backend *backend,
342 struct drm_framebuffer *fb,
343 dma_addr_t paddr)
344 {
345 /* TODO: Add support for the multi-planar YUV formats */
346 DRM_DEBUG_DRIVER("Setting packed YUV buffer address to %pad\n", &paddr);
347 regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVADD_REG(0), paddr);
348
349 DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8);
350 regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVLINEWIDTH_REG(0),
351 fb->pitches[0] * 8);
352
353 return 0;
354 }
355
sun4i_backend_update_layer_buffer(struct sun4i_backend * backend,int layer,struct drm_plane * plane)356 int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend,
357 int layer, struct drm_plane *plane)
358 {
359 struct drm_plane_state *state = plane->state;
360 struct drm_framebuffer *fb = state->fb;
361 u32 lo_paddr, hi_paddr;
362 dma_addr_t paddr;
363
364 /* Set the line width */
365 DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8);
366 regmap_write(backend->engine.regs,
367 SUN4I_BACKEND_LAYLINEWIDTH_REG(layer),
368 fb->pitches[0] * 8);
369
370 /* Get the start of the displayed memory */
371 paddr = drm_fb_cma_get_gem_addr(fb, state, 0);
372 DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr);
373
374 /*
375 * backend DMA accesses DRAM directly, bypassing the system
376 * bus. As such, the address range is different and the buffer
377 * address needs to be corrected.
378 */
379 paddr -= PHYS_OFFSET;
380
381 if (fb->format->is_yuv)
382 return sun4i_backend_update_yuv_buffer(backend, fb, paddr);
383
384 /* Write the 32 lower bits of the address (in bits) */
385 lo_paddr = paddr << 3;
386 DRM_DEBUG_DRIVER("Setting address lower bits to 0x%x\n", lo_paddr);
387 regmap_write(backend->engine.regs,
388 SUN4I_BACKEND_LAYFB_L32ADD_REG(layer),
389 lo_paddr);
390
391 /* And the upper bits */
392 hi_paddr = paddr >> 29;
393 DRM_DEBUG_DRIVER("Setting address high bits to 0x%x\n", hi_paddr);
394 regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_LAYFB_H4ADD_REG,
395 SUN4I_BACKEND_LAYFB_H4ADD_MSK(layer),
396 SUN4I_BACKEND_LAYFB_H4ADD(layer, hi_paddr));
397
398 return 0;
399 }
400
sun4i_backend_update_layer_zpos(struct sun4i_backend * backend,int layer,struct drm_plane * plane)401 int sun4i_backend_update_layer_zpos(struct sun4i_backend *backend, int layer,
402 struct drm_plane *plane)
403 {
404 struct drm_plane_state *state = plane->state;
405 struct sun4i_layer_state *p_state = state_to_sun4i_layer_state(state);
406 unsigned int priority = state->normalized_zpos;
407 unsigned int pipe = p_state->pipe;
408
409 DRM_DEBUG_DRIVER("Setting layer %d's priority to %d and pipe %d\n",
410 layer, priority, pipe);
411 regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
412 SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL_MASK |
413 SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL_MASK,
414 SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL(p_state->pipe) |
415 SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL(priority));
416
417 return 0;
418 }
419
sun4i_backend_plane_uses_scaler(struct drm_plane_state * state)420 static bool sun4i_backend_plane_uses_scaler(struct drm_plane_state *state)
421 {
422 u16 src_h = state->src_h >> 16;
423 u16 src_w = state->src_w >> 16;
424
425 DRM_DEBUG_DRIVER("Input size %dx%d, output size %dx%d\n",
426 src_w, src_h, state->crtc_w, state->crtc_h);
427
428 if ((state->crtc_h != src_h) || (state->crtc_w != src_w))
429 return true;
430
431 return false;
432 }
433
sun4i_backend_plane_uses_frontend(struct drm_plane_state * state)434 static bool sun4i_backend_plane_uses_frontend(struct drm_plane_state *state)
435 {
436 struct sun4i_layer *layer = plane_to_sun4i_layer(state->plane);
437 struct sun4i_backend *backend = layer->backend;
438
439 if (IS_ERR(backend->frontend))
440 return false;
441
442 return sun4i_backend_plane_uses_scaler(state);
443 }
444
sun4i_backend_atomic_begin(struct sunxi_engine * engine,struct drm_crtc_state * old_state)445 static void sun4i_backend_atomic_begin(struct sunxi_engine *engine,
446 struct drm_crtc_state *old_state)
447 {
448 u32 val;
449
450 WARN_ON(regmap_read_poll_timeout(engine->regs,
451 SUN4I_BACKEND_REGBUFFCTL_REG,
452 val, !(val & SUN4I_BACKEND_REGBUFFCTL_LOADCTL),
453 100, 50000));
454 }
455
sun4i_backend_atomic_check(struct sunxi_engine * engine,struct drm_crtc_state * crtc_state)456 static int sun4i_backend_atomic_check(struct sunxi_engine *engine,
457 struct drm_crtc_state *crtc_state)
458 {
459 struct drm_plane_state *plane_states[SUN4I_BACKEND_NUM_LAYERS] = { 0 };
460 struct drm_atomic_state *state = crtc_state->state;
461 struct drm_device *drm = state->dev;
462 struct drm_plane *plane;
463 unsigned int num_planes = 0;
464 unsigned int num_alpha_planes = 0;
465 unsigned int num_frontend_planes = 0;
466 unsigned int num_yuv_planes = 0;
467 unsigned int current_pipe = 0;
468 unsigned int i;
469
470 DRM_DEBUG_DRIVER("Starting checking our planes\n");
471
472 if (!crtc_state->planes_changed)
473 return 0;
474
475 drm_for_each_plane_mask(plane, drm, crtc_state->plane_mask) {
476 struct drm_plane_state *plane_state =
477 drm_atomic_get_plane_state(state, plane);
478 struct sun4i_layer_state *layer_state =
479 state_to_sun4i_layer_state(plane_state);
480 struct drm_framebuffer *fb = plane_state->fb;
481 struct drm_format_name_buf format_name;
482
483 if (sun4i_backend_plane_uses_frontend(plane_state)) {
484 DRM_DEBUG_DRIVER("Using the frontend for plane %d\n",
485 plane->index);
486
487 layer_state->uses_frontend = true;
488 num_frontend_planes++;
489 } else {
490 layer_state->uses_frontend = false;
491 }
492
493 DRM_DEBUG_DRIVER("Plane FB format is %s\n",
494 drm_get_format_name(fb->format->format,
495 &format_name));
496 if (fb->format->has_alpha || (plane_state->alpha != DRM_BLEND_ALPHA_OPAQUE))
497 num_alpha_planes++;
498
499 if (fb->format->is_yuv) {
500 DRM_DEBUG_DRIVER("Plane FB format is YUV\n");
501 num_yuv_planes++;
502 }
503
504 DRM_DEBUG_DRIVER("Plane zpos is %d\n",
505 plane_state->normalized_zpos);
506
507 /* Sort our planes by Zpos */
508 plane_states[plane_state->normalized_zpos] = plane_state;
509
510 num_planes++;
511 }
512
513 /* All our planes were disabled, bail out */
514 if (!num_planes)
515 return 0;
516
517 /*
518 * The hardware is a bit unusual here.
519 *
520 * Even though it supports 4 layers, it does the composition
521 * in two separate steps.
522 *
523 * The first one is assigning a layer to one of its two
524 * pipes. If more that 1 layer is assigned to the same pipe,
525 * and if pixels overlaps, the pipe will take the pixel from
526 * the layer with the highest priority.
527 *
528 * The second step is the actual alpha blending, that takes
529 * the two pipes as input, and uses the eventual alpha
530 * component to do the transparency between the two.
531 *
532 * This two steps scenario makes us unable to guarantee a
533 * robust alpha blending between the 4 layers in all
534 * situations, since this means that we need to have one layer
535 * with alpha at the lowest position of our two pipes.
536 *
537 * However, we cannot even do that, since the hardware has a
538 * bug where the lowest plane of the lowest pipe (pipe 0,
539 * priority 0), if it has any alpha, will discard the pixel
540 * entirely and just display the pixels in the background
541 * color (black by default).
542 *
543 * This means that we effectively have only three valid
544 * configurations with alpha, all of them with the alpha being
545 * on pipe1 with the lowest position, which can be 1, 2 or 3
546 * depending on the number of planes and their zpos.
547 */
548 if (num_alpha_planes > SUN4I_BACKEND_NUM_ALPHA_LAYERS) {
549 DRM_DEBUG_DRIVER("Too many planes with alpha, rejecting...\n");
550 return -EINVAL;
551 }
552
553 /* We can't have an alpha plane at the lowest position */
554 if (plane_states[0]->fb->format->has_alpha ||
555 (plane_states[0]->alpha != DRM_BLEND_ALPHA_OPAQUE))
556 return -EINVAL;
557
558 for (i = 1; i < num_planes; i++) {
559 struct drm_plane_state *p_state = plane_states[i];
560 struct drm_framebuffer *fb = p_state->fb;
561 struct sun4i_layer_state *s_state = state_to_sun4i_layer_state(p_state);
562
563 /*
564 * The only alpha position is the lowest plane of the
565 * second pipe.
566 */
567 if (fb->format->has_alpha || (p_state->alpha != DRM_BLEND_ALPHA_OPAQUE))
568 current_pipe++;
569
570 s_state->pipe = current_pipe;
571 }
572
573 /* We can only have a single YUV plane at a time */
574 if (num_yuv_planes > SUN4I_BACKEND_NUM_YUV_PLANES) {
575 DRM_DEBUG_DRIVER("Too many planes with YUV, rejecting...\n");
576 return -EINVAL;
577 }
578
579 if (num_frontend_planes > SUN4I_BACKEND_NUM_FRONTEND_LAYERS) {
580 DRM_DEBUG_DRIVER("Too many planes going through the frontend, rejecting\n");
581 return -EINVAL;
582 }
583
584 DRM_DEBUG_DRIVER("State valid with %u planes, %u alpha, %u video, %u YUV\n",
585 num_planes, num_alpha_planes, num_frontend_planes,
586 num_yuv_planes);
587
588 return 0;
589 }
590
sun4i_backend_vblank_quirk(struct sunxi_engine * engine)591 static void sun4i_backend_vblank_quirk(struct sunxi_engine *engine)
592 {
593 struct sun4i_backend *backend = engine_to_sun4i_backend(engine);
594 struct sun4i_frontend *frontend = backend->frontend;
595
596 if (!frontend)
597 return;
598
599 /*
600 * In a teardown scenario with the frontend involved, we have
601 * to keep the frontend enabled until the next vblank, and
602 * only then disable it.
603 *
604 * This is due to the fact that the backend will not take into
605 * account the new configuration (with the plane that used to
606 * be fed by the frontend now disabled) until we write to the
607 * commit bit and the hardware fetches the new configuration
608 * during the next vblank.
609 *
610 * So we keep the frontend around in order to prevent any
611 * visual artifacts.
612 */
613 spin_lock(&backend->frontend_lock);
614 if (backend->frontend_teardown) {
615 sun4i_frontend_exit(frontend);
616 backend->frontend_teardown = false;
617 }
618 spin_unlock(&backend->frontend_lock);
619 };
620
sun4i_backend_init_sat(struct device * dev)621 static int sun4i_backend_init_sat(struct device *dev) {
622 struct sun4i_backend *backend = dev_get_drvdata(dev);
623 int ret;
624
625 backend->sat_reset = devm_reset_control_get(dev, "sat");
626 if (IS_ERR(backend->sat_reset)) {
627 dev_err(dev, "Couldn't get the SAT reset line\n");
628 return PTR_ERR(backend->sat_reset);
629 }
630
631 ret = reset_control_deassert(backend->sat_reset);
632 if (ret) {
633 dev_err(dev, "Couldn't deassert the SAT reset line\n");
634 return ret;
635 }
636
637 backend->sat_clk = devm_clk_get(dev, "sat");
638 if (IS_ERR(backend->sat_clk)) {
639 dev_err(dev, "Couldn't get our SAT clock\n");
640 ret = PTR_ERR(backend->sat_clk);
641 goto err_assert_reset;
642 }
643
644 ret = clk_prepare_enable(backend->sat_clk);
645 if (ret) {
646 dev_err(dev, "Couldn't enable the SAT clock\n");
647 return ret;
648 }
649
650 return 0;
651
652 err_assert_reset:
653 reset_control_assert(backend->sat_reset);
654 return ret;
655 }
656
sun4i_backend_free_sat(struct device * dev)657 static int sun4i_backend_free_sat(struct device *dev) {
658 struct sun4i_backend *backend = dev_get_drvdata(dev);
659
660 clk_disable_unprepare(backend->sat_clk);
661 reset_control_assert(backend->sat_reset);
662
663 return 0;
664 }
665
666 /*
667 * The display backend can take video output from the display frontend, or
668 * the display enhancement unit on the A80, as input for one it its layers.
669 * This relationship within the display pipeline is encoded in the device
670 * tree with of_graph, and we use it here to figure out which backend, if
671 * there are 2 or more, we are currently probing. The number would be in
672 * the "reg" property of the upstream output port endpoint.
673 */
sun4i_backend_of_get_id(struct device_node * node)674 static int sun4i_backend_of_get_id(struct device_node *node)
675 {
676 struct device_node *port, *ep;
677 int ret = -EINVAL;
678
679 /* input is port 0 */
680 port = of_graph_get_port_by_id(node, 0);
681 if (!port)
682 return -EINVAL;
683
684 /* try finding an upstream endpoint */
685 for_each_available_child_of_node(port, ep) {
686 struct device_node *remote;
687 u32 reg;
688
689 remote = of_graph_get_remote_endpoint(ep);
690 if (!remote)
691 continue;
692
693 ret = of_property_read_u32(remote, "reg", ®);
694 if (ret)
695 continue;
696
697 ret = reg;
698 }
699
700 of_node_put(port);
701
702 return ret;
703 }
704
705 /* TODO: This needs to take multiple pipelines into account */
sun4i_backend_find_frontend(struct sun4i_drv * drv,struct device_node * node)706 static struct sun4i_frontend *sun4i_backend_find_frontend(struct sun4i_drv *drv,
707 struct device_node *node)
708 {
709 struct device_node *port, *ep, *remote;
710 struct sun4i_frontend *frontend;
711
712 port = of_graph_get_port_by_id(node, 0);
713 if (!port)
714 return ERR_PTR(-EINVAL);
715
716 for_each_available_child_of_node(port, ep) {
717 remote = of_graph_get_remote_port_parent(ep);
718 if (!remote)
719 continue;
720
721 /* does this node match any registered engines? */
722 list_for_each_entry(frontend, &drv->frontend_list, list) {
723 if (remote == frontend->node) {
724 of_node_put(remote);
725 of_node_put(port);
726 return frontend;
727 }
728 }
729 }
730
731 return ERR_PTR(-EINVAL);
732 }
733
734 static const struct sunxi_engine_ops sun4i_backend_engine_ops = {
735 .atomic_begin = sun4i_backend_atomic_begin,
736 .atomic_check = sun4i_backend_atomic_check,
737 .commit = sun4i_backend_commit,
738 .layers_init = sun4i_layers_init,
739 .apply_color_correction = sun4i_backend_apply_color_correction,
740 .disable_color_correction = sun4i_backend_disable_color_correction,
741 .vblank_quirk = sun4i_backend_vblank_quirk,
742 };
743
744 static struct regmap_config sun4i_backend_regmap_config = {
745 .reg_bits = 32,
746 .val_bits = 32,
747 .reg_stride = 4,
748 .max_register = 0x5800,
749 };
750
sun4i_backend_bind(struct device * dev,struct device * master,void * data)751 static int sun4i_backend_bind(struct device *dev, struct device *master,
752 void *data)
753 {
754 struct platform_device *pdev = to_platform_device(dev);
755 struct drm_device *drm = data;
756 struct sun4i_drv *drv = drm->dev_private;
757 struct sun4i_backend *backend;
758 const struct sun4i_backend_quirks *quirks;
759 struct resource *res;
760 void __iomem *regs;
761 int i, ret;
762
763 backend = devm_kzalloc(dev, sizeof(*backend), GFP_KERNEL);
764 if (!backend)
765 return -ENOMEM;
766 dev_set_drvdata(dev, backend);
767 spin_lock_init(&backend->frontend_lock);
768
769 backend->engine.node = dev->of_node;
770 backend->engine.ops = &sun4i_backend_engine_ops;
771 backend->engine.id = sun4i_backend_of_get_id(dev->of_node);
772 if (backend->engine.id < 0)
773 return backend->engine.id;
774
775 backend->frontend = sun4i_backend_find_frontend(drv, dev->of_node);
776 if (IS_ERR(backend->frontend))
777 dev_warn(dev, "Couldn't find matching frontend, frontend features disabled\n");
778
779 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
780 regs = devm_ioremap_resource(dev, res);
781 if (IS_ERR(regs))
782 return PTR_ERR(regs);
783
784 backend->reset = devm_reset_control_get(dev, NULL);
785 if (IS_ERR(backend->reset)) {
786 dev_err(dev, "Couldn't get our reset line\n");
787 return PTR_ERR(backend->reset);
788 }
789
790 ret = reset_control_deassert(backend->reset);
791 if (ret) {
792 dev_err(dev, "Couldn't deassert our reset line\n");
793 return ret;
794 }
795
796 backend->bus_clk = devm_clk_get(dev, "ahb");
797 if (IS_ERR(backend->bus_clk)) {
798 dev_err(dev, "Couldn't get the backend bus clock\n");
799 ret = PTR_ERR(backend->bus_clk);
800 goto err_assert_reset;
801 }
802 clk_prepare_enable(backend->bus_clk);
803
804 backend->mod_clk = devm_clk_get(dev, "mod");
805 if (IS_ERR(backend->mod_clk)) {
806 dev_err(dev, "Couldn't get the backend module clock\n");
807 ret = PTR_ERR(backend->mod_clk);
808 goto err_disable_bus_clk;
809 }
810 clk_prepare_enable(backend->mod_clk);
811
812 backend->ram_clk = devm_clk_get(dev, "ram");
813 if (IS_ERR(backend->ram_clk)) {
814 dev_err(dev, "Couldn't get the backend RAM clock\n");
815 ret = PTR_ERR(backend->ram_clk);
816 goto err_disable_mod_clk;
817 }
818 clk_prepare_enable(backend->ram_clk);
819
820 if (of_device_is_compatible(dev->of_node,
821 "allwinner,sun8i-a33-display-backend")) {
822 ret = sun4i_backend_init_sat(dev);
823 if (ret) {
824 dev_err(dev, "Couldn't init SAT resources\n");
825 goto err_disable_ram_clk;
826 }
827 }
828
829 backend->engine.regs = devm_regmap_init_mmio(dev, regs,
830 &sun4i_backend_regmap_config);
831 if (IS_ERR(backend->engine.regs)) {
832 dev_err(dev, "Couldn't create the backend regmap\n");
833 return PTR_ERR(backend->engine.regs);
834 }
835
836 list_add_tail(&backend->engine.list, &drv->engine_list);
837
838 /*
839 * Many of the backend's layer configuration registers have
840 * undefined default values. This poses a risk as we use
841 * regmap_update_bits in some places, and don't overwrite
842 * the whole register.
843 *
844 * Clear the registers here to have something predictable.
845 */
846 for (i = 0x800; i < 0x1000; i += 4)
847 regmap_write(backend->engine.regs, i, 0);
848
849 /* Disable registers autoloading */
850 regmap_write(backend->engine.regs, SUN4I_BACKEND_REGBUFFCTL_REG,
851 SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS);
852
853 /* Enable the backend */
854 regmap_write(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
855 SUN4I_BACKEND_MODCTL_DEBE_EN |
856 SUN4I_BACKEND_MODCTL_START_CTL);
857
858 /* Set output selection if needed */
859 quirks = of_device_get_match_data(dev);
860 if (quirks->needs_output_muxing) {
861 /*
862 * We assume there is no dynamic muxing of backends
863 * and TCONs, so we select the backend with same ID.
864 *
865 * While dynamic selection might be interesting, since
866 * the CRTC is tied to the TCON, while the layers are
867 * tied to the backends, this means, we will need to
868 * switch between groups of layers. There might not be
869 * a way to represent this constraint in DRM.
870 */
871 regmap_update_bits(backend->engine.regs,
872 SUN4I_BACKEND_MODCTL_REG,
873 SUN4I_BACKEND_MODCTL_OUT_SEL,
874 (backend->engine.id
875 ? SUN4I_BACKEND_MODCTL_OUT_LCD1
876 : SUN4I_BACKEND_MODCTL_OUT_LCD0));
877 }
878
879 return 0;
880
881 err_disable_ram_clk:
882 clk_disable_unprepare(backend->ram_clk);
883 err_disable_mod_clk:
884 clk_disable_unprepare(backend->mod_clk);
885 err_disable_bus_clk:
886 clk_disable_unprepare(backend->bus_clk);
887 err_assert_reset:
888 reset_control_assert(backend->reset);
889 return ret;
890 }
891
sun4i_backend_unbind(struct device * dev,struct device * master,void * data)892 static void sun4i_backend_unbind(struct device *dev, struct device *master,
893 void *data)
894 {
895 struct sun4i_backend *backend = dev_get_drvdata(dev);
896
897 list_del(&backend->engine.list);
898
899 if (of_device_is_compatible(dev->of_node,
900 "allwinner,sun8i-a33-display-backend"))
901 sun4i_backend_free_sat(dev);
902
903 clk_disable_unprepare(backend->ram_clk);
904 clk_disable_unprepare(backend->mod_clk);
905 clk_disable_unprepare(backend->bus_clk);
906 reset_control_assert(backend->reset);
907 }
908
909 static const struct component_ops sun4i_backend_ops = {
910 .bind = sun4i_backend_bind,
911 .unbind = sun4i_backend_unbind,
912 };
913
sun4i_backend_probe(struct platform_device * pdev)914 static int sun4i_backend_probe(struct platform_device *pdev)
915 {
916 return component_add(&pdev->dev, &sun4i_backend_ops);
917 }
918
sun4i_backend_remove(struct platform_device * pdev)919 static int sun4i_backend_remove(struct platform_device *pdev)
920 {
921 component_del(&pdev->dev, &sun4i_backend_ops);
922
923 return 0;
924 }
925
926 static const struct sun4i_backend_quirks sun4i_backend_quirks = {
927 .needs_output_muxing = true,
928 };
929
930 static const struct sun4i_backend_quirks sun5i_backend_quirks = {
931 };
932
933 static const struct sun4i_backend_quirks sun6i_backend_quirks = {
934 };
935
936 static const struct sun4i_backend_quirks sun7i_backend_quirks = {
937 .needs_output_muxing = true,
938 };
939
940 static const struct sun4i_backend_quirks sun8i_a33_backend_quirks = {
941 };
942
943 static const struct sun4i_backend_quirks sun9i_backend_quirks = {
944 };
945
946 static const struct of_device_id sun4i_backend_of_table[] = {
947 {
948 .compatible = "allwinner,sun4i-a10-display-backend",
949 .data = &sun4i_backend_quirks,
950 },
951 {
952 .compatible = "allwinner,sun5i-a13-display-backend",
953 .data = &sun5i_backend_quirks,
954 },
955 {
956 .compatible = "allwinner,sun6i-a31-display-backend",
957 .data = &sun6i_backend_quirks,
958 },
959 {
960 .compatible = "allwinner,sun7i-a20-display-backend",
961 .data = &sun7i_backend_quirks,
962 },
963 {
964 .compatible = "allwinner,sun8i-a33-display-backend",
965 .data = &sun8i_a33_backend_quirks,
966 },
967 {
968 .compatible = "allwinner,sun9i-a80-display-backend",
969 .data = &sun9i_backend_quirks,
970 },
971 { }
972 };
973 MODULE_DEVICE_TABLE(of, sun4i_backend_of_table);
974
975 static struct platform_driver sun4i_backend_platform_driver = {
976 .probe = sun4i_backend_probe,
977 .remove = sun4i_backend_remove,
978 .driver = {
979 .name = "sun4i-backend",
980 .of_match_table = sun4i_backend_of_table,
981 },
982 };
983 module_platform_driver(sun4i_backend_platform_driver);
984
985 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
986 MODULE_DESCRIPTION("Allwinner A10 Display Backend Driver");
987 MODULE_LICENSE("GPL");
988
