1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Sun3 SCSI stuff by Erik Verbruggen (erik@bigmama.xtdnet.nl)
4 *
5 * Sun3 DMA routines added by Sam Creasey (sammy@sammy.net)
6 *
7 * VME support added by Sam Creasey
8 *
9 * TODO: modify this driver to support multiple Sun3 SCSI VME boards
10 *
11 * Adapted from mac_scsinew.c:
12 */
13 /*
14 * Generic Macintosh NCR5380 driver
15 *
16 * Copyright 1998, Michael Schmitz <mschmitz@lbl.gov>
17 *
18 * derived in part from:
19 */
20 /*
21 * Generic Generic NCR5380 driver
22 *
23 * Copyright 1995, Russell King
24 */
25
26 #include <linux/types.h>
27 #include <linux/delay.h>
28 #include <linux/module.h>
29 #include <linux/ioport.h>
30 #include <linux/init.h>
31 #include <linux/blkdev.h>
32 #include <linux/platform_device.h>
33
34 #include <asm/io.h>
35 #include <asm/dvma.h>
36
37 #include <scsi/scsi_host.h>
38
39 /* minimum number of bytes to do dma on */
40 #define DMA_MIN_SIZE 129
41
42 /* Definitions for the core NCR5380 driver. */
43
44 #define NCR5380_implementation_fields /* none */
45
46 #define NCR5380_read(reg) in_8(hostdata->io + (reg))
47 #define NCR5380_write(reg, value) out_8(hostdata->io + (reg), value)
48
49 #define NCR5380_queue_command sun3scsi_queue_command
50 #define NCR5380_host_reset sun3scsi_host_reset
51 #define NCR5380_abort sun3scsi_abort
52 #define NCR5380_info sun3scsi_info
53
54 #define NCR5380_dma_xfer_len sun3scsi_dma_xfer_len
55 #define NCR5380_dma_recv_setup sun3scsi_dma_count
56 #define NCR5380_dma_send_setup sun3scsi_dma_count
57 #define NCR5380_dma_residual sun3scsi_dma_residual
58
59 #include "NCR5380.h"
60
61 /* dma regs start at regbase + 8, directly after the NCR regs */
62 struct sun3_dma_regs {
63 unsigned short dma_addr_hi; /* vme only */
64 unsigned short dma_addr_lo; /* vme only */
65 unsigned short dma_count_hi; /* vme only */
66 unsigned short dma_count_lo; /* vme only */
67 unsigned short udc_data; /* udc dma data reg (obio only) */
68 unsigned short udc_addr; /* uda dma addr reg (obio only) */
69 unsigned short fifo_data; /* fifo data reg,
70 * holds extra byte on odd dma reads
71 */
72 unsigned short fifo_count;
73 unsigned short csr; /* control/status reg */
74 unsigned short bpack_hi; /* vme only */
75 unsigned short bpack_lo; /* vme only */
76 unsigned short ivect; /* vme only */
77 unsigned short fifo_count_hi; /* vme only */
78 };
79
80 /* ucd chip specific regs - live in dvma space */
81 struct sun3_udc_regs {
82 unsigned short rsel; /* select regs to load */
83 unsigned short addr_hi; /* high word of addr */
84 unsigned short addr_lo; /* low word */
85 unsigned short count; /* words to be xfer'd */
86 unsigned short mode_hi; /* high word of channel mode */
87 unsigned short mode_lo; /* low word of channel mode */
88 };
89
90 /* addresses of the udc registers */
91 #define UDC_MODE 0x38
92 #define UDC_CSR 0x2e /* command/status */
93 #define UDC_CHN_HI 0x26 /* chain high word */
94 #define UDC_CHN_LO 0x22 /* chain lo word */
95 #define UDC_CURA_HI 0x1a /* cur reg A high */
96 #define UDC_CURA_LO 0x0a /* cur reg A low */
97 #define UDC_CURB_HI 0x12 /* cur reg B high */
98 #define UDC_CURB_LO 0x02 /* cur reg B low */
99 #define UDC_MODE_HI 0x56 /* mode reg high */
100 #define UDC_MODE_LO 0x52 /* mode reg low */
101 #define UDC_COUNT 0x32 /* words to xfer */
102
103 /* some udc commands */
104 #define UDC_RESET 0
105 #define UDC_CHN_START 0xa0 /* start chain */
106 #define UDC_INT_ENABLE 0x32 /* channel 1 int on */
107
108 /* udc mode words */
109 #define UDC_MODE_HIWORD 0x40
110 #define UDC_MODE_LSEND 0xc2
111 #define UDC_MODE_LRECV 0xd2
112
113 /* udc reg selections */
114 #define UDC_RSEL_SEND 0x282
115 #define UDC_RSEL_RECV 0x182
116
117 /* bits in csr reg */
118 #define CSR_DMA_ACTIVE 0x8000
119 #define CSR_DMA_CONFLICT 0x4000
120 #define CSR_DMA_BUSERR 0x2000
121
122 #define CSR_FIFO_EMPTY 0x400 /* fifo flushed? */
123 #define CSR_SDB_INT 0x200 /* sbc interrupt pending */
124 #define CSR_DMA_INT 0x100 /* dma interrupt pending */
125
126 #define CSR_LEFT 0xc0
127 #define CSR_LEFT_3 0xc0
128 #define CSR_LEFT_2 0x80
129 #define CSR_LEFT_1 0x40
130 #define CSR_PACK_ENABLE 0x20
131
132 #define CSR_DMA_ENABLE 0x10
133
134 #define CSR_SEND 0x8 /* 1 = send 0 = recv */
135 #define CSR_FIFO 0x2 /* reset fifo */
136 #define CSR_INTR 0x4 /* interrupt enable */
137 #define CSR_SCSI 0x1
138
139 #define VME_DATA24 0x3d00
140
141 extern int sun3_map_test(unsigned long, char *);
142
143 static int setup_can_queue = -1;
144 module_param(setup_can_queue, int, 0);
145 static int setup_cmd_per_lun = -1;
146 module_param(setup_cmd_per_lun, int, 0);
147 static int setup_sg_tablesize = -1;
148 module_param(setup_sg_tablesize, int, 0);
149 static int setup_hostid = -1;
150 module_param(setup_hostid, int, 0);
151
152 /* ms to wait after hitting dma regs */
153 #define SUN3_DMA_DELAY 10
154
155 /* dvma buffer to allocate -- 32k should hopefully be more than sufficient */
156 #define SUN3_DVMA_BUFSIZE 0xe000
157
158 static struct scsi_cmnd *sun3_dma_setup_done;
159 static volatile struct sun3_dma_regs *dregs;
160 static struct sun3_udc_regs *udc_regs;
161 static unsigned char *sun3_dma_orig_addr;
162 static unsigned long sun3_dma_orig_count;
163 static int sun3_dma_active;
164 static unsigned long last_residual;
165
166 #ifndef SUN3_SCSI_VME
167 /* dma controller register access functions */
168
sun3_udc_read(unsigned char reg)169 static inline unsigned short sun3_udc_read(unsigned char reg)
170 {
171 unsigned short ret;
172
173 dregs->udc_addr = UDC_CSR;
174 udelay(SUN3_DMA_DELAY);
175 ret = dregs->udc_data;
176 udelay(SUN3_DMA_DELAY);
177
178 return ret;
179 }
180
sun3_udc_write(unsigned short val,unsigned char reg)181 static inline void sun3_udc_write(unsigned short val, unsigned char reg)
182 {
183 dregs->udc_addr = reg;
184 udelay(SUN3_DMA_DELAY);
185 dregs->udc_data = val;
186 udelay(SUN3_DMA_DELAY);
187 }
188 #endif
189
190 // safe bits for the CSR
191 #define CSR_GOOD 0x060f
192
scsi_sun3_intr(int irq,void * dev)193 static irqreturn_t scsi_sun3_intr(int irq, void *dev)
194 {
195 struct Scsi_Host *instance = dev;
196 unsigned short csr = dregs->csr;
197 int handled = 0;
198
199 #ifdef SUN3_SCSI_VME
200 dregs->csr &= ~CSR_DMA_ENABLE;
201 #endif
202
203 if(csr & ~CSR_GOOD) {
204 if (csr & CSR_DMA_BUSERR)
205 shost_printk(KERN_ERR, instance, "bus error in DMA\n");
206 if (csr & CSR_DMA_CONFLICT)
207 shost_printk(KERN_ERR, instance, "DMA conflict\n");
208 handled = 1;
209 }
210
211 if(csr & (CSR_SDB_INT | CSR_DMA_INT)) {
212 NCR5380_intr(irq, dev);
213 handled = 1;
214 }
215
216 return IRQ_RETVAL(handled);
217 }
218
219 /* sun3scsi_dma_setup() -- initialize the dma controller for a read/write */
sun3scsi_dma_setup(struct NCR5380_hostdata * hostdata,unsigned char * data,int count,int write_flag)220 static int sun3scsi_dma_setup(struct NCR5380_hostdata *hostdata,
221 unsigned char *data, int count, int write_flag)
222 {
223 void *addr;
224
225 if(sun3_dma_orig_addr != NULL)
226 dvma_unmap(sun3_dma_orig_addr);
227
228 #ifdef SUN3_SCSI_VME
229 addr = (void *)dvma_map_vme((unsigned long) data, count);
230 #else
231 addr = (void *)dvma_map((unsigned long) data, count);
232 #endif
233
234 sun3_dma_orig_addr = addr;
235 sun3_dma_orig_count = count;
236
237 #ifndef SUN3_SCSI_VME
238 dregs->fifo_count = 0;
239 sun3_udc_write(UDC_RESET, UDC_CSR);
240
241 /* reset fifo */
242 dregs->csr &= ~CSR_FIFO;
243 dregs->csr |= CSR_FIFO;
244 #endif
245
246 /* set direction */
247 if(write_flag)
248 dregs->csr |= CSR_SEND;
249 else
250 dregs->csr &= ~CSR_SEND;
251
252 #ifdef SUN3_SCSI_VME
253 dregs->csr |= CSR_PACK_ENABLE;
254
255 dregs->dma_addr_hi = ((unsigned long)addr >> 16);
256 dregs->dma_addr_lo = ((unsigned long)addr & 0xffff);
257
258 dregs->dma_count_hi = 0;
259 dregs->dma_count_lo = 0;
260 dregs->fifo_count_hi = 0;
261 dregs->fifo_count = 0;
262 #else
263 /* byte count for fifo */
264 dregs->fifo_count = count;
265
266 sun3_udc_write(UDC_RESET, UDC_CSR);
267
268 /* reset fifo */
269 dregs->csr &= ~CSR_FIFO;
270 dregs->csr |= CSR_FIFO;
271
272 if(dregs->fifo_count != count) {
273 shost_printk(KERN_ERR, hostdata->host,
274 "FIFO mismatch %04x not %04x\n",
275 dregs->fifo_count, (unsigned int) count);
276 NCR5380_dprint(NDEBUG_DMA, hostdata->host);
277 }
278
279 /* setup udc */
280 udc_regs->addr_hi = (((unsigned long)(addr) & 0xff0000) >> 8);
281 udc_regs->addr_lo = ((unsigned long)(addr) & 0xffff);
282 udc_regs->count = count/2; /* count in words */
283 udc_regs->mode_hi = UDC_MODE_HIWORD;
284 if(write_flag) {
285 if(count & 1)
286 udc_regs->count++;
287 udc_regs->mode_lo = UDC_MODE_LSEND;
288 udc_regs->rsel = UDC_RSEL_SEND;
289 } else {
290 udc_regs->mode_lo = UDC_MODE_LRECV;
291 udc_regs->rsel = UDC_RSEL_RECV;
292 }
293
294 /* announce location of regs block */
295 sun3_udc_write(((dvma_vtob(udc_regs) & 0xff0000) >> 8),
296 UDC_CHN_HI);
297
298 sun3_udc_write((dvma_vtob(udc_regs) & 0xffff), UDC_CHN_LO);
299
300 /* set dma master on */
301 sun3_udc_write(0xd, UDC_MODE);
302
303 /* interrupt enable */
304 sun3_udc_write(UDC_INT_ENABLE, UDC_CSR);
305 #endif
306
307 return count;
308
309 }
310
sun3scsi_dma_count(struct NCR5380_hostdata * hostdata,unsigned char * data,int count)311 static int sun3scsi_dma_count(struct NCR5380_hostdata *hostdata,
312 unsigned char *data, int count)
313 {
314 return count;
315 }
316
sun3scsi_dma_recv_setup(struct NCR5380_hostdata * hostdata,unsigned char * data,int count)317 static inline int sun3scsi_dma_recv_setup(struct NCR5380_hostdata *hostdata,
318 unsigned char *data, int count)
319 {
320 return sun3scsi_dma_setup(hostdata, data, count, 0);
321 }
322
sun3scsi_dma_send_setup(struct NCR5380_hostdata * hostdata,unsigned char * data,int count)323 static inline int sun3scsi_dma_send_setup(struct NCR5380_hostdata *hostdata,
324 unsigned char *data, int count)
325 {
326 return sun3scsi_dma_setup(hostdata, data, count, 1);
327 }
328
sun3scsi_dma_residual(struct NCR5380_hostdata * hostdata)329 static int sun3scsi_dma_residual(struct NCR5380_hostdata *hostdata)
330 {
331 return last_residual;
332 }
333
sun3scsi_dma_xfer_len(struct NCR5380_hostdata * hostdata,struct scsi_cmnd * cmd)334 static int sun3scsi_dma_xfer_len(struct NCR5380_hostdata *hostdata,
335 struct scsi_cmnd *cmd)
336 {
337 int wanted_len = cmd->SCp.this_residual;
338
339 if (wanted_len < DMA_MIN_SIZE || blk_rq_is_passthrough(cmd->request))
340 return 0;
341
342 return wanted_len;
343 }
344
sun3scsi_dma_start(unsigned long count,unsigned char * data)345 static inline int sun3scsi_dma_start(unsigned long count, unsigned char *data)
346 {
347 #ifdef SUN3_SCSI_VME
348 unsigned short csr;
349
350 csr = dregs->csr;
351
352 dregs->dma_count_hi = (sun3_dma_orig_count >> 16);
353 dregs->dma_count_lo = (sun3_dma_orig_count & 0xffff);
354
355 dregs->fifo_count_hi = (sun3_dma_orig_count >> 16);
356 dregs->fifo_count = (sun3_dma_orig_count & 0xffff);
357
358 /* if(!(csr & CSR_DMA_ENABLE))
359 * dregs->csr |= CSR_DMA_ENABLE;
360 */
361 #else
362 sun3_udc_write(UDC_CHN_START, UDC_CSR);
363 #endif
364
365 return 0;
366 }
367
368 /* clean up after our dma is done */
sun3scsi_dma_finish(int write_flag)369 static int sun3scsi_dma_finish(int write_flag)
370 {
371 unsigned short __maybe_unused count;
372 unsigned short fifo;
373 int ret = 0;
374
375 sun3_dma_active = 0;
376
377 #ifdef SUN3_SCSI_VME
378 dregs->csr &= ~CSR_DMA_ENABLE;
379
380 fifo = dregs->fifo_count;
381 if (write_flag) {
382 if ((fifo > 0) && (fifo < sun3_dma_orig_count))
383 fifo++;
384 }
385
386 last_residual = fifo;
387 /* empty bytes from the fifo which didn't make it */
388 if ((!write_flag) && (dregs->csr & CSR_LEFT)) {
389 unsigned char *vaddr;
390
391 vaddr = (unsigned char *)dvma_vmetov(sun3_dma_orig_addr);
392
393 vaddr += (sun3_dma_orig_count - fifo);
394 vaddr--;
395
396 switch (dregs->csr & CSR_LEFT) {
397 case CSR_LEFT_3:
398 *vaddr = (dregs->bpack_lo & 0xff00) >> 8;
399 vaddr--;
400 fallthrough;
401
402 case CSR_LEFT_2:
403 *vaddr = (dregs->bpack_hi & 0x00ff);
404 vaddr--;
405 fallthrough;
406
407 case CSR_LEFT_1:
408 *vaddr = (dregs->bpack_hi & 0xff00) >> 8;
409 break;
410 }
411 }
412 #else
413 // check to empty the fifo on a read
414 if(!write_flag) {
415 int tmo = 20000; /* .2 sec */
416
417 while(1) {
418 if(dregs->csr & CSR_FIFO_EMPTY)
419 break;
420
421 if(--tmo <= 0) {
422 printk("sun3scsi: fifo failed to empty!\n");
423 return 1;
424 }
425 udelay(10);
426 }
427 }
428
429 dregs->udc_addr = 0x32;
430 udelay(SUN3_DMA_DELAY);
431 count = 2 * dregs->udc_data;
432 udelay(SUN3_DMA_DELAY);
433
434 fifo = dregs->fifo_count;
435 last_residual = fifo;
436
437 /* empty bytes from the fifo which didn't make it */
438 if((!write_flag) && (count - fifo) == 2) {
439 unsigned short data;
440 unsigned char *vaddr;
441
442 data = dregs->fifo_data;
443 vaddr = (unsigned char *)dvma_btov(sun3_dma_orig_addr);
444
445 vaddr += (sun3_dma_orig_count - fifo);
446
447 vaddr[-2] = (data & 0xff00) >> 8;
448 vaddr[-1] = (data & 0xff);
449 }
450 #endif
451
452 dvma_unmap(sun3_dma_orig_addr);
453 sun3_dma_orig_addr = NULL;
454
455 #ifdef SUN3_SCSI_VME
456 dregs->dma_addr_hi = 0;
457 dregs->dma_addr_lo = 0;
458 dregs->dma_count_hi = 0;
459 dregs->dma_count_lo = 0;
460
461 dregs->fifo_count = 0;
462 dregs->fifo_count_hi = 0;
463
464 dregs->csr &= ~CSR_SEND;
465 /* dregs->csr |= CSR_DMA_ENABLE; */
466 #else
467 sun3_udc_write(UDC_RESET, UDC_CSR);
468 dregs->fifo_count = 0;
469 dregs->csr &= ~CSR_SEND;
470
471 /* reset fifo */
472 dregs->csr &= ~CSR_FIFO;
473 dregs->csr |= CSR_FIFO;
474 #endif
475
476 sun3_dma_setup_done = NULL;
477
478 return ret;
479
480 }
481
482 #include "NCR5380.c"
483
484 #ifdef SUN3_SCSI_VME
485 #define SUN3_SCSI_NAME "Sun3 NCR5380 VME SCSI"
486 #define DRV_MODULE_NAME "sun3_scsi_vme"
487 #else
488 #define SUN3_SCSI_NAME "Sun3 NCR5380 SCSI"
489 #define DRV_MODULE_NAME "sun3_scsi"
490 #endif
491
492 #define PFX DRV_MODULE_NAME ": "
493
494 static struct scsi_host_template sun3_scsi_template = {
495 .module = THIS_MODULE,
496 .proc_name = DRV_MODULE_NAME,
497 .name = SUN3_SCSI_NAME,
498 .info = sun3scsi_info,
499 .queuecommand = sun3scsi_queue_command,
500 .eh_abort_handler = sun3scsi_abort,
501 .eh_host_reset_handler = sun3scsi_host_reset,
502 .can_queue = 16,
503 .this_id = 7,
504 .sg_tablesize = 1,
505 .cmd_per_lun = 2,
506 .dma_boundary = PAGE_SIZE - 1,
507 .cmd_size = NCR5380_CMD_SIZE,
508 };
509
sun3_scsi_probe(struct platform_device * pdev)510 static int __init sun3_scsi_probe(struct platform_device *pdev)
511 {
512 struct Scsi_Host *instance;
513 struct NCR5380_hostdata *hostdata;
514 int error;
515 struct resource *irq, *mem;
516 void __iomem *ioaddr;
517 int host_flags = 0;
518 #ifdef SUN3_SCSI_VME
519 int i;
520 #endif
521
522 if (setup_can_queue > 0)
523 sun3_scsi_template.can_queue = setup_can_queue;
524 if (setup_cmd_per_lun > 0)
525 sun3_scsi_template.cmd_per_lun = setup_cmd_per_lun;
526 if (setup_sg_tablesize > 0)
527 sun3_scsi_template.sg_tablesize = setup_sg_tablesize;
528 if (setup_hostid >= 0)
529 sun3_scsi_template.this_id = setup_hostid & 7;
530
531 #ifdef SUN3_SCSI_VME
532 ioaddr = NULL;
533 for (i = 0; i < 2; i++) {
534 unsigned char x;
535
536 irq = platform_get_resource(pdev, IORESOURCE_IRQ, i);
537 mem = platform_get_resource(pdev, IORESOURCE_MEM, i);
538 if (!irq || !mem)
539 break;
540
541 ioaddr = sun3_ioremap(mem->start, resource_size(mem),
542 SUN3_PAGE_TYPE_VME16);
543 dregs = (struct sun3_dma_regs *)(ioaddr + 8);
544
545 if (sun3_map_test((unsigned long)dregs, &x)) {
546 unsigned short oldcsr;
547
548 oldcsr = dregs->csr;
549 dregs->csr = 0;
550 udelay(SUN3_DMA_DELAY);
551 if (dregs->csr == 0x1400)
552 break;
553
554 dregs->csr = oldcsr;
555 }
556
557 iounmap(ioaddr);
558 ioaddr = NULL;
559 }
560 if (!ioaddr)
561 return -ENODEV;
562 #else
563 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
564 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
565 if (!irq || !mem)
566 return -ENODEV;
567
568 ioaddr = ioremap(mem->start, resource_size(mem));
569 dregs = (struct sun3_dma_regs *)(ioaddr + 8);
570
571 udc_regs = dvma_malloc(sizeof(struct sun3_udc_regs));
572 if (!udc_regs) {
573 pr_err(PFX "couldn't allocate DVMA memory!\n");
574 iounmap(ioaddr);
575 return -ENOMEM;
576 }
577 #endif
578
579 instance = scsi_host_alloc(&sun3_scsi_template,
580 sizeof(struct NCR5380_hostdata));
581 if (!instance) {
582 error = -ENOMEM;
583 goto fail_alloc;
584 }
585
586 instance->irq = irq->start;
587
588 hostdata = shost_priv(instance);
589 hostdata->base = mem->start;
590 hostdata->io = ioaddr;
591
592 error = NCR5380_init(instance, host_flags);
593 if (error)
594 goto fail_init;
595
596 error = request_irq(instance->irq, scsi_sun3_intr, 0,
597 "NCR5380", instance);
598 if (error) {
599 pr_err(PFX "scsi%d: IRQ %d not free, bailing out\n",
600 instance->host_no, instance->irq);
601 goto fail_irq;
602 }
603
604 dregs->csr = 0;
605 udelay(SUN3_DMA_DELAY);
606 dregs->csr = CSR_SCSI | CSR_FIFO | CSR_INTR;
607 udelay(SUN3_DMA_DELAY);
608 dregs->fifo_count = 0;
609 #ifdef SUN3_SCSI_VME
610 dregs->fifo_count_hi = 0;
611 dregs->dma_addr_hi = 0;
612 dregs->dma_addr_lo = 0;
613 dregs->dma_count_hi = 0;
614 dregs->dma_count_lo = 0;
615
616 dregs->ivect = VME_DATA24 | (instance->irq & 0xff);
617 #endif
618
619 NCR5380_maybe_reset_bus(instance);
620
621 error = scsi_add_host(instance, NULL);
622 if (error)
623 goto fail_host;
624
625 platform_set_drvdata(pdev, instance);
626
627 scsi_scan_host(instance);
628 return 0;
629
630 fail_host:
631 free_irq(instance->irq, instance);
632 fail_irq:
633 NCR5380_exit(instance);
634 fail_init:
635 scsi_host_put(instance);
636 fail_alloc:
637 if (udc_regs)
638 dvma_free(udc_regs);
639 iounmap(ioaddr);
640 return error;
641 }
642
sun3_scsi_remove(struct platform_device * pdev)643 static int __exit sun3_scsi_remove(struct platform_device *pdev)
644 {
645 struct Scsi_Host *instance = platform_get_drvdata(pdev);
646 struct NCR5380_hostdata *hostdata = shost_priv(instance);
647 void __iomem *ioaddr = hostdata->io;
648
649 scsi_remove_host(instance);
650 free_irq(instance->irq, instance);
651 NCR5380_exit(instance);
652 scsi_host_put(instance);
653 if (udc_regs)
654 dvma_free(udc_regs);
655 iounmap(ioaddr);
656 return 0;
657 }
658
659 static struct platform_driver sun3_scsi_driver = {
660 .remove = __exit_p(sun3_scsi_remove),
661 .driver = {
662 .name = DRV_MODULE_NAME,
663 },
664 };
665
666 module_platform_driver_probe(sun3_scsi_driver, sun3_scsi_probe);
667
668 MODULE_ALIAS("platform:" DRV_MODULE_NAME);
669 MODULE_LICENSE("GPL");
670
