1 /* 2 * omap3isp.h 3 * 4 * TI OMAP3 ISP - Bus Configuration 5 * 6 * Copyright (C) 2011 Nokia Corporation 7 * 8 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com> 9 * Sakari Ailus <sakari.ailus@iki.fi> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 */ 20 21 #ifndef __OMAP3ISP_H__ 22 #define __OMAP3ISP_H__ 23 24 enum isp_interface_type { 25 ISP_INTERFACE_PARALLEL, 26 ISP_INTERFACE_CSI2A_PHY2, 27 ISP_INTERFACE_CCP2B_PHY1, 28 ISP_INTERFACE_CCP2B_PHY2, 29 ISP_INTERFACE_CSI2C_PHY1, 30 }; 31 32 /** 33 * struct isp_parallel_cfg - Parallel interface configuration 34 * @data_lane_shift: Data lane shifter 35 * 0 - CAMEXT[13:0] -> CAM[13:0] 36 * 2 - CAMEXT[13:2] -> CAM[11:0] 37 * 4 - CAMEXT[13:4] -> CAM[9:0] 38 * 6 - CAMEXT[13:6] -> CAM[7:0] 39 * @clk_pol: Pixel clock polarity 40 * 0 - Sample on rising edge, 1 - Sample on falling edge 41 * @hs_pol: Horizontal synchronization polarity 42 * 0 - Active high, 1 - Active low 43 * @vs_pol: Vertical synchronization polarity 44 * 0 - Active high, 1 - Active low 45 * @fld_pol: Field signal polarity 46 * 0 - Positive, 1 - Negative 47 * @data_pol: Data polarity 48 * 0 - Normal, 1 - One's complement 49 * @bt656: Data contain BT.656 embedded synchronization 50 */ 51 struct isp_parallel_cfg { 52 unsigned int data_lane_shift:3; 53 unsigned int clk_pol:1; 54 unsigned int hs_pol:1; 55 unsigned int vs_pol:1; 56 unsigned int fld_pol:1; 57 unsigned int data_pol:1; 58 unsigned int bt656:1; 59 }; 60 61 enum { 62 ISP_CCP2_PHY_DATA_CLOCK = 0, 63 ISP_CCP2_PHY_DATA_STROBE = 1, 64 }; 65 66 enum { 67 ISP_CCP2_MODE_MIPI = 0, 68 ISP_CCP2_MODE_CCP2 = 1, 69 }; 70 71 /** 72 * struct isp_csiphy_lane: CCP2/CSI2 lane position and polarity 73 * @pos: position of the lane 74 * @pol: polarity of the lane 75 */ 76 struct isp_csiphy_lane { 77 u8 pos; 78 u8 pol; 79 }; 80 81 #define ISP_CSIPHY1_NUM_DATA_LANES 1 82 #define ISP_CSIPHY2_NUM_DATA_LANES 2 83 84 /** 85 * struct isp_csiphy_lanes_cfg - CCP2/CSI2 lane configuration 86 * @data: Configuration of one or two data lanes 87 * @clk: Clock lane configuration 88 */ 89 struct isp_csiphy_lanes_cfg { 90 struct isp_csiphy_lane data[ISP_CSIPHY2_NUM_DATA_LANES]; 91 struct isp_csiphy_lane clk; 92 }; 93 94 /** 95 * struct isp_ccp2_cfg - CCP2 interface configuration 96 * @strobe_clk_pol: Strobe/clock polarity 97 * 0 - Non Inverted, 1 - Inverted 98 * @crc: Enable the cyclic redundancy check 99 * @ccp2_mode: Enable CCP2 compatibility mode 100 * ISP_CCP2_MODE_MIPI - MIPI-CSI1 mode 101 * ISP_CCP2_MODE_CCP2 - CCP2 mode 102 * @phy_layer: Physical layer selection 103 * ISP_CCP2_PHY_DATA_CLOCK - Data/clock physical layer 104 * ISP_CCP2_PHY_DATA_STROBE - Data/strobe physical layer 105 * @vpclk_div: Video port output clock control 106 */ 107 struct isp_ccp2_cfg { 108 unsigned int strobe_clk_pol:1; 109 unsigned int crc:1; 110 unsigned int ccp2_mode:1; 111 unsigned int phy_layer:1; 112 unsigned int vpclk_div:2; 113 unsigned int vp_clk_pol:1; 114 struct isp_csiphy_lanes_cfg lanecfg; 115 }; 116 117 /** 118 * struct isp_csi2_cfg - CSI2 interface configuration 119 * @crc: Enable the cyclic redundancy check 120 * @lanecfg: CSI-2 lane configuration 121 * @num_data_lanes: The number of data lanes in use 122 */ 123 struct isp_csi2_cfg { 124 unsigned crc:1; 125 struct isp_csiphy_lanes_cfg lanecfg; 126 u8 num_data_lanes; 127 }; 128 129 struct isp_bus_cfg { 130 enum isp_interface_type interface; 131 union { 132 struct isp_parallel_cfg parallel; 133 struct isp_ccp2_cfg ccp2; 134 struct isp_csi2_cfg csi2; 135 } bus; /* gcc < 4.6.0 chokes on anonymous union initializers */ 136 }; 137 138 #endif /* __OMAP3ISP_H__ */ 139
