1 /*
2 * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver
3 *
4 * Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
5 *
6 * Copyright 1999-2000 Jeff Garzik
7 *
8 * Contributors:
9 *
10 * Ani Joshi: Lots of debugging and cleanup work, really helped
11 * get the driver going
12 *
13 * Ferenc Bakonyi: Bug fixes, cleanup, modularization
14 *
15 * Jindrich Makovicka: Accel code help, hw cursor, mtrr
16 *
17 * Paul Richards: Bug fixes, updates
18 *
19 * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven
20 * Includes riva_hw.c from nVidia, see copyright below.
21 * KGI code provided the basis for state storage, init, and mode switching.
22 *
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive
25 * for more details.
26 *
27 * Known bugs and issues:
28 * restoring text mode fails
29 * doublescan modes are broken
30 */
31
32 #include <linux/aperture.h>
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/errno.h>
36 #include <linux/string.h>
37 #include <linux/mm.h>
38 #include <linux/slab.h>
39 #include <linux/delay.h>
40 #include <linux/fb.h>
41 #include <linux/init.h>
42 #include <linux/pci.h>
43 #include <linux/backlight.h>
44 #include <linux/bitrev.h>
45 #ifdef CONFIG_PMAC_BACKLIGHT
46 #include <asm/machdep.h>
47 #include <asm/backlight.h>
48 #endif
49
50 #include "rivafb.h"
51 #include "nvreg.h"
52
53 /* version number of this driver */
54 #define RIVAFB_VERSION "0.9.5b"
55
56 /* ------------------------------------------------------------------------- *
57 *
58 * various helpful macros and constants
59 *
60 * ------------------------------------------------------------------------- */
61 #ifdef CONFIG_FB_RIVA_DEBUG
62 #define NVTRACE printk
63 #else
64 #define NVTRACE if(0) printk
65 #endif
66
67 #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __func__)
68 #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __func__)
69
70 #ifdef CONFIG_FB_RIVA_DEBUG
71 #define assert(expr) \
72 if(!(expr)) { \
73 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
74 #expr,__FILE__,__func__,__LINE__); \
75 BUG(); \
76 }
77 #else
78 #define assert(expr)
79 #endif
80
81 #define PFX "rivafb: "
82
83 /* macro that allows you to set overflow bits */
84 #define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
85 #define SetBit(n) (1<<(n))
86 #define Set8Bits(value) ((value)&0xff)
87
88 /* HW cursor parameters */
89 #define MAX_CURS 32
90
91 /* ------------------------------------------------------------------------- *
92 *
93 * prototypes
94 *
95 * ------------------------------------------------------------------------- */
96
97 static int rivafb_blank(int blank, struct fb_info *info);
98
99 /* ------------------------------------------------------------------------- *
100 *
101 * card identification
102 *
103 * ------------------------------------------------------------------------- */
104
105 static const struct pci_device_id rivafb_pci_tbl[] = {
106 { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128,
107 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
108 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
109 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
110 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
112 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
114 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
116 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
118 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
120 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
122 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
124 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
126 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
128 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
130 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
132 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
134 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
136 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
138 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
140 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
142 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
144 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
146 // NF2/IGP version, GeForce 4 MX, NV18
147 { PCI_VENDOR_ID_NVIDIA, 0x01f0,
148 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
149 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
150 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
151 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
152 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
153 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
155 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
156 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
157 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
159 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
161 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
163 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
165 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
167 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
169 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
171 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
173 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
175 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
177 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
179 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
181 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
183 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
185 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
187 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
189 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
191 { 0, } /* terminate list */
192 };
193 MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
194
195 /* ------------------------------------------------------------------------- *
196 *
197 * global variables
198 *
199 * ------------------------------------------------------------------------- */
200
201 /* command line data, set in rivafb_setup() */
202 static int flatpanel = -1; /* Autodetect later */
203 static int forceCRTC = -1;
204 static bool noaccel = 0;
205 static bool nomtrr = 0;
206 static int backlight = IS_BUILTIN(CONFIG_PMAC_BACKLIGHT);
207
208 static char *mode_option = NULL;
209 static bool strictmode = 0;
210
211 static struct fb_fix_screeninfo rivafb_fix = {
212 .type = FB_TYPE_PACKED_PIXELS,
213 .xpanstep = 1,
214 .ypanstep = 1,
215 };
216
217 static struct fb_var_screeninfo rivafb_default_var = {
218 .xres = 640,
219 .yres = 480,
220 .xres_virtual = 640,
221 .yres_virtual = 480,
222 .bits_per_pixel = 8,
223 .red = {0, 8, 0},
224 .green = {0, 8, 0},
225 .blue = {0, 8, 0},
226 .transp = {0, 0, 0},
227 .activate = FB_ACTIVATE_NOW,
228 .height = -1,
229 .width = -1,
230 .pixclock = 39721,
231 .left_margin = 40,
232 .right_margin = 24,
233 .upper_margin = 32,
234 .lower_margin = 11,
235 .hsync_len = 96,
236 .vsync_len = 2,
237 .vmode = FB_VMODE_NONINTERLACED
238 };
239
240 /* from GGI */
241 static const struct riva_regs reg_template = {
242 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */
243 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
244 0x41, 0x01, 0x0F, 0x00, 0x00},
245 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */
246 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
247 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */
248 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
249 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */
250 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
251 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */
252 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
253 0x00, /* 0x40 */
254 },
255 {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */
256 0xFF},
257 {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */
258 0xEB /* MISC */
259 };
260
261 /*
262 * Backlight control
263 */
264 #ifdef CONFIG_FB_RIVA_BACKLIGHT
265 /* We do not have any information about which values are allowed, thus
266 * we used safe values.
267 */
268 #define MIN_LEVEL 0x158
269 #define MAX_LEVEL 0x534
270 #define LEVEL_STEP ((MAX_LEVEL - MIN_LEVEL) / FB_BACKLIGHT_MAX)
271
riva_bl_get_level_brightness(struct riva_par * par,int level)272 static int riva_bl_get_level_brightness(struct riva_par *par,
273 int level)
274 {
275 struct fb_info *info = pci_get_drvdata(par->pdev);
276 int nlevel;
277
278 /* Get and convert the value */
279 /* No locking on bl_curve since accessing a single value */
280 nlevel = MIN_LEVEL + info->bl_curve[level] * LEVEL_STEP;
281
282 if (nlevel < 0)
283 nlevel = 0;
284 else if (nlevel < MIN_LEVEL)
285 nlevel = MIN_LEVEL;
286 else if (nlevel > MAX_LEVEL)
287 nlevel = MAX_LEVEL;
288
289 return nlevel;
290 }
291
riva_bl_update_status(struct backlight_device * bd)292 static int riva_bl_update_status(struct backlight_device *bd)
293 {
294 struct riva_par *par = bl_get_data(bd);
295 U032 tmp_pcrt, tmp_pmc;
296 int level;
297
298 if (bd->props.power != FB_BLANK_UNBLANK ||
299 bd->props.fb_blank != FB_BLANK_UNBLANK)
300 level = 0;
301 else
302 level = bd->props.brightness;
303
304 tmp_pmc = NV_RD32(par->riva.PMC, 0x10F0) & 0x0000FFFF;
305 tmp_pcrt = NV_RD32(par->riva.PCRTC0, 0x081C) & 0xFFFFFFFC;
306 if(level > 0) {
307 tmp_pcrt |= 0x1;
308 tmp_pmc |= (1 << 31); /* backlight bit */
309 tmp_pmc |= riva_bl_get_level_brightness(par, level) << 16; /* level */
310 }
311 NV_WR32(par->riva.PCRTC0, 0x081C, tmp_pcrt);
312 NV_WR32(par->riva.PMC, 0x10F0, tmp_pmc);
313
314 return 0;
315 }
316
317 static const struct backlight_ops riva_bl_ops = {
318 .update_status = riva_bl_update_status,
319 };
320
riva_bl_init(struct riva_par * par)321 static void riva_bl_init(struct riva_par *par)
322 {
323 struct backlight_properties props;
324 struct fb_info *info = pci_get_drvdata(par->pdev);
325 struct backlight_device *bd;
326 char name[12];
327
328 if (!par->FlatPanel)
329 return;
330
331 #ifdef CONFIG_PMAC_BACKLIGHT
332 if (!machine_is(powermac) ||
333 !pmac_has_backlight_type("mnca"))
334 return;
335 #endif
336
337 snprintf(name, sizeof(name), "rivabl%d", info->node);
338
339 memset(&props, 0, sizeof(struct backlight_properties));
340 props.type = BACKLIGHT_RAW;
341 props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
342 bd = backlight_device_register(name, info->dev, par, &riva_bl_ops,
343 &props);
344 if (IS_ERR(bd)) {
345 info->bl_dev = NULL;
346 printk(KERN_WARNING "riva: Backlight registration failed\n");
347 goto error;
348 }
349
350 info->bl_dev = bd;
351 fb_bl_default_curve(info, 0,
352 MIN_LEVEL * FB_BACKLIGHT_MAX / MAX_LEVEL,
353 FB_BACKLIGHT_MAX);
354
355 bd->props.brightness = bd->props.max_brightness;
356 bd->props.power = FB_BLANK_UNBLANK;
357 backlight_update_status(bd);
358
359 printk("riva: Backlight initialized (%s)\n", name);
360
361 return;
362
363 error:
364 return;
365 }
366
riva_bl_exit(struct fb_info * info)367 static void riva_bl_exit(struct fb_info *info)
368 {
369 struct backlight_device *bd = info->bl_dev;
370
371 backlight_device_unregister(bd);
372 printk("riva: Backlight unloaded\n");
373 }
374 #else
riva_bl_init(struct riva_par * par)375 static inline void riva_bl_init(struct riva_par *par) {}
riva_bl_exit(struct fb_info * info)376 static inline void riva_bl_exit(struct fb_info *info) {}
377 #endif /* CONFIG_FB_RIVA_BACKLIGHT */
378
379 /* ------------------------------------------------------------------------- *
380 *
381 * MMIO access macros
382 *
383 * ------------------------------------------------------------------------- */
384
CRTCout(struct riva_par * par,unsigned char index,unsigned char val)385 static inline void CRTCout(struct riva_par *par, unsigned char index,
386 unsigned char val)
387 {
388 VGA_WR08(par->riva.PCIO, 0x3d4, index);
389 VGA_WR08(par->riva.PCIO, 0x3d5, val);
390 }
391
CRTCin(struct riva_par * par,unsigned char index)392 static inline unsigned char CRTCin(struct riva_par *par,
393 unsigned char index)
394 {
395 VGA_WR08(par->riva.PCIO, 0x3d4, index);
396 return (VGA_RD08(par->riva.PCIO, 0x3d5));
397 }
398
GRAout(struct riva_par * par,unsigned char index,unsigned char val)399 static inline void GRAout(struct riva_par *par, unsigned char index,
400 unsigned char val)
401 {
402 VGA_WR08(par->riva.PVIO, 0x3ce, index);
403 VGA_WR08(par->riva.PVIO, 0x3cf, val);
404 }
405
GRAin(struct riva_par * par,unsigned char index)406 static inline unsigned char GRAin(struct riva_par *par,
407 unsigned char index)
408 {
409 VGA_WR08(par->riva.PVIO, 0x3ce, index);
410 return (VGA_RD08(par->riva.PVIO, 0x3cf));
411 }
412
SEQout(struct riva_par * par,unsigned char index,unsigned char val)413 static inline void SEQout(struct riva_par *par, unsigned char index,
414 unsigned char val)
415 {
416 VGA_WR08(par->riva.PVIO, 0x3c4, index);
417 VGA_WR08(par->riva.PVIO, 0x3c5, val);
418 }
419
SEQin(struct riva_par * par,unsigned char index)420 static inline unsigned char SEQin(struct riva_par *par,
421 unsigned char index)
422 {
423 VGA_WR08(par->riva.PVIO, 0x3c4, index);
424 return (VGA_RD08(par->riva.PVIO, 0x3c5));
425 }
426
ATTRout(struct riva_par * par,unsigned char index,unsigned char val)427 static inline void ATTRout(struct riva_par *par, unsigned char index,
428 unsigned char val)
429 {
430 VGA_WR08(par->riva.PCIO, 0x3c0, index);
431 VGA_WR08(par->riva.PCIO, 0x3c0, val);
432 }
433
ATTRin(struct riva_par * par,unsigned char index)434 static inline unsigned char ATTRin(struct riva_par *par,
435 unsigned char index)
436 {
437 VGA_WR08(par->riva.PCIO, 0x3c0, index);
438 return (VGA_RD08(par->riva.PCIO, 0x3c1));
439 }
440
MISCout(struct riva_par * par,unsigned char val)441 static inline void MISCout(struct riva_par *par, unsigned char val)
442 {
443 VGA_WR08(par->riva.PVIO, 0x3c2, val);
444 }
445
MISCin(struct riva_par * par)446 static inline unsigned char MISCin(struct riva_par *par)
447 {
448 return (VGA_RD08(par->riva.PVIO, 0x3cc));
449 }
450
reverse_order(u32 * l)451 static inline void reverse_order(u32 *l)
452 {
453 u8 *a = (u8 *)l;
454 a[0] = bitrev8(a[0]);
455 a[1] = bitrev8(a[1]);
456 a[2] = bitrev8(a[2]);
457 a[3] = bitrev8(a[3]);
458 }
459
460 /* ------------------------------------------------------------------------- *
461 *
462 * cursor stuff
463 *
464 * ------------------------------------------------------------------------- */
465
466 /**
467 * rivafb_load_cursor_image - load cursor image to hardware
468 * @data8: address to monochrome bitmap (1 = foreground color, 0 = background)
469 * @par: pointer to private data
470 * @w: width of cursor image in pixels
471 * @h: height of cursor image in scanlines
472 * @bg: background color (ARGB1555) - alpha bit determines opacity
473 * @fg: foreground color (ARGB1555)
474 *
475 * DESCRIPTiON:
476 * Loads cursor image based on a monochrome source and mask bitmap. The
477 * image bits determines the color of the pixel, 0 for background, 1 for
478 * foreground. Only the affected region (as determined by @w and @h
479 * parameters) will be updated.
480 *
481 * CALLED FROM:
482 * rivafb_cursor()
483 */
rivafb_load_cursor_image(struct riva_par * par,u8 * data8,u16 bg,u16 fg,u32 w,u32 h)484 static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8,
485 u16 bg, u16 fg, u32 w, u32 h)
486 {
487 int i, j, k = 0;
488 u32 b, tmp;
489 u32 *data = (u32 *)data8;
490 bg = le16_to_cpu(bg);
491 fg = le16_to_cpu(fg);
492
493 w = (w + 1) & ~1;
494
495 for (i = 0; i < h; i++) {
496 b = *data++;
497 reverse_order(&b);
498
499 for (j = 0; j < w/2; j++) {
500 tmp = 0;
501 #if defined (__BIG_ENDIAN)
502 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
503 b <<= 1;
504 tmp |= (b & (1 << 31)) ? fg : bg;
505 b <<= 1;
506 #else
507 tmp = (b & 1) ? fg : bg;
508 b >>= 1;
509 tmp |= (b & 1) ? fg << 16 : bg << 16;
510 b >>= 1;
511 #endif
512 writel(tmp, &par->riva.CURSOR[k++]);
513 }
514 k += (MAX_CURS - w)/2;
515 }
516 }
517
518 /* ------------------------------------------------------------------------- *
519 *
520 * general utility functions
521 *
522 * ------------------------------------------------------------------------- */
523
524 /**
525 * riva_wclut - set CLUT entry
526 * @chip: pointer to RIVA_HW_INST object
527 * @regnum: register number
528 * @red: red component
529 * @green: green component
530 * @blue: blue component
531 *
532 * DESCRIPTION:
533 * Sets color register @regnum.
534 *
535 * CALLED FROM:
536 * rivafb_setcolreg()
537 */
riva_wclut(RIVA_HW_INST * chip,unsigned char regnum,unsigned char red,unsigned char green,unsigned char blue)538 static void riva_wclut(RIVA_HW_INST *chip,
539 unsigned char regnum, unsigned char red,
540 unsigned char green, unsigned char blue)
541 {
542 VGA_WR08(chip->PDIO, 0x3c8, regnum);
543 VGA_WR08(chip->PDIO, 0x3c9, red);
544 VGA_WR08(chip->PDIO, 0x3c9, green);
545 VGA_WR08(chip->PDIO, 0x3c9, blue);
546 }
547
548 /**
549 * riva_rclut - read fromCLUT register
550 * @chip: pointer to RIVA_HW_INST object
551 * @regnum: register number
552 * @red: red component
553 * @green: green component
554 * @blue: blue component
555 *
556 * DESCRIPTION:
557 * Reads red, green, and blue from color register @regnum.
558 *
559 * CALLED FROM:
560 * rivafb_setcolreg()
561 */
riva_rclut(RIVA_HW_INST * chip,unsigned char regnum,unsigned char * red,unsigned char * green,unsigned char * blue)562 static void riva_rclut(RIVA_HW_INST *chip,
563 unsigned char regnum, unsigned char *red,
564 unsigned char *green, unsigned char *blue)
565 {
566
567 VGA_WR08(chip->PDIO, 0x3c7, regnum);
568 *red = VGA_RD08(chip->PDIO, 0x3c9);
569 *green = VGA_RD08(chip->PDIO, 0x3c9);
570 *blue = VGA_RD08(chip->PDIO, 0x3c9);
571 }
572
573 /**
574 * riva_save_state - saves current chip state
575 * @par: pointer to riva_par object containing info for current riva board
576 * @regs: pointer to riva_regs object
577 *
578 * DESCRIPTION:
579 * Saves current chip state to @regs.
580 *
581 * CALLED FROM:
582 * rivafb_probe()
583 */
584 /* from GGI */
riva_save_state(struct riva_par * par,struct riva_regs * regs)585 static void riva_save_state(struct riva_par *par, struct riva_regs *regs)
586 {
587 int i;
588
589 NVTRACE_ENTER();
590 par->riva.LockUnlock(&par->riva, 0);
591
592 par->riva.UnloadStateExt(&par->riva, ®s->ext);
593
594 regs->misc_output = MISCin(par);
595
596 for (i = 0; i < NUM_CRT_REGS; i++)
597 regs->crtc[i] = CRTCin(par, i);
598
599 for (i = 0; i < NUM_ATC_REGS; i++)
600 regs->attr[i] = ATTRin(par, i);
601
602 for (i = 0; i < NUM_GRC_REGS; i++)
603 regs->gra[i] = GRAin(par, i);
604
605 for (i = 0; i < NUM_SEQ_REGS; i++)
606 regs->seq[i] = SEQin(par, i);
607 NVTRACE_LEAVE();
608 }
609
610 /**
611 * riva_load_state - loads current chip state
612 * @par: pointer to riva_par object containing info for current riva board
613 * @regs: pointer to riva_regs object
614 *
615 * DESCRIPTION:
616 * Loads chip state from @regs.
617 *
618 * CALLED FROM:
619 * riva_load_video_mode()
620 * rivafb_probe()
621 * rivafb_remove()
622 */
623 /* from GGI */
riva_load_state(struct riva_par * par,struct riva_regs * regs)624 static void riva_load_state(struct riva_par *par, struct riva_regs *regs)
625 {
626 RIVA_HW_STATE *state = ®s->ext;
627 int i;
628
629 NVTRACE_ENTER();
630 CRTCout(par, 0x11, 0x00);
631
632 par->riva.LockUnlock(&par->riva, 0);
633
634 par->riva.LoadStateExt(&par->riva, state);
635
636 MISCout(par, regs->misc_output);
637
638 for (i = 0; i < NUM_CRT_REGS; i++) {
639 switch (i) {
640 case 0x19:
641 case 0x20 ... 0x40:
642 break;
643 default:
644 CRTCout(par, i, regs->crtc[i]);
645 }
646 }
647
648 for (i = 0; i < NUM_ATC_REGS; i++)
649 ATTRout(par, i, regs->attr[i]);
650
651 for (i = 0; i < NUM_GRC_REGS; i++)
652 GRAout(par, i, regs->gra[i]);
653
654 for (i = 0; i < NUM_SEQ_REGS; i++)
655 SEQout(par, i, regs->seq[i]);
656 NVTRACE_LEAVE();
657 }
658
659 /**
660 * riva_load_video_mode - calculate timings
661 * @info: pointer to fb_info object containing info for current riva board
662 *
663 * DESCRIPTION:
664 * Calculate some timings and then send em off to riva_load_state().
665 *
666 * CALLED FROM:
667 * rivafb_set_par()
668 */
riva_load_video_mode(struct fb_info * info)669 static int riva_load_video_mode(struct fb_info *info)
670 {
671 int bpp, width, hDisplaySize, hDisplay, hStart,
672 hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock;
673 int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd;
674 int rc;
675 struct riva_par *par = info->par;
676 struct riva_regs newmode;
677
678 NVTRACE_ENTER();
679 /* time to calculate */
680 rivafb_blank(FB_BLANK_NORMAL, info);
681
682 bpp = info->var.bits_per_pixel;
683 if (bpp == 16 && info->var.green.length == 5)
684 bpp = 15;
685 width = info->var.xres_virtual;
686 hDisplaySize = info->var.xres;
687 hDisplay = (hDisplaySize / 8) - 1;
688 hStart = (hDisplaySize + info->var.right_margin) / 8 - 1;
689 hEnd = (hDisplaySize + info->var.right_margin +
690 info->var.hsync_len) / 8 - 1;
691 hTotal = (hDisplaySize + info->var.right_margin +
692 info->var.hsync_len + info->var.left_margin) / 8 - 5;
693 hBlankStart = hDisplay;
694 hBlankEnd = hTotal + 4;
695
696 height = info->var.yres_virtual;
697 vDisplay = info->var.yres - 1;
698 vStart = info->var.yres + info->var.lower_margin - 1;
699 vEnd = info->var.yres + info->var.lower_margin +
700 info->var.vsync_len - 1;
701 vTotal = info->var.yres + info->var.lower_margin +
702 info->var.vsync_len + info->var.upper_margin + 2;
703 vBlankStart = vDisplay;
704 vBlankEnd = vTotal + 1;
705 dotClock = 1000000000 / info->var.pixclock;
706
707 memcpy(&newmode, ®_template, sizeof(struct riva_regs));
708
709 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
710 vTotal |= 1;
711
712 if (par->FlatPanel) {
713 vStart = vTotal - 3;
714 vEnd = vTotal - 2;
715 vBlankStart = vStart;
716 hStart = hTotal - 3;
717 hEnd = hTotal - 2;
718 hBlankEnd = hTotal + 4;
719 }
720
721 newmode.crtc[0x0] = Set8Bits (hTotal);
722 newmode.crtc[0x1] = Set8Bits (hDisplay);
723 newmode.crtc[0x2] = Set8Bits (hBlankStart);
724 newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7);
725 newmode.crtc[0x4] = Set8Bits (hStart);
726 newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7)
727 | SetBitField (hEnd, 4: 0, 4:0);
728 newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);
729 newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)
730 | SetBitField (vDisplay, 8: 8, 1:1)
731 | SetBitField (vStart, 8: 8, 2:2)
732 | SetBitField (vBlankStart, 8: 8, 3:3)
733 | SetBit (4)
734 | SetBitField (vTotal, 9: 9, 5:5)
735 | SetBitField (vDisplay, 9: 9, 6:6)
736 | SetBitField (vStart, 9: 9, 7:7);
737 newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5)
738 | SetBit (6);
739 newmode.crtc[0x10] = Set8Bits (vStart);
740 newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)
741 | SetBit (5);
742 newmode.crtc[0x12] = Set8Bits (vDisplay);
743 newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8);
744 newmode.crtc[0x15] = Set8Bits (vBlankStart);
745 newmode.crtc[0x16] = Set8Bits (vBlankEnd);
746
747 newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4)
748 | SetBitField(vBlankStart,10:10,3:3)
749 | SetBitField(vStart,10:10,2:2)
750 | SetBitField(vDisplay,10:10,1:1)
751 | SetBitField(vTotal,10:10,0:0);
752 newmode.ext.horiz = SetBitField(hTotal,8:8,0:0)
753 | SetBitField(hDisplay,8:8,1:1)
754 | SetBitField(hBlankStart,8:8,2:2)
755 | SetBitField(hStart,8:8,3:3);
756 newmode.ext.extra = SetBitField(vTotal,11:11,0:0)
757 | SetBitField(vDisplay,11:11,2:2)
758 | SetBitField(vStart,11:11,4:4)
759 | SetBitField(vBlankStart,11:11,6:6);
760
761 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
762 int tmp = (hTotal >> 1) & ~1;
763 newmode.ext.interlace = Set8Bits(tmp);
764 newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4);
765 } else
766 newmode.ext.interlace = 0xff; /* interlace off */
767
768 if (par->riva.Architecture >= NV_ARCH_10)
769 par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart);
770
771 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
772 newmode.misc_output &= ~0x40;
773 else
774 newmode.misc_output |= 0x40;
775 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
776 newmode.misc_output &= ~0x80;
777 else
778 newmode.misc_output |= 0x80;
779
780 rc = CalcStateExt(&par->riva, &newmode.ext, par->pdev, bpp, width,
781 hDisplaySize, height, dotClock);
782 if (rc)
783 goto out;
784
785 newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) &
786 0xfff000ff;
787 if (par->FlatPanel == 1) {
788 newmode.ext.pixel |= (1 << 7);
789 newmode.ext.scale |= (1 << 8);
790 }
791 if (par->SecondCRTC) {
792 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) &
793 ~0x00001000;
794 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) |
795 0x00001000;
796 newmode.ext.crtcOwner = 3;
797 newmode.ext.pllsel |= 0x20000800;
798 newmode.ext.vpll2 = newmode.ext.vpll;
799 } else if (par->riva.twoHeads) {
800 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) |
801 0x00001000;
802 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) &
803 ~0x00001000;
804 newmode.ext.crtcOwner = 0;
805 newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520);
806 }
807 if (par->FlatPanel == 1) {
808 newmode.ext.pixel |= (1 << 7);
809 newmode.ext.scale |= (1 << 8);
810 }
811 newmode.ext.cursorConfig = 0x02000100;
812 par->current_state = newmode;
813 riva_load_state(par, &par->current_state);
814 par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */
815
816 out:
817 rivafb_blank(FB_BLANK_UNBLANK, info);
818 NVTRACE_LEAVE();
819
820 return rc;
821 }
822
riva_update_var(struct fb_var_screeninfo * var,const struct fb_videomode * modedb)823 static void riva_update_var(struct fb_var_screeninfo *var,
824 const struct fb_videomode *modedb)
825 {
826 NVTRACE_ENTER();
827 var->xres = var->xres_virtual = modedb->xres;
828 var->yres = modedb->yres;
829 if (var->yres_virtual < var->yres)
830 var->yres_virtual = var->yres;
831 var->xoffset = var->yoffset = 0;
832 var->pixclock = modedb->pixclock;
833 var->left_margin = modedb->left_margin;
834 var->right_margin = modedb->right_margin;
835 var->upper_margin = modedb->upper_margin;
836 var->lower_margin = modedb->lower_margin;
837 var->hsync_len = modedb->hsync_len;
838 var->vsync_len = modedb->vsync_len;
839 var->sync = modedb->sync;
840 var->vmode = modedb->vmode;
841 NVTRACE_LEAVE();
842 }
843
844 /**
845 * rivafb_do_maximize -
846 * @info: pointer to fb_info object containing info for current riva board
847 * @var: standard kernel fb changeable data
848 * @nom: nom
849 * @den: den
850 *
851 * DESCRIPTION:
852 * .
853 *
854 * RETURNS:
855 * -EINVAL on failure, 0 on success
856 *
857 *
858 * CALLED FROM:
859 * rivafb_check_var()
860 */
rivafb_do_maximize(struct fb_info * info,struct fb_var_screeninfo * var,int nom,int den)861 static int rivafb_do_maximize(struct fb_info *info,
862 struct fb_var_screeninfo *var,
863 int nom, int den)
864 {
865 static struct {
866 int xres, yres;
867 } modes[] = {
868 {1600, 1280},
869 {1280, 1024},
870 {1024, 768},
871 {800, 600},
872 {640, 480},
873 {-1, -1}
874 };
875 int i;
876
877 NVTRACE_ENTER();
878 /* use highest possible virtual resolution */
879 if (var->xres_virtual == -1 && var->yres_virtual == -1) {
880 printk(KERN_WARNING PFX
881 "using maximum available virtual resolution\n");
882 for (i = 0; modes[i].xres != -1; i++) {
883 if (modes[i].xres * nom / den * modes[i].yres <
884 info->fix.smem_len)
885 break;
886 }
887 if (modes[i].xres == -1) {
888 printk(KERN_ERR PFX
889 "could not find a virtual resolution that fits into video memory!!\n");
890 NVTRACE("EXIT - EINVAL error\n");
891 return -EINVAL;
892 }
893 var->xres_virtual = modes[i].xres;
894 var->yres_virtual = modes[i].yres;
895
896 printk(KERN_INFO PFX
897 "virtual resolution set to maximum of %dx%d\n",
898 var->xres_virtual, var->yres_virtual);
899 } else if (var->xres_virtual == -1) {
900 var->xres_virtual = (info->fix.smem_len * den /
901 (nom * var->yres_virtual)) & ~15;
902 printk(KERN_WARNING PFX
903 "setting virtual X resolution to %d\n", var->xres_virtual);
904 } else if (var->yres_virtual == -1) {
905 var->xres_virtual = (var->xres_virtual + 15) & ~15;
906 var->yres_virtual = info->fix.smem_len * den /
907 (nom * var->xres_virtual);
908 printk(KERN_WARNING PFX
909 "setting virtual Y resolution to %d\n", var->yres_virtual);
910 } else {
911 var->xres_virtual = (var->xres_virtual + 15) & ~15;
912 if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) {
913 printk(KERN_ERR PFX
914 "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
915 var->xres, var->yres, var->bits_per_pixel);
916 NVTRACE("EXIT - EINVAL error\n");
917 return -EINVAL;
918 }
919 }
920
921 if (var->xres_virtual * nom / den >= 8192) {
922 printk(KERN_WARNING PFX
923 "virtual X resolution (%d) is too high, lowering to %d\n",
924 var->xres_virtual, 8192 * den / nom - 16);
925 var->xres_virtual = 8192 * den / nom - 16;
926 }
927
928 if (var->xres_virtual < var->xres) {
929 printk(KERN_ERR PFX
930 "virtual X resolution (%d) is smaller than real\n", var->xres_virtual);
931 return -EINVAL;
932 }
933
934 if (var->yres_virtual < var->yres) {
935 printk(KERN_ERR PFX
936 "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual);
937 return -EINVAL;
938 }
939 if (var->yres_virtual > 0x7fff/nom)
940 var->yres_virtual = 0x7fff/nom;
941 if (var->xres_virtual > 0x7fff/nom)
942 var->xres_virtual = 0x7fff/nom;
943 NVTRACE_LEAVE();
944 return 0;
945 }
946
947 static void
riva_set_pattern(struct riva_par * par,int clr0,int clr1,int pat0,int pat1)948 riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1)
949 {
950 RIVA_FIFO_FREE(par->riva, Patt, 4);
951 NV_WR32(&par->riva.Patt->Color0, 0, clr0);
952 NV_WR32(&par->riva.Patt->Color1, 0, clr1);
953 NV_WR32(par->riva.Patt->Monochrome, 0, pat0);
954 NV_WR32(par->riva.Patt->Monochrome, 4, pat1);
955 }
956
957 /* acceleration routines */
wait_for_idle(struct riva_par * par)958 static inline void wait_for_idle(struct riva_par *par)
959 {
960 while (par->riva.Busy(&par->riva));
961 }
962
963 /*
964 * Set ROP. Translate X rop into ROP3. Internal routine.
965 */
966 static void
riva_set_rop_solid(struct riva_par * par,int rop)967 riva_set_rop_solid(struct riva_par *par, int rop)
968 {
969 riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
970 RIVA_FIFO_FREE(par->riva, Rop, 1);
971 NV_WR32(&par->riva.Rop->Rop3, 0, rop);
972
973 }
974
riva_setup_accel(struct fb_info * info)975 static void riva_setup_accel(struct fb_info *info)
976 {
977 struct riva_par *par = info->par;
978
979 RIVA_FIFO_FREE(par->riva, Clip, 2);
980 NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0);
981 NV_WR32(&par->riva.Clip->WidthHeight, 0,
982 (info->var.xres_virtual & 0xffff) |
983 (info->var.yres_virtual << 16));
984 riva_set_rop_solid(par, 0xcc);
985 wait_for_idle(par);
986 }
987
988 /**
989 * riva_get_cmap_len - query current color map length
990 * @var: standard kernel fb changeable data
991 *
992 * DESCRIPTION:
993 * Get current color map length.
994 *
995 * RETURNS:
996 * Length of color map
997 *
998 * CALLED FROM:
999 * rivafb_setcolreg()
1000 */
riva_get_cmap_len(const struct fb_var_screeninfo * var)1001 static int riva_get_cmap_len(const struct fb_var_screeninfo *var)
1002 {
1003 int rc = 256; /* reasonable default */
1004
1005 switch (var->green.length) {
1006 case 8:
1007 rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */
1008 break;
1009 case 5:
1010 rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */
1011 break;
1012 case 6:
1013 rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */
1014 break;
1015 default:
1016 /* should not occur */
1017 break;
1018 }
1019 return rc;
1020 }
1021
1022 /* ------------------------------------------------------------------------- *
1023 *
1024 * framebuffer operations
1025 *
1026 * ------------------------------------------------------------------------- */
1027
rivafb_open(struct fb_info * info,int user)1028 static int rivafb_open(struct fb_info *info, int user)
1029 {
1030 struct riva_par *par = info->par;
1031
1032 NVTRACE_ENTER();
1033 mutex_lock(&par->open_lock);
1034 if (!par->ref_count) {
1035 #ifdef CONFIG_X86
1036 memset(&par->state, 0, sizeof(struct vgastate));
1037 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
1038 /* save the DAC for Riva128 */
1039 if (par->riva.Architecture == NV_ARCH_03)
1040 par->state.flags |= VGA_SAVE_CMAP;
1041 save_vga(&par->state);
1042 #endif
1043 /* vgaHWunlock() + riva unlock (0x7F) */
1044 CRTCout(par, 0x11, 0xFF);
1045 par->riva.LockUnlock(&par->riva, 0);
1046
1047 riva_save_state(par, &par->initial_state);
1048 }
1049 par->ref_count++;
1050 mutex_unlock(&par->open_lock);
1051 NVTRACE_LEAVE();
1052 return 0;
1053 }
1054
rivafb_release(struct fb_info * info,int user)1055 static int rivafb_release(struct fb_info *info, int user)
1056 {
1057 struct riva_par *par = info->par;
1058
1059 NVTRACE_ENTER();
1060 mutex_lock(&par->open_lock);
1061 if (!par->ref_count) {
1062 mutex_unlock(&par->open_lock);
1063 return -EINVAL;
1064 }
1065 if (par->ref_count == 1) {
1066 par->riva.LockUnlock(&par->riva, 0);
1067 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext);
1068 riva_load_state(par, &par->initial_state);
1069 #ifdef CONFIG_X86
1070 restore_vga(&par->state);
1071 #endif
1072 par->riva.LockUnlock(&par->riva, 1);
1073 }
1074 par->ref_count--;
1075 mutex_unlock(&par->open_lock);
1076 NVTRACE_LEAVE();
1077 return 0;
1078 }
1079
rivafb_check_var(struct fb_var_screeninfo * var,struct fb_info * info)1080 static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1081 {
1082 const struct fb_videomode *mode;
1083 struct riva_par *par = info->par;
1084 int nom, den; /* translating from pixels->bytes */
1085 int mode_valid = 0;
1086
1087 NVTRACE_ENTER();
1088 if (!var->pixclock)
1089 return -EINVAL;
1090
1091 switch (var->bits_per_pixel) {
1092 case 1 ... 8:
1093 var->red.offset = var->green.offset = var->blue.offset = 0;
1094 var->red.length = var->green.length = var->blue.length = 8;
1095 var->bits_per_pixel = 8;
1096 nom = den = 1;
1097 break;
1098 case 9 ... 15:
1099 var->green.length = 5;
1100 fallthrough;
1101 case 16:
1102 var->bits_per_pixel = 16;
1103 /* The Riva128 supports RGB555 only */
1104 if (par->riva.Architecture == NV_ARCH_03)
1105 var->green.length = 5;
1106 if (var->green.length == 5) {
1107 /* 0rrrrrgg gggbbbbb */
1108 var->red.offset = 10;
1109 var->green.offset = 5;
1110 var->blue.offset = 0;
1111 var->red.length = 5;
1112 var->green.length = 5;
1113 var->blue.length = 5;
1114 } else {
1115 /* rrrrrggg gggbbbbb */
1116 var->red.offset = 11;
1117 var->green.offset = 5;
1118 var->blue.offset = 0;
1119 var->red.length = 5;
1120 var->green.length = 6;
1121 var->blue.length = 5;
1122 }
1123 nom = 2;
1124 den = 1;
1125 break;
1126 case 17 ... 32:
1127 var->red.length = var->green.length = var->blue.length = 8;
1128 var->bits_per_pixel = 32;
1129 var->red.offset = 16;
1130 var->green.offset = 8;
1131 var->blue.offset = 0;
1132 nom = 4;
1133 den = 1;
1134 break;
1135 default:
1136 printk(KERN_ERR PFX
1137 "mode %dx%dx%d rejected...color depth not supported.\n",
1138 var->xres, var->yres, var->bits_per_pixel);
1139 NVTRACE("EXIT, returning -EINVAL\n");
1140 return -EINVAL;
1141 }
1142
1143 if (!strictmode) {
1144 if (!info->monspecs.vfmax || !info->monspecs.hfmax ||
1145 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1146 mode_valid = 1;
1147 }
1148
1149 /* calculate modeline if supported by monitor */
1150 if (!mode_valid && info->monspecs.gtf) {
1151 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1152 mode_valid = 1;
1153 }
1154
1155 if (!mode_valid) {
1156 mode = fb_find_best_mode(var, &info->modelist);
1157 if (mode) {
1158 riva_update_var(var, mode);
1159 mode_valid = 1;
1160 }
1161 }
1162
1163 if (!mode_valid && info->monspecs.modedb_len)
1164 return -EINVAL;
1165
1166 if (var->xres_virtual < var->xres)
1167 var->xres_virtual = var->xres;
1168 if (var->yres_virtual <= var->yres)
1169 var->yres_virtual = -1;
1170 if (rivafb_do_maximize(info, var, nom, den) < 0)
1171 return -EINVAL;
1172
1173 /* truncate xoffset and yoffset to maximum if too high */
1174 if (var->xoffset > var->xres_virtual - var->xres)
1175 var->xoffset = var->xres_virtual - var->xres - 1;
1176
1177 if (var->yoffset > var->yres_virtual - var->yres)
1178 var->yoffset = var->yres_virtual - var->yres - 1;
1179
1180 var->red.msb_right =
1181 var->green.msb_right =
1182 var->blue.msb_right =
1183 var->transp.offset = var->transp.length = var->transp.msb_right = 0;
1184 NVTRACE_LEAVE();
1185 return 0;
1186 }
1187
rivafb_set_par(struct fb_info * info)1188 static int rivafb_set_par(struct fb_info *info)
1189 {
1190 struct riva_par *par = info->par;
1191 int rc = 0;
1192
1193 NVTRACE_ENTER();
1194 /* vgaHWunlock() + riva unlock (0x7F) */
1195 CRTCout(par, 0x11, 0xFF);
1196 par->riva.LockUnlock(&par->riva, 0);
1197 rc = riva_load_video_mode(info);
1198 if (rc)
1199 goto out;
1200 if(!(info->flags & FBINFO_HWACCEL_DISABLED))
1201 riva_setup_accel(info);
1202
1203 par->cursor_reset = 1;
1204 info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3));
1205 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1206 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1207
1208 if (info->flags & FBINFO_HWACCEL_DISABLED)
1209 info->pixmap.scan_align = 1;
1210 else
1211 info->pixmap.scan_align = 4;
1212
1213 out:
1214 NVTRACE_LEAVE();
1215 return rc;
1216 }
1217
1218 /**
1219 * rivafb_pan_display
1220 * @var: standard kernel fb changeable data
1221 * @info: pointer to fb_info object containing info for current riva board
1222 *
1223 * DESCRIPTION:
1224 * Pan (or wrap, depending on the `vmode' field) the display using the
1225 * `xoffset' and `yoffset' fields of the `var' structure.
1226 * If the values don't fit, return -EINVAL.
1227 *
1228 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1229 */
rivafb_pan_display(struct fb_var_screeninfo * var,struct fb_info * info)1230 static int rivafb_pan_display(struct fb_var_screeninfo *var,
1231 struct fb_info *info)
1232 {
1233 struct riva_par *par = info->par;
1234 unsigned int base;
1235
1236 NVTRACE_ENTER();
1237 base = var->yoffset * info->fix.line_length + var->xoffset;
1238 par->riva.SetStartAddress(&par->riva, base);
1239 NVTRACE_LEAVE();
1240 return 0;
1241 }
1242
rivafb_blank(int blank,struct fb_info * info)1243 static int rivafb_blank(int blank, struct fb_info *info)
1244 {
1245 struct riva_par *par= info->par;
1246 unsigned char tmp, vesa;
1247
1248 tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */
1249 vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */
1250
1251 NVTRACE_ENTER();
1252
1253 if (blank)
1254 tmp |= 0x20;
1255
1256 switch (blank) {
1257 case FB_BLANK_UNBLANK:
1258 case FB_BLANK_NORMAL:
1259 break;
1260 case FB_BLANK_VSYNC_SUSPEND:
1261 vesa |= 0x80;
1262 break;
1263 case FB_BLANK_HSYNC_SUSPEND:
1264 vesa |= 0x40;
1265 break;
1266 case FB_BLANK_POWERDOWN:
1267 vesa |= 0xc0;
1268 break;
1269 }
1270
1271 SEQout(par, 0x01, tmp);
1272 CRTCout(par, 0x1a, vesa);
1273
1274 NVTRACE_LEAVE();
1275
1276 return 0;
1277 }
1278
1279 /**
1280 * rivafb_setcolreg
1281 * @regno: register index
1282 * @red: red component
1283 * @green: green component
1284 * @blue: blue component
1285 * @transp: transparency
1286 * @info: pointer to fb_info object containing info for current riva board
1287 *
1288 * DESCRIPTION:
1289 * Set a single color register. The values supplied have a 16 bit
1290 * magnitude.
1291 *
1292 * RETURNS:
1293 * Return != 0 for invalid regno.
1294 *
1295 * CALLED FROM:
1296 * fbcmap.c:fb_set_cmap()
1297 */
rivafb_setcolreg(unsigned regno,unsigned red,unsigned green,unsigned blue,unsigned transp,struct fb_info * info)1298 static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1299 unsigned blue, unsigned transp,
1300 struct fb_info *info)
1301 {
1302 struct riva_par *par = info->par;
1303 RIVA_HW_INST *chip = &par->riva;
1304 int i;
1305
1306 if (regno >= riva_get_cmap_len(&info->var))
1307 return -EINVAL;
1308
1309 if (info->var.grayscale) {
1310 /* gray = 0.30*R + 0.59*G + 0.11*B */
1311 red = green = blue =
1312 (red * 77 + green * 151 + blue * 28) >> 8;
1313 }
1314
1315 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1316 ((u32 *) info->pseudo_palette)[regno] =
1317 (regno << info->var.red.offset) |
1318 (regno << info->var.green.offset) |
1319 (regno << info->var.blue.offset);
1320 /*
1321 * The Riva128 2D engine requires color information in
1322 * TrueColor format even if framebuffer is in DirectColor
1323 */
1324 if (par->riva.Architecture == NV_ARCH_03) {
1325 switch (info->var.bits_per_pixel) {
1326 case 16:
1327 par->palette[regno] = ((red & 0xf800) >> 1) |
1328 ((green & 0xf800) >> 6) |
1329 ((blue & 0xf800) >> 11);
1330 break;
1331 case 32:
1332 par->palette[regno] = ((red & 0xff00) << 8) |
1333 ((green & 0xff00)) |
1334 ((blue & 0xff00) >> 8);
1335 break;
1336 }
1337 }
1338 }
1339
1340 switch (info->var.bits_per_pixel) {
1341 case 8:
1342 /* "transparent" stuff is completely ignored. */
1343 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1344 break;
1345 case 16:
1346 if (info->var.green.length == 5) {
1347 for (i = 0; i < 8; i++) {
1348 riva_wclut(chip, regno*8+i, red >> 8,
1349 green >> 8, blue >> 8);
1350 }
1351 } else {
1352 u8 r, g, b;
1353
1354 if (regno < 32) {
1355 for (i = 0; i < 8; i++) {
1356 riva_wclut(chip, regno*8+i,
1357 red >> 8, green >> 8,
1358 blue >> 8);
1359 }
1360 }
1361 riva_rclut(chip, regno*4, &r, &g, &b);
1362 for (i = 0; i < 4; i++)
1363 riva_wclut(chip, regno*4+i, r,
1364 green >> 8, b);
1365 }
1366 break;
1367 case 32:
1368 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1369 break;
1370 default:
1371 /* do nothing */
1372 break;
1373 }
1374 return 0;
1375 }
1376
1377 /**
1378 * rivafb_fillrect - hardware accelerated color fill function
1379 * @info: pointer to fb_info structure
1380 * @rect: pointer to fb_fillrect structure
1381 *
1382 * DESCRIPTION:
1383 * This function fills up a region of framebuffer memory with a solid
1384 * color with a choice of two different ROP's, copy or invert.
1385 *
1386 * CALLED FROM:
1387 * framebuffer hook
1388 */
rivafb_fillrect(struct fb_info * info,const struct fb_fillrect * rect)1389 static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1390 {
1391 struct riva_par *par = info->par;
1392 u_int color, rop = 0;
1393
1394 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1395 cfb_fillrect(info, rect);
1396 return;
1397 }
1398
1399 if (info->var.bits_per_pixel == 8)
1400 color = rect->color;
1401 else {
1402 if (par->riva.Architecture != NV_ARCH_03)
1403 color = ((u32 *)info->pseudo_palette)[rect->color];
1404 else
1405 color = par->palette[rect->color];
1406 }
1407
1408 switch (rect->rop) {
1409 case ROP_XOR:
1410 rop = 0x66;
1411 break;
1412 case ROP_COPY:
1413 default:
1414 rop = 0xCC;
1415 break;
1416 }
1417
1418 riva_set_rop_solid(par, rop);
1419
1420 RIVA_FIFO_FREE(par->riva, Bitmap, 1);
1421 NV_WR32(&par->riva.Bitmap->Color1A, 0, color);
1422
1423 RIVA_FIFO_FREE(par->riva, Bitmap, 2);
1424 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0,
1425 (rect->dx << 16) | rect->dy);
1426 mb();
1427 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0,
1428 (rect->width << 16) | rect->height);
1429 mb();
1430 riva_set_rop_solid(par, 0xcc);
1431
1432 }
1433
1434 /**
1435 * rivafb_copyarea - hardware accelerated blit function
1436 * @info: pointer to fb_info structure
1437 * @region: pointer to fb_copyarea structure
1438 *
1439 * DESCRIPTION:
1440 * This copies an area of pixels from one location to another
1441 *
1442 * CALLED FROM:
1443 * framebuffer hook
1444 */
rivafb_copyarea(struct fb_info * info,const struct fb_copyarea * region)1445 static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
1446 {
1447 struct riva_par *par = info->par;
1448
1449 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1450 cfb_copyarea(info, region);
1451 return;
1452 }
1453
1454 RIVA_FIFO_FREE(par->riva, Blt, 3);
1455 NV_WR32(&par->riva.Blt->TopLeftSrc, 0,
1456 (region->sy << 16) | region->sx);
1457 NV_WR32(&par->riva.Blt->TopLeftDst, 0,
1458 (region->dy << 16) | region->dx);
1459 mb();
1460 NV_WR32(&par->riva.Blt->WidthHeight, 0,
1461 (region->height << 16) | region->width);
1462 mb();
1463 }
1464
convert_bgcolor_16(u32 * col)1465 static inline void convert_bgcolor_16(u32 *col)
1466 {
1467 *col = ((*col & 0x0000F800) << 8)
1468 | ((*col & 0x00007E0) << 5)
1469 | ((*col & 0x0000001F) << 3)
1470 | 0xFF000000;
1471 mb();
1472 }
1473
1474 /**
1475 * rivafb_imageblit: hardware accelerated color expand function
1476 * @info: pointer to fb_info structure
1477 * @image: pointer to fb_image structure
1478 *
1479 * DESCRIPTION:
1480 * If the source is a monochrome bitmap, the function fills up a a region
1481 * of framebuffer memory with pixels whose color is determined by the bit
1482 * setting of the bitmap, 1 - foreground, 0 - background.
1483 *
1484 * If the source is not a monochrome bitmap, color expansion is not done.
1485 * In this case, it is channeled to a software function.
1486 *
1487 * CALLED FROM:
1488 * framebuffer hook
1489 */
rivafb_imageblit(struct fb_info * info,const struct fb_image * image)1490 static void rivafb_imageblit(struct fb_info *info,
1491 const struct fb_image *image)
1492 {
1493 struct riva_par *par = info->par;
1494 u32 fgx = 0, bgx = 0, width, tmp;
1495 u8 *cdat = (u8 *) image->data;
1496 volatile u32 __iomem *d;
1497 int i, size;
1498
1499 if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) {
1500 cfb_imageblit(info, image);
1501 return;
1502 }
1503
1504 switch (info->var.bits_per_pixel) {
1505 case 8:
1506 fgx = image->fg_color;
1507 bgx = image->bg_color;
1508 break;
1509 case 16:
1510 case 32:
1511 if (par->riva.Architecture != NV_ARCH_03) {
1512 fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
1513 bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
1514 } else {
1515 fgx = par->palette[image->fg_color];
1516 bgx = par->palette[image->bg_color];
1517 }
1518 if (info->var.green.length == 6)
1519 convert_bgcolor_16(&bgx);
1520 break;
1521 }
1522
1523 RIVA_FIFO_FREE(par->riva, Bitmap, 7);
1524 NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0,
1525 (image->dy << 16) | (image->dx & 0xFFFF));
1526 NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0,
1527 (((image->dy + image->height) << 16) |
1528 ((image->dx + image->width) & 0xffff)));
1529 NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx);
1530 NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx);
1531 NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0,
1532 (image->height << 16) | ((image->width + 31) & ~31));
1533 NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0,
1534 (image->height << 16) | ((image->width + 31) & ~31));
1535 NV_WR32(&par->riva.Bitmap->PointE, 0,
1536 (image->dy << 16) | (image->dx & 0xFFFF));
1537
1538 d = &par->riva.Bitmap->MonochromeData01E;
1539
1540 width = (image->width + 31)/32;
1541 size = width * image->height;
1542 while (size >= 16) {
1543 RIVA_FIFO_FREE(par->riva, Bitmap, 16);
1544 for (i = 0; i < 16; i++) {
1545 tmp = *((u32 *)cdat);
1546 cdat = (u8 *)((u32 *)cdat + 1);
1547 reverse_order(&tmp);
1548 NV_WR32(d, i*4, tmp);
1549 }
1550 size -= 16;
1551 }
1552 if (size) {
1553 RIVA_FIFO_FREE(par->riva, Bitmap, size);
1554 for (i = 0; i < size; i++) {
1555 tmp = *((u32 *) cdat);
1556 cdat = (u8 *)((u32 *)cdat + 1);
1557 reverse_order(&tmp);
1558 NV_WR32(d, i*4, tmp);
1559 }
1560 }
1561 }
1562
1563 /**
1564 * rivafb_cursor - hardware cursor function
1565 * @info: pointer to info structure
1566 * @cursor: pointer to fbcursor structure
1567 *
1568 * DESCRIPTION:
1569 * A cursor function that supports displaying a cursor image via hardware.
1570 * Within the kernel, copy and invert rops are supported. If exported
1571 * to user space, only the copy rop will be supported.
1572 *
1573 * CALLED FROM
1574 * framebuffer hook
1575 */
rivafb_cursor(struct fb_info * info,struct fb_cursor * cursor)1576 static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1577 {
1578 struct riva_par *par = info->par;
1579 u8 data[MAX_CURS * MAX_CURS/8];
1580 int i, set = cursor->set;
1581 u16 fg, bg;
1582
1583 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
1584 return -ENXIO;
1585
1586 par->riva.ShowHideCursor(&par->riva, 0);
1587
1588 if (par->cursor_reset) {
1589 set = FB_CUR_SETALL;
1590 par->cursor_reset = 0;
1591 }
1592
1593 if (set & FB_CUR_SETSIZE)
1594 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
1595
1596 if (set & FB_CUR_SETPOS) {
1597 u32 xx, yy, temp;
1598
1599 yy = cursor->image.dy - info->var.yoffset;
1600 xx = cursor->image.dx - info->var.xoffset;
1601 temp = xx & 0xFFFF;
1602 temp |= yy << 16;
1603
1604 NV_WR32(par->riva.PRAMDAC, 0x0000300, temp);
1605 }
1606
1607
1608 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
1609 u32 bg_idx = cursor->image.bg_color;
1610 u32 fg_idx = cursor->image.fg_color;
1611 u32 s_pitch = (cursor->image.width+7) >> 3;
1612 u32 d_pitch = MAX_CURS/8;
1613 u8 *dat = (u8 *) cursor->image.data;
1614 u8 *msk = (u8 *) cursor->mask;
1615 u8 *src;
1616
1617 src = kmalloc_array(s_pitch, cursor->image.height, GFP_ATOMIC);
1618
1619 if (src) {
1620 switch (cursor->rop) {
1621 case ROP_XOR:
1622 for (i = 0; i < s_pitch * cursor->image.height; i++)
1623 src[i] = dat[i] ^ msk[i];
1624 break;
1625 case ROP_COPY:
1626 default:
1627 for (i = 0; i < s_pitch * cursor->image.height; i++)
1628 src[i] = dat[i] & msk[i];
1629 break;
1630 }
1631
1632 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
1633 cursor->image.height);
1634
1635 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
1636 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
1637 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) |
1638 1 << 15;
1639
1640 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1641 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1642 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) |
1643 1 << 15;
1644
1645 par->riva.LockUnlock(&par->riva, 0);
1646
1647 rivafb_load_cursor_image(par, data, bg, fg,
1648 cursor->image.width,
1649 cursor->image.height);
1650 kfree(src);
1651 }
1652 }
1653
1654 if (cursor->enable)
1655 par->riva.ShowHideCursor(&par->riva, 1);
1656
1657 return 0;
1658 }
1659
rivafb_sync(struct fb_info * info)1660 static int rivafb_sync(struct fb_info *info)
1661 {
1662 struct riva_par *par = info->par;
1663
1664 wait_for_idle(par);
1665 return 0;
1666 }
1667
1668 /* ------------------------------------------------------------------------- *
1669 *
1670 * initialization helper functions
1671 *
1672 * ------------------------------------------------------------------------- */
1673
1674 /* kernel interface */
1675 static const struct fb_ops riva_fb_ops = {
1676 .owner = THIS_MODULE,
1677 .fb_open = rivafb_open,
1678 .fb_release = rivafb_release,
1679 .fb_check_var = rivafb_check_var,
1680 .fb_set_par = rivafb_set_par,
1681 .fb_setcolreg = rivafb_setcolreg,
1682 .fb_pan_display = rivafb_pan_display,
1683 .fb_blank = rivafb_blank,
1684 .fb_fillrect = rivafb_fillrect,
1685 .fb_copyarea = rivafb_copyarea,
1686 .fb_imageblit = rivafb_imageblit,
1687 .fb_cursor = rivafb_cursor,
1688 .fb_sync = rivafb_sync,
1689 };
1690
riva_set_fbinfo(struct fb_info * info)1691 static int riva_set_fbinfo(struct fb_info *info)
1692 {
1693 unsigned int cmap_len;
1694 struct riva_par *par = info->par;
1695
1696 NVTRACE_ENTER();
1697 info->flags = FBINFO_DEFAULT
1698 | FBINFO_HWACCEL_XPAN
1699 | FBINFO_HWACCEL_YPAN
1700 | FBINFO_HWACCEL_COPYAREA
1701 | FBINFO_HWACCEL_FILLRECT
1702 | FBINFO_HWACCEL_IMAGEBLIT;
1703
1704 /* Accel seems to not work properly on NV30 yet...*/
1705 if ((par->riva.Architecture == NV_ARCH_30) || noaccel) {
1706 printk(KERN_DEBUG PFX "disabling acceleration\n");
1707 info->flags |= FBINFO_HWACCEL_DISABLED;
1708 }
1709
1710 info->var = rivafb_default_var;
1711 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1712 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1713
1714 info->pseudo_palette = par->pseudo_palette;
1715
1716 cmap_len = riva_get_cmap_len(&info->var);
1717 fb_alloc_cmap(&info->cmap, cmap_len, 0);
1718
1719 info->pixmap.size = 8 * 1024;
1720 info->pixmap.buf_align = 4;
1721 info->pixmap.access_align = 32;
1722 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1723 info->var.yres_virtual = -1;
1724 NVTRACE_LEAVE();
1725 return (rivafb_check_var(&info->var, info));
1726 }
1727
riva_get_EDID_OF(struct fb_info * info,struct pci_dev * pd)1728 static int riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd)
1729 {
1730 struct riva_par *par = info->par;
1731 struct device_node *dp;
1732 const unsigned char *pedid = NULL;
1733 const unsigned char *disptype = NULL;
1734 static char *propnames[] = {
1735 "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL };
1736 int i;
1737
1738 NVTRACE_ENTER();
1739 dp = pci_device_to_OF_node(pd);
1740 for (; dp != NULL; dp = dp->child) {
1741 disptype = of_get_property(dp, "display-type", NULL);
1742 if (disptype == NULL)
1743 continue;
1744 if (strncmp(disptype, "LCD", 3) != 0)
1745 continue;
1746 for (i = 0; propnames[i] != NULL; ++i) {
1747 pedid = of_get_property(dp, propnames[i], NULL);
1748 if (pedid != NULL) {
1749 par->EDID = (unsigned char *)pedid;
1750 NVTRACE("LCD found.\n");
1751 return 1;
1752 }
1753 }
1754 }
1755 NVTRACE_LEAVE();
1756 return 0;
1757 }
1758
1759 #if defined(CONFIG_FB_RIVA_I2C)
riva_get_EDID_i2c(struct fb_info * info)1760 static int riva_get_EDID_i2c(struct fb_info *info)
1761 {
1762 struct riva_par *par = info->par;
1763 struct fb_var_screeninfo var;
1764 int i;
1765
1766 NVTRACE_ENTER();
1767 par->riva.LockUnlock(&par->riva, 0);
1768 riva_create_i2c_busses(par);
1769 for (i = 0; i < 3; i++) {
1770 if (!par->chan[i].par)
1771 continue;
1772 riva_probe_i2c_connector(par, i, &par->EDID);
1773 if (par->EDID && !fb_parse_edid(par->EDID, &var)) {
1774 printk(PFX "Found EDID Block from BUS %i\n", i);
1775 break;
1776 }
1777 }
1778
1779 NVTRACE_LEAVE();
1780 return (par->EDID) ? 1 : 0;
1781 }
1782 #endif /* CONFIG_FB_RIVA_I2C */
1783
riva_update_default_var(struct fb_var_screeninfo * var,struct fb_info * info)1784 static void riva_update_default_var(struct fb_var_screeninfo *var,
1785 struct fb_info *info)
1786 {
1787 struct fb_monspecs *specs = &info->monspecs;
1788 struct fb_videomode modedb;
1789
1790 NVTRACE_ENTER();
1791 /* respect mode options */
1792 if (mode_option) {
1793 fb_find_mode(var, info, mode_option,
1794 specs->modedb, specs->modedb_len,
1795 NULL, 8);
1796 } else if (specs->modedb != NULL) {
1797 /* get first mode in database as fallback */
1798 modedb = specs->modedb[0];
1799 /* get preferred timing */
1800 if (info->monspecs.misc & FB_MISC_1ST_DETAIL) {
1801 int i;
1802
1803 for (i = 0; i < specs->modedb_len; i++) {
1804 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1805 modedb = specs->modedb[i];
1806 break;
1807 }
1808 }
1809 }
1810 var->bits_per_pixel = 8;
1811 riva_update_var(var, &modedb);
1812 }
1813 NVTRACE_LEAVE();
1814 }
1815
1816
riva_get_EDID(struct fb_info * info,struct pci_dev * pdev)1817 static void riva_get_EDID(struct fb_info *info, struct pci_dev *pdev)
1818 {
1819 NVTRACE_ENTER();
1820 if (riva_get_EDID_OF(info, pdev)) {
1821 NVTRACE_LEAVE();
1822 return;
1823 }
1824 if (IS_ENABLED(CONFIG_OF))
1825 printk(PFX "could not retrieve EDID from OF\n");
1826 #if defined(CONFIG_FB_RIVA_I2C)
1827 if (!riva_get_EDID_i2c(info))
1828 printk(PFX "could not retrieve EDID from DDC/I2C\n");
1829 #endif
1830 NVTRACE_LEAVE();
1831 }
1832
1833
riva_get_edidinfo(struct fb_info * info)1834 static void riva_get_edidinfo(struct fb_info *info)
1835 {
1836 struct fb_var_screeninfo *var = &rivafb_default_var;
1837 struct riva_par *par = info->par;
1838
1839 fb_edid_to_monspecs(par->EDID, &info->monspecs);
1840 fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len,
1841 &info->modelist);
1842 riva_update_default_var(var, info);
1843
1844 /* if user specified flatpanel, we respect that */
1845 if (info->monspecs.input & FB_DISP_DDI)
1846 par->FlatPanel = 1;
1847 }
1848
1849 /* ------------------------------------------------------------------------- *
1850 *
1851 * PCI bus
1852 *
1853 * ------------------------------------------------------------------------- */
1854
riva_get_arch(struct pci_dev * pd)1855 static u32 riva_get_arch(struct pci_dev *pd)
1856 {
1857 u32 arch = 0;
1858
1859 switch (pd->device & 0x0ff0) {
1860 case 0x0100: /* GeForce 256 */
1861 case 0x0110: /* GeForce2 MX */
1862 case 0x0150: /* GeForce2 */
1863 case 0x0170: /* GeForce4 MX */
1864 case 0x0180: /* GeForce4 MX (8x AGP) */
1865 case 0x01A0: /* nForce */
1866 case 0x01F0: /* nForce2 */
1867 arch = NV_ARCH_10;
1868 break;
1869 case 0x0200: /* GeForce3 */
1870 case 0x0250: /* GeForce4 Ti */
1871 case 0x0280: /* GeForce4 Ti (8x AGP) */
1872 arch = NV_ARCH_20;
1873 break;
1874 case 0x0300: /* GeForceFX 5800 */
1875 case 0x0310: /* GeForceFX 5600 */
1876 case 0x0320: /* GeForceFX 5200 */
1877 case 0x0330: /* GeForceFX 5900 */
1878 case 0x0340: /* GeForceFX 5700 */
1879 arch = NV_ARCH_30;
1880 break;
1881 case 0x0020: /* TNT, TNT2 */
1882 arch = NV_ARCH_04;
1883 break;
1884 case 0x0010: /* Riva128 */
1885 arch = NV_ARCH_03;
1886 break;
1887 default: /* unknown architecture */
1888 break;
1889 }
1890 return arch;
1891 }
1892
rivafb_probe(struct pci_dev * pd,const struct pci_device_id * ent)1893 static int rivafb_probe(struct pci_dev *pd, const struct pci_device_id *ent)
1894 {
1895 struct riva_par *default_par;
1896 struct fb_info *info;
1897 int ret;
1898
1899 NVTRACE_ENTER();
1900 assert(pd != NULL);
1901
1902 ret = aperture_remove_conflicting_pci_devices(pd, "rivafb");
1903 if (ret)
1904 return ret;
1905
1906 info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev);
1907 if (!info) {
1908 ret = -ENOMEM;
1909 goto err_ret;
1910 }
1911 default_par = info->par;
1912 default_par->pdev = pd;
1913
1914 info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL);
1915 if (info->pixmap.addr == NULL) {
1916 ret = -ENOMEM;
1917 goto err_framebuffer_release;
1918 }
1919
1920 ret = pci_enable_device(pd);
1921 if (ret < 0) {
1922 printk(KERN_ERR PFX "cannot enable PCI device\n");
1923 goto err_free_pixmap;
1924 }
1925
1926 ret = pci_request_regions(pd, "rivafb");
1927 if (ret < 0) {
1928 printk(KERN_ERR PFX "cannot request PCI regions\n");
1929 goto err_disable_device;
1930 }
1931
1932 mutex_init(&default_par->open_lock);
1933 default_par->riva.Architecture = riva_get_arch(pd);
1934
1935 default_par->Chipset = (pd->vendor << 16) | pd->device;
1936 printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset);
1937
1938 if(default_par->riva.Architecture == 0) {
1939 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1940 ret=-ENODEV;
1941 goto err_release_region;
1942 }
1943 if(default_par->riva.Architecture == NV_ARCH_10 ||
1944 default_par->riva.Architecture == NV_ARCH_20 ||
1945 default_par->riva.Architecture == NV_ARCH_30) {
1946 sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1947 } else {
1948 sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture);
1949 }
1950
1951 default_par->FlatPanel = flatpanel;
1952 if (flatpanel == 1)
1953 printk(KERN_INFO PFX "flatpanel support enabled\n");
1954 default_par->forceCRTC = forceCRTC;
1955
1956 rivafb_fix.mmio_len = pci_resource_len(pd, 0);
1957 rivafb_fix.smem_len = pci_resource_len(pd, 1);
1958
1959 {
1960 /* enable IO and mem if not already done */
1961 unsigned short cmd;
1962
1963 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1964 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1965 pci_write_config_word(pd, PCI_COMMAND, cmd);
1966 }
1967
1968 rivafb_fix.mmio_start = pci_resource_start(pd, 0);
1969 rivafb_fix.smem_start = pci_resource_start(pd, 1);
1970
1971 default_par->ctrl_base = ioremap(rivafb_fix.mmio_start,
1972 rivafb_fix.mmio_len);
1973 if (!default_par->ctrl_base) {
1974 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1975 ret = -EIO;
1976 goto err_release_region;
1977 }
1978
1979 switch (default_par->riva.Architecture) {
1980 case NV_ARCH_03:
1981 /* Riva128's PRAMIN is in the "framebuffer" space
1982 * Since these cards were never made with more than 8 megabytes
1983 * we can safely allocate this separately.
1984 */
1985 default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
1986 if (!default_par->riva.PRAMIN) {
1987 printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n");
1988 ret = -EIO;
1989 goto err_iounmap_ctrl_base;
1990 }
1991 break;
1992 case NV_ARCH_04:
1993 case NV_ARCH_10:
1994 case NV_ARCH_20:
1995 case NV_ARCH_30:
1996 default_par->riva.PCRTC0 =
1997 (u32 __iomem *)(default_par->ctrl_base + 0x00600000);
1998 default_par->riva.PRAMIN =
1999 (u32 __iomem *)(default_par->ctrl_base + 0x00710000);
2000 break;
2001 }
2002 riva_common_setup(default_par);
2003
2004 if (default_par->riva.Architecture == NV_ARCH_03) {
2005 default_par->riva.PCRTC = default_par->riva.PCRTC0
2006 = default_par->riva.PGRAPH;
2007 }
2008
2009 rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024;
2010 default_par->dclk_max = riva_get_maxdclk(default_par) * 1000;
2011 info->screen_base = ioremap_wc(rivafb_fix.smem_start,
2012 rivafb_fix.smem_len);
2013 if (!info->screen_base) {
2014 printk(KERN_ERR PFX "cannot ioremap FB base\n");
2015 ret = -EIO;
2016 goto err_iounmap_pramin;
2017 }
2018
2019 if (!nomtrr)
2020 default_par->wc_cookie =
2021 arch_phys_wc_add(rivafb_fix.smem_start,
2022 rivafb_fix.smem_len);
2023
2024 info->fbops = &riva_fb_ops;
2025 info->fix = rivafb_fix;
2026 riva_get_EDID(info, pd);
2027 riva_get_edidinfo(info);
2028
2029 ret=riva_set_fbinfo(info);
2030 if (ret < 0) {
2031 printk(KERN_ERR PFX "error setting initial video mode\n");
2032 goto err_iounmap_screen_base;
2033 }
2034
2035 fb_destroy_modedb(info->monspecs.modedb);
2036 info->monspecs.modedb = NULL;
2037
2038 pci_set_drvdata(pd, info);
2039
2040 if (backlight)
2041 riva_bl_init(info->par);
2042
2043 ret = register_framebuffer(info);
2044 if (ret < 0) {
2045 printk(KERN_ERR PFX
2046 "error registering riva framebuffer\n");
2047 goto err_iounmap_screen_base;
2048 }
2049
2050 printk(KERN_INFO PFX
2051 "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n",
2052 info->fix.id,
2053 RIVAFB_VERSION,
2054 info->fix.smem_len / (1024 * 1024),
2055 info->fix.smem_start);
2056
2057 NVTRACE_LEAVE();
2058 return 0;
2059
2060 err_iounmap_screen_base:
2061 #ifdef CONFIG_FB_RIVA_I2C
2062 riva_delete_i2c_busses(info->par);
2063 #endif
2064 iounmap(info->screen_base);
2065 err_iounmap_pramin:
2066 if (default_par->riva.Architecture == NV_ARCH_03)
2067 iounmap(default_par->riva.PRAMIN);
2068 err_iounmap_ctrl_base:
2069 iounmap(default_par->ctrl_base);
2070 err_release_region:
2071 pci_release_regions(pd);
2072 err_disable_device:
2073 err_free_pixmap:
2074 kfree(info->pixmap.addr);
2075 err_framebuffer_release:
2076 framebuffer_release(info);
2077 err_ret:
2078 return ret;
2079 }
2080
rivafb_remove(struct pci_dev * pd)2081 static void rivafb_remove(struct pci_dev *pd)
2082 {
2083 struct fb_info *info = pci_get_drvdata(pd);
2084 struct riva_par *par = info->par;
2085
2086 NVTRACE_ENTER();
2087
2088 #ifdef CONFIG_FB_RIVA_I2C
2089 riva_delete_i2c_busses(par);
2090 kfree(par->EDID);
2091 #endif
2092
2093 unregister_framebuffer(info);
2094
2095 riva_bl_exit(info);
2096 arch_phys_wc_del(par->wc_cookie);
2097 iounmap(par->ctrl_base);
2098 iounmap(info->screen_base);
2099 if (par->riva.Architecture == NV_ARCH_03)
2100 iounmap(par->riva.PRAMIN);
2101 pci_release_regions(pd);
2102 kfree(info->pixmap.addr);
2103 framebuffer_release(info);
2104 NVTRACE_LEAVE();
2105 }
2106
2107 /* ------------------------------------------------------------------------- *
2108 *
2109 * initialization
2110 *
2111 * ------------------------------------------------------------------------- */
2112
2113 #ifndef MODULE
rivafb_setup(char * options)2114 static int rivafb_setup(char *options)
2115 {
2116 char *this_opt;
2117
2118 NVTRACE_ENTER();
2119 if (!options || !*options)
2120 return 0;
2121
2122 while ((this_opt = strsep(&options, ",")) != NULL) {
2123 if (!strncmp(this_opt, "forceCRTC", 9)) {
2124 char *p;
2125
2126 p = this_opt + 9;
2127 if (!*p || !*(++p)) continue;
2128 forceCRTC = *p - '0';
2129 if (forceCRTC < 0 || forceCRTC > 1)
2130 forceCRTC = -1;
2131 } else if (!strncmp(this_opt, "flatpanel", 9)) {
2132 flatpanel = 1;
2133 } else if (!strncmp(this_opt, "backlight:", 10)) {
2134 backlight = simple_strtoul(this_opt+10, NULL, 0);
2135 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2136 nomtrr = 1;
2137 } else if (!strncmp(this_opt, "strictmode", 10)) {
2138 strictmode = 1;
2139 } else if (!strncmp(this_opt, "noaccel", 7)) {
2140 noaccel = 1;
2141 } else
2142 mode_option = this_opt;
2143 }
2144 NVTRACE_LEAVE();
2145 return 0;
2146 }
2147 #endif /* !MODULE */
2148
2149 static struct pci_driver rivafb_driver = {
2150 .name = "rivafb",
2151 .id_table = rivafb_pci_tbl,
2152 .probe = rivafb_probe,
2153 .remove = rivafb_remove,
2154 };
2155
2156
2157
2158 /* ------------------------------------------------------------------------- *
2159 *
2160 * modularization
2161 *
2162 * ------------------------------------------------------------------------- */
2163
rivafb_init(void)2164 static int rivafb_init(void)
2165 {
2166 #ifndef MODULE
2167 char *option = NULL;
2168
2169 if (fb_get_options("rivafb", &option))
2170 return -ENODEV;
2171 rivafb_setup(option);
2172 #endif
2173 return pci_register_driver(&rivafb_driver);
2174 }
2175
2176
2177 module_init(rivafb_init);
2178
rivafb_exit(void)2179 static void __exit rivafb_exit(void)
2180 {
2181 pci_unregister_driver(&rivafb_driver);
2182 }
2183
2184 module_exit(rivafb_exit);
2185
2186 module_param(noaccel, bool, 0);
2187 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2188 module_param(flatpanel, int, 0);
2189 MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)");
2190 module_param(forceCRTC, int, 0);
2191 MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)");
2192 module_param(nomtrr, bool, 0);
2193 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");
2194 module_param(strictmode, bool, 0);
2195 MODULE_PARM_DESC(strictmode, "Only use video modes from EDID");
2196
2197 MODULE_AUTHOR("Ani Joshi, maintainer");
2198 MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");
2199 MODULE_LICENSE("GPL");
2200