1 // SPDX-License-Identifier: GPL-2.0
2 /******************************************************************************
3 *
4 * Copyright(c) 2007 - 2016 Realtek Corporation.
5 *
6 * Contact Information:
7 * wlanfae <wlanfae@realtek.com>
8 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
9 * Hsinchu 300, Taiwan.
10 *
11 * Larry Finger <Larry.Finger@lwfinger.net>
12 *
13 *****************************************************************************/
14
15 /*============================================================
16 * include files
17 *============================================================
18 */
19 #include "mp_precomp.h"
20 #include "phydm_precomp.h"
21
phydm_get_psd_data(void * dm_void,u32 psd_tone_idx,u32 igi)22 u32 phydm_get_psd_data(void *dm_void, u32 psd_tone_idx, u32 igi)
23 {
24 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
25 struct psd_info *dm_psd_table = &dm->dm_psd_table;
26 u32 psd_report = 0;
27
28 odm_set_bb_reg(dm, dm_psd_table->psd_reg, 0x3ff, psd_tone_idx);
29
30 odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22),
31 1); /*PSD trigger start*/
32 ODM_delay_us(10);
33 odm_set_bb_reg(dm, dm_psd_table->psd_reg, BIT(22),
34 0); /*PSD trigger stop*/
35
36 psd_report = odm_get_bb_reg(dm, dm_psd_table->psd_report_reg, 0xffff);
37 psd_report = odm_convert_to_db(psd_report) + igi;
38
39 return psd_report;
40 }
41
phydm_psd_stop_trx(void * dm_void)42 static u8 phydm_psd_stop_trx(void *dm_void)
43 {
44 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
45 u32 i;
46 u8 trx_idle_success = false;
47 u32 dbg_port_value = 0;
48
49 /*[Stop TRX]----------------------------------------------------------*/
50 if (!phydm_set_bb_dbg_port(dm, BB_DBGPORT_PRIORITY_3,
51 0x0)) /*set debug port to 0x0*/
52 return STOP_TRX_FAIL;
53
54 for (i = 0; i < 10000; i++) {
55 dbg_port_value = phydm_get_bb_dbg_port_value(dm);
56 if ((dbg_port_value & (BIT(17) | BIT(3))) ==
57 0) /* PHYTXON && CCA_all */ {
58 ODM_RT_TRACE(dm, ODM_COMP_API,
59 "PSD wait for ((%d)) times\n", i);
60
61 trx_idle_success = true;
62 break;
63 }
64 }
65
66 if (trx_idle_success) {
67 /*pause all TX queue*/
68 odm_set_bb_reg(dm, 0x520, 0xff0000, 0xff);
69
70 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
71 /*disable CCK block*/
72 odm_set_bb_reg(dm, 0x808, BIT(28), 0);
73 /*disable OFDM RX CCA*/
74 odm_set_bb_reg(dm, 0x838, BIT(1), 1);
75 } else {
76 /*TBD*/
77 /* disable whole CCK block */
78 odm_set_bb_reg(dm, 0x800, BIT(24), 0);
79 /*[ Set IQK Matrix = 0 ] equivalent to [ Turn off CCA]*/
80 odm_set_bb_reg(dm, 0xC14, MASKDWORD, 0x0);
81 }
82
83 } else {
84 return STOP_TRX_FAIL;
85 }
86
87 phydm_release_bb_dbg_port(dm);
88
89 return STOP_TRX_SUCCESS;
90 }
91
92 static u8 psd_result_cali_tone_8821[7] = {21, 28, 33, 93, 98, 105, 127};
93 static u8 psd_result_cali_val_8821[7] = {67, 69, 71, 72, 71, 69, 67};
94
phydm_psd(void * dm_void,u32 igi,u16 start_point,u16 stop_point)95 void phydm_psd(void *dm_void, u32 igi, u16 start_point, u16 stop_point)
96 {
97 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
98 struct psd_info *dm_psd_table = &dm->dm_psd_table;
99 u32 i = 0, mod_tone_idx;
100 u32 t = 0;
101 u16 fft_max_half_bw;
102 u32 psd_igi_a_reg;
103 u32 psd_igi_b_reg;
104 u16 psd_fc_channel = dm_psd_table->psd_fc_channel;
105 u8 ag_rf_mode_reg = 0;
106 u8 rf_reg18_9_8 = 0;
107 u32 psd_result_tmp = 0;
108 u8 psd_result = 0;
109 u8 psd_result_cali_tone[7] = {0};
110 u8 psd_result_cali_val[7] = {0};
111 u8 noise_table_idx = 0;
112
113 if (dm->support_ic_type == ODM_RTL8821) {
114 odm_move_memory(dm, psd_result_cali_tone,
115 psd_result_cali_tone_8821, 7);
116 odm_move_memory(dm, psd_result_cali_val,
117 psd_result_cali_val_8821, 7);
118 }
119
120 dm_psd_table->psd_in_progress = 1;
121
122 /*[Stop DIG]*/
123 dm->support_ability &= ~(ODM_BB_DIG);
124 dm->support_ability &= ~(ODM_BB_FA_CNT);
125
126 ODM_RT_TRACE(dm, ODM_COMP_API, "PSD Start =>\n");
127
128 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
129 psd_igi_a_reg = 0xc50;
130 psd_igi_b_reg = 0xe50;
131 } else {
132 psd_igi_a_reg = 0xc50;
133 psd_igi_b_reg = 0xc58;
134 }
135
136 /*[back up IGI]*/
137 dm_psd_table->initial_gain_backup =
138 odm_get_bb_reg(dm, psd_igi_a_reg, 0xff);
139 odm_set_bb_reg(dm, psd_igi_a_reg, 0xff,
140 0x6e); /*IGI target at 0dBm & make it can't CCA*/
141 odm_set_bb_reg(dm, psd_igi_b_reg, 0xff,
142 0x6e); /*IGI target at 0dBm & make it can't CCA*/
143 ODM_delay_us(10);
144
145 if (phydm_psd_stop_trx(dm) == STOP_TRX_FAIL) {
146 ODM_RT_TRACE(dm, ODM_COMP_API, "STOP_TRX_FAIL\n");
147 return;
148 }
149
150 /*[Set IGI]*/
151 odm_set_bb_reg(dm, psd_igi_a_reg, 0xff, igi);
152 odm_set_bb_reg(dm, psd_igi_b_reg, 0xff, igi);
153
154 /*[Backup RF Reg]*/
155 dm_psd_table->rf_0x18_bkp =
156 odm_get_rf_reg(dm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK);
157
158 if (psd_fc_channel > 14) {
159 rf_reg18_9_8 = 1;
160
161 if (psd_fc_channel >= 36 && psd_fc_channel <= 64)
162 ag_rf_mode_reg = 0x1;
163 else if (psd_fc_channel >= 100 && psd_fc_channel <= 140)
164 ag_rf_mode_reg = 0x3;
165 else if (psd_fc_channel > 140)
166 ag_rf_mode_reg = 0x5;
167 }
168
169 /* Set RF fc*/
170 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x18, 0xff, psd_fc_channel);
171 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x18, 0x300, rf_reg18_9_8);
172 /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
173 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x18, 0xc00,
174 dm_psd_table->psd_bw_rf_reg);
175 /* Set RF ag fc mode*/
176 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x18, 0xf0000, ag_rf_mode_reg);
177
178 ODM_RT_TRACE(dm, ODM_COMP_API, "0xc50=((0x%x))\n",
179 odm_get_bb_reg(dm, 0xc50, MASKDWORD));
180 ODM_RT_TRACE(dm, ODM_COMP_API, "RF0x18=((0x%x))\n",
181 odm_get_rf_reg(dm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK));
182
183 /*[Stop 3-wires]*/
184 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
185 odm_set_bb_reg(dm, 0xc00, 0xf, 0x4); /* hardware 3-wire off */
186 odm_set_bb_reg(dm, 0xe00, 0xf, 0x4); /* hardware 3-wire off */
187 } else {
188 odm_set_bb_reg(dm, 0x88c, 0xf00000,
189 0xf); /* 3 wire Disable 88c[23:20]=0xf */
190 }
191 ODM_delay_us(10);
192
193 if (stop_point > (dm_psd_table->fft_smp_point - 1))
194 stop_point = (dm_psd_table->fft_smp_point - 1);
195
196 if (start_point > (dm_psd_table->fft_smp_point - 1))
197 start_point = (dm_psd_table->fft_smp_point - 1);
198
199 if (start_point > stop_point)
200 stop_point = start_point;
201
202 if (stop_point > 127) /* limit of psd_result[128] */
203 stop_point = 127;
204
205 for (i = start_point; i <= stop_point; i++) {
206 fft_max_half_bw = (dm_psd_table->fft_smp_point) >> 1;
207
208 if (i < fft_max_half_bw)
209 mod_tone_idx = i + fft_max_half_bw;
210 else
211 mod_tone_idx = i - fft_max_half_bw;
212
213 psd_result_tmp = 0;
214 for (t = 0; t < dm_psd_table->sw_avg_time; t++)
215 psd_result_tmp +=
216 phydm_get_psd_data(dm, mod_tone_idx, igi);
217 psd_result =
218 (u8)((psd_result_tmp / dm_psd_table->sw_avg_time)) -
219 dm_psd_table->psd_pwr_common_offset;
220
221 if (dm_psd_table->fft_smp_point == 128 &&
222 (dm_psd_table->noise_k_en)) {
223 if (i > psd_result_cali_tone[noise_table_idx])
224 noise_table_idx++;
225
226 if (noise_table_idx > 6)
227 noise_table_idx = 6;
228
229 if (psd_result >= psd_result_cali_val[noise_table_idx])
230 psd_result =
231 psd_result -
232 psd_result_cali_val[noise_table_idx];
233 else
234 psd_result = 0;
235
236 dm_psd_table->psd_result[i] = psd_result;
237 }
238
239 ODM_RT_TRACE(dm, ODM_COMP_API, "[%d] N_cali = %d, PSD = %d\n",
240 mod_tone_idx, psd_result_cali_val[noise_table_idx],
241 psd_result);
242 }
243
244 /*[Start 3-wires]*/
245 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
246 odm_set_bb_reg(dm, 0xc00, 0xf, 0x7); /* hardware 3-wire on */
247 odm_set_bb_reg(dm, 0xe00, 0xf, 0x7); /* hardware 3-wire on */
248 } else {
249 odm_set_bb_reg(dm, 0x88c, 0xf00000,
250 0x0); /* 3 wire enable 88c[23:20]=0x0 */
251 }
252 ODM_delay_us(10);
253
254 /*[Revert Reg]*/
255 odm_set_bb_reg(dm, 0x520, 0xff0000, 0x0); /*start all TX queue*/
256 odm_set_bb_reg(dm, 0x808, BIT(28), 1); /*enable CCK block*/
257 odm_set_bb_reg(dm, 0x838, BIT(1), 0); /*enable OFDM RX CCA*/
258
259 odm_set_bb_reg(dm, psd_igi_a_reg, 0xff,
260 dm_psd_table->initial_gain_backup);
261 odm_set_bb_reg(dm, psd_igi_b_reg, 0xff,
262 dm_psd_table->initial_gain_backup);
263
264 odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x18, RFREGOFFSETMASK,
265 dm_psd_table->rf_0x18_bkp);
266
267 ODM_RT_TRACE(dm, ODM_COMP_API, "PSD finished\n\n");
268
269 dm->support_ability |= ODM_BB_DIG;
270 dm->support_ability |= ODM_BB_FA_CNT;
271 dm_psd_table->psd_in_progress = 0;
272 }
273
phydm_psd_para_setting(void * dm_void,u8 sw_avg_time,u8 hw_avg_time,u8 i_q_setting,u16 fft_smp_point,u8 ant_sel,u8 psd_input,u8 channel,u8 noise_k_en)274 void phydm_psd_para_setting(void *dm_void, u8 sw_avg_time, u8 hw_avg_time,
275 u8 i_q_setting, u16 fft_smp_point, u8 ant_sel,
276 u8 psd_input, u8 channel, u8 noise_k_en)
277 {
278 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
279 struct psd_info *dm_psd_table = &dm->dm_psd_table;
280 u8 fft_smp_point_idx = 0;
281
282 dm_psd_table->fft_smp_point = fft_smp_point;
283
284 if (sw_avg_time == 0)
285 sw_avg_time = 1;
286
287 dm_psd_table->sw_avg_time = sw_avg_time;
288 dm_psd_table->psd_fc_channel = channel;
289 dm_psd_table->noise_k_en = noise_k_en;
290
291 if (fft_smp_point == 128)
292 fft_smp_point_idx = 0;
293 else if (fft_smp_point == 256)
294 fft_smp_point_idx = 1;
295 else if (fft_smp_point == 512)
296 fft_smp_point_idx = 2;
297 else if (fft_smp_point == 1024)
298 fft_smp_point_idx = 3;
299
300 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
301 odm_set_bb_reg(dm, 0x910, BIT(11) | BIT(10), i_q_setting);
302 odm_set_bb_reg(dm, 0x910, BIT(13) | BIT(12), hw_avg_time);
303 odm_set_bb_reg(dm, 0x910, BIT(15) | BIT(14), fft_smp_point_idx);
304 odm_set_bb_reg(dm, 0x910, BIT(17) | BIT(16), ant_sel);
305 odm_set_bb_reg(dm, 0x910, BIT(23), psd_input);
306 }
307
308 /*bw = (*dm->band_width); //ODM_BW20M */
309 /*channel = *(dm->channel);*/
310 }
311
phydm_psd_init(void * dm_void)312 void phydm_psd_init(void *dm_void)
313 {
314 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
315 struct psd_info *dm_psd_table = &dm->dm_psd_table;
316
317 ODM_RT_TRACE(dm, ODM_COMP_API, "PSD para init\n");
318
319 dm_psd_table->psd_in_progress = false;
320
321 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
322 dm_psd_table->psd_reg = 0x910;
323 dm_psd_table->psd_report_reg = 0xF44;
324
325 if (ODM_IC_11AC_2_SERIES)
326 dm_psd_table->psd_bw_rf_reg =
327 1; /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
328 else
329 dm_psd_table->psd_bw_rf_reg =
330 2; /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
331
332 } else {
333 dm_psd_table->psd_reg = 0x808;
334 dm_psd_table->psd_report_reg = 0x8B4;
335 dm_psd_table->psd_bw_rf_reg =
336 2; /*2b'11: 20MHz, 2b'10: 40MHz, 2b'01: 80MHz */
337 }
338
339 if (dm->support_ic_type == ODM_RTL8812)
340 dm_psd_table->psd_pwr_common_offset = 0;
341 else if (dm->support_ic_type == ODM_RTL8821)
342 dm_psd_table->psd_pwr_common_offset = 0;
343 else
344 dm_psd_table->psd_pwr_common_offset = 0;
345
346 phydm_psd_para_setting(dm, 1, 2, 3, 128, 0, 0, 7, 0);
347 /*phydm_psd(dm, 0x3c, 0, 127);*/ /* target at -50dBm */
348 }
349
phydm_psd_debug(void * dm_void,char input[][16],u32 * _used,char * output,u32 * _out_len,u32 input_num)350 void phydm_psd_debug(void *dm_void, char input[][16], u32 *_used, char *output,
351 u32 *_out_len, u32 input_num)
352 {
353 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
354 char help[] = "-h";
355 u32 var1[10] = {0};
356 u32 used = *_used;
357 u32 out_len = *_out_len;
358 u8 i;
359
360 if ((strcmp(input[1], help) == 0)) {
361 PHYDM_SNPRINTF(
362 output + used, out_len - used,
363 "{0} {sw_avg} {hw_avg 0:3} {1:I,2:Q,3:IQ} {fft_point: 128*(1:4)} {path_sel 0~3} {0:ADC, 1:RXIQC} {CH} {noise_k}\n");
364 PHYDM_SNPRINTF(output + used, out_len - used,
365 "{1} {IGI(hex)} {start_point} {stop_point}\n");
366 return;
367 }
368
369 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
370
371 if (var1[0] == 0) {
372 for (i = 1; i < 10; i++) {
373 if (input[i + 1])
374 PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL,
375 &var1[i]);
376 }
377
378 PHYDM_SNPRINTF(
379 output + used, out_len - used,
380 "sw_avg_time=((%d)), hw_avg_time=((%d)), IQ=((%d)), fft=((%d)), path=((%d)), input =((%d)) ch=((%d)), noise_k=((%d))\n",
381 var1[1], var1[2], var1[3], var1[4], var1[5], var1[6],
382 (u8)var1[7], (u8)var1[8]);
383 phydm_psd_para_setting(dm, (u8)var1[1], (u8)var1[2],
384 (u8)var1[3], (u16)var1[4], (u8)var1[5],
385 (u8)var1[6], (u8)var1[7], (u8)var1[8]);
386
387 } else if (var1[0] == 1) {
388 PHYDM_SSCANF(input[2], DCMD_HEX, &var1[1]);
389 PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
390 PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);
391 PHYDM_SNPRINTF(
392 output + used, out_len - used,
393 "IGI=((0x%x)), start_point=((%d)), stop_point=((%d))\n",
394 var1[1], var1[2], var1[3]);
395 dm->debug_components |= ODM_COMP_API;
396 phydm_psd(dm, var1[1], (u16)var1[2], (u16)var1[3]);
397 dm->debug_components &= (~ODM_COMP_API);
398 }
399 }
400
phydm_get_psd_result_table(void * dm_void,int index)401 u8 phydm_get_psd_result_table(void *dm_void, int index)
402 {
403 struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
404 struct psd_info *dm_psd_table = &dm->dm_psd_table;
405 u8 temp_result = 0;
406
407 if (index < 128)
408 temp_result = dm_psd_table->psd_result[index];
409
410 return temp_result;
411 }
412
