1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) STMicroelectronics SA 2014
4 * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics.
5 */
6
7 #include <linux/clk.h>
8 #include <linux/component.h>
9 #include <linux/debugfs.h>
10 #include <linux/hdmi.h>
11 #include <linux/i2c.h>
12 #include <linux/module.h>
13 #include <linux/io.h>
14 #include <linux/platform_device.h>
15 #include <linux/reset.h>
16
17 #include <drm/drm_atomic_helper.h>
18 #include <drm/drm_bridge.h>
19 #include <drm/drm_debugfs.h>
20 #include <drm/drm_drv.h>
21 #include <drm/drm_edid.h>
22 #include <drm/drm_file.h>
23 #include <drm/drm_print.h>
24 #include <drm/drm_probe_helper.h>
25
26 #include <sound/hdmi-codec.h>
27
28 #include "sti_hdmi.h"
29 #include "sti_hdmi_tx3g4c28phy.h"
30 #include "sti_vtg.h"
31
32 #define HDMI_CFG 0x0000
33 #define HDMI_INT_EN 0x0004
34 #define HDMI_INT_STA 0x0008
35 #define HDMI_INT_CLR 0x000C
36 #define HDMI_STA 0x0010
37 #define HDMI_ACTIVE_VID_XMIN 0x0100
38 #define HDMI_ACTIVE_VID_XMAX 0x0104
39 #define HDMI_ACTIVE_VID_YMIN 0x0108
40 #define HDMI_ACTIVE_VID_YMAX 0x010C
41 #define HDMI_DFLT_CHL0_DAT 0x0110
42 #define HDMI_DFLT_CHL1_DAT 0x0114
43 #define HDMI_DFLT_CHL2_DAT 0x0118
44 #define HDMI_AUDIO_CFG 0x0200
45 #define HDMI_SPDIF_FIFO_STATUS 0x0204
46 #define HDMI_SW_DI_1_HEAD_WORD 0x0210
47 #define HDMI_SW_DI_1_PKT_WORD0 0x0214
48 #define HDMI_SW_DI_1_PKT_WORD1 0x0218
49 #define HDMI_SW_DI_1_PKT_WORD2 0x021C
50 #define HDMI_SW_DI_1_PKT_WORD3 0x0220
51 #define HDMI_SW_DI_1_PKT_WORD4 0x0224
52 #define HDMI_SW_DI_1_PKT_WORD5 0x0228
53 #define HDMI_SW_DI_1_PKT_WORD6 0x022C
54 #define HDMI_SW_DI_CFG 0x0230
55 #define HDMI_SAMPLE_FLAT_MASK 0x0244
56 #define HDMI_AUDN 0x0400
57 #define HDMI_AUD_CTS 0x0404
58 #define HDMI_SW_DI_2_HEAD_WORD 0x0600
59 #define HDMI_SW_DI_2_PKT_WORD0 0x0604
60 #define HDMI_SW_DI_2_PKT_WORD1 0x0608
61 #define HDMI_SW_DI_2_PKT_WORD2 0x060C
62 #define HDMI_SW_DI_2_PKT_WORD3 0x0610
63 #define HDMI_SW_DI_2_PKT_WORD4 0x0614
64 #define HDMI_SW_DI_2_PKT_WORD5 0x0618
65 #define HDMI_SW_DI_2_PKT_WORD6 0x061C
66 #define HDMI_SW_DI_3_HEAD_WORD 0x0620
67 #define HDMI_SW_DI_3_PKT_WORD0 0x0624
68 #define HDMI_SW_DI_3_PKT_WORD1 0x0628
69 #define HDMI_SW_DI_3_PKT_WORD2 0x062C
70 #define HDMI_SW_DI_3_PKT_WORD3 0x0630
71 #define HDMI_SW_DI_3_PKT_WORD4 0x0634
72 #define HDMI_SW_DI_3_PKT_WORD5 0x0638
73 #define HDMI_SW_DI_3_PKT_WORD6 0x063C
74
75 #define HDMI_IFRAME_SLOT_AVI 1
76 #define HDMI_IFRAME_SLOT_AUDIO 2
77 #define HDMI_IFRAME_SLOT_VENDOR 3
78
79 #define XCAT(prefix, x, suffix) prefix ## x ## suffix
80 #define HDMI_SW_DI_N_HEAD_WORD(x) XCAT(HDMI_SW_DI_, x, _HEAD_WORD)
81 #define HDMI_SW_DI_N_PKT_WORD0(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD0)
82 #define HDMI_SW_DI_N_PKT_WORD1(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD1)
83 #define HDMI_SW_DI_N_PKT_WORD2(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD2)
84 #define HDMI_SW_DI_N_PKT_WORD3(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD3)
85 #define HDMI_SW_DI_N_PKT_WORD4(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD4)
86 #define HDMI_SW_DI_N_PKT_WORD5(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD5)
87 #define HDMI_SW_DI_N_PKT_WORD6(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD6)
88
89 #define HDMI_SW_DI_MAX_WORD 7
90
91 #define HDMI_IFRAME_DISABLED 0x0
92 #define HDMI_IFRAME_SINGLE_SHOT 0x1
93 #define HDMI_IFRAME_FIELD 0x2
94 #define HDMI_IFRAME_FRAME 0x3
95 #define HDMI_IFRAME_MASK 0x3
96 #define HDMI_IFRAME_CFG_DI_N(x, n) ((x) << ((n-1)*4)) /* n from 1 to 6 */
97
98 #define HDMI_CFG_DEVICE_EN BIT(0)
99 #define HDMI_CFG_HDMI_NOT_DVI BIT(1)
100 #define HDMI_CFG_HDCP_EN BIT(2)
101 #define HDMI_CFG_ESS_NOT_OESS BIT(3)
102 #define HDMI_CFG_H_SYNC_POL_NEG BIT(4)
103 #define HDMI_CFG_V_SYNC_POL_NEG BIT(6)
104 #define HDMI_CFG_422_EN BIT(8)
105 #define HDMI_CFG_FIFO_OVERRUN_CLR BIT(12)
106 #define HDMI_CFG_FIFO_UNDERRUN_CLR BIT(13)
107 #define HDMI_CFG_SW_RST_EN BIT(31)
108
109 #define HDMI_INT_GLOBAL BIT(0)
110 #define HDMI_INT_SW_RST BIT(1)
111 #define HDMI_INT_PIX_CAP BIT(3)
112 #define HDMI_INT_HOT_PLUG BIT(4)
113 #define HDMI_INT_DLL_LCK BIT(5)
114 #define HDMI_INT_NEW_FRAME BIT(6)
115 #define HDMI_INT_GENCTRL_PKT BIT(7)
116 #define HDMI_INT_AUDIO_FIFO_XRUN BIT(8)
117 #define HDMI_INT_SINK_TERM_PRESENT BIT(11)
118
119 #define HDMI_DEFAULT_INT (HDMI_INT_SINK_TERM_PRESENT \
120 | HDMI_INT_DLL_LCK \
121 | HDMI_INT_HOT_PLUG \
122 | HDMI_INT_GLOBAL)
123
124 #define HDMI_WORKING_INT (HDMI_INT_SINK_TERM_PRESENT \
125 | HDMI_INT_AUDIO_FIFO_XRUN \
126 | HDMI_INT_GENCTRL_PKT \
127 | HDMI_INT_NEW_FRAME \
128 | HDMI_INT_DLL_LCK \
129 | HDMI_INT_HOT_PLUG \
130 | HDMI_INT_PIX_CAP \
131 | HDMI_INT_SW_RST \
132 | HDMI_INT_GLOBAL)
133
134 #define HDMI_STA_SW_RST BIT(1)
135
136 #define HDMI_AUD_CFG_8CH BIT(0)
137 #define HDMI_AUD_CFG_SPDIF_DIV_2 BIT(1)
138 #define HDMI_AUD_CFG_SPDIF_DIV_3 BIT(2)
139 #define HDMI_AUD_CFG_SPDIF_CLK_DIV_4 (BIT(1) | BIT(2))
140 #define HDMI_AUD_CFG_CTS_CLK_256FS BIT(12)
141 #define HDMI_AUD_CFG_DTS_INVALID BIT(16)
142 #define HDMI_AUD_CFG_ONE_BIT_INVALID (BIT(18) | BIT(19) | BIT(20) | BIT(21))
143 #define HDMI_AUD_CFG_CH12_VALID BIT(28)
144 #define HDMI_AUD_CFG_CH34_VALID BIT(29)
145 #define HDMI_AUD_CFG_CH56_VALID BIT(30)
146 #define HDMI_AUD_CFG_CH78_VALID BIT(31)
147
148 /* sample flat mask */
149 #define HDMI_SAMPLE_FLAT_NO 0
150 #define HDMI_SAMPLE_FLAT_SP0 BIT(0)
151 #define HDMI_SAMPLE_FLAT_SP1 BIT(1)
152 #define HDMI_SAMPLE_FLAT_SP2 BIT(2)
153 #define HDMI_SAMPLE_FLAT_SP3 BIT(3)
154 #define HDMI_SAMPLE_FLAT_ALL (HDMI_SAMPLE_FLAT_SP0 | HDMI_SAMPLE_FLAT_SP1 |\
155 HDMI_SAMPLE_FLAT_SP2 | HDMI_SAMPLE_FLAT_SP3)
156
157 #define HDMI_INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0)
158 #define HDMI_INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8)
159 #define HDMI_INFOFRAME_HEADER_LEN(x) (((x) & 0x0f) << 16)
160
161 struct sti_hdmi_connector {
162 struct drm_connector drm_connector;
163 struct drm_encoder *encoder;
164 struct sti_hdmi *hdmi;
165 struct drm_property *colorspace_property;
166 };
167
168 #define to_sti_hdmi_connector(x) \
169 container_of(x, struct sti_hdmi_connector, drm_connector)
170
171 static const struct drm_prop_enum_list colorspace_mode_names[] = {
172 { HDMI_COLORSPACE_RGB, "rgb" },
173 { HDMI_COLORSPACE_YUV422, "yuv422" },
174 { HDMI_COLORSPACE_YUV444, "yuv444" },
175 };
176
hdmi_read(struct sti_hdmi * hdmi,int offset)177 u32 hdmi_read(struct sti_hdmi *hdmi, int offset)
178 {
179 return readl(hdmi->regs + offset);
180 }
181
hdmi_write(struct sti_hdmi * hdmi,u32 val,int offset)182 void hdmi_write(struct sti_hdmi *hdmi, u32 val, int offset)
183 {
184 writel(val, hdmi->regs + offset);
185 }
186
187 /*
188 * HDMI interrupt handler threaded
189 *
190 * @irq: irq number
191 * @arg: connector structure
192 */
hdmi_irq_thread(int irq,void * arg)193 static irqreturn_t hdmi_irq_thread(int irq, void *arg)
194 {
195 struct sti_hdmi *hdmi = arg;
196
197 /* Hot plug/unplug IRQ */
198 if (hdmi->irq_status & HDMI_INT_HOT_PLUG) {
199 hdmi->hpd = readl(hdmi->regs + HDMI_STA) & HDMI_STA_HOT_PLUG;
200 if (hdmi->drm_dev)
201 drm_helper_hpd_irq_event(hdmi->drm_dev);
202 }
203
204 /* Sw reset and PLL lock are exclusive so we can use the same
205 * event to signal them
206 */
207 if (hdmi->irq_status & (HDMI_INT_SW_RST | HDMI_INT_DLL_LCK)) {
208 hdmi->event_received = true;
209 wake_up_interruptible(&hdmi->wait_event);
210 }
211
212 /* Audio FIFO underrun IRQ */
213 if (hdmi->irq_status & HDMI_INT_AUDIO_FIFO_XRUN)
214 DRM_INFO("Warning: audio FIFO underrun occurs!\n");
215
216 return IRQ_HANDLED;
217 }
218
219 /*
220 * HDMI interrupt handler
221 *
222 * @irq: irq number
223 * @arg: connector structure
224 */
hdmi_irq(int irq,void * arg)225 static irqreturn_t hdmi_irq(int irq, void *arg)
226 {
227 struct sti_hdmi *hdmi = arg;
228
229 /* read interrupt status */
230 hdmi->irq_status = hdmi_read(hdmi, HDMI_INT_STA);
231
232 /* clear interrupt status */
233 hdmi_write(hdmi, hdmi->irq_status, HDMI_INT_CLR);
234
235 /* force sync bus write */
236 hdmi_read(hdmi, HDMI_INT_STA);
237
238 return IRQ_WAKE_THREAD;
239 }
240
241 /*
242 * Set hdmi active area depending on the drm display mode selected
243 *
244 * @hdmi: pointer on the hdmi internal structure
245 */
hdmi_active_area(struct sti_hdmi * hdmi)246 static void hdmi_active_area(struct sti_hdmi *hdmi)
247 {
248 u32 xmin, xmax;
249 u32 ymin, ymax;
250
251 xmin = sti_vtg_get_pixel_number(hdmi->mode, 1);
252 xmax = sti_vtg_get_pixel_number(hdmi->mode, hdmi->mode.hdisplay);
253 ymin = sti_vtg_get_line_number(hdmi->mode, 0);
254 ymax = sti_vtg_get_line_number(hdmi->mode, hdmi->mode.vdisplay - 1);
255
256 hdmi_write(hdmi, xmin, HDMI_ACTIVE_VID_XMIN);
257 hdmi_write(hdmi, xmax, HDMI_ACTIVE_VID_XMAX);
258 hdmi_write(hdmi, ymin, HDMI_ACTIVE_VID_YMIN);
259 hdmi_write(hdmi, ymax, HDMI_ACTIVE_VID_YMAX);
260 }
261
262 /*
263 * Overall hdmi configuration
264 *
265 * @hdmi: pointer on the hdmi internal structure
266 */
hdmi_config(struct sti_hdmi * hdmi)267 static void hdmi_config(struct sti_hdmi *hdmi)
268 {
269 u32 conf;
270
271 DRM_DEBUG_DRIVER("\n");
272
273 /* Clear overrun and underrun fifo */
274 conf = HDMI_CFG_FIFO_OVERRUN_CLR | HDMI_CFG_FIFO_UNDERRUN_CLR;
275
276 /* Select encryption type and the framing mode */
277 conf |= HDMI_CFG_ESS_NOT_OESS;
278 if (hdmi->hdmi_monitor)
279 conf |= HDMI_CFG_HDMI_NOT_DVI;
280
281 /* Set Hsync polarity */
282 if (hdmi->mode.flags & DRM_MODE_FLAG_NHSYNC) {
283 DRM_DEBUG_DRIVER("H Sync Negative\n");
284 conf |= HDMI_CFG_H_SYNC_POL_NEG;
285 }
286
287 /* Set Vsync polarity */
288 if (hdmi->mode.flags & DRM_MODE_FLAG_NVSYNC) {
289 DRM_DEBUG_DRIVER("V Sync Negative\n");
290 conf |= HDMI_CFG_V_SYNC_POL_NEG;
291 }
292
293 /* Enable HDMI */
294 conf |= HDMI_CFG_DEVICE_EN;
295
296 hdmi_write(hdmi, conf, HDMI_CFG);
297 }
298
299 /*
300 * Helper to reset info frame
301 *
302 * @hdmi: pointer on the hdmi internal structure
303 * @slot: infoframe to reset
304 */
hdmi_infoframe_reset(struct sti_hdmi * hdmi,u32 slot)305 static void hdmi_infoframe_reset(struct sti_hdmi *hdmi,
306 u32 slot)
307 {
308 u32 val, i;
309 u32 head_offset, pack_offset;
310
311 switch (slot) {
312 case HDMI_IFRAME_SLOT_AVI:
313 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI);
314 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI);
315 break;
316 case HDMI_IFRAME_SLOT_AUDIO:
317 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AUDIO);
318 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AUDIO);
319 break;
320 case HDMI_IFRAME_SLOT_VENDOR:
321 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_VENDOR);
322 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_VENDOR);
323 break;
324 default:
325 DRM_ERROR("unsupported infoframe slot: %#x\n", slot);
326 return;
327 }
328
329 /* Disable transmission for the selected slot */
330 val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
331 val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, slot);
332 hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
333
334 /* Reset info frame registers */
335 hdmi_write(hdmi, 0x0, head_offset);
336 for (i = 0; i < HDMI_SW_DI_MAX_WORD; i += sizeof(u32))
337 hdmi_write(hdmi, 0x0, pack_offset + i);
338 }
339
340 /*
341 * Helper to concatenate infoframe in 32 bits word
342 *
343 * @ptr: pointer on the hdmi internal structure
344 * @size: size to write
345 */
hdmi_infoframe_subpack(const u8 * ptr,size_t size)346 static inline unsigned int hdmi_infoframe_subpack(const u8 *ptr, size_t size)
347 {
348 unsigned long value = 0;
349 size_t i;
350
351 for (i = size; i > 0; i--)
352 value = (value << 8) | ptr[i - 1];
353
354 return value;
355 }
356
357 /*
358 * Helper to write info frame
359 *
360 * @hdmi: pointer on the hdmi internal structure
361 * @data: infoframe to write
362 * @size: size to write
363 */
hdmi_infoframe_write_infopack(struct sti_hdmi * hdmi,const u8 * data,size_t size)364 static void hdmi_infoframe_write_infopack(struct sti_hdmi *hdmi,
365 const u8 *data,
366 size_t size)
367 {
368 const u8 *ptr = data;
369 u32 val, slot, mode, i;
370 u32 head_offset, pack_offset;
371
372 switch (*ptr) {
373 case HDMI_INFOFRAME_TYPE_AVI:
374 slot = HDMI_IFRAME_SLOT_AVI;
375 mode = HDMI_IFRAME_FIELD;
376 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI);
377 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI);
378 break;
379 case HDMI_INFOFRAME_TYPE_AUDIO:
380 slot = HDMI_IFRAME_SLOT_AUDIO;
381 mode = HDMI_IFRAME_FRAME;
382 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AUDIO);
383 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AUDIO);
384 break;
385 case HDMI_INFOFRAME_TYPE_VENDOR:
386 slot = HDMI_IFRAME_SLOT_VENDOR;
387 mode = HDMI_IFRAME_FRAME;
388 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_VENDOR);
389 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_VENDOR);
390 break;
391 default:
392 DRM_ERROR("unsupported infoframe type: %#x\n", *ptr);
393 return;
394 }
395
396 /* Disable transmission slot for updated infoframe */
397 val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
398 val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, slot);
399 hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
400
401 val = HDMI_INFOFRAME_HEADER_TYPE(*ptr++);
402 val |= HDMI_INFOFRAME_HEADER_VERSION(*ptr++);
403 val |= HDMI_INFOFRAME_HEADER_LEN(*ptr++);
404 writel(val, hdmi->regs + head_offset);
405
406 /*
407 * Each subpack contains 4 bytes
408 * The First Bytes of the first subpacket must contain the checksum
409 * Packet size is increase by one.
410 */
411 size = size - HDMI_INFOFRAME_HEADER_SIZE + 1;
412 for (i = 0; i < size; i += sizeof(u32)) {
413 size_t num;
414
415 num = min_t(size_t, size - i, sizeof(u32));
416 val = hdmi_infoframe_subpack(ptr, num);
417 ptr += sizeof(u32);
418 writel(val, hdmi->regs + pack_offset + i);
419 }
420
421 /* Enable transmission slot for updated infoframe */
422 val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
423 val |= HDMI_IFRAME_CFG_DI_N(mode, slot);
424 hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
425 }
426
427 /*
428 * Prepare and configure the AVI infoframe
429 *
430 * AVI infoframe are transmitted at least once per two video field and
431 * contains information about HDMI transmission mode such as color space,
432 * colorimetry, ...
433 *
434 * @hdmi: pointer on the hdmi internal structure
435 *
436 * Return negative value if error occurs
437 */
hdmi_avi_infoframe_config(struct sti_hdmi * hdmi)438 static int hdmi_avi_infoframe_config(struct sti_hdmi *hdmi)
439 {
440 struct drm_display_mode *mode = &hdmi->mode;
441 struct hdmi_avi_infoframe infoframe;
442 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
443 int ret;
444
445 DRM_DEBUG_DRIVER("\n");
446
447 ret = drm_hdmi_avi_infoframe_from_display_mode(&infoframe,
448 hdmi->drm_connector, mode);
449 if (ret < 0) {
450 DRM_ERROR("failed to setup AVI infoframe: %d\n", ret);
451 return ret;
452 }
453
454 /* fixed infoframe configuration not linked to the mode */
455 infoframe.colorspace = hdmi->colorspace;
456 infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
457 infoframe.colorimetry = HDMI_COLORIMETRY_NONE;
458
459 ret = hdmi_avi_infoframe_pack(&infoframe, buffer, sizeof(buffer));
460 if (ret < 0) {
461 DRM_ERROR("failed to pack AVI infoframe: %d\n", ret);
462 return ret;
463 }
464
465 hdmi_infoframe_write_infopack(hdmi, buffer, ret);
466
467 return 0;
468 }
469
470 /*
471 * Prepare and configure the AUDIO infoframe
472 *
473 * AUDIO infoframe are transmitted once per frame and
474 * contains information about HDMI transmission mode such as audio codec,
475 * sample size, ...
476 *
477 * @hdmi: pointer on the hdmi internal structure
478 *
479 * Return negative value if error occurs
480 */
hdmi_audio_infoframe_config(struct sti_hdmi * hdmi)481 static int hdmi_audio_infoframe_config(struct sti_hdmi *hdmi)
482 {
483 struct hdmi_audio_params *audio = &hdmi->audio;
484 u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
485 int ret, val;
486
487 DRM_DEBUG_DRIVER("enter %s, AIF %s\n", __func__,
488 audio->enabled ? "enable" : "disable");
489 if (audio->enabled) {
490 /* set audio parameters stored*/
491 ret = hdmi_audio_infoframe_pack(&audio->cea, buffer,
492 sizeof(buffer));
493 if (ret < 0) {
494 DRM_ERROR("failed to pack audio infoframe: %d\n", ret);
495 return ret;
496 }
497 hdmi_infoframe_write_infopack(hdmi, buffer, ret);
498 } else {
499 /*disable audio info frame transmission */
500 val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
501 val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK,
502 HDMI_IFRAME_SLOT_AUDIO);
503 hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
504 }
505
506 return 0;
507 }
508
509 /*
510 * Prepare and configure the VS infoframe
511 *
512 * Vendor Specific infoframe are transmitted once per frame and
513 * contains vendor specific information.
514 *
515 * @hdmi: pointer on the hdmi internal structure
516 *
517 * Return negative value if error occurs
518 */
519 #define HDMI_VENDOR_INFOFRAME_MAX_SIZE 6
hdmi_vendor_infoframe_config(struct sti_hdmi * hdmi)520 static int hdmi_vendor_infoframe_config(struct sti_hdmi *hdmi)
521 {
522 struct drm_display_mode *mode = &hdmi->mode;
523 struct hdmi_vendor_infoframe infoframe;
524 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_VENDOR_INFOFRAME_MAX_SIZE];
525 int ret;
526
527 DRM_DEBUG_DRIVER("\n");
528
529 ret = drm_hdmi_vendor_infoframe_from_display_mode(&infoframe,
530 hdmi->drm_connector,
531 mode);
532 if (ret < 0) {
533 /*
534 * Going into that statement does not means vendor infoframe
535 * fails. It just informed us that vendor infoframe is not
536 * needed for the selected mode. Only 4k or stereoscopic 3D
537 * mode requires vendor infoframe. So just simply return 0.
538 */
539 return 0;
540 }
541
542 ret = hdmi_vendor_infoframe_pack(&infoframe, buffer, sizeof(buffer));
543 if (ret < 0) {
544 DRM_ERROR("failed to pack VS infoframe: %d\n", ret);
545 return ret;
546 }
547
548 hdmi_infoframe_write_infopack(hdmi, buffer, ret);
549
550 return 0;
551 }
552
553 #define HDMI_TIMEOUT_SWRESET 100 /*milliseconds */
554
555 /*
556 * Software reset of the hdmi subsystem
557 *
558 * @hdmi: pointer on the hdmi internal structure
559 *
560 */
hdmi_swreset(struct sti_hdmi * hdmi)561 static void hdmi_swreset(struct sti_hdmi *hdmi)
562 {
563 u32 val;
564
565 DRM_DEBUG_DRIVER("\n");
566
567 /* Enable hdmi_audio clock only during hdmi reset */
568 if (clk_prepare_enable(hdmi->clk_audio))
569 DRM_INFO("Failed to prepare/enable hdmi_audio clk\n");
570
571 /* Sw reset */
572 hdmi->event_received = false;
573
574 val = hdmi_read(hdmi, HDMI_CFG);
575 val |= HDMI_CFG_SW_RST_EN;
576 hdmi_write(hdmi, val, HDMI_CFG);
577
578 /* Wait reset completed */
579 wait_event_interruptible_timeout(hdmi->wait_event,
580 hdmi->event_received,
581 msecs_to_jiffies
582 (HDMI_TIMEOUT_SWRESET));
583
584 /*
585 * HDMI_STA_SW_RST bit is set to '1' when SW_RST bit in HDMI_CFG is
586 * set to '1' and clk_audio is running.
587 */
588 if ((hdmi_read(hdmi, HDMI_STA) & HDMI_STA_SW_RST) == 0)
589 DRM_DEBUG_DRIVER("Warning: HDMI sw reset timeout occurs\n");
590
591 val = hdmi_read(hdmi, HDMI_CFG);
592 val &= ~HDMI_CFG_SW_RST_EN;
593 hdmi_write(hdmi, val, HDMI_CFG);
594
595 /* Disable hdmi_audio clock. Not used anymore for drm purpose */
596 clk_disable_unprepare(hdmi->clk_audio);
597 }
598
599 #define DBGFS_PRINT_STR(str1, str2) seq_printf(s, "%-24s %s\n", str1, str2)
600 #define DBGFS_PRINT_INT(str1, int2) seq_printf(s, "%-24s %d\n", str1, int2)
601 #define DBGFS_DUMP(str, reg) seq_printf(s, "%s %-25s 0x%08X", str, #reg, \
602 hdmi_read(hdmi, reg))
603 #define DBGFS_DUMP_DI(reg, slot) DBGFS_DUMP("\n", reg(slot))
604
hdmi_dbg_cfg(struct seq_file * s,int val)605 static void hdmi_dbg_cfg(struct seq_file *s, int val)
606 {
607 int tmp;
608
609 seq_putc(s, '\t');
610 tmp = val & HDMI_CFG_HDMI_NOT_DVI;
611 DBGFS_PRINT_STR("mode:", tmp ? "HDMI" : "DVI");
612 seq_puts(s, "\t\t\t\t\t");
613 tmp = val & HDMI_CFG_HDCP_EN;
614 DBGFS_PRINT_STR("HDCP:", tmp ? "enable" : "disable");
615 seq_puts(s, "\t\t\t\t\t");
616 tmp = val & HDMI_CFG_ESS_NOT_OESS;
617 DBGFS_PRINT_STR("HDCP mode:", tmp ? "ESS enable" : "OESS enable");
618 seq_puts(s, "\t\t\t\t\t");
619 tmp = val & HDMI_CFG_H_SYNC_POL_NEG;
620 DBGFS_PRINT_STR("Hsync polarity:", tmp ? "inverted" : "normal");
621 seq_puts(s, "\t\t\t\t\t");
622 tmp = val & HDMI_CFG_V_SYNC_POL_NEG;
623 DBGFS_PRINT_STR("Vsync polarity:", tmp ? "inverted" : "normal");
624 seq_puts(s, "\t\t\t\t\t");
625 tmp = val & HDMI_CFG_422_EN;
626 DBGFS_PRINT_STR("YUV422 format:", tmp ? "enable" : "disable");
627 }
628
hdmi_dbg_sta(struct seq_file * s,int val)629 static void hdmi_dbg_sta(struct seq_file *s, int val)
630 {
631 int tmp;
632
633 seq_putc(s, '\t');
634 tmp = (val & HDMI_STA_DLL_LCK);
635 DBGFS_PRINT_STR("pll:", tmp ? "locked" : "not locked");
636 seq_puts(s, "\t\t\t\t\t");
637 tmp = (val & HDMI_STA_HOT_PLUG);
638 DBGFS_PRINT_STR("hdmi cable:", tmp ? "connected" : "not connected");
639 }
640
hdmi_dbg_sw_di_cfg(struct seq_file * s,int val)641 static void hdmi_dbg_sw_di_cfg(struct seq_file *s, int val)
642 {
643 int tmp;
644 char *const en_di[] = {"no transmission",
645 "single transmission",
646 "once every field",
647 "once every frame"};
648
649 seq_putc(s, '\t');
650 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 1));
651 DBGFS_PRINT_STR("Data island 1:", en_di[tmp]);
652 seq_puts(s, "\t\t\t\t\t");
653 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 2)) >> 4;
654 DBGFS_PRINT_STR("Data island 2:", en_di[tmp]);
655 seq_puts(s, "\t\t\t\t\t");
656 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 3)) >> 8;
657 DBGFS_PRINT_STR("Data island 3:", en_di[tmp]);
658 seq_puts(s, "\t\t\t\t\t");
659 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 4)) >> 12;
660 DBGFS_PRINT_STR("Data island 4:", en_di[tmp]);
661 seq_puts(s, "\t\t\t\t\t");
662 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 5)) >> 16;
663 DBGFS_PRINT_STR("Data island 5:", en_di[tmp]);
664 seq_puts(s, "\t\t\t\t\t");
665 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 6)) >> 20;
666 DBGFS_PRINT_STR("Data island 6:", en_di[tmp]);
667 }
668
hdmi_dbg_show(struct seq_file * s,void * data)669 static int hdmi_dbg_show(struct seq_file *s, void *data)
670 {
671 struct drm_info_node *node = s->private;
672 struct sti_hdmi *hdmi = (struct sti_hdmi *)node->info_ent->data;
673
674 seq_printf(s, "HDMI: (vaddr = 0x%p)", hdmi->regs);
675 DBGFS_DUMP("\n", HDMI_CFG);
676 hdmi_dbg_cfg(s, hdmi_read(hdmi, HDMI_CFG));
677 DBGFS_DUMP("", HDMI_INT_EN);
678 DBGFS_DUMP("\n", HDMI_STA);
679 hdmi_dbg_sta(s, hdmi_read(hdmi, HDMI_STA));
680 DBGFS_DUMP("", HDMI_ACTIVE_VID_XMIN);
681 seq_putc(s, '\t');
682 DBGFS_PRINT_INT("Xmin:", hdmi_read(hdmi, HDMI_ACTIVE_VID_XMIN));
683 DBGFS_DUMP("", HDMI_ACTIVE_VID_XMAX);
684 seq_putc(s, '\t');
685 DBGFS_PRINT_INT("Xmax:", hdmi_read(hdmi, HDMI_ACTIVE_VID_XMAX));
686 DBGFS_DUMP("", HDMI_ACTIVE_VID_YMIN);
687 seq_putc(s, '\t');
688 DBGFS_PRINT_INT("Ymin:", hdmi_read(hdmi, HDMI_ACTIVE_VID_YMIN));
689 DBGFS_DUMP("", HDMI_ACTIVE_VID_YMAX);
690 seq_putc(s, '\t');
691 DBGFS_PRINT_INT("Ymax:", hdmi_read(hdmi, HDMI_ACTIVE_VID_YMAX));
692 DBGFS_DUMP("", HDMI_SW_DI_CFG);
693 hdmi_dbg_sw_di_cfg(s, hdmi_read(hdmi, HDMI_SW_DI_CFG));
694
695 DBGFS_DUMP("\n", HDMI_AUDIO_CFG);
696 DBGFS_DUMP("\n", HDMI_SPDIF_FIFO_STATUS);
697 DBGFS_DUMP("\n", HDMI_AUDN);
698
699 seq_printf(s, "\n AVI Infoframe (Data Island slot N=%d):",
700 HDMI_IFRAME_SLOT_AVI);
701 DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_AVI);
702 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_AVI);
703 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_AVI);
704 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_AVI);
705 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_AVI);
706 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_AVI);
707 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_AVI);
708 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_AVI);
709 seq_printf(s, "\n\n AUDIO Infoframe (Data Island slot N=%d):",
710 HDMI_IFRAME_SLOT_AUDIO);
711 DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_AUDIO);
712 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_AUDIO);
713 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_AUDIO);
714 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_AUDIO);
715 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_AUDIO);
716 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_AUDIO);
717 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_AUDIO);
718 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_AUDIO);
719 seq_printf(s, "\n\n VENDOR SPECIFIC Infoframe (Data Island slot N=%d):",
720 HDMI_IFRAME_SLOT_VENDOR);
721 DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_VENDOR);
722 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_VENDOR);
723 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_VENDOR);
724 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_VENDOR);
725 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_VENDOR);
726 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_VENDOR);
727 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_VENDOR);
728 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_VENDOR);
729 seq_putc(s, '\n');
730 return 0;
731 }
732
733 static struct drm_info_list hdmi_debugfs_files[] = {
734 { "hdmi", hdmi_dbg_show, 0, NULL },
735 };
736
hdmi_debugfs_init(struct sti_hdmi * hdmi,struct drm_minor * minor)737 static void hdmi_debugfs_init(struct sti_hdmi *hdmi, struct drm_minor *minor)
738 {
739 unsigned int i;
740
741 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_files); i++)
742 hdmi_debugfs_files[i].data = hdmi;
743
744 drm_debugfs_create_files(hdmi_debugfs_files,
745 ARRAY_SIZE(hdmi_debugfs_files),
746 minor->debugfs_root, minor);
747 }
748
sti_hdmi_disable(struct drm_bridge * bridge)749 static void sti_hdmi_disable(struct drm_bridge *bridge)
750 {
751 struct sti_hdmi *hdmi = bridge->driver_private;
752
753 u32 val = hdmi_read(hdmi, HDMI_CFG);
754
755 if (!hdmi->enabled)
756 return;
757
758 DRM_DEBUG_DRIVER("\n");
759
760 /* Disable HDMI */
761 val &= ~HDMI_CFG_DEVICE_EN;
762 hdmi_write(hdmi, val, HDMI_CFG);
763
764 hdmi_write(hdmi, 0xffffffff, HDMI_INT_CLR);
765
766 /* Stop the phy */
767 hdmi->phy_ops->stop(hdmi);
768
769 /* Reset info frame transmission */
770 hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_AVI);
771 hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_AUDIO);
772 hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_VENDOR);
773
774 /* Set the default channel data to be a dark red */
775 hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL0_DAT);
776 hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL1_DAT);
777 hdmi_write(hdmi, 0x0060, HDMI_DFLT_CHL2_DAT);
778
779 /* Disable/unprepare hdmi clock */
780 clk_disable_unprepare(hdmi->clk_phy);
781 clk_disable_unprepare(hdmi->clk_tmds);
782 clk_disable_unprepare(hdmi->clk_pix);
783
784 hdmi->enabled = false;
785
786 cec_notifier_set_phys_addr(hdmi->notifier, CEC_PHYS_ADDR_INVALID);
787 }
788
789 /*
790 * sti_hdmi_audio_get_non_coherent_n() - get N parameter for non-coherent
791 * clocks. None-coherent clocks means that audio and TMDS clocks have not the
792 * same source (drifts between clocks). In this case assumption is that CTS is
793 * automatically calculated by hardware.
794 *
795 * @audio_fs: audio frame clock frequency in Hz
796 *
797 * Values computed are based on table described in HDMI specification 1.4b
798 *
799 * Returns n value.
800 */
sti_hdmi_audio_get_non_coherent_n(unsigned int audio_fs)801 static int sti_hdmi_audio_get_non_coherent_n(unsigned int audio_fs)
802 {
803 unsigned int n;
804
805 switch (audio_fs) {
806 case 32000:
807 n = 4096;
808 break;
809 case 44100:
810 n = 6272;
811 break;
812 case 48000:
813 n = 6144;
814 break;
815 case 88200:
816 n = 6272 * 2;
817 break;
818 case 96000:
819 n = 6144 * 2;
820 break;
821 case 176400:
822 n = 6272 * 4;
823 break;
824 case 192000:
825 n = 6144 * 4;
826 break;
827 default:
828 /* Not pre-defined, recommended value: 128 * fs / 1000 */
829 n = (audio_fs * 128) / 1000;
830 }
831
832 return n;
833 }
834
hdmi_audio_configure(struct sti_hdmi * hdmi)835 static int hdmi_audio_configure(struct sti_hdmi *hdmi)
836 {
837 int audio_cfg, n;
838 struct hdmi_audio_params *params = &hdmi->audio;
839 struct hdmi_audio_infoframe *info = ¶ms->cea;
840
841 DRM_DEBUG_DRIVER("\n");
842
843 if (!hdmi->enabled)
844 return 0;
845
846 /* update N parameter */
847 n = sti_hdmi_audio_get_non_coherent_n(params->sample_rate);
848
849 DRM_DEBUG_DRIVER("Audio rate = %d Hz, TMDS clock = %d Hz, n = %d\n",
850 params->sample_rate, hdmi->mode.clock * 1000, n);
851 hdmi_write(hdmi, n, HDMI_AUDN);
852
853 /* update HDMI registers according to configuration */
854 audio_cfg = HDMI_AUD_CFG_SPDIF_DIV_2 | HDMI_AUD_CFG_DTS_INVALID |
855 HDMI_AUD_CFG_ONE_BIT_INVALID;
856
857 switch (info->channels) {
858 case 8:
859 audio_cfg |= HDMI_AUD_CFG_CH78_VALID;
860 fallthrough;
861 case 6:
862 audio_cfg |= HDMI_AUD_CFG_CH56_VALID;
863 fallthrough;
864 case 4:
865 audio_cfg |= HDMI_AUD_CFG_CH34_VALID | HDMI_AUD_CFG_8CH;
866 fallthrough;
867 case 2:
868 audio_cfg |= HDMI_AUD_CFG_CH12_VALID;
869 break;
870 default:
871 DRM_ERROR("ERROR: Unsupported number of channels (%d)!\n",
872 info->channels);
873 return -EINVAL;
874 }
875
876 hdmi_write(hdmi, audio_cfg, HDMI_AUDIO_CFG);
877
878 return hdmi_audio_infoframe_config(hdmi);
879 }
880
sti_hdmi_pre_enable(struct drm_bridge * bridge)881 static void sti_hdmi_pre_enable(struct drm_bridge *bridge)
882 {
883 struct sti_hdmi *hdmi = bridge->driver_private;
884
885 DRM_DEBUG_DRIVER("\n");
886
887 if (hdmi->enabled)
888 return;
889
890 /* Prepare/enable clocks */
891 if (clk_prepare_enable(hdmi->clk_pix))
892 DRM_ERROR("Failed to prepare/enable hdmi_pix clk\n");
893 if (clk_prepare_enable(hdmi->clk_tmds))
894 DRM_ERROR("Failed to prepare/enable hdmi_tmds clk\n");
895 if (clk_prepare_enable(hdmi->clk_phy))
896 DRM_ERROR("Failed to prepare/enable hdmi_rejection_pll clk\n");
897
898 hdmi->enabled = true;
899
900 /* Program hdmi serializer and start phy */
901 if (!hdmi->phy_ops->start(hdmi)) {
902 DRM_ERROR("Unable to start hdmi phy\n");
903 return;
904 }
905
906 /* Program hdmi active area */
907 hdmi_active_area(hdmi);
908
909 /* Enable working interrupts */
910 hdmi_write(hdmi, HDMI_WORKING_INT, HDMI_INT_EN);
911
912 /* Program hdmi config */
913 hdmi_config(hdmi);
914
915 /* Program AVI infoframe */
916 if (hdmi_avi_infoframe_config(hdmi))
917 DRM_ERROR("Unable to configure AVI infoframe\n");
918
919 if (hdmi->audio.enabled) {
920 if (hdmi_audio_configure(hdmi))
921 DRM_ERROR("Unable to configure audio\n");
922 } else {
923 hdmi_audio_infoframe_config(hdmi);
924 }
925
926 /* Program VS infoframe */
927 if (hdmi_vendor_infoframe_config(hdmi))
928 DRM_ERROR("Unable to configure VS infoframe\n");
929
930 /* Sw reset */
931 hdmi_swreset(hdmi);
932 }
933
sti_hdmi_set_mode(struct drm_bridge * bridge,const struct drm_display_mode * mode,const struct drm_display_mode * adjusted_mode)934 static void sti_hdmi_set_mode(struct drm_bridge *bridge,
935 const struct drm_display_mode *mode,
936 const struct drm_display_mode *adjusted_mode)
937 {
938 struct sti_hdmi *hdmi = bridge->driver_private;
939 int ret;
940
941 DRM_DEBUG_DRIVER("\n");
942
943 /* Copy the drm display mode in the connector local structure */
944 memcpy(&hdmi->mode, mode, sizeof(struct drm_display_mode));
945
946 /* Update clock framerate according to the selected mode */
947 ret = clk_set_rate(hdmi->clk_pix, mode->clock * 1000);
948 if (ret < 0) {
949 DRM_ERROR("Cannot set rate (%dHz) for hdmi_pix clk\n",
950 mode->clock * 1000);
951 return;
952 }
953 ret = clk_set_rate(hdmi->clk_phy, mode->clock * 1000);
954 if (ret < 0) {
955 DRM_ERROR("Cannot set rate (%dHz) for hdmi_rejection_pll clk\n",
956 mode->clock * 1000);
957 return;
958 }
959 }
960
sti_hdmi_bridge_nope(struct drm_bridge * bridge)961 static void sti_hdmi_bridge_nope(struct drm_bridge *bridge)
962 {
963 /* do nothing */
964 }
965
966 static const struct drm_bridge_funcs sti_hdmi_bridge_funcs = {
967 .pre_enable = sti_hdmi_pre_enable,
968 .enable = sti_hdmi_bridge_nope,
969 .disable = sti_hdmi_disable,
970 .post_disable = sti_hdmi_bridge_nope,
971 .mode_set = sti_hdmi_set_mode,
972 };
973
sti_hdmi_connector_get_modes(struct drm_connector * connector)974 static int sti_hdmi_connector_get_modes(struct drm_connector *connector)
975 {
976 struct sti_hdmi_connector *hdmi_connector
977 = to_sti_hdmi_connector(connector);
978 struct sti_hdmi *hdmi = hdmi_connector->hdmi;
979 struct edid *edid;
980 int count;
981
982 DRM_DEBUG_DRIVER("\n");
983
984 edid = drm_get_edid(connector, hdmi->ddc_adapt);
985 if (!edid)
986 goto fail;
987
988 hdmi->hdmi_monitor = drm_detect_hdmi_monitor(edid);
989 DRM_DEBUG_KMS("%s : %dx%d cm\n",
990 (hdmi->hdmi_monitor ? "hdmi monitor" : "dvi monitor"),
991 edid->width_cm, edid->height_cm);
992 cec_notifier_set_phys_addr_from_edid(hdmi->notifier, edid);
993
994 count = drm_add_edid_modes(connector, edid);
995 drm_connector_update_edid_property(connector, edid);
996
997 kfree(edid);
998 return count;
999
1000 fail:
1001 DRM_ERROR("Can't read HDMI EDID\n");
1002 return 0;
1003 }
1004
1005 #define CLK_TOLERANCE_HZ 50
1006
sti_hdmi_connector_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)1007 static int sti_hdmi_connector_mode_valid(struct drm_connector *connector,
1008 struct drm_display_mode *mode)
1009 {
1010 int target = mode->clock * 1000;
1011 int target_min = target - CLK_TOLERANCE_HZ;
1012 int target_max = target + CLK_TOLERANCE_HZ;
1013 int result;
1014 struct sti_hdmi_connector *hdmi_connector
1015 = to_sti_hdmi_connector(connector);
1016 struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1017
1018
1019 result = clk_round_rate(hdmi->clk_pix, target);
1020
1021 DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n",
1022 target, result);
1023
1024 if ((result < target_min) || (result > target_max)) {
1025 DRM_DEBUG_DRIVER("hdmi pixclk=%d not supported\n", target);
1026 return MODE_BAD;
1027 }
1028
1029 return MODE_OK;
1030 }
1031
1032 static const
1033 struct drm_connector_helper_funcs sti_hdmi_connector_helper_funcs = {
1034 .get_modes = sti_hdmi_connector_get_modes,
1035 .mode_valid = sti_hdmi_connector_mode_valid,
1036 };
1037
1038 /* get detection status of display device */
1039 static enum drm_connector_status
sti_hdmi_connector_detect(struct drm_connector * connector,bool force)1040 sti_hdmi_connector_detect(struct drm_connector *connector, bool force)
1041 {
1042 struct sti_hdmi_connector *hdmi_connector
1043 = to_sti_hdmi_connector(connector);
1044 struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1045
1046 DRM_DEBUG_DRIVER("\n");
1047
1048 if (hdmi->hpd) {
1049 DRM_DEBUG_DRIVER("hdmi cable connected\n");
1050 return connector_status_connected;
1051 }
1052
1053 DRM_DEBUG_DRIVER("hdmi cable disconnected\n");
1054 cec_notifier_set_phys_addr(hdmi->notifier, CEC_PHYS_ADDR_INVALID);
1055 return connector_status_disconnected;
1056 }
1057
sti_hdmi_connector_init_property(struct drm_device * drm_dev,struct drm_connector * connector)1058 static void sti_hdmi_connector_init_property(struct drm_device *drm_dev,
1059 struct drm_connector *connector)
1060 {
1061 struct sti_hdmi_connector *hdmi_connector
1062 = to_sti_hdmi_connector(connector);
1063 struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1064 struct drm_property *prop;
1065
1066 /* colorspace property */
1067 hdmi->colorspace = DEFAULT_COLORSPACE_MODE;
1068 prop = drm_property_create_enum(drm_dev, 0, "colorspace",
1069 colorspace_mode_names,
1070 ARRAY_SIZE(colorspace_mode_names));
1071 if (!prop) {
1072 DRM_ERROR("fails to create colorspace property\n");
1073 return;
1074 }
1075 hdmi_connector->colorspace_property = prop;
1076 drm_object_attach_property(&connector->base, prop, hdmi->colorspace);
1077 }
1078
1079 static int
sti_hdmi_connector_set_property(struct drm_connector * connector,struct drm_connector_state * state,struct drm_property * property,uint64_t val)1080 sti_hdmi_connector_set_property(struct drm_connector *connector,
1081 struct drm_connector_state *state,
1082 struct drm_property *property,
1083 uint64_t val)
1084 {
1085 struct sti_hdmi_connector *hdmi_connector
1086 = to_sti_hdmi_connector(connector);
1087 struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1088
1089 if (property == hdmi_connector->colorspace_property) {
1090 hdmi->colorspace = val;
1091 return 0;
1092 }
1093
1094 DRM_ERROR("failed to set hdmi connector property\n");
1095 return -EINVAL;
1096 }
1097
1098 static int
sti_hdmi_connector_get_property(struct drm_connector * connector,const struct drm_connector_state * state,struct drm_property * property,uint64_t * val)1099 sti_hdmi_connector_get_property(struct drm_connector *connector,
1100 const struct drm_connector_state *state,
1101 struct drm_property *property,
1102 uint64_t *val)
1103 {
1104 struct sti_hdmi_connector *hdmi_connector
1105 = to_sti_hdmi_connector(connector);
1106 struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1107
1108 if (property == hdmi_connector->colorspace_property) {
1109 *val = hdmi->colorspace;
1110 return 0;
1111 }
1112
1113 DRM_ERROR("failed to get hdmi connector property\n");
1114 return -EINVAL;
1115 }
1116
sti_hdmi_late_register(struct drm_connector * connector)1117 static int sti_hdmi_late_register(struct drm_connector *connector)
1118 {
1119 struct sti_hdmi_connector *hdmi_connector
1120 = to_sti_hdmi_connector(connector);
1121 struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1122
1123 hdmi_debugfs_init(hdmi, hdmi->drm_dev->primary);
1124
1125 return 0;
1126 }
1127
1128 static const struct drm_connector_funcs sti_hdmi_connector_funcs = {
1129 .fill_modes = drm_helper_probe_single_connector_modes,
1130 .detect = sti_hdmi_connector_detect,
1131 .destroy = drm_connector_cleanup,
1132 .reset = drm_atomic_helper_connector_reset,
1133 .atomic_set_property = sti_hdmi_connector_set_property,
1134 .atomic_get_property = sti_hdmi_connector_get_property,
1135 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1136 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1137 .late_register = sti_hdmi_late_register,
1138 };
1139
sti_hdmi_find_encoder(struct drm_device * dev)1140 static struct drm_encoder *sti_hdmi_find_encoder(struct drm_device *dev)
1141 {
1142 struct drm_encoder *encoder;
1143
1144 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1145 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1146 return encoder;
1147 }
1148
1149 return NULL;
1150 }
1151
hdmi_audio_shutdown(struct device * dev,void * data)1152 static void hdmi_audio_shutdown(struct device *dev, void *data)
1153 {
1154 struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1155 int audio_cfg;
1156
1157 DRM_DEBUG_DRIVER("\n");
1158
1159 /* disable audio */
1160 audio_cfg = HDMI_AUD_CFG_SPDIF_DIV_2 | HDMI_AUD_CFG_DTS_INVALID |
1161 HDMI_AUD_CFG_ONE_BIT_INVALID;
1162 hdmi_write(hdmi, audio_cfg, HDMI_AUDIO_CFG);
1163
1164 hdmi->audio.enabled = false;
1165 hdmi_audio_infoframe_config(hdmi);
1166 }
1167
hdmi_audio_hw_params(struct device * dev,void * data,struct hdmi_codec_daifmt * daifmt,struct hdmi_codec_params * params)1168 static int hdmi_audio_hw_params(struct device *dev,
1169 void *data,
1170 struct hdmi_codec_daifmt *daifmt,
1171 struct hdmi_codec_params *params)
1172 {
1173 struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1174 int ret;
1175
1176 DRM_DEBUG_DRIVER("\n");
1177
1178 if ((daifmt->fmt != HDMI_I2S) || daifmt->bit_clk_inv ||
1179 daifmt->frame_clk_inv || daifmt->bit_clk_provider ||
1180 daifmt->frame_clk_provider) {
1181 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__,
1182 daifmt->bit_clk_inv, daifmt->frame_clk_inv,
1183 daifmt->bit_clk_provider,
1184 daifmt->frame_clk_provider);
1185 return -EINVAL;
1186 }
1187
1188 hdmi->audio.sample_width = params->sample_width;
1189 hdmi->audio.sample_rate = params->sample_rate;
1190 hdmi->audio.cea = params->cea;
1191
1192 hdmi->audio.enabled = true;
1193
1194 ret = hdmi_audio_configure(hdmi);
1195 if (ret < 0)
1196 return ret;
1197
1198 return 0;
1199 }
1200
hdmi_audio_mute(struct device * dev,void * data,bool enable,int direction)1201 static int hdmi_audio_mute(struct device *dev, void *data,
1202 bool enable, int direction)
1203 {
1204 struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1205
1206 DRM_DEBUG_DRIVER("%s\n", enable ? "enable" : "disable");
1207
1208 if (enable)
1209 hdmi_write(hdmi, HDMI_SAMPLE_FLAT_ALL, HDMI_SAMPLE_FLAT_MASK);
1210 else
1211 hdmi_write(hdmi, HDMI_SAMPLE_FLAT_NO, HDMI_SAMPLE_FLAT_MASK);
1212
1213 return 0;
1214 }
1215
hdmi_audio_get_eld(struct device * dev,void * data,uint8_t * buf,size_t len)1216 static int hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
1217 {
1218 struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1219 struct drm_connector *connector = hdmi->drm_connector;
1220
1221 DRM_DEBUG_DRIVER("\n");
1222 memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
1223
1224 return 0;
1225 }
1226
1227 static const struct hdmi_codec_ops audio_codec_ops = {
1228 .hw_params = hdmi_audio_hw_params,
1229 .audio_shutdown = hdmi_audio_shutdown,
1230 .mute_stream = hdmi_audio_mute,
1231 .get_eld = hdmi_audio_get_eld,
1232 .no_capture_mute = 1,
1233 };
1234
sti_hdmi_register_audio_driver(struct device * dev,struct sti_hdmi * hdmi)1235 static int sti_hdmi_register_audio_driver(struct device *dev,
1236 struct sti_hdmi *hdmi)
1237 {
1238 struct hdmi_codec_pdata codec_data = {
1239 .ops = &audio_codec_ops,
1240 .max_i2s_channels = 8,
1241 .i2s = 1,
1242 };
1243
1244 DRM_DEBUG_DRIVER("\n");
1245
1246 hdmi->audio.enabled = false;
1247
1248 hdmi->audio_pdev = platform_device_register_data(
1249 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
1250 &codec_data, sizeof(codec_data));
1251
1252 if (IS_ERR(hdmi->audio_pdev))
1253 return PTR_ERR(hdmi->audio_pdev);
1254
1255 DRM_INFO("%s Driver bound %s\n", HDMI_CODEC_DRV_NAME, dev_name(dev));
1256
1257 return 0;
1258 }
1259
sti_hdmi_bind(struct device * dev,struct device * master,void * data)1260 static int sti_hdmi_bind(struct device *dev, struct device *master, void *data)
1261 {
1262 struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1263 struct drm_device *drm_dev = data;
1264 struct drm_encoder *encoder;
1265 struct sti_hdmi_connector *connector;
1266 struct cec_connector_info conn_info;
1267 struct drm_connector *drm_connector;
1268 struct drm_bridge *bridge;
1269 int err;
1270
1271 /* Set the drm device handle */
1272 hdmi->drm_dev = drm_dev;
1273
1274 encoder = sti_hdmi_find_encoder(drm_dev);
1275 if (!encoder)
1276 return -EINVAL;
1277
1278 connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL);
1279 if (!connector)
1280 return -EINVAL;
1281
1282 connector->hdmi = hdmi;
1283
1284 bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);
1285 if (!bridge)
1286 return -EINVAL;
1287
1288 bridge->driver_private = hdmi;
1289 bridge->funcs = &sti_hdmi_bridge_funcs;
1290 drm_bridge_attach(encoder, bridge, NULL, 0);
1291
1292 connector->encoder = encoder;
1293
1294 drm_connector = (struct drm_connector *)connector;
1295
1296 drm_connector->polled = DRM_CONNECTOR_POLL_HPD;
1297
1298 drm_connector_init_with_ddc(drm_dev, drm_connector,
1299 &sti_hdmi_connector_funcs,
1300 DRM_MODE_CONNECTOR_HDMIA,
1301 hdmi->ddc_adapt);
1302 drm_connector_helper_add(drm_connector,
1303 &sti_hdmi_connector_helper_funcs);
1304
1305 /* initialise property */
1306 sti_hdmi_connector_init_property(drm_dev, drm_connector);
1307
1308 hdmi->drm_connector = drm_connector;
1309
1310 err = drm_connector_attach_encoder(drm_connector, encoder);
1311 if (err) {
1312 DRM_ERROR("Failed to attach a connector to a encoder\n");
1313 goto err_sysfs;
1314 }
1315
1316 err = sti_hdmi_register_audio_driver(dev, hdmi);
1317 if (err) {
1318 DRM_ERROR("Failed to attach an audio codec\n");
1319 goto err_sysfs;
1320 }
1321
1322 /* Initialize audio infoframe */
1323 err = hdmi_audio_infoframe_init(&hdmi->audio.cea);
1324 if (err) {
1325 DRM_ERROR("Failed to init audio infoframe\n");
1326 goto err_sysfs;
1327 }
1328
1329 cec_fill_conn_info_from_drm(&conn_info, drm_connector);
1330 hdmi->notifier = cec_notifier_conn_register(&hdmi->dev, NULL,
1331 &conn_info);
1332 if (!hdmi->notifier) {
1333 hdmi->drm_connector = NULL;
1334 return -ENOMEM;
1335 }
1336
1337 /* Enable default interrupts */
1338 hdmi_write(hdmi, HDMI_DEFAULT_INT, HDMI_INT_EN);
1339
1340 return 0;
1341
1342 err_sysfs:
1343 hdmi->drm_connector = NULL;
1344 return -EINVAL;
1345 }
1346
sti_hdmi_unbind(struct device * dev,struct device * master,void * data)1347 static void sti_hdmi_unbind(struct device *dev,
1348 struct device *master, void *data)
1349 {
1350 struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1351
1352 cec_notifier_conn_unregister(hdmi->notifier);
1353 }
1354
1355 static const struct component_ops sti_hdmi_ops = {
1356 .bind = sti_hdmi_bind,
1357 .unbind = sti_hdmi_unbind,
1358 };
1359
1360 static const struct of_device_id hdmi_of_match[] = {
1361 {
1362 .compatible = "st,stih407-hdmi",
1363 .data = &tx3g4c28phy_ops,
1364 }, {
1365 /* end node */
1366 }
1367 };
1368 MODULE_DEVICE_TABLE(of, hdmi_of_match);
1369
sti_hdmi_probe(struct platform_device * pdev)1370 static int sti_hdmi_probe(struct platform_device *pdev)
1371 {
1372 struct device *dev = &pdev->dev;
1373 struct sti_hdmi *hdmi;
1374 struct device_node *np = dev->of_node;
1375 struct resource *res;
1376 struct device_node *ddc;
1377 int ret;
1378
1379 DRM_INFO("%s\n", __func__);
1380
1381 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1382 if (!hdmi)
1383 return -ENOMEM;
1384
1385 ddc = of_parse_phandle(pdev->dev.of_node, "ddc", 0);
1386 if (ddc) {
1387 hdmi->ddc_adapt = of_get_i2c_adapter_by_node(ddc);
1388 of_node_put(ddc);
1389 if (!hdmi->ddc_adapt)
1390 return -EPROBE_DEFER;
1391 }
1392
1393 hdmi->dev = pdev->dev;
1394
1395 /* Get resources */
1396 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi-reg");
1397 if (!res) {
1398 DRM_ERROR("Invalid hdmi resource\n");
1399 ret = -ENOMEM;
1400 goto release_adapter;
1401 }
1402 hdmi->regs = devm_ioremap(dev, res->start, resource_size(res));
1403 if (!hdmi->regs) {
1404 ret = -ENOMEM;
1405 goto release_adapter;
1406 }
1407
1408 hdmi->phy_ops = (struct hdmi_phy_ops *)
1409 of_match_node(hdmi_of_match, np)->data;
1410
1411 /* Get clock resources */
1412 hdmi->clk_pix = devm_clk_get(dev, "pix");
1413 if (IS_ERR(hdmi->clk_pix)) {
1414 DRM_ERROR("Cannot get hdmi_pix clock\n");
1415 ret = PTR_ERR(hdmi->clk_pix);
1416 goto release_adapter;
1417 }
1418
1419 hdmi->clk_tmds = devm_clk_get(dev, "tmds");
1420 if (IS_ERR(hdmi->clk_tmds)) {
1421 DRM_ERROR("Cannot get hdmi_tmds clock\n");
1422 ret = PTR_ERR(hdmi->clk_tmds);
1423 goto release_adapter;
1424 }
1425
1426 hdmi->clk_phy = devm_clk_get(dev, "phy");
1427 if (IS_ERR(hdmi->clk_phy)) {
1428 DRM_ERROR("Cannot get hdmi_phy clock\n");
1429 ret = PTR_ERR(hdmi->clk_phy);
1430 goto release_adapter;
1431 }
1432
1433 hdmi->clk_audio = devm_clk_get(dev, "audio");
1434 if (IS_ERR(hdmi->clk_audio)) {
1435 DRM_ERROR("Cannot get hdmi_audio clock\n");
1436 ret = PTR_ERR(hdmi->clk_audio);
1437 goto release_adapter;
1438 }
1439
1440 hdmi->hpd = readl(hdmi->regs + HDMI_STA) & HDMI_STA_HOT_PLUG;
1441
1442 init_waitqueue_head(&hdmi->wait_event);
1443
1444 hdmi->irq = platform_get_irq_byname(pdev, "irq");
1445 if (hdmi->irq < 0) {
1446 DRM_ERROR("Cannot get HDMI irq\n");
1447 ret = hdmi->irq;
1448 goto release_adapter;
1449 }
1450
1451 ret = devm_request_threaded_irq(dev, hdmi->irq, hdmi_irq,
1452 hdmi_irq_thread, IRQF_ONESHOT, dev_name(dev), hdmi);
1453 if (ret) {
1454 DRM_ERROR("Failed to register HDMI interrupt\n");
1455 goto release_adapter;
1456 }
1457
1458 hdmi->reset = devm_reset_control_get(dev, "hdmi");
1459 /* Take hdmi out of reset */
1460 if (!IS_ERR(hdmi->reset))
1461 reset_control_deassert(hdmi->reset);
1462
1463 platform_set_drvdata(pdev, hdmi);
1464
1465 return component_add(&pdev->dev, &sti_hdmi_ops);
1466
1467 release_adapter:
1468 i2c_put_adapter(hdmi->ddc_adapt);
1469
1470 return ret;
1471 }
1472
sti_hdmi_remove(struct platform_device * pdev)1473 static int sti_hdmi_remove(struct platform_device *pdev)
1474 {
1475 struct sti_hdmi *hdmi = dev_get_drvdata(&pdev->dev);
1476
1477 i2c_put_adapter(hdmi->ddc_adapt);
1478 if (hdmi->audio_pdev)
1479 platform_device_unregister(hdmi->audio_pdev);
1480 component_del(&pdev->dev, &sti_hdmi_ops);
1481
1482 return 0;
1483 }
1484
1485 struct platform_driver sti_hdmi_driver = {
1486 .driver = {
1487 .name = "sti-hdmi",
1488 .owner = THIS_MODULE,
1489 .of_match_table = hdmi_of_match,
1490 },
1491 .probe = sti_hdmi_probe,
1492 .remove = sti_hdmi_remove,
1493 };
1494
1495 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
1496 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
1497 MODULE_LICENSE("GPL");
1498
