1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * STMicroelectronics st_lsm6dsx sensor driver
4 *
5 * The ST LSM6DSx IMU MEMS series consists of 3D digital accelerometer
6 * and 3D digital gyroscope system-in-package with a digital I2C/SPI serial
7 * interface standard output.
8 * LSM6DSx IMU MEMS series has a dynamic user-selectable full-scale
9 * acceleration range of +-2/+-4/+-8/+-16 g and an angular rate range of
10 * +-125/+-245/+-500/+-1000/+-2000 dps
11 * LSM6DSx series has an integrated First-In-First-Out (FIFO) buffer
12 * allowing dynamic batching of sensor data.
13 * LSM9DSx series is similar but includes an additional magnetometer, handled
14 * by a different driver.
15 *
16 * Supported sensors:
17 * - LSM6DS3:
18 * - Accelerometer/Gyroscope supported ODR [Hz]: 12.5, 26, 52, 104, 208, 416
19 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16
20 * - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000
21 * - FIFO size: 8KB
22 *
23 * - LSM6DS3H/LSM6DSL/LSM6DSM/ISM330DLC/LSM6DS3TR-C:
24 * - Accelerometer/Gyroscope supported ODR [Hz]: 12.5, 26, 52, 104, 208, 416
25 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16
26 * - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000
27 * - FIFO size: 4KB
28 *
29 * - LSM6DSO/LSM6DSOX/ASM330LHH/LSM6DSR/ISM330DHCX/LSM6DST/LSM6DSOP:
30 * - Accelerometer/Gyroscope supported ODR [Hz]: 12.5, 26, 52, 104, 208, 416,
31 * 833
32 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16
33 * - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000
34 * - FIFO size: 3KB
35 *
36 * - LSM9DS1/LSM6DS0:
37 * - Accelerometer supported ODR [Hz]: 10, 50, 119, 238, 476, 952
38 * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16
39 * - Gyroscope supported ODR [Hz]: 15, 60, 119, 238, 476, 952
40 * - Gyroscope supported full-scale [dps]: +-245/+-500/+-2000
41 * - FIFO size: 32
42 *
43 * Copyright 2016 STMicroelectronics Inc.
44 *
45 * Lorenzo Bianconi <lorenzo.bianconi@st.com>
46 * Denis Ciocca <denis.ciocca@st.com>
47 */
48
49 #include <linux/kernel.h>
50 #include <linux/module.h>
51 #include <linux/delay.h>
52 #include <linux/iio/events.h>
53 #include <linux/iio/iio.h>
54 #include <linux/iio/sysfs.h>
55 #include <linux/interrupt.h>
56 #include <linux/irq.h>
57 #include <linux/pm.h>
58 #include <linux/property.h>
59 #include <linux/regmap.h>
60 #include <linux/bitfield.h>
61
62 #include <linux/platform_data/st_sensors_pdata.h>
63
64 #include "st_lsm6dsx.h"
65
66 #define ST_LSM6DSX_REG_WHOAMI_ADDR 0x0f
67
68 #define ST_LSM6DSX_TS_SENSITIVITY 25000UL /* 25us */
69
70 static const struct iio_chan_spec st_lsm6dsx_acc_channels[] = {
71 ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x28, IIO_MOD_X, 0),
72 ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x2a, IIO_MOD_Y, 1),
73 ST_LSM6DSX_CHANNEL_ACC(IIO_ACCEL, 0x2c, IIO_MOD_Z, 2),
74 IIO_CHAN_SOFT_TIMESTAMP(3),
75 };
76
77 static const struct iio_chan_spec st_lsm6dsx_gyro_channels[] = {
78 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x22, IIO_MOD_X, 0),
79 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x24, IIO_MOD_Y, 1),
80 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x26, IIO_MOD_Z, 2),
81 IIO_CHAN_SOFT_TIMESTAMP(3),
82 };
83
84 static const struct iio_chan_spec st_lsm6ds0_gyro_channels[] = {
85 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x18, IIO_MOD_X, 0),
86 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x1a, IIO_MOD_Y, 1),
87 ST_LSM6DSX_CHANNEL(IIO_ANGL_VEL, 0x1c, IIO_MOD_Z, 2),
88 IIO_CHAN_SOFT_TIMESTAMP(3),
89 };
90
91 static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
92 {
93 .reset = {
94 .addr = 0x22,
95 .mask = BIT(0),
96 },
97 .boot = {
98 .addr = 0x22,
99 .mask = BIT(7),
100 },
101 .bdu = {
102 .addr = 0x22,
103 .mask = BIT(6),
104 },
105 .max_fifo_size = 32,
106 .id = {
107 {
108 .hw_id = ST_LSM9DS1_ID,
109 .name = ST_LSM9DS1_DEV_NAME,
110 .wai = 0x68,
111 }, {
112 .hw_id = ST_LSM6DS0_ID,
113 .name = ST_LSM6DS0_DEV_NAME,
114 .wai = 0x68,
115 },
116 },
117 .channels = {
118 [ST_LSM6DSX_ID_ACC] = {
119 .chan = st_lsm6dsx_acc_channels,
120 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels),
121 },
122 [ST_LSM6DSX_ID_GYRO] = {
123 .chan = st_lsm6ds0_gyro_channels,
124 .len = ARRAY_SIZE(st_lsm6ds0_gyro_channels),
125 },
126 },
127 .odr_table = {
128 [ST_LSM6DSX_ID_ACC] = {
129 .reg = {
130 .addr = 0x20,
131 .mask = GENMASK(7, 5),
132 },
133 .odr_avl[0] = { 10000, 0x01 },
134 .odr_avl[1] = { 50000, 0x02 },
135 .odr_avl[2] = { 119000, 0x03 },
136 .odr_avl[3] = { 238000, 0x04 },
137 .odr_avl[4] = { 476000, 0x05 },
138 .odr_avl[5] = { 952000, 0x06 },
139 .odr_len = 6,
140 },
141 [ST_LSM6DSX_ID_GYRO] = {
142 .reg = {
143 .addr = 0x10,
144 .mask = GENMASK(7, 5),
145 },
146 .odr_avl[0] = { 14900, 0x01 },
147 .odr_avl[1] = { 59500, 0x02 },
148 .odr_avl[2] = { 119000, 0x03 },
149 .odr_avl[3] = { 238000, 0x04 },
150 .odr_avl[4] = { 476000, 0x05 },
151 .odr_avl[5] = { 952000, 0x06 },
152 .odr_len = 6,
153 },
154 },
155 .fs_table = {
156 [ST_LSM6DSX_ID_ACC] = {
157 .reg = {
158 .addr = 0x20,
159 .mask = GENMASK(4, 3),
160 },
161 .fs_avl[0] = { IIO_G_TO_M_S_2(61000), 0x0 },
162 .fs_avl[1] = { IIO_G_TO_M_S_2(122000), 0x2 },
163 .fs_avl[2] = { IIO_G_TO_M_S_2(244000), 0x3 },
164 .fs_avl[3] = { IIO_G_TO_M_S_2(732000), 0x1 },
165 .fs_len = 4,
166 },
167 [ST_LSM6DSX_ID_GYRO] = {
168 .reg = {
169 .addr = 0x10,
170 .mask = GENMASK(4, 3),
171 },
172
173 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750000), 0x0 },
174 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500000), 0x1 },
175 .fs_avl[2] = { IIO_DEGREE_TO_RAD(70000000), 0x3 },
176 .fs_len = 3,
177 },
178 },
179 .irq_config = {
180 .irq1 = {
181 .addr = 0x0c,
182 .mask = BIT(3),
183 },
184 .irq2 = {
185 .addr = 0x0d,
186 .mask = BIT(3),
187 },
188 .hla = {
189 .addr = 0x22,
190 .mask = BIT(5),
191 },
192 .od = {
193 .addr = 0x22,
194 .mask = BIT(4),
195 },
196 },
197 },
198 {
199 .reset = {
200 .addr = 0x12,
201 .mask = BIT(0),
202 },
203 .boot = {
204 .addr = 0x12,
205 .mask = BIT(7),
206 },
207 .bdu = {
208 .addr = 0x12,
209 .mask = BIT(6),
210 },
211 .max_fifo_size = 1365,
212 .id = {
213 {
214 .hw_id = ST_LSM6DS3_ID,
215 .name = ST_LSM6DS3_DEV_NAME,
216 .wai = 0x69,
217 },
218 },
219 .channels = {
220 [ST_LSM6DSX_ID_ACC] = {
221 .chan = st_lsm6dsx_acc_channels,
222 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels),
223 },
224 [ST_LSM6DSX_ID_GYRO] = {
225 .chan = st_lsm6dsx_gyro_channels,
226 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels),
227 },
228 },
229 .odr_table = {
230 [ST_LSM6DSX_ID_ACC] = {
231 .reg = {
232 .addr = 0x10,
233 .mask = GENMASK(7, 4),
234 },
235 .odr_avl[0] = { 12500, 0x01 },
236 .odr_avl[1] = { 26000, 0x02 },
237 .odr_avl[2] = { 52000, 0x03 },
238 .odr_avl[3] = { 104000, 0x04 },
239 .odr_avl[4] = { 208000, 0x05 },
240 .odr_avl[5] = { 416000, 0x06 },
241 .odr_len = 6,
242 },
243 [ST_LSM6DSX_ID_GYRO] = {
244 .reg = {
245 .addr = 0x11,
246 .mask = GENMASK(7, 4),
247 },
248 .odr_avl[0] = { 12500, 0x01 },
249 .odr_avl[1] = { 26000, 0x02 },
250 .odr_avl[2] = { 52000, 0x03 },
251 .odr_avl[3] = { 104000, 0x04 },
252 .odr_avl[4] = { 208000, 0x05 },
253 .odr_avl[5] = { 416000, 0x06 },
254 .odr_len = 6,
255 },
256 },
257 .fs_table = {
258 [ST_LSM6DSX_ID_ACC] = {
259 .reg = {
260 .addr = 0x10,
261 .mask = GENMASK(3, 2),
262 },
263 .fs_avl[0] = { IIO_G_TO_M_S_2(61000), 0x0 },
264 .fs_avl[1] = { IIO_G_TO_M_S_2(122000), 0x2 },
265 .fs_avl[2] = { IIO_G_TO_M_S_2(244000), 0x3 },
266 .fs_avl[3] = { IIO_G_TO_M_S_2(488000), 0x1 },
267 .fs_len = 4,
268 },
269 [ST_LSM6DSX_ID_GYRO] = {
270 .reg = {
271 .addr = 0x11,
272 .mask = GENMASK(3, 2),
273 },
274 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750000), 0x0 },
275 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500000), 0x1 },
276 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000000), 0x2 },
277 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000000), 0x3 },
278 .fs_len = 4,
279 },
280 },
281 .irq_config = {
282 .irq1 = {
283 .addr = 0x0d,
284 .mask = BIT(3),
285 },
286 .irq2 = {
287 .addr = 0x0e,
288 .mask = BIT(3),
289 },
290 .lir = {
291 .addr = 0x58,
292 .mask = BIT(0),
293 },
294 .irq1_func = {
295 .addr = 0x5e,
296 .mask = BIT(5),
297 },
298 .irq2_func = {
299 .addr = 0x5f,
300 .mask = BIT(5),
301 },
302 .hla = {
303 .addr = 0x12,
304 .mask = BIT(5),
305 },
306 .od = {
307 .addr = 0x12,
308 .mask = BIT(4),
309 },
310 },
311 .decimator = {
312 [ST_LSM6DSX_ID_ACC] = {
313 .addr = 0x08,
314 .mask = GENMASK(2, 0),
315 },
316 [ST_LSM6DSX_ID_GYRO] = {
317 .addr = 0x08,
318 .mask = GENMASK(5, 3),
319 },
320 },
321 .fifo_ops = {
322 .update_fifo = st_lsm6dsx_update_fifo,
323 .read_fifo = st_lsm6dsx_read_fifo,
324 .fifo_th = {
325 .addr = 0x06,
326 .mask = GENMASK(11, 0),
327 },
328 .fifo_diff = {
329 .addr = 0x3a,
330 .mask = GENMASK(11, 0),
331 },
332 .th_wl = 3, /* 1LSB = 2B */
333 },
334 .ts_settings = {
335 .timer_en = {
336 .addr = 0x58,
337 .mask = BIT(7),
338 },
339 .hr_timer = {
340 .addr = 0x5c,
341 .mask = BIT(4),
342 },
343 .fifo_en = {
344 .addr = 0x07,
345 .mask = BIT(7),
346 },
347 .decimator = {
348 .addr = 0x09,
349 .mask = GENMASK(5, 3),
350 },
351 },
352 .event_settings = {
353 .wakeup_reg = {
354 .addr = 0x5B,
355 .mask = GENMASK(5, 0),
356 },
357 .wakeup_src_reg = 0x1b,
358 .wakeup_src_status_mask = BIT(3),
359 .wakeup_src_z_mask = BIT(0),
360 .wakeup_src_y_mask = BIT(1),
361 .wakeup_src_x_mask = BIT(2),
362 },
363 },
364 {
365 .reset = {
366 .addr = 0x12,
367 .mask = BIT(0),
368 },
369 .boot = {
370 .addr = 0x12,
371 .mask = BIT(7),
372 },
373 .bdu = {
374 .addr = 0x12,
375 .mask = BIT(6),
376 },
377 .max_fifo_size = 682,
378 .id = {
379 {
380 .hw_id = ST_LSM6DS3H_ID,
381 .name = ST_LSM6DS3H_DEV_NAME,
382 .wai = 0x69,
383 },
384 },
385 .channels = {
386 [ST_LSM6DSX_ID_ACC] = {
387 .chan = st_lsm6dsx_acc_channels,
388 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels),
389 },
390 [ST_LSM6DSX_ID_GYRO] = {
391 .chan = st_lsm6dsx_gyro_channels,
392 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels),
393 },
394 },
395 .odr_table = {
396 [ST_LSM6DSX_ID_ACC] = {
397 .reg = {
398 .addr = 0x10,
399 .mask = GENMASK(7, 4),
400 },
401 .odr_avl[0] = { 12500, 0x01 },
402 .odr_avl[1] = { 26000, 0x02 },
403 .odr_avl[2] = { 52000, 0x03 },
404 .odr_avl[3] = { 104000, 0x04 },
405 .odr_avl[4] = { 208000, 0x05 },
406 .odr_avl[5] = { 416000, 0x06 },
407 .odr_len = 6,
408 },
409 [ST_LSM6DSX_ID_GYRO] = {
410 .reg = {
411 .addr = 0x11,
412 .mask = GENMASK(7, 4),
413 },
414 .odr_avl[0] = { 12500, 0x01 },
415 .odr_avl[1] = { 26000, 0x02 },
416 .odr_avl[2] = { 52000, 0x03 },
417 .odr_avl[3] = { 104000, 0x04 },
418 .odr_avl[4] = { 208000, 0x05 },
419 .odr_avl[5] = { 416000, 0x06 },
420 .odr_len = 6,
421 },
422 },
423 .fs_table = {
424 [ST_LSM6DSX_ID_ACC] = {
425 .reg = {
426 .addr = 0x10,
427 .mask = GENMASK(3, 2),
428 },
429 .fs_avl[0] = { IIO_G_TO_M_S_2(61000), 0x0 },
430 .fs_avl[1] = { IIO_G_TO_M_S_2(122000), 0x2 },
431 .fs_avl[2] = { IIO_G_TO_M_S_2(244000), 0x3 },
432 .fs_avl[3] = { IIO_G_TO_M_S_2(488000), 0x1 },
433 .fs_len = 4,
434 },
435 [ST_LSM6DSX_ID_GYRO] = {
436 .reg = {
437 .addr = 0x11,
438 .mask = GENMASK(3, 2),
439 },
440 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750000), 0x0 },
441 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500000), 0x1 },
442 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000000), 0x2 },
443 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000000), 0x3 },
444 .fs_len = 4,
445 },
446 },
447 .irq_config = {
448 .irq1 = {
449 .addr = 0x0d,
450 .mask = BIT(3),
451 },
452 .irq2 = {
453 .addr = 0x0e,
454 .mask = BIT(3),
455 },
456 .lir = {
457 .addr = 0x58,
458 .mask = BIT(0),
459 },
460 .irq1_func = {
461 .addr = 0x5e,
462 .mask = BIT(5),
463 },
464 .irq2_func = {
465 .addr = 0x5f,
466 .mask = BIT(5),
467 },
468 .hla = {
469 .addr = 0x12,
470 .mask = BIT(5),
471 },
472 .od = {
473 .addr = 0x12,
474 .mask = BIT(4),
475 },
476 },
477 .decimator = {
478 [ST_LSM6DSX_ID_ACC] = {
479 .addr = 0x08,
480 .mask = GENMASK(2, 0),
481 },
482 [ST_LSM6DSX_ID_GYRO] = {
483 .addr = 0x08,
484 .mask = GENMASK(5, 3),
485 },
486 },
487 .fifo_ops = {
488 .update_fifo = st_lsm6dsx_update_fifo,
489 .read_fifo = st_lsm6dsx_read_fifo,
490 .fifo_th = {
491 .addr = 0x06,
492 .mask = GENMASK(11, 0),
493 },
494 .fifo_diff = {
495 .addr = 0x3a,
496 .mask = GENMASK(11, 0),
497 },
498 .th_wl = 3, /* 1LSB = 2B */
499 },
500 .ts_settings = {
501 .timer_en = {
502 .addr = 0x58,
503 .mask = BIT(7),
504 },
505 .hr_timer = {
506 .addr = 0x5c,
507 .mask = BIT(4),
508 },
509 .fifo_en = {
510 .addr = 0x07,
511 .mask = BIT(7),
512 },
513 .decimator = {
514 .addr = 0x09,
515 .mask = GENMASK(5, 3),
516 },
517 },
518 .event_settings = {
519 .wakeup_reg = {
520 .addr = 0x5B,
521 .mask = GENMASK(5, 0),
522 },
523 .wakeup_src_reg = 0x1b,
524 .wakeup_src_status_mask = BIT(3),
525 .wakeup_src_z_mask = BIT(0),
526 .wakeup_src_y_mask = BIT(1),
527 .wakeup_src_x_mask = BIT(2),
528 },
529 },
530 {
531 .reset = {
532 .addr = 0x12,
533 .mask = BIT(0),
534 },
535 .boot = {
536 .addr = 0x12,
537 .mask = BIT(7),
538 },
539 .bdu = {
540 .addr = 0x12,
541 .mask = BIT(6),
542 },
543 .max_fifo_size = 682,
544 .id = {
545 {
546 .hw_id = ST_LSM6DSL_ID,
547 .name = ST_LSM6DSL_DEV_NAME,
548 .wai = 0x6a,
549 }, {
550 .hw_id = ST_LSM6DSM_ID,
551 .name = ST_LSM6DSM_DEV_NAME,
552 .wai = 0x6a,
553 }, {
554 .hw_id = ST_ISM330DLC_ID,
555 .name = ST_ISM330DLC_DEV_NAME,
556 .wai = 0x6a,
557 }, {
558 .hw_id = ST_LSM6DS3TRC_ID,
559 .name = ST_LSM6DS3TRC_DEV_NAME,
560 .wai = 0x6a,
561 },
562 },
563 .channels = {
564 [ST_LSM6DSX_ID_ACC] = {
565 .chan = st_lsm6dsx_acc_channels,
566 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels),
567 },
568 [ST_LSM6DSX_ID_GYRO] = {
569 .chan = st_lsm6dsx_gyro_channels,
570 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels),
571 },
572 },
573 .odr_table = {
574 [ST_LSM6DSX_ID_ACC] = {
575 .reg = {
576 .addr = 0x10,
577 .mask = GENMASK(7, 4),
578 },
579 .odr_avl[0] = { 12500, 0x01 },
580 .odr_avl[1] = { 26000, 0x02 },
581 .odr_avl[2] = { 52000, 0x03 },
582 .odr_avl[3] = { 104000, 0x04 },
583 .odr_avl[4] = { 208000, 0x05 },
584 .odr_avl[5] = { 416000, 0x06 },
585 .odr_len = 6,
586 },
587 [ST_LSM6DSX_ID_GYRO] = {
588 .reg = {
589 .addr = 0x11,
590 .mask = GENMASK(7, 4),
591 },
592 .odr_avl[0] = { 12500, 0x01 },
593 .odr_avl[1] = { 26000, 0x02 },
594 .odr_avl[2] = { 52000, 0x03 },
595 .odr_avl[3] = { 104000, 0x04 },
596 .odr_avl[4] = { 208000, 0x05 },
597 .odr_avl[5] = { 416000, 0x06 },
598 .odr_len = 6,
599 },
600 },
601 .fs_table = {
602 [ST_LSM6DSX_ID_ACC] = {
603 .reg = {
604 .addr = 0x10,
605 .mask = GENMASK(3, 2),
606 },
607 .fs_avl[0] = { IIO_G_TO_M_S_2(61000), 0x0 },
608 .fs_avl[1] = { IIO_G_TO_M_S_2(122000), 0x2 },
609 .fs_avl[2] = { IIO_G_TO_M_S_2(244000), 0x3 },
610 .fs_avl[3] = { IIO_G_TO_M_S_2(488000), 0x1 },
611 .fs_len = 4,
612 },
613 [ST_LSM6DSX_ID_GYRO] = {
614 .reg = {
615 .addr = 0x11,
616 .mask = GENMASK(3, 2),
617 },
618 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750000), 0x0 },
619 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500000), 0x1 },
620 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000000), 0x2 },
621 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000000), 0x3 },
622 .fs_len = 4,
623 },
624 },
625 .irq_config = {
626 .irq1 = {
627 .addr = 0x0d,
628 .mask = BIT(3),
629 },
630 .irq2 = {
631 .addr = 0x0e,
632 .mask = BIT(3),
633 },
634 .lir = {
635 .addr = 0x58,
636 .mask = BIT(0),
637 },
638 .irq1_func = {
639 .addr = 0x5e,
640 .mask = BIT(5),
641 },
642 .irq2_func = {
643 .addr = 0x5f,
644 .mask = BIT(5),
645 },
646 .hla = {
647 .addr = 0x12,
648 .mask = BIT(5),
649 },
650 .od = {
651 .addr = 0x12,
652 .mask = BIT(4),
653 },
654 },
655 .decimator = {
656 [ST_LSM6DSX_ID_ACC] = {
657 .addr = 0x08,
658 .mask = GENMASK(2, 0),
659 },
660 [ST_LSM6DSX_ID_GYRO] = {
661 .addr = 0x08,
662 .mask = GENMASK(5, 3),
663 },
664 [ST_LSM6DSX_ID_EXT0] = {
665 .addr = 0x09,
666 .mask = GENMASK(2, 0),
667 },
668 },
669 .fifo_ops = {
670 .update_fifo = st_lsm6dsx_update_fifo,
671 .read_fifo = st_lsm6dsx_read_fifo,
672 .fifo_th = {
673 .addr = 0x06,
674 .mask = GENMASK(10, 0),
675 },
676 .fifo_diff = {
677 .addr = 0x3a,
678 .mask = GENMASK(10, 0),
679 },
680 .th_wl = 3, /* 1LSB = 2B */
681 },
682 .ts_settings = {
683 .timer_en = {
684 .addr = 0x19,
685 .mask = BIT(5),
686 },
687 .hr_timer = {
688 .addr = 0x5c,
689 .mask = BIT(4),
690 },
691 .fifo_en = {
692 .addr = 0x07,
693 .mask = BIT(7),
694 },
695 .decimator = {
696 .addr = 0x09,
697 .mask = GENMASK(5, 3),
698 },
699 },
700 .shub_settings = {
701 .page_mux = {
702 .addr = 0x01,
703 .mask = BIT(7),
704 },
705 .master_en = {
706 .addr = 0x1a,
707 .mask = BIT(0),
708 },
709 .pullup_en = {
710 .addr = 0x1a,
711 .mask = BIT(3),
712 },
713 .aux_sens = {
714 .addr = 0x04,
715 .mask = GENMASK(5, 4),
716 },
717 .wr_once = {
718 .addr = 0x07,
719 .mask = BIT(5),
720 },
721 .emb_func = {
722 .addr = 0x19,
723 .mask = BIT(2),
724 },
725 .num_ext_dev = 1,
726 .shub_out = {
727 .addr = 0x2e,
728 },
729 .slv0_addr = 0x02,
730 .dw_slv0_addr = 0x0e,
731 .pause = 0x7,
732 },
733 .event_settings = {
734 .enable_reg = {
735 .addr = 0x58,
736 .mask = BIT(7),
737 },
738 .wakeup_reg = {
739 .addr = 0x5B,
740 .mask = GENMASK(5, 0),
741 },
742 .wakeup_src_reg = 0x1b,
743 .wakeup_src_status_mask = BIT(3),
744 .wakeup_src_z_mask = BIT(0),
745 .wakeup_src_y_mask = BIT(1),
746 .wakeup_src_x_mask = BIT(2),
747 },
748 },
749 {
750 .reset = {
751 .addr = 0x12,
752 .mask = BIT(0),
753 },
754 .boot = {
755 .addr = 0x12,
756 .mask = BIT(7),
757 },
758 .bdu = {
759 .addr = 0x12,
760 .mask = BIT(6),
761 },
762 .max_fifo_size = 512,
763 .id = {
764 {
765 .hw_id = ST_LSM6DSR_ID,
766 .name = ST_LSM6DSR_DEV_NAME,
767 .wai = 0x6b,
768 }, {
769 .hw_id = ST_ISM330DHCX_ID,
770 .name = ST_ISM330DHCX_DEV_NAME,
771 .wai = 0x6b,
772 }, {
773 .hw_id = ST_LSM6DSRX_ID,
774 .name = ST_LSM6DSRX_DEV_NAME,
775 .wai = 0x6b,
776 }, {
777 .hw_id = ST_LSM6DSO_ID,
778 .name = ST_LSM6DSO_DEV_NAME,
779 .wai = 0x6c,
780 }, {
781 .hw_id = ST_LSM6DSOX_ID,
782 .name = ST_LSM6DSOX_DEV_NAME,
783 .wai = 0x6c,
784 }, {
785 .hw_id = ST_LSM6DST_ID,
786 .name = ST_LSM6DST_DEV_NAME,
787 .wai = 0x6d,
788 },
789 },
790 .channels = {
791 [ST_LSM6DSX_ID_ACC] = {
792 .chan = st_lsm6dsx_acc_channels,
793 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels),
794 },
795 [ST_LSM6DSX_ID_GYRO] = {
796 .chan = st_lsm6dsx_gyro_channels,
797 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels),
798 },
799 },
800 .drdy_mask = {
801 .addr = 0x13,
802 .mask = BIT(3),
803 },
804 .odr_table = {
805 [ST_LSM6DSX_ID_ACC] = {
806 .reg = {
807 .addr = 0x10,
808 .mask = GENMASK(7, 4),
809 },
810 .odr_avl[0] = { 12500, 0x01 },
811 .odr_avl[1] = { 26000, 0x02 },
812 .odr_avl[2] = { 52000, 0x03 },
813 .odr_avl[3] = { 104000, 0x04 },
814 .odr_avl[4] = { 208000, 0x05 },
815 .odr_avl[5] = { 416000, 0x06 },
816 .odr_avl[6] = { 833000, 0x07 },
817 .odr_len = 7,
818 },
819 [ST_LSM6DSX_ID_GYRO] = {
820 .reg = {
821 .addr = 0x11,
822 .mask = GENMASK(7, 4),
823 },
824 .odr_avl[0] = { 12500, 0x01 },
825 .odr_avl[1] = { 26000, 0x02 },
826 .odr_avl[2] = { 52000, 0x03 },
827 .odr_avl[3] = { 104000, 0x04 },
828 .odr_avl[4] = { 208000, 0x05 },
829 .odr_avl[5] = { 416000, 0x06 },
830 .odr_avl[6] = { 833000, 0x07 },
831 .odr_len = 7,
832 },
833 },
834 .fs_table = {
835 [ST_LSM6DSX_ID_ACC] = {
836 .reg = {
837 .addr = 0x10,
838 .mask = GENMASK(3, 2),
839 },
840 .fs_avl[0] = { IIO_G_TO_M_S_2(61000), 0x0 },
841 .fs_avl[1] = { IIO_G_TO_M_S_2(122000), 0x2 },
842 .fs_avl[2] = { IIO_G_TO_M_S_2(244000), 0x3 },
843 .fs_avl[3] = { IIO_G_TO_M_S_2(488000), 0x1 },
844 .fs_len = 4,
845 },
846 [ST_LSM6DSX_ID_GYRO] = {
847 .reg = {
848 .addr = 0x11,
849 .mask = GENMASK(3, 2),
850 },
851 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750000), 0x0 },
852 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500000), 0x1 },
853 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000000), 0x2 },
854 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000000), 0x3 },
855 .fs_len = 4,
856 },
857 },
858 .irq_config = {
859 .irq1 = {
860 .addr = 0x0d,
861 .mask = BIT(3),
862 },
863 .irq2 = {
864 .addr = 0x0e,
865 .mask = BIT(3),
866 },
867 .lir = {
868 .addr = 0x56,
869 .mask = BIT(0),
870 },
871 .clear_on_read = {
872 .addr = 0x56,
873 .mask = BIT(6),
874 },
875 .irq1_func = {
876 .addr = 0x5e,
877 .mask = BIT(5),
878 },
879 .irq2_func = {
880 .addr = 0x5f,
881 .mask = BIT(5),
882 },
883 .hla = {
884 .addr = 0x12,
885 .mask = BIT(5),
886 },
887 .od = {
888 .addr = 0x12,
889 .mask = BIT(4),
890 },
891 },
892 .batch = {
893 [ST_LSM6DSX_ID_ACC] = {
894 .addr = 0x09,
895 .mask = GENMASK(3, 0),
896 },
897 [ST_LSM6DSX_ID_GYRO] = {
898 .addr = 0x09,
899 .mask = GENMASK(7, 4),
900 },
901 },
902 .fifo_ops = {
903 .update_fifo = st_lsm6dsx_update_fifo,
904 .read_fifo = st_lsm6dsx_read_tagged_fifo,
905 .fifo_th = {
906 .addr = 0x07,
907 .mask = GENMASK(8, 0),
908 },
909 .fifo_diff = {
910 .addr = 0x3a,
911 .mask = GENMASK(9, 0),
912 },
913 .th_wl = 1,
914 },
915 .ts_settings = {
916 .timer_en = {
917 .addr = 0x19,
918 .mask = BIT(5),
919 },
920 .decimator = {
921 .addr = 0x0a,
922 .mask = GENMASK(7, 6),
923 },
924 .freq_fine = 0x63,
925 },
926 .shub_settings = {
927 .page_mux = {
928 .addr = 0x01,
929 .mask = BIT(6),
930 },
931 .master_en = {
932 .sec_page = true,
933 .addr = 0x14,
934 .mask = BIT(2),
935 },
936 .pullup_en = {
937 .sec_page = true,
938 .addr = 0x14,
939 .mask = BIT(3),
940 },
941 .aux_sens = {
942 .addr = 0x14,
943 .mask = GENMASK(1, 0),
944 },
945 .wr_once = {
946 .addr = 0x14,
947 .mask = BIT(6),
948 },
949 .num_ext_dev = 3,
950 .shub_out = {
951 .sec_page = true,
952 .addr = 0x02,
953 },
954 .slv0_addr = 0x15,
955 .dw_slv0_addr = 0x21,
956 .batch_en = BIT(3),
957 },
958 .event_settings = {
959 .enable_reg = {
960 .addr = 0x58,
961 .mask = BIT(7),
962 },
963 .wakeup_reg = {
964 .addr = 0x5b,
965 .mask = GENMASK(5, 0),
966 },
967 .wakeup_src_reg = 0x1b,
968 .wakeup_src_status_mask = BIT(3),
969 .wakeup_src_z_mask = BIT(0),
970 .wakeup_src_y_mask = BIT(1),
971 .wakeup_src_x_mask = BIT(2),
972 },
973 },
974 {
975 .reset = {
976 .addr = 0x12,
977 .mask = BIT(0),
978 },
979 .boot = {
980 .addr = 0x12,
981 .mask = BIT(7),
982 },
983 .bdu = {
984 .addr = 0x12,
985 .mask = BIT(6),
986 },
987 .max_fifo_size = 512,
988 .id = {
989 {
990 .hw_id = ST_ASM330LHH_ID,
991 .name = ST_ASM330LHH_DEV_NAME,
992 .wai = 0x6b,
993 }, {
994 .hw_id = ST_LSM6DSOP_ID,
995 .name = ST_LSM6DSOP_DEV_NAME,
996 .wai = 0x6c,
997 },
998 },
999 .channels = {
1000 [ST_LSM6DSX_ID_ACC] = {
1001 .chan = st_lsm6dsx_acc_channels,
1002 .len = ARRAY_SIZE(st_lsm6dsx_acc_channels),
1003 },
1004 [ST_LSM6DSX_ID_GYRO] = {
1005 .chan = st_lsm6dsx_gyro_channels,
1006 .len = ARRAY_SIZE(st_lsm6dsx_gyro_channels),
1007 },
1008 },
1009 .drdy_mask = {
1010 .addr = 0x13,
1011 .mask = BIT(3),
1012 },
1013 .odr_table = {
1014 [ST_LSM6DSX_ID_ACC] = {
1015 .reg = {
1016 .addr = 0x10,
1017 .mask = GENMASK(7, 4),
1018 },
1019 .odr_avl[0] = { 12500, 0x01 },
1020 .odr_avl[1] = { 26000, 0x02 },
1021 .odr_avl[2] = { 52000, 0x03 },
1022 .odr_avl[3] = { 104000, 0x04 },
1023 .odr_avl[4] = { 208000, 0x05 },
1024 .odr_avl[5] = { 416000, 0x06 },
1025 .odr_avl[6] = { 833000, 0x07 },
1026 .odr_len = 7,
1027 },
1028 [ST_LSM6DSX_ID_GYRO] = {
1029 .reg = {
1030 .addr = 0x11,
1031 .mask = GENMASK(7, 4),
1032 },
1033 .odr_avl[0] = { 12500, 0x01 },
1034 .odr_avl[1] = { 26000, 0x02 },
1035 .odr_avl[2] = { 52000, 0x03 },
1036 .odr_avl[3] = { 104000, 0x04 },
1037 .odr_avl[4] = { 208000, 0x05 },
1038 .odr_avl[5] = { 416000, 0x06 },
1039 .odr_avl[6] = { 833000, 0x07 },
1040 .odr_len = 7,
1041 },
1042 },
1043 .fs_table = {
1044 [ST_LSM6DSX_ID_ACC] = {
1045 .reg = {
1046 .addr = 0x10,
1047 .mask = GENMASK(3, 2),
1048 },
1049 .fs_avl[0] = { IIO_G_TO_M_S_2(61000), 0x0 },
1050 .fs_avl[1] = { IIO_G_TO_M_S_2(122000), 0x2 },
1051 .fs_avl[2] = { IIO_G_TO_M_S_2(244000), 0x3 },
1052 .fs_avl[3] = { IIO_G_TO_M_S_2(488000), 0x1 },
1053 .fs_len = 4,
1054 },
1055 [ST_LSM6DSX_ID_GYRO] = {
1056 .reg = {
1057 .addr = 0x11,
1058 .mask = GENMASK(3, 2),
1059 },
1060 .fs_avl[0] = { IIO_DEGREE_TO_RAD(8750000), 0x0 },
1061 .fs_avl[1] = { IIO_DEGREE_TO_RAD(17500000), 0x1 },
1062 .fs_avl[2] = { IIO_DEGREE_TO_RAD(35000000), 0x2 },
1063 .fs_avl[3] = { IIO_DEGREE_TO_RAD(70000000), 0x3 },
1064 .fs_len = 4,
1065 },
1066 },
1067 .irq_config = {
1068 .irq1 = {
1069 .addr = 0x0d,
1070 .mask = BIT(3),
1071 },
1072 .irq2 = {
1073 .addr = 0x0e,
1074 .mask = BIT(3),
1075 },
1076 .lir = {
1077 .addr = 0x56,
1078 .mask = BIT(0),
1079 },
1080 .clear_on_read = {
1081 .addr = 0x56,
1082 .mask = BIT(6),
1083 },
1084 .irq1_func = {
1085 .addr = 0x5e,
1086 .mask = BIT(5),
1087 },
1088 .irq2_func = {
1089 .addr = 0x5f,
1090 .mask = BIT(5),
1091 },
1092 .hla = {
1093 .addr = 0x12,
1094 .mask = BIT(5),
1095 },
1096 .od = {
1097 .addr = 0x12,
1098 .mask = BIT(4),
1099 },
1100 },
1101 .batch = {
1102 [ST_LSM6DSX_ID_ACC] = {
1103 .addr = 0x09,
1104 .mask = GENMASK(3, 0),
1105 },
1106 [ST_LSM6DSX_ID_GYRO] = {
1107 .addr = 0x09,
1108 .mask = GENMASK(7, 4),
1109 },
1110 },
1111 .fifo_ops = {
1112 .update_fifo = st_lsm6dsx_update_fifo,
1113 .read_fifo = st_lsm6dsx_read_tagged_fifo,
1114 .fifo_th = {
1115 .addr = 0x07,
1116 .mask = GENMASK(8, 0),
1117 },
1118 .fifo_diff = {
1119 .addr = 0x3a,
1120 .mask = GENMASK(9, 0),
1121 },
1122 .th_wl = 1,
1123 },
1124 .ts_settings = {
1125 .timer_en = {
1126 .addr = 0x19,
1127 .mask = BIT(5),
1128 },
1129 .decimator = {
1130 .addr = 0x0a,
1131 .mask = GENMASK(7, 6),
1132 },
1133 .freq_fine = 0x63,
1134 },
1135 .event_settings = {
1136 .enable_reg = {
1137 .addr = 0x58,
1138 .mask = BIT(7),
1139 },
1140 .wakeup_reg = {
1141 .addr = 0x5B,
1142 .mask = GENMASK(5, 0),
1143 },
1144 .wakeup_src_reg = 0x1b,
1145 .wakeup_src_status_mask = BIT(3),
1146 .wakeup_src_z_mask = BIT(0),
1147 .wakeup_src_y_mask = BIT(1),
1148 .wakeup_src_x_mask = BIT(2),
1149 },
1150 },
1151 };
1152
st_lsm6dsx_set_page(struct st_lsm6dsx_hw * hw,bool enable)1153 int st_lsm6dsx_set_page(struct st_lsm6dsx_hw *hw, bool enable)
1154 {
1155 const struct st_lsm6dsx_shub_settings *hub_settings;
1156 unsigned int data;
1157 int err;
1158
1159 hub_settings = &hw->settings->shub_settings;
1160 data = ST_LSM6DSX_SHIFT_VAL(enable, hub_settings->page_mux.mask);
1161 err = regmap_update_bits(hw->regmap, hub_settings->page_mux.addr,
1162 hub_settings->page_mux.mask, data);
1163 usleep_range(100, 150);
1164
1165 return err;
1166 }
1167
st_lsm6dsx_check_whoami(struct st_lsm6dsx_hw * hw,int id,const char ** name)1168 static int st_lsm6dsx_check_whoami(struct st_lsm6dsx_hw *hw, int id,
1169 const char **name)
1170 {
1171 int err, i, j, data;
1172
1173 for (i = 0; i < ARRAY_SIZE(st_lsm6dsx_sensor_settings); i++) {
1174 for (j = 0; j < ST_LSM6DSX_MAX_ID; j++) {
1175 if (st_lsm6dsx_sensor_settings[i].id[j].name &&
1176 id == st_lsm6dsx_sensor_settings[i].id[j].hw_id)
1177 break;
1178 }
1179 if (j < ST_LSM6DSX_MAX_ID)
1180 break;
1181 }
1182
1183 if (i == ARRAY_SIZE(st_lsm6dsx_sensor_settings)) {
1184 dev_err(hw->dev, "unsupported hw id [%02x]\n", id);
1185 return -ENODEV;
1186 }
1187
1188 err = regmap_read(hw->regmap, ST_LSM6DSX_REG_WHOAMI_ADDR, &data);
1189 if (err < 0) {
1190 dev_err(hw->dev, "failed to read whoami register\n");
1191 return err;
1192 }
1193
1194 if (data != st_lsm6dsx_sensor_settings[i].id[j].wai) {
1195 dev_err(hw->dev, "unsupported whoami [%02x]\n", data);
1196 return -ENODEV;
1197 }
1198
1199 *name = st_lsm6dsx_sensor_settings[i].id[j].name;
1200 hw->settings = &st_lsm6dsx_sensor_settings[i];
1201
1202 return 0;
1203 }
1204
st_lsm6dsx_set_full_scale(struct st_lsm6dsx_sensor * sensor,u32 gain)1205 static int st_lsm6dsx_set_full_scale(struct st_lsm6dsx_sensor *sensor,
1206 u32 gain)
1207 {
1208 const struct st_lsm6dsx_fs_table_entry *fs_table;
1209 unsigned int data;
1210 int i, err;
1211
1212 fs_table = &sensor->hw->settings->fs_table[sensor->id];
1213 for (i = 0; i < fs_table->fs_len; i++) {
1214 if (fs_table->fs_avl[i].gain == gain)
1215 break;
1216 }
1217
1218 if (i == fs_table->fs_len)
1219 return -EINVAL;
1220
1221 data = ST_LSM6DSX_SHIFT_VAL(fs_table->fs_avl[i].val,
1222 fs_table->reg.mask);
1223 err = st_lsm6dsx_update_bits_locked(sensor->hw, fs_table->reg.addr,
1224 fs_table->reg.mask, data);
1225 if (err < 0)
1226 return err;
1227
1228 sensor->gain = gain;
1229
1230 return 0;
1231 }
1232
st_lsm6dsx_check_odr(struct st_lsm6dsx_sensor * sensor,u32 odr,u8 * val)1233 int st_lsm6dsx_check_odr(struct st_lsm6dsx_sensor *sensor, u32 odr, u8 *val)
1234 {
1235 const struct st_lsm6dsx_odr_table_entry *odr_table;
1236 int i;
1237
1238 odr_table = &sensor->hw->settings->odr_table[sensor->id];
1239 for (i = 0; i < odr_table->odr_len; i++) {
1240 /*
1241 * ext devices can run at different odr respect to
1242 * accel sensor
1243 */
1244 if (odr_table->odr_avl[i].milli_hz >= odr)
1245 break;
1246 }
1247
1248 if (i == odr_table->odr_len)
1249 return -EINVAL;
1250
1251 *val = odr_table->odr_avl[i].val;
1252 return odr_table->odr_avl[i].milli_hz;
1253 }
1254
1255 static int
st_lsm6dsx_check_odr_dependency(struct st_lsm6dsx_hw * hw,u32 odr,enum st_lsm6dsx_sensor_id id)1256 st_lsm6dsx_check_odr_dependency(struct st_lsm6dsx_hw *hw, u32 odr,
1257 enum st_lsm6dsx_sensor_id id)
1258 {
1259 struct st_lsm6dsx_sensor *ref = iio_priv(hw->iio_devs[id]);
1260
1261 if (odr > 0) {
1262 if (hw->enable_mask & BIT(id))
1263 return max_t(u32, ref->odr, odr);
1264 else
1265 return odr;
1266 } else {
1267 return (hw->enable_mask & BIT(id)) ? ref->odr : 0;
1268 }
1269 }
1270
1271 static int
st_lsm6dsx_set_odr(struct st_lsm6dsx_sensor * sensor,u32 req_odr)1272 st_lsm6dsx_set_odr(struct st_lsm6dsx_sensor *sensor, u32 req_odr)
1273 {
1274 struct st_lsm6dsx_sensor *ref_sensor = sensor;
1275 struct st_lsm6dsx_hw *hw = sensor->hw;
1276 const struct st_lsm6dsx_reg *reg;
1277 unsigned int data;
1278 u8 val = 0;
1279 int err;
1280
1281 switch (sensor->id) {
1282 case ST_LSM6DSX_ID_EXT0:
1283 case ST_LSM6DSX_ID_EXT1:
1284 case ST_LSM6DSX_ID_EXT2:
1285 case ST_LSM6DSX_ID_ACC: {
1286 u32 odr;
1287 int i;
1288
1289 /*
1290 * i2c embedded controller relies on the accelerometer sensor as
1291 * bus read/write trigger so we need to enable accel device
1292 * at odr = max(accel_odr, ext_odr) in order to properly
1293 * communicate with i2c slave devices
1294 */
1295 ref_sensor = iio_priv(hw->iio_devs[ST_LSM6DSX_ID_ACC]);
1296 for (i = ST_LSM6DSX_ID_ACC; i < ST_LSM6DSX_ID_MAX; i++) {
1297 if (!hw->iio_devs[i] || i == sensor->id)
1298 continue;
1299
1300 odr = st_lsm6dsx_check_odr_dependency(hw, req_odr, i);
1301 if (odr != req_odr)
1302 /* device already configured */
1303 return 0;
1304 }
1305 break;
1306 }
1307 default:
1308 break;
1309 }
1310
1311 if (req_odr > 0) {
1312 err = st_lsm6dsx_check_odr(ref_sensor, req_odr, &val);
1313 if (err < 0)
1314 return err;
1315 }
1316
1317 reg = &hw->settings->odr_table[ref_sensor->id].reg;
1318 data = ST_LSM6DSX_SHIFT_VAL(val, reg->mask);
1319 return st_lsm6dsx_update_bits_locked(hw, reg->addr, reg->mask, data);
1320 }
1321
1322 static int
__st_lsm6dsx_sensor_set_enable(struct st_lsm6dsx_sensor * sensor,bool enable)1323 __st_lsm6dsx_sensor_set_enable(struct st_lsm6dsx_sensor *sensor,
1324 bool enable)
1325 {
1326 struct st_lsm6dsx_hw *hw = sensor->hw;
1327 u32 odr = enable ? sensor->odr : 0;
1328 int err;
1329
1330 err = st_lsm6dsx_set_odr(sensor, odr);
1331 if (err < 0)
1332 return err;
1333
1334 if (enable)
1335 hw->enable_mask |= BIT(sensor->id);
1336 else
1337 hw->enable_mask &= ~BIT(sensor->id);
1338
1339 return 0;
1340 }
1341
1342 static int
st_lsm6dsx_check_events(struct st_lsm6dsx_sensor * sensor,bool enable)1343 st_lsm6dsx_check_events(struct st_lsm6dsx_sensor *sensor, bool enable)
1344 {
1345 struct st_lsm6dsx_hw *hw = sensor->hw;
1346
1347 if (sensor->id == ST_LSM6DSX_ID_GYRO || enable)
1348 return 0;
1349
1350 return hw->enable_event;
1351 }
1352
st_lsm6dsx_sensor_set_enable(struct st_lsm6dsx_sensor * sensor,bool enable)1353 int st_lsm6dsx_sensor_set_enable(struct st_lsm6dsx_sensor *sensor,
1354 bool enable)
1355 {
1356 if (st_lsm6dsx_check_events(sensor, enable))
1357 return 0;
1358
1359 return __st_lsm6dsx_sensor_set_enable(sensor, enable);
1360 }
1361
st_lsm6dsx_read_oneshot(struct st_lsm6dsx_sensor * sensor,u8 addr,int * val)1362 static int st_lsm6dsx_read_oneshot(struct st_lsm6dsx_sensor *sensor,
1363 u8 addr, int *val)
1364 {
1365 struct st_lsm6dsx_hw *hw = sensor->hw;
1366 int err, delay;
1367 __le16 data;
1368
1369 err = st_lsm6dsx_sensor_set_enable(sensor, true);
1370 if (err < 0)
1371 return err;
1372
1373 delay = 1000000000 / sensor->odr;
1374 usleep_range(delay, 2 * delay);
1375
1376 err = st_lsm6dsx_read_locked(hw, addr, &data, sizeof(data));
1377 if (err < 0)
1378 return err;
1379
1380 if (!hw->enable_event) {
1381 err = st_lsm6dsx_sensor_set_enable(sensor, false);
1382 if (err < 0)
1383 return err;
1384 }
1385
1386 *val = (s16)le16_to_cpu(data);
1387
1388 return IIO_VAL_INT;
1389 }
1390
st_lsm6dsx_read_raw(struct iio_dev * iio_dev,struct iio_chan_spec const * ch,int * val,int * val2,long mask)1391 static int st_lsm6dsx_read_raw(struct iio_dev *iio_dev,
1392 struct iio_chan_spec const *ch,
1393 int *val, int *val2, long mask)
1394 {
1395 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev);
1396 int ret;
1397
1398 switch (mask) {
1399 case IIO_CHAN_INFO_RAW:
1400 ret = iio_device_claim_direct_mode(iio_dev);
1401 if (ret)
1402 break;
1403
1404 ret = st_lsm6dsx_read_oneshot(sensor, ch->address, val);
1405 iio_device_release_direct_mode(iio_dev);
1406 break;
1407 case IIO_CHAN_INFO_SAMP_FREQ:
1408 *val = sensor->odr / 1000;
1409 *val2 = (sensor->odr % 1000) * 1000;
1410 ret = IIO_VAL_INT_PLUS_MICRO;
1411 break;
1412 case IIO_CHAN_INFO_SCALE:
1413 *val = 0;
1414 *val2 = sensor->gain;
1415 ret = IIO_VAL_INT_PLUS_NANO;
1416 break;
1417 default:
1418 ret = -EINVAL;
1419 break;
1420 }
1421
1422 return ret;
1423 }
1424
st_lsm6dsx_write_raw(struct iio_dev * iio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)1425 static int st_lsm6dsx_write_raw(struct iio_dev *iio_dev,
1426 struct iio_chan_spec const *chan,
1427 int val, int val2, long mask)
1428 {
1429 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev);
1430 int err;
1431
1432 err = iio_device_claim_direct_mode(iio_dev);
1433 if (err)
1434 return err;
1435
1436 switch (mask) {
1437 case IIO_CHAN_INFO_SCALE:
1438 err = st_lsm6dsx_set_full_scale(sensor, val2);
1439 break;
1440 case IIO_CHAN_INFO_SAMP_FREQ: {
1441 u8 data;
1442
1443 val = val * 1000 + val2 / 1000;
1444 val = st_lsm6dsx_check_odr(sensor, val, &data);
1445 if (val < 0)
1446 err = val;
1447 else
1448 sensor->odr = val;
1449 break;
1450 }
1451 default:
1452 err = -EINVAL;
1453 break;
1454 }
1455
1456 iio_device_release_direct_mode(iio_dev);
1457
1458 return err;
1459 }
1460
st_lsm6dsx_event_setup(struct st_lsm6dsx_hw * hw,int state)1461 static int st_lsm6dsx_event_setup(struct st_lsm6dsx_hw *hw, int state)
1462 {
1463 const struct st_lsm6dsx_reg *reg;
1464 unsigned int data;
1465 int err;
1466
1467 if (!hw->settings->irq_config.irq1_func.addr)
1468 return -ENOTSUPP;
1469
1470 reg = &hw->settings->event_settings.enable_reg;
1471 if (reg->addr) {
1472 data = ST_LSM6DSX_SHIFT_VAL(state, reg->mask);
1473 err = st_lsm6dsx_update_bits_locked(hw, reg->addr,
1474 reg->mask, data);
1475 if (err < 0)
1476 return err;
1477 }
1478
1479 /* Enable wakeup interrupt */
1480 data = ST_LSM6DSX_SHIFT_VAL(state, hw->irq_routing->mask);
1481 return st_lsm6dsx_update_bits_locked(hw, hw->irq_routing->addr,
1482 hw->irq_routing->mask, data);
1483 }
1484
st_lsm6dsx_read_event(struct iio_dev * iio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)1485 static int st_lsm6dsx_read_event(struct iio_dev *iio_dev,
1486 const struct iio_chan_spec *chan,
1487 enum iio_event_type type,
1488 enum iio_event_direction dir,
1489 enum iio_event_info info,
1490 int *val, int *val2)
1491 {
1492 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev);
1493 struct st_lsm6dsx_hw *hw = sensor->hw;
1494
1495 if (type != IIO_EV_TYPE_THRESH)
1496 return -EINVAL;
1497
1498 *val2 = 0;
1499 *val = hw->event_threshold;
1500
1501 return IIO_VAL_INT;
1502 }
1503
1504 static int
st_lsm6dsx_write_event(struct iio_dev * iio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)1505 st_lsm6dsx_write_event(struct iio_dev *iio_dev,
1506 const struct iio_chan_spec *chan,
1507 enum iio_event_type type,
1508 enum iio_event_direction dir,
1509 enum iio_event_info info,
1510 int val, int val2)
1511 {
1512 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev);
1513 struct st_lsm6dsx_hw *hw = sensor->hw;
1514 const struct st_lsm6dsx_reg *reg;
1515 unsigned int data;
1516 int err;
1517
1518 if (type != IIO_EV_TYPE_THRESH)
1519 return -EINVAL;
1520
1521 if (val < 0 || val > 31)
1522 return -EINVAL;
1523
1524 reg = &hw->settings->event_settings.wakeup_reg;
1525 data = ST_LSM6DSX_SHIFT_VAL(val, reg->mask);
1526 err = st_lsm6dsx_update_bits_locked(hw, reg->addr,
1527 reg->mask, data);
1528 if (err < 0)
1529 return -EINVAL;
1530
1531 hw->event_threshold = val;
1532
1533 return 0;
1534 }
1535
1536 static int
st_lsm6dsx_read_event_config(struct iio_dev * iio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)1537 st_lsm6dsx_read_event_config(struct iio_dev *iio_dev,
1538 const struct iio_chan_spec *chan,
1539 enum iio_event_type type,
1540 enum iio_event_direction dir)
1541 {
1542 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev);
1543 struct st_lsm6dsx_hw *hw = sensor->hw;
1544
1545 if (type != IIO_EV_TYPE_THRESH)
1546 return -EINVAL;
1547
1548 return !!(hw->enable_event & BIT(chan->channel2));
1549 }
1550
1551 static int
st_lsm6dsx_write_event_config(struct iio_dev * iio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)1552 st_lsm6dsx_write_event_config(struct iio_dev *iio_dev,
1553 const struct iio_chan_spec *chan,
1554 enum iio_event_type type,
1555 enum iio_event_direction dir, int state)
1556 {
1557 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev);
1558 struct st_lsm6dsx_hw *hw = sensor->hw;
1559 u8 enable_event;
1560 int err;
1561
1562 if (type != IIO_EV_TYPE_THRESH)
1563 return -EINVAL;
1564
1565 if (state) {
1566 enable_event = hw->enable_event | BIT(chan->channel2);
1567
1568 /* do not enable events if they are already enabled */
1569 if (hw->enable_event)
1570 goto out;
1571 } else {
1572 enable_event = hw->enable_event & ~BIT(chan->channel2);
1573
1574 /* only turn off sensor if no events is enabled */
1575 if (enable_event)
1576 goto out;
1577 }
1578
1579 /* stop here if no changes have been made */
1580 if (hw->enable_event == enable_event)
1581 return 0;
1582
1583 err = st_lsm6dsx_event_setup(hw, state);
1584 if (err < 0)
1585 return err;
1586
1587 mutex_lock(&hw->conf_lock);
1588 if (enable_event || !(hw->fifo_mask & BIT(sensor->id)))
1589 err = __st_lsm6dsx_sensor_set_enable(sensor, state);
1590 mutex_unlock(&hw->conf_lock);
1591 if (err < 0)
1592 return err;
1593
1594 out:
1595 hw->enable_event = enable_event;
1596
1597 return 0;
1598 }
1599
st_lsm6dsx_set_watermark(struct iio_dev * iio_dev,unsigned int val)1600 int st_lsm6dsx_set_watermark(struct iio_dev *iio_dev, unsigned int val)
1601 {
1602 struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev);
1603 struct st_lsm6dsx_hw *hw = sensor->hw;
1604 int err;
1605
1606 if (val < 1 || val > hw->settings->max_fifo_size)
1607 return -EINVAL;
1608
1609 mutex_lock(&hw->conf_lock);
1610
1611 err = st_lsm6dsx_update_watermark(sensor, val);
1612
1613 mutex_unlock(&hw->conf_lock);
1614
1615 if (err < 0)
1616 return err;
1617
1618 sensor->watermark = val;
1619
1620 return 0;
1621 }
1622
1623 static ssize_t
st_lsm6dsx_sysfs_sampling_frequency_avail(struct device * dev,struct device_attribute * attr,char * buf)1624 st_lsm6dsx_sysfs_sampling_frequency_avail(struct device *dev,
1625 struct device_attribute *attr,
1626 char *buf)
1627 {
1628 struct st_lsm6dsx_sensor *sensor = iio_priv(dev_get_drvdata(dev));
1629 const struct st_lsm6dsx_odr_table_entry *odr_table;
1630 int i, len = 0;
1631
1632 odr_table = &sensor->hw->settings->odr_table[sensor->id];
1633 for (i = 0; i < odr_table->odr_len; i++)
1634 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%03d ",
1635 odr_table->odr_avl[i].milli_hz / 1000,
1636 odr_table->odr_avl[i].milli_hz % 1000);
1637 buf[len - 1] = '\n';
1638
1639 return len;
1640 }
1641
st_lsm6dsx_sysfs_scale_avail(struct device * dev,struct device_attribute * attr,char * buf)1642 static ssize_t st_lsm6dsx_sysfs_scale_avail(struct device *dev,
1643 struct device_attribute *attr,
1644 char *buf)
1645 {
1646 struct st_lsm6dsx_sensor *sensor = iio_priv(dev_get_drvdata(dev));
1647 const struct st_lsm6dsx_fs_table_entry *fs_table;
1648 struct st_lsm6dsx_hw *hw = sensor->hw;
1649 int i, len = 0;
1650
1651 fs_table = &hw->settings->fs_table[sensor->id];
1652 for (i = 0; i < fs_table->fs_len; i++)
1653 len += scnprintf(buf + len, PAGE_SIZE - len, "0.%09u ",
1654 fs_table->fs_avl[i].gain);
1655 buf[len - 1] = '\n';
1656
1657 return len;
1658 }
1659
st_lsm6dsx_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)1660 static int st_lsm6dsx_write_raw_get_fmt(struct iio_dev *indio_dev,
1661 struct iio_chan_spec const *chan,
1662 long mask)
1663 {
1664 switch (mask) {
1665 case IIO_CHAN_INFO_SCALE:
1666 switch (chan->type) {
1667 case IIO_ANGL_VEL:
1668 case IIO_ACCEL:
1669 return IIO_VAL_INT_PLUS_NANO;
1670 default:
1671 return IIO_VAL_INT_PLUS_MICRO;
1672 }
1673 default:
1674 return IIO_VAL_INT_PLUS_MICRO;
1675 }
1676 }
1677
1678 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(st_lsm6dsx_sysfs_sampling_frequency_avail);
1679 static IIO_DEVICE_ATTR(in_accel_scale_available, 0444,
1680 st_lsm6dsx_sysfs_scale_avail, NULL, 0);
1681 static IIO_DEVICE_ATTR(in_anglvel_scale_available, 0444,
1682 st_lsm6dsx_sysfs_scale_avail, NULL, 0);
1683
1684 static struct attribute *st_lsm6dsx_acc_attributes[] = {
1685 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
1686 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
1687 NULL,
1688 };
1689
1690 static const struct attribute_group st_lsm6dsx_acc_attribute_group = {
1691 .attrs = st_lsm6dsx_acc_attributes,
1692 };
1693
1694 static const struct iio_info st_lsm6dsx_acc_info = {
1695 .attrs = &st_lsm6dsx_acc_attribute_group,
1696 .read_raw = st_lsm6dsx_read_raw,
1697 .write_raw = st_lsm6dsx_write_raw,
1698 .read_event_value = st_lsm6dsx_read_event,
1699 .write_event_value = st_lsm6dsx_write_event,
1700 .read_event_config = st_lsm6dsx_read_event_config,
1701 .write_event_config = st_lsm6dsx_write_event_config,
1702 .hwfifo_set_watermark = st_lsm6dsx_set_watermark,
1703 .write_raw_get_fmt = st_lsm6dsx_write_raw_get_fmt,
1704 };
1705
1706 static struct attribute *st_lsm6dsx_gyro_attributes[] = {
1707 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
1708 &iio_dev_attr_in_anglvel_scale_available.dev_attr.attr,
1709 NULL,
1710 };
1711
1712 static const struct attribute_group st_lsm6dsx_gyro_attribute_group = {
1713 .attrs = st_lsm6dsx_gyro_attributes,
1714 };
1715
1716 static const struct iio_info st_lsm6dsx_gyro_info = {
1717 .attrs = &st_lsm6dsx_gyro_attribute_group,
1718 .read_raw = st_lsm6dsx_read_raw,
1719 .write_raw = st_lsm6dsx_write_raw,
1720 .hwfifo_set_watermark = st_lsm6dsx_set_watermark,
1721 .write_raw_get_fmt = st_lsm6dsx_write_raw_get_fmt,
1722 };
1723
st_lsm6dsx_get_drdy_pin(struct st_lsm6dsx_hw * hw,int * drdy_pin)1724 static int st_lsm6dsx_get_drdy_pin(struct st_lsm6dsx_hw *hw, int *drdy_pin)
1725 {
1726 struct device *dev = hw->dev;
1727
1728 if (!dev_fwnode(dev))
1729 return -EINVAL;
1730
1731 return device_property_read_u32(dev, "st,drdy-int-pin", drdy_pin);
1732 }
1733
1734 static int
st_lsm6dsx_get_drdy_reg(struct st_lsm6dsx_hw * hw,const struct st_lsm6dsx_reg ** drdy_reg)1735 st_lsm6dsx_get_drdy_reg(struct st_lsm6dsx_hw *hw,
1736 const struct st_lsm6dsx_reg **drdy_reg)
1737 {
1738 int err = 0, drdy_pin;
1739
1740 if (st_lsm6dsx_get_drdy_pin(hw, &drdy_pin) < 0) {
1741 struct st_sensors_platform_data *pdata;
1742 struct device *dev = hw->dev;
1743
1744 pdata = (struct st_sensors_platform_data *)dev->platform_data;
1745 drdy_pin = pdata ? pdata->drdy_int_pin : 1;
1746 }
1747
1748 switch (drdy_pin) {
1749 case 1:
1750 hw->irq_routing = &hw->settings->irq_config.irq1_func;
1751 *drdy_reg = &hw->settings->irq_config.irq1;
1752 break;
1753 case 2:
1754 hw->irq_routing = &hw->settings->irq_config.irq2_func;
1755 *drdy_reg = &hw->settings->irq_config.irq2;
1756 break;
1757 default:
1758 dev_err(hw->dev, "unsupported data ready pin\n");
1759 err = -EINVAL;
1760 break;
1761 }
1762
1763 return err;
1764 }
1765
st_lsm6dsx_init_shub(struct st_lsm6dsx_hw * hw)1766 static int st_lsm6dsx_init_shub(struct st_lsm6dsx_hw *hw)
1767 {
1768 const struct st_lsm6dsx_shub_settings *hub_settings;
1769 struct st_sensors_platform_data *pdata;
1770 struct device *dev = hw->dev;
1771 unsigned int data;
1772 int err = 0;
1773
1774 hub_settings = &hw->settings->shub_settings;
1775
1776 pdata = (struct st_sensors_platform_data *)dev->platform_data;
1777 if ((dev_fwnode(dev) && device_property_read_bool(dev, "st,pullups")) ||
1778 (pdata && pdata->pullups)) {
1779 if (hub_settings->pullup_en.sec_page) {
1780 err = st_lsm6dsx_set_page(hw, true);
1781 if (err < 0)
1782 return err;
1783 }
1784
1785 data = ST_LSM6DSX_SHIFT_VAL(1, hub_settings->pullup_en.mask);
1786 err = regmap_update_bits(hw->regmap,
1787 hub_settings->pullup_en.addr,
1788 hub_settings->pullup_en.mask, data);
1789
1790 if (hub_settings->pullup_en.sec_page)
1791 st_lsm6dsx_set_page(hw, false);
1792
1793 if (err < 0)
1794 return err;
1795 }
1796
1797 if (hub_settings->aux_sens.addr) {
1798 /* configure aux sensors */
1799 err = st_lsm6dsx_set_page(hw, true);
1800 if (err < 0)
1801 return err;
1802
1803 data = ST_LSM6DSX_SHIFT_VAL(3, hub_settings->aux_sens.mask);
1804 err = regmap_update_bits(hw->regmap,
1805 hub_settings->aux_sens.addr,
1806 hub_settings->aux_sens.mask, data);
1807
1808 st_lsm6dsx_set_page(hw, false);
1809
1810 if (err < 0)
1811 return err;
1812 }
1813
1814 if (hub_settings->emb_func.addr) {
1815 data = ST_LSM6DSX_SHIFT_VAL(1, hub_settings->emb_func.mask);
1816 err = regmap_update_bits(hw->regmap,
1817 hub_settings->emb_func.addr,
1818 hub_settings->emb_func.mask, data);
1819 }
1820
1821 return err;
1822 }
1823
st_lsm6dsx_init_hw_timer(struct st_lsm6dsx_hw * hw)1824 static int st_lsm6dsx_init_hw_timer(struct st_lsm6dsx_hw *hw)
1825 {
1826 const struct st_lsm6dsx_hw_ts_settings *ts_settings;
1827 int err, val;
1828
1829 ts_settings = &hw->settings->ts_settings;
1830 /* enable hw timestamp generation if necessary */
1831 if (ts_settings->timer_en.addr) {
1832 val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->timer_en.mask);
1833 err = regmap_update_bits(hw->regmap,
1834 ts_settings->timer_en.addr,
1835 ts_settings->timer_en.mask, val);
1836 if (err < 0)
1837 return err;
1838 }
1839
1840 /* enable high resolution for hw ts timer if necessary */
1841 if (ts_settings->hr_timer.addr) {
1842 val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->hr_timer.mask);
1843 err = regmap_update_bits(hw->regmap,
1844 ts_settings->hr_timer.addr,
1845 ts_settings->hr_timer.mask, val);
1846 if (err < 0)
1847 return err;
1848 }
1849
1850 /* enable ts queueing in FIFO if necessary */
1851 if (ts_settings->fifo_en.addr) {
1852 val = ST_LSM6DSX_SHIFT_VAL(1, ts_settings->fifo_en.mask);
1853 err = regmap_update_bits(hw->regmap,
1854 ts_settings->fifo_en.addr,
1855 ts_settings->fifo_en.mask, val);
1856 if (err < 0)
1857 return err;
1858 }
1859
1860 /* calibrate timestamp sensitivity */
1861 hw->ts_gain = ST_LSM6DSX_TS_SENSITIVITY;
1862 if (ts_settings->freq_fine) {
1863 err = regmap_read(hw->regmap, ts_settings->freq_fine, &val);
1864 if (err < 0)
1865 return err;
1866
1867 /*
1868 * linearize the AN5192 formula:
1869 * 1 / (1 + x) ~= 1 - x (Taylor’s Series)
1870 * ttrim[s] = 1 / (40000 * (1 + 0.0015 * val))
1871 * ttrim[ns] ~= 25000 - 37.5 * val
1872 * ttrim[ns] ~= 25000 - (37500 * val) / 1000
1873 */
1874 hw->ts_gain -= ((s8)val * 37500) / 1000;
1875 }
1876
1877 return 0;
1878 }
1879
st_lsm6dsx_reset_device(struct st_lsm6dsx_hw * hw)1880 static int st_lsm6dsx_reset_device(struct st_lsm6dsx_hw *hw)
1881 {
1882 const struct st_lsm6dsx_reg *reg;
1883 int err;
1884
1885 /*
1886 * flush hw FIFO before device reset in order to avoid
1887 * possible races on interrupt line 1. If the first interrupt
1888 * line is asserted during hw reset the device will work in
1889 * I3C-only mode (if it is supported)
1890 */
1891 err = st_lsm6dsx_flush_fifo(hw);
1892 if (err < 0 && err != -ENOTSUPP)
1893 return err;
1894
1895 /* device sw reset */
1896 reg = &hw->settings->reset;
1897 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
1898 ST_LSM6DSX_SHIFT_VAL(1, reg->mask));
1899 if (err < 0)
1900 return err;
1901
1902 msleep(50);
1903
1904 /* reload trimming parameter */
1905 reg = &hw->settings->boot;
1906 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
1907 ST_LSM6DSX_SHIFT_VAL(1, reg->mask));
1908 if (err < 0)
1909 return err;
1910
1911 msleep(50);
1912
1913 return 0;
1914 }
1915
st_lsm6dsx_init_device(struct st_lsm6dsx_hw * hw)1916 static int st_lsm6dsx_init_device(struct st_lsm6dsx_hw *hw)
1917 {
1918 const struct st_lsm6dsx_reg *reg;
1919 int err;
1920
1921 err = st_lsm6dsx_reset_device(hw);
1922 if (err < 0)
1923 return err;
1924
1925 /* enable Block Data Update */
1926 reg = &hw->settings->bdu;
1927 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
1928 ST_LSM6DSX_SHIFT_VAL(1, reg->mask));
1929 if (err < 0)
1930 return err;
1931
1932 /* enable FIFO watermak interrupt */
1933 err = st_lsm6dsx_get_drdy_reg(hw, ®);
1934 if (err < 0)
1935 return err;
1936
1937 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
1938 ST_LSM6DSX_SHIFT_VAL(1, reg->mask));
1939 if (err < 0)
1940 return err;
1941
1942 /* enable Latched interrupts for device events */
1943 if (hw->settings->irq_config.lir.addr) {
1944 reg = &hw->settings->irq_config.lir;
1945 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
1946 ST_LSM6DSX_SHIFT_VAL(1, reg->mask));
1947 if (err < 0)
1948 return err;
1949
1950 /* enable clear on read for latched interrupts */
1951 if (hw->settings->irq_config.clear_on_read.addr) {
1952 reg = &hw->settings->irq_config.clear_on_read;
1953 err = regmap_update_bits(hw->regmap,
1954 reg->addr, reg->mask,
1955 ST_LSM6DSX_SHIFT_VAL(1, reg->mask));
1956 if (err < 0)
1957 return err;
1958 }
1959 }
1960
1961 /* enable drdy-mas if available */
1962 if (hw->settings->drdy_mask.addr) {
1963 reg = &hw->settings->drdy_mask;
1964 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
1965 ST_LSM6DSX_SHIFT_VAL(1, reg->mask));
1966 if (err < 0)
1967 return err;
1968 }
1969
1970 err = st_lsm6dsx_init_shub(hw);
1971 if (err < 0)
1972 return err;
1973
1974 return st_lsm6dsx_init_hw_timer(hw);
1975 }
1976
st_lsm6dsx_alloc_iiodev(struct st_lsm6dsx_hw * hw,enum st_lsm6dsx_sensor_id id,const char * name)1977 static struct iio_dev *st_lsm6dsx_alloc_iiodev(struct st_lsm6dsx_hw *hw,
1978 enum st_lsm6dsx_sensor_id id,
1979 const char *name)
1980 {
1981 struct st_lsm6dsx_sensor *sensor;
1982 struct iio_dev *iio_dev;
1983
1984 iio_dev = devm_iio_device_alloc(hw->dev, sizeof(*sensor));
1985 if (!iio_dev)
1986 return NULL;
1987
1988 iio_dev->modes = INDIO_DIRECT_MODE;
1989 iio_dev->available_scan_masks = st_lsm6dsx_available_scan_masks;
1990 iio_dev->channels = hw->settings->channels[id].chan;
1991 iio_dev->num_channels = hw->settings->channels[id].len;
1992
1993 sensor = iio_priv(iio_dev);
1994 sensor->id = id;
1995 sensor->hw = hw;
1996 sensor->odr = hw->settings->odr_table[id].odr_avl[0].milli_hz;
1997 sensor->gain = hw->settings->fs_table[id].fs_avl[0].gain;
1998 sensor->watermark = 1;
1999
2000 switch (id) {
2001 case ST_LSM6DSX_ID_ACC:
2002 iio_dev->info = &st_lsm6dsx_acc_info;
2003 scnprintf(sensor->name, sizeof(sensor->name), "%s_accel",
2004 name);
2005 break;
2006 case ST_LSM6DSX_ID_GYRO:
2007 iio_dev->info = &st_lsm6dsx_gyro_info;
2008 scnprintf(sensor->name, sizeof(sensor->name), "%s_gyro",
2009 name);
2010 break;
2011 default:
2012 return NULL;
2013 }
2014 iio_dev->name = sensor->name;
2015
2016 return iio_dev;
2017 }
2018
2019 static bool
st_lsm6dsx_report_motion_event(struct st_lsm6dsx_hw * hw)2020 st_lsm6dsx_report_motion_event(struct st_lsm6dsx_hw *hw)
2021 {
2022 const struct st_lsm6dsx_event_settings *event_settings;
2023 int err, data;
2024 s64 timestamp;
2025
2026 if (!hw->enable_event)
2027 return false;
2028
2029 event_settings = &hw->settings->event_settings;
2030 err = st_lsm6dsx_read_locked(hw, event_settings->wakeup_src_reg,
2031 &data, sizeof(data));
2032 if (err < 0)
2033 return false;
2034
2035 timestamp = iio_get_time_ns(hw->iio_devs[ST_LSM6DSX_ID_ACC]);
2036 if ((data & hw->settings->event_settings.wakeup_src_z_mask) &&
2037 (hw->enable_event & BIT(IIO_MOD_Z)))
2038 iio_push_event(hw->iio_devs[ST_LSM6DSX_ID_ACC],
2039 IIO_MOD_EVENT_CODE(IIO_ACCEL,
2040 0,
2041 IIO_MOD_Z,
2042 IIO_EV_TYPE_THRESH,
2043 IIO_EV_DIR_EITHER),
2044 timestamp);
2045
2046 if ((data & hw->settings->event_settings.wakeup_src_y_mask) &&
2047 (hw->enable_event & BIT(IIO_MOD_Y)))
2048 iio_push_event(hw->iio_devs[ST_LSM6DSX_ID_ACC],
2049 IIO_MOD_EVENT_CODE(IIO_ACCEL,
2050 0,
2051 IIO_MOD_Y,
2052 IIO_EV_TYPE_THRESH,
2053 IIO_EV_DIR_EITHER),
2054 timestamp);
2055
2056 if ((data & hw->settings->event_settings.wakeup_src_x_mask) &&
2057 (hw->enable_event & BIT(IIO_MOD_X)))
2058 iio_push_event(hw->iio_devs[ST_LSM6DSX_ID_ACC],
2059 IIO_MOD_EVENT_CODE(IIO_ACCEL,
2060 0,
2061 IIO_MOD_X,
2062 IIO_EV_TYPE_THRESH,
2063 IIO_EV_DIR_EITHER),
2064 timestamp);
2065
2066 return data & event_settings->wakeup_src_status_mask;
2067 }
2068
st_lsm6dsx_handler_thread(int irq,void * private)2069 static irqreturn_t st_lsm6dsx_handler_thread(int irq, void *private)
2070 {
2071 struct st_lsm6dsx_hw *hw = private;
2072 int fifo_len = 0, len;
2073 bool event;
2074
2075 event = st_lsm6dsx_report_motion_event(hw);
2076
2077 if (!hw->settings->fifo_ops.read_fifo)
2078 return event ? IRQ_HANDLED : IRQ_NONE;
2079
2080 /*
2081 * If we are using edge IRQs, new samples can arrive while
2082 * processing current interrupt since there are no hw
2083 * guarantees the irq line stays "low" long enough to properly
2084 * detect the new interrupt. In this case the new sample will
2085 * be missed.
2086 * Polling FIFO status register allow us to read new
2087 * samples even if the interrupt arrives while processing
2088 * previous data and the timeslot where the line is "low" is
2089 * too short to be properly detected.
2090 */
2091 do {
2092 mutex_lock(&hw->fifo_lock);
2093 len = hw->settings->fifo_ops.read_fifo(hw);
2094 mutex_unlock(&hw->fifo_lock);
2095
2096 if (len > 0)
2097 fifo_len += len;
2098 } while (len > 0);
2099
2100 return fifo_len || event ? IRQ_HANDLED : IRQ_NONE;
2101 }
2102
st_lsm6dsx_irq_setup(struct st_lsm6dsx_hw * hw)2103 static int st_lsm6dsx_irq_setup(struct st_lsm6dsx_hw *hw)
2104 {
2105 struct st_sensors_platform_data *pdata;
2106 const struct st_lsm6dsx_reg *reg;
2107 struct device *dev = hw->dev;
2108 unsigned long irq_type;
2109 bool irq_active_low;
2110 int err;
2111
2112 irq_type = irqd_get_trigger_type(irq_get_irq_data(hw->irq));
2113
2114 switch (irq_type) {
2115 case IRQF_TRIGGER_HIGH:
2116 case IRQF_TRIGGER_RISING:
2117 irq_active_low = false;
2118 break;
2119 case IRQF_TRIGGER_LOW:
2120 case IRQF_TRIGGER_FALLING:
2121 irq_active_low = true;
2122 break;
2123 default:
2124 dev_info(hw->dev, "mode %lx unsupported\n", irq_type);
2125 return -EINVAL;
2126 }
2127
2128 reg = &hw->settings->irq_config.hla;
2129 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
2130 ST_LSM6DSX_SHIFT_VAL(irq_active_low,
2131 reg->mask));
2132 if (err < 0)
2133 return err;
2134
2135 pdata = (struct st_sensors_platform_data *)dev->platform_data;
2136 if ((dev_fwnode(dev) && device_property_read_bool(dev, "drive-open-drain")) ||
2137 (pdata && pdata->open_drain)) {
2138 reg = &hw->settings->irq_config.od;
2139 err = regmap_update_bits(hw->regmap, reg->addr, reg->mask,
2140 ST_LSM6DSX_SHIFT_VAL(1, reg->mask));
2141 if (err < 0)
2142 return err;
2143
2144 irq_type |= IRQF_SHARED;
2145 }
2146
2147 err = devm_request_threaded_irq(hw->dev, hw->irq,
2148 NULL,
2149 st_lsm6dsx_handler_thread,
2150 irq_type | IRQF_ONESHOT,
2151 "lsm6dsx", hw);
2152 if (err) {
2153 dev_err(hw->dev, "failed to request trigger irq %d\n",
2154 hw->irq);
2155 return err;
2156 }
2157
2158 return 0;
2159 }
2160
st_lsm6dsx_init_regulators(struct device * dev)2161 static int st_lsm6dsx_init_regulators(struct device *dev)
2162 {
2163 struct st_lsm6dsx_hw *hw = dev_get_drvdata(dev);
2164 int err;
2165
2166 /* vdd-vddio power regulators */
2167 hw->regulators[0].supply = "vdd";
2168 hw->regulators[1].supply = "vddio";
2169 err = devm_regulator_bulk_get(dev, ARRAY_SIZE(hw->regulators),
2170 hw->regulators);
2171 if (err)
2172 return dev_err_probe(dev, err, "failed to get regulators\n");
2173
2174 err = regulator_bulk_enable(ARRAY_SIZE(hw->regulators),
2175 hw->regulators);
2176 if (err) {
2177 dev_err(dev, "failed to enable regulators: %d\n", err);
2178 return err;
2179 }
2180
2181 msleep(50);
2182
2183 return 0;
2184 }
2185
st_lsm6dsx_chip_uninit(void * data)2186 static void st_lsm6dsx_chip_uninit(void *data)
2187 {
2188 struct st_lsm6dsx_hw *hw = data;
2189
2190 regulator_bulk_disable(ARRAY_SIZE(hw->regulators), hw->regulators);
2191 }
2192
st_lsm6dsx_probe(struct device * dev,int irq,int hw_id,struct regmap * regmap)2193 int st_lsm6dsx_probe(struct device *dev, int irq, int hw_id,
2194 struct regmap *regmap)
2195 {
2196 struct st_sensors_platform_data *pdata = dev->platform_data;
2197 const struct st_lsm6dsx_shub_settings *hub_settings;
2198 struct st_lsm6dsx_hw *hw;
2199 const char *name = NULL;
2200 int i, err;
2201
2202 hw = devm_kzalloc(dev, sizeof(*hw), GFP_KERNEL);
2203 if (!hw)
2204 return -ENOMEM;
2205
2206 dev_set_drvdata(dev, (void *)hw);
2207
2208 mutex_init(&hw->fifo_lock);
2209 mutex_init(&hw->conf_lock);
2210 mutex_init(&hw->page_lock);
2211
2212 err = st_lsm6dsx_init_regulators(dev);
2213 if (err)
2214 return err;
2215
2216 err = devm_add_action_or_reset(dev, st_lsm6dsx_chip_uninit, hw);
2217 if (err)
2218 return err;
2219
2220 hw->buff = devm_kzalloc(dev, ST_LSM6DSX_BUFF_SIZE, GFP_KERNEL);
2221 if (!hw->buff)
2222 return -ENOMEM;
2223
2224 hw->dev = dev;
2225 hw->irq = irq;
2226 hw->regmap = regmap;
2227
2228 err = st_lsm6dsx_check_whoami(hw, hw_id, &name);
2229 if (err < 0)
2230 return err;
2231
2232 for (i = 0; i < ST_LSM6DSX_ID_EXT0; i++) {
2233 hw->iio_devs[i] = st_lsm6dsx_alloc_iiodev(hw, i, name);
2234 if (!hw->iio_devs[i])
2235 return -ENOMEM;
2236 }
2237
2238 err = st_lsm6dsx_init_device(hw);
2239 if (err < 0)
2240 return err;
2241
2242 hub_settings = &hw->settings->shub_settings;
2243 if (hub_settings->master_en.addr) {
2244 err = st_lsm6dsx_shub_probe(hw, name);
2245 if (err < 0)
2246 return err;
2247 }
2248
2249 if (hw->irq > 0) {
2250 err = st_lsm6dsx_irq_setup(hw);
2251 if (err < 0)
2252 return err;
2253
2254 err = st_lsm6dsx_fifo_setup(hw);
2255 if (err < 0)
2256 return err;
2257 }
2258
2259 err = iio_read_mount_matrix(hw->dev, &hw->orientation);
2260 if (err)
2261 return err;
2262
2263 for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) {
2264 if (!hw->iio_devs[i])
2265 continue;
2266
2267 err = devm_iio_device_register(hw->dev, hw->iio_devs[i]);
2268 if (err)
2269 return err;
2270 }
2271
2272 if ((dev_fwnode(dev) && device_property_read_bool(dev, "wakeup-source")) ||
2273 (pdata && pdata->wakeup_source))
2274 device_init_wakeup(dev, true);
2275
2276 return 0;
2277 }
2278 EXPORT_SYMBOL(st_lsm6dsx_probe);
2279
st_lsm6dsx_suspend(struct device * dev)2280 static int __maybe_unused st_lsm6dsx_suspend(struct device *dev)
2281 {
2282 struct st_lsm6dsx_hw *hw = dev_get_drvdata(dev);
2283 struct st_lsm6dsx_sensor *sensor;
2284 int i, err = 0;
2285
2286 for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) {
2287 if (!hw->iio_devs[i])
2288 continue;
2289
2290 sensor = iio_priv(hw->iio_devs[i]);
2291 if (!(hw->enable_mask & BIT(sensor->id)))
2292 continue;
2293
2294 if (device_may_wakeup(dev) &&
2295 sensor->id == ST_LSM6DSX_ID_ACC && hw->enable_event) {
2296 /* Enable wake from IRQ */
2297 enable_irq_wake(hw->irq);
2298 continue;
2299 }
2300
2301 if (sensor->id == ST_LSM6DSX_ID_EXT0 ||
2302 sensor->id == ST_LSM6DSX_ID_EXT1 ||
2303 sensor->id == ST_LSM6DSX_ID_EXT2)
2304 err = st_lsm6dsx_shub_set_enable(sensor, false);
2305 else
2306 err = st_lsm6dsx_sensor_set_enable(sensor, false);
2307 if (err < 0)
2308 return err;
2309
2310 hw->suspend_mask |= BIT(sensor->id);
2311 }
2312
2313 if (hw->fifo_mask)
2314 err = st_lsm6dsx_flush_fifo(hw);
2315
2316 return err;
2317 }
2318
st_lsm6dsx_resume(struct device * dev)2319 static int __maybe_unused st_lsm6dsx_resume(struct device *dev)
2320 {
2321 struct st_lsm6dsx_hw *hw = dev_get_drvdata(dev);
2322 struct st_lsm6dsx_sensor *sensor;
2323 int i, err = 0;
2324
2325 for (i = 0; i < ST_LSM6DSX_ID_MAX; i++) {
2326 if (!hw->iio_devs[i])
2327 continue;
2328
2329 sensor = iio_priv(hw->iio_devs[i]);
2330 if (device_may_wakeup(dev) &&
2331 sensor->id == ST_LSM6DSX_ID_ACC && hw->enable_event)
2332 disable_irq_wake(hw->irq);
2333
2334 if (!(hw->suspend_mask & BIT(sensor->id)))
2335 continue;
2336
2337 if (sensor->id == ST_LSM6DSX_ID_EXT0 ||
2338 sensor->id == ST_LSM6DSX_ID_EXT1 ||
2339 sensor->id == ST_LSM6DSX_ID_EXT2)
2340 err = st_lsm6dsx_shub_set_enable(sensor, true);
2341 else
2342 err = st_lsm6dsx_sensor_set_enable(sensor, true);
2343 if (err < 0)
2344 return err;
2345
2346 hw->suspend_mask &= ~BIT(sensor->id);
2347 }
2348
2349 if (hw->fifo_mask)
2350 err = st_lsm6dsx_resume_fifo(hw);
2351
2352 return err;
2353 }
2354
2355 const struct dev_pm_ops st_lsm6dsx_pm_ops = {
2356 SET_SYSTEM_SLEEP_PM_OPS(st_lsm6dsx_suspend, st_lsm6dsx_resume)
2357 };
2358 EXPORT_SYMBOL(st_lsm6dsx_pm_ops);
2359
2360 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo.bianconi@st.com>");
2361 MODULE_AUTHOR("Denis Ciocca <denis.ciocca@st.com>");
2362 MODULE_DESCRIPTION("STMicroelectronics st_lsm6dsx driver");
2363 MODULE_LICENSE("GPL v2");
2364
