1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * srmmu.c: SRMMU specific routines for memory management.
4 *
5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
6 * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
7 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
8 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
9 * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org)
10 */
11
12 #include <linux/seq_file.h>
13 #include <linux/spinlock.h>
14 #include <linux/memblock.h>
15 #include <linux/pagemap.h>
16 #include <linux/vmalloc.h>
17 #include <linux/kdebug.h>
18 #include <linux/export.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/log2.h>
22 #include <linux/gfp.h>
23 #include <linux/fs.h>
24 #include <linux/mm.h>
25
26 #include <asm/mmu_context.h>
27 #include <asm/cacheflush.h>
28 #include <asm/tlbflush.h>
29 #include <asm/io-unit.h>
30 #include <asm/pgalloc.h>
31 #include <asm/pgtable.h>
32 #include <asm/bitext.h>
33 #include <asm/vaddrs.h>
34 #include <asm/cache.h>
35 #include <asm/traps.h>
36 #include <asm/oplib.h>
37 #include <asm/mbus.h>
38 #include <asm/page.h>
39 #include <asm/asi.h>
40 #include <asm/smp.h>
41 #include <asm/io.h>
42
43 /* Now the cpu specific definitions. */
44 #include <asm/turbosparc.h>
45 #include <asm/tsunami.h>
46 #include <asm/viking.h>
47 #include <asm/swift.h>
48 #include <asm/leon.h>
49 #include <asm/mxcc.h>
50 #include <asm/ross.h>
51
52 #include "mm_32.h"
53
54 enum mbus_module srmmu_modtype;
55 static unsigned int hwbug_bitmask;
56 int vac_cache_size;
57 EXPORT_SYMBOL(vac_cache_size);
58 int vac_line_size;
59
60 extern struct resource sparc_iomap;
61
62 extern unsigned long last_valid_pfn;
63
64 static pgd_t *srmmu_swapper_pg_dir;
65
66 const struct sparc32_cachetlb_ops *sparc32_cachetlb_ops;
67 EXPORT_SYMBOL(sparc32_cachetlb_ops);
68
69 #ifdef CONFIG_SMP
70 const struct sparc32_cachetlb_ops *local_ops;
71
72 #define FLUSH_BEGIN(mm)
73 #define FLUSH_END
74 #else
75 #define FLUSH_BEGIN(mm) if ((mm)->context != NO_CONTEXT) {
76 #define FLUSH_END }
77 #endif
78
79 int flush_page_for_dma_global = 1;
80
81 char *srmmu_name;
82
83 ctxd_t *srmmu_ctx_table_phys;
84 static ctxd_t *srmmu_context_table;
85
86 int viking_mxcc_present;
87 static DEFINE_SPINLOCK(srmmu_context_spinlock);
88
89 static int is_hypersparc;
90
91 static int srmmu_cache_pagetables;
92
93 /* these will be initialized in srmmu_nocache_calcsize() */
94 static unsigned long srmmu_nocache_size;
95 static unsigned long srmmu_nocache_end;
96
97 /* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */
98 #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)
99
100 /* The context table is a nocache user with the biggest alignment needs. */
101 #define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS)
102
103 void *srmmu_nocache_pool;
104 static struct bit_map srmmu_nocache_map;
105
srmmu_pmd_none(pmd_t pmd)106 static inline int srmmu_pmd_none(pmd_t pmd)
107 { return !(pmd_val(pmd) & 0xFFFFFFF); }
108
109 /* XXX should we hyper_flush_whole_icache here - Anton */
srmmu_ctxd_set(ctxd_t * ctxp,pgd_t * pgdp)110 static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp)
111 {
112 pte_t pte;
113
114 pte = __pte((SRMMU_ET_PTD | (__nocache_pa(pgdp) >> 4)));
115 set_pte((pte_t *)ctxp, pte);
116 }
117
118 /*
119 * Locations of MSI Registers.
120 */
121 #define MSI_MBUS_ARBEN 0xe0001008 /* MBus Arbiter Enable register */
122
123 /*
124 * Useful bits in the MSI Registers.
125 */
126 #define MSI_ASYNC_MODE 0x80000000 /* Operate the MSI asynchronously */
127
msi_set_sync(void)128 static void msi_set_sync(void)
129 {
130 __asm__ __volatile__ ("lda [%0] %1, %%g3\n\t"
131 "andn %%g3, %2, %%g3\n\t"
132 "sta %%g3, [%0] %1\n\t" : :
133 "r" (MSI_MBUS_ARBEN),
134 "i" (ASI_M_CTL), "r" (MSI_ASYNC_MODE) : "g3");
135 }
136
pmd_set(pmd_t * pmdp,pte_t * ptep)137 void pmd_set(pmd_t *pmdp, pte_t *ptep)
138 {
139 unsigned long ptp = __nocache_pa(ptep) >> 4;
140 set_pte((pte_t *)&pmd_val(*pmdp), __pte(SRMMU_ET_PTD | ptp));
141 }
142
143 /*
144 * size: bytes to allocate in the nocache area.
145 * align: bytes, number to align at.
146 * Returns the virtual address of the allocated area.
147 */
__srmmu_get_nocache(int size,int align)148 static void *__srmmu_get_nocache(int size, int align)
149 {
150 int offset, minsz = 1 << SRMMU_NOCACHE_BITMAP_SHIFT;
151 unsigned long addr;
152
153 if (size < minsz) {
154 printk(KERN_ERR "Size 0x%x too small for nocache request\n",
155 size);
156 size = minsz;
157 }
158 if (size & (minsz - 1)) {
159 printk(KERN_ERR "Size 0x%x unaligned in nocache request\n",
160 size);
161 size += minsz - 1;
162 }
163 BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX);
164
165 offset = bit_map_string_get(&srmmu_nocache_map,
166 size >> SRMMU_NOCACHE_BITMAP_SHIFT,
167 align >> SRMMU_NOCACHE_BITMAP_SHIFT);
168 if (offset == -1) {
169 printk(KERN_ERR "srmmu: out of nocache %d: %d/%d\n",
170 size, (int) srmmu_nocache_size,
171 srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
172 return NULL;
173 }
174
175 addr = SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT);
176 return (void *)addr;
177 }
178
srmmu_get_nocache(int size,int align)179 void *srmmu_get_nocache(int size, int align)
180 {
181 void *tmp;
182
183 tmp = __srmmu_get_nocache(size, align);
184
185 if (tmp)
186 memset(tmp, 0, size);
187
188 return tmp;
189 }
190
srmmu_free_nocache(void * addr,int size)191 void srmmu_free_nocache(void *addr, int size)
192 {
193 unsigned long vaddr;
194 int offset;
195
196 vaddr = (unsigned long)addr;
197 if (vaddr < SRMMU_NOCACHE_VADDR) {
198 printk("Vaddr %lx is smaller than nocache base 0x%lx\n",
199 vaddr, (unsigned long)SRMMU_NOCACHE_VADDR);
200 BUG();
201 }
202 if (vaddr + size > srmmu_nocache_end) {
203 printk("Vaddr %lx is bigger than nocache end 0x%lx\n",
204 vaddr, srmmu_nocache_end);
205 BUG();
206 }
207 if (!is_power_of_2(size)) {
208 printk("Size 0x%x is not a power of 2\n", size);
209 BUG();
210 }
211 if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
212 printk("Size 0x%x is too small\n", size);
213 BUG();
214 }
215 if (vaddr & (size - 1)) {
216 printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size);
217 BUG();
218 }
219
220 offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT;
221 size = size >> SRMMU_NOCACHE_BITMAP_SHIFT;
222
223 bit_map_clear(&srmmu_nocache_map, offset, size);
224 }
225
226 static void srmmu_early_allocate_ptable_skeleton(unsigned long start,
227 unsigned long end);
228
229 /* Return how much physical memory we have. */
probe_memory(void)230 static unsigned long __init probe_memory(void)
231 {
232 unsigned long total = 0;
233 int i;
234
235 for (i = 0; sp_banks[i].num_bytes; i++)
236 total += sp_banks[i].num_bytes;
237
238 return total;
239 }
240
241 /*
242 * Reserve nocache dynamically proportionally to the amount of
243 * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002
244 */
srmmu_nocache_calcsize(void)245 static void __init srmmu_nocache_calcsize(void)
246 {
247 unsigned long sysmemavail = probe_memory() / 1024;
248 int srmmu_nocache_npages;
249
250 srmmu_nocache_npages =
251 sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256;
252
253 /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */
254 // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256;
255 if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES)
256 srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES;
257
258 /* anything above 1280 blows up */
259 if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES)
260 srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES;
261
262 srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE;
263 srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size;
264 }
265
srmmu_nocache_init(void)266 static void __init srmmu_nocache_init(void)
267 {
268 void *srmmu_nocache_bitmap;
269 unsigned int bitmap_bits;
270 pgd_t *pgd;
271 p4d_t *p4d;
272 pud_t *pud;
273 pmd_t *pmd;
274 pte_t *pte;
275 unsigned long paddr, vaddr;
276 unsigned long pteval;
277
278 bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT;
279
280 srmmu_nocache_pool = memblock_alloc(srmmu_nocache_size,
281 SRMMU_NOCACHE_ALIGN_MAX);
282 if (!srmmu_nocache_pool)
283 panic("%s: Failed to allocate %lu bytes align=0x%x\n",
284 __func__, srmmu_nocache_size, SRMMU_NOCACHE_ALIGN_MAX);
285 memset(srmmu_nocache_pool, 0, srmmu_nocache_size);
286
287 srmmu_nocache_bitmap =
288 memblock_alloc(BITS_TO_LONGS(bitmap_bits) * sizeof(long),
289 SMP_CACHE_BYTES);
290 if (!srmmu_nocache_bitmap)
291 panic("%s: Failed to allocate %zu bytes\n", __func__,
292 BITS_TO_LONGS(bitmap_bits) * sizeof(long));
293 bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits);
294
295 srmmu_swapper_pg_dir = __srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
296 memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE);
297 init_mm.pgd = srmmu_swapper_pg_dir;
298
299 srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end);
300
301 paddr = __pa((unsigned long)srmmu_nocache_pool);
302 vaddr = SRMMU_NOCACHE_VADDR;
303
304 while (vaddr < srmmu_nocache_end) {
305 pgd = pgd_offset_k(vaddr);
306 p4d = p4d_offset(pgd, vaddr);
307 pud = pud_offset(p4d, vaddr);
308 pmd = pmd_offset(__nocache_fix(pud), vaddr);
309 pte = pte_offset_kernel(__nocache_fix(pmd), vaddr);
310
311 pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV);
312
313 if (srmmu_cache_pagetables)
314 pteval |= SRMMU_CACHE;
315
316 set_pte(__nocache_fix(pte), __pte(pteval));
317
318 vaddr += PAGE_SIZE;
319 paddr += PAGE_SIZE;
320 }
321
322 flush_cache_all();
323 flush_tlb_all();
324 }
325
get_pgd_fast(void)326 pgd_t *get_pgd_fast(void)
327 {
328 pgd_t *pgd = NULL;
329
330 pgd = __srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
331 if (pgd) {
332 pgd_t *init = pgd_offset_k(0);
333 memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
334 memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
335 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
336 }
337
338 return pgd;
339 }
340
341 /*
342 * Hardware needs alignment to 256 only, but we align to whole page size
343 * to reduce fragmentation problems due to the buddy principle.
344 * XXX Provide actual fragmentation statistics in /proc.
345 *
346 * Alignments up to the page size are the same for physical and virtual
347 * addresses of the nocache area.
348 */
pte_alloc_one(struct mm_struct * mm)349 pgtable_t pte_alloc_one(struct mm_struct *mm)
350 {
351 pte_t *ptep;
352 struct page *page;
353
354 if ((ptep = pte_alloc_one_kernel(mm)) == 0)
355 return NULL;
356 page = pfn_to_page(__nocache_pa((unsigned long)ptep) >> PAGE_SHIFT);
357 spin_lock(&mm->page_table_lock);
358 if (page_ref_inc_return(page) == 2 && !pgtable_pte_page_ctor(page)) {
359 page_ref_dec(page);
360 ptep = NULL;
361 }
362 spin_unlock(&mm->page_table_lock);
363
364 return ptep;
365 }
366
pte_free(struct mm_struct * mm,pgtable_t ptep)367 void pte_free(struct mm_struct *mm, pgtable_t ptep)
368 {
369 struct page *page;
370
371 page = pfn_to_page(__nocache_pa((unsigned long)ptep) >> PAGE_SHIFT);
372 spin_lock(&mm->page_table_lock);
373 if (page_ref_dec_return(page) == 1)
374 pgtable_pte_page_dtor(page);
375 spin_unlock(&mm->page_table_lock);
376
377 srmmu_free_nocache(ptep, SRMMU_PTE_TABLE_SIZE);
378 }
379
380 /* context handling - a dynamically sized pool is used */
381 #define NO_CONTEXT -1
382
383 struct ctx_list {
384 struct ctx_list *next;
385 struct ctx_list *prev;
386 unsigned int ctx_number;
387 struct mm_struct *ctx_mm;
388 };
389
390 static struct ctx_list *ctx_list_pool;
391 static struct ctx_list ctx_free;
392 static struct ctx_list ctx_used;
393
394 /* At boot time we determine the number of contexts */
395 static int num_contexts;
396
remove_from_ctx_list(struct ctx_list * entry)397 static inline void remove_from_ctx_list(struct ctx_list *entry)
398 {
399 entry->next->prev = entry->prev;
400 entry->prev->next = entry->next;
401 }
402
add_to_ctx_list(struct ctx_list * head,struct ctx_list * entry)403 static inline void add_to_ctx_list(struct ctx_list *head, struct ctx_list *entry)
404 {
405 entry->next = head;
406 (entry->prev = head->prev)->next = entry;
407 head->prev = entry;
408 }
409 #define add_to_free_ctxlist(entry) add_to_ctx_list(&ctx_free, entry)
410 #define add_to_used_ctxlist(entry) add_to_ctx_list(&ctx_used, entry)
411
412
alloc_context(struct mm_struct * old_mm,struct mm_struct * mm)413 static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm)
414 {
415 struct ctx_list *ctxp;
416
417 ctxp = ctx_free.next;
418 if (ctxp != &ctx_free) {
419 remove_from_ctx_list(ctxp);
420 add_to_used_ctxlist(ctxp);
421 mm->context = ctxp->ctx_number;
422 ctxp->ctx_mm = mm;
423 return;
424 }
425 ctxp = ctx_used.next;
426 if (ctxp->ctx_mm == old_mm)
427 ctxp = ctxp->next;
428 if (ctxp == &ctx_used)
429 panic("out of mmu contexts");
430 flush_cache_mm(ctxp->ctx_mm);
431 flush_tlb_mm(ctxp->ctx_mm);
432 remove_from_ctx_list(ctxp);
433 add_to_used_ctxlist(ctxp);
434 ctxp->ctx_mm->context = NO_CONTEXT;
435 ctxp->ctx_mm = mm;
436 mm->context = ctxp->ctx_number;
437 }
438
free_context(int context)439 static inline void free_context(int context)
440 {
441 struct ctx_list *ctx_old;
442
443 ctx_old = ctx_list_pool + context;
444 remove_from_ctx_list(ctx_old);
445 add_to_free_ctxlist(ctx_old);
446 }
447
sparc_context_init(int numctx)448 static void __init sparc_context_init(int numctx)
449 {
450 int ctx;
451 unsigned long size;
452
453 size = numctx * sizeof(struct ctx_list);
454 ctx_list_pool = memblock_alloc(size, SMP_CACHE_BYTES);
455 if (!ctx_list_pool)
456 panic("%s: Failed to allocate %lu bytes\n", __func__, size);
457
458 for (ctx = 0; ctx < numctx; ctx++) {
459 struct ctx_list *clist;
460
461 clist = (ctx_list_pool + ctx);
462 clist->ctx_number = ctx;
463 clist->ctx_mm = NULL;
464 }
465 ctx_free.next = ctx_free.prev = &ctx_free;
466 ctx_used.next = ctx_used.prev = &ctx_used;
467 for (ctx = 0; ctx < numctx; ctx++)
468 add_to_free_ctxlist(ctx_list_pool + ctx);
469 }
470
switch_mm(struct mm_struct * old_mm,struct mm_struct * mm,struct task_struct * tsk)471 void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
472 struct task_struct *tsk)
473 {
474 unsigned long flags;
475
476 if (mm->context == NO_CONTEXT) {
477 spin_lock_irqsave(&srmmu_context_spinlock, flags);
478 alloc_context(old_mm, mm);
479 spin_unlock_irqrestore(&srmmu_context_spinlock, flags);
480 srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd);
481 }
482
483 if (sparc_cpu_model == sparc_leon)
484 leon_switch_mm();
485
486 if (is_hypersparc)
487 hyper_flush_whole_icache();
488
489 srmmu_set_context(mm->context);
490 }
491
492 /* Low level IO area allocation on the SRMMU. */
srmmu_mapioaddr(unsigned long physaddr,unsigned long virt_addr,int bus_type)493 static inline void srmmu_mapioaddr(unsigned long physaddr,
494 unsigned long virt_addr, int bus_type)
495 {
496 pgd_t *pgdp;
497 p4d_t *p4dp;
498 pud_t *pudp;
499 pmd_t *pmdp;
500 pte_t *ptep;
501 unsigned long tmp;
502
503 physaddr &= PAGE_MASK;
504 pgdp = pgd_offset_k(virt_addr);
505 p4dp = p4d_offset(pgdp, virt_addr);
506 pudp = pud_offset(p4dp, virt_addr);
507 pmdp = pmd_offset(pudp, virt_addr);
508 ptep = pte_offset_kernel(pmdp, virt_addr);
509 tmp = (physaddr >> 4) | SRMMU_ET_PTE;
510
511 /* I need to test whether this is consistent over all
512 * sun4m's. The bus_type represents the upper 4 bits of
513 * 36-bit physical address on the I/O space lines...
514 */
515 tmp |= (bus_type << 28);
516 tmp |= SRMMU_PRIV;
517 __flush_page_to_ram(virt_addr);
518 set_pte(ptep, __pte(tmp));
519 }
520
srmmu_mapiorange(unsigned int bus,unsigned long xpa,unsigned long xva,unsigned int len)521 void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
522 unsigned long xva, unsigned int len)
523 {
524 while (len != 0) {
525 len -= PAGE_SIZE;
526 srmmu_mapioaddr(xpa, xva, bus);
527 xva += PAGE_SIZE;
528 xpa += PAGE_SIZE;
529 }
530 flush_tlb_all();
531 }
532
srmmu_unmapioaddr(unsigned long virt_addr)533 static inline void srmmu_unmapioaddr(unsigned long virt_addr)
534 {
535 pgd_t *pgdp;
536 p4d_t *p4dp;
537 pud_t *pudp;
538 pmd_t *pmdp;
539 pte_t *ptep;
540
541
542 pgdp = pgd_offset_k(virt_addr);
543 p4dp = p4d_offset(pgdp, virt_addr);
544 pudp = pud_offset(p4dp, virt_addr);
545 pmdp = pmd_offset(pudp, virt_addr);
546 ptep = pte_offset_kernel(pmdp, virt_addr);
547
548 /* No need to flush uncacheable page. */
549 __pte_clear(ptep);
550 }
551
srmmu_unmapiorange(unsigned long virt_addr,unsigned int len)552 void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len)
553 {
554 while (len != 0) {
555 len -= PAGE_SIZE;
556 srmmu_unmapioaddr(virt_addr);
557 virt_addr += PAGE_SIZE;
558 }
559 flush_tlb_all();
560 }
561
562 /* tsunami.S */
563 extern void tsunami_flush_cache_all(void);
564 extern void tsunami_flush_cache_mm(struct mm_struct *mm);
565 extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
566 extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
567 extern void tsunami_flush_page_to_ram(unsigned long page);
568 extern void tsunami_flush_page_for_dma(unsigned long page);
569 extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
570 extern void tsunami_flush_tlb_all(void);
571 extern void tsunami_flush_tlb_mm(struct mm_struct *mm);
572 extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
573 extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
574 extern void tsunami_setup_blockops(void);
575
576 /* swift.S */
577 extern void swift_flush_cache_all(void);
578 extern void swift_flush_cache_mm(struct mm_struct *mm);
579 extern void swift_flush_cache_range(struct vm_area_struct *vma,
580 unsigned long start, unsigned long end);
581 extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
582 extern void swift_flush_page_to_ram(unsigned long page);
583 extern void swift_flush_page_for_dma(unsigned long page);
584 extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
585 extern void swift_flush_tlb_all(void);
586 extern void swift_flush_tlb_mm(struct mm_struct *mm);
587 extern void swift_flush_tlb_range(struct vm_area_struct *vma,
588 unsigned long start, unsigned long end);
589 extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
590
591 #if 0 /* P3: deadwood to debug precise flushes on Swift. */
592 void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
593 {
594 int cctx, ctx1;
595
596 page &= PAGE_MASK;
597 if ((ctx1 = vma->vm_mm->context) != -1) {
598 cctx = srmmu_get_context();
599 /* Is context # ever different from current context? P3 */
600 if (cctx != ctx1) {
601 printk("flush ctx %02x curr %02x\n", ctx1, cctx);
602 srmmu_set_context(ctx1);
603 swift_flush_page(page);
604 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
605 "r" (page), "i" (ASI_M_FLUSH_PROBE));
606 srmmu_set_context(cctx);
607 } else {
608 /* Rm. prot. bits from virt. c. */
609 /* swift_flush_cache_all(); */
610 /* swift_flush_cache_page(vma, page); */
611 swift_flush_page(page);
612
613 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
614 "r" (page), "i" (ASI_M_FLUSH_PROBE));
615 /* same as above: srmmu_flush_tlb_page() */
616 }
617 }
618 }
619 #endif
620
621 /*
622 * The following are all MBUS based SRMMU modules, and therefore could
623 * be found in a multiprocessor configuration. On the whole, these
624 * chips seems to be much more touchy about DVMA and page tables
625 * with respect to cache coherency.
626 */
627
628 /* viking.S */
629 extern void viking_flush_cache_all(void);
630 extern void viking_flush_cache_mm(struct mm_struct *mm);
631 extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
632 unsigned long end);
633 extern void viking_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
634 extern void viking_flush_page_to_ram(unsigned long page);
635 extern void viking_flush_page_for_dma(unsigned long page);
636 extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr);
637 extern void viking_flush_page(unsigned long page);
638 extern void viking_mxcc_flush_page(unsigned long page);
639 extern void viking_flush_tlb_all(void);
640 extern void viking_flush_tlb_mm(struct mm_struct *mm);
641 extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
642 unsigned long end);
643 extern void viking_flush_tlb_page(struct vm_area_struct *vma,
644 unsigned long page);
645 extern void sun4dsmp_flush_tlb_all(void);
646 extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm);
647 extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
648 unsigned long end);
649 extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma,
650 unsigned long page);
651
652 /* hypersparc.S */
653 extern void hypersparc_flush_cache_all(void);
654 extern void hypersparc_flush_cache_mm(struct mm_struct *mm);
655 extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
656 extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
657 extern void hypersparc_flush_page_to_ram(unsigned long page);
658 extern void hypersparc_flush_page_for_dma(unsigned long page);
659 extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
660 extern void hypersparc_flush_tlb_all(void);
661 extern void hypersparc_flush_tlb_mm(struct mm_struct *mm);
662 extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
663 extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
664 extern void hypersparc_setup_blockops(void);
665
666 /*
667 * NOTE: All of this startup code assumes the low 16mb (approx.) of
668 * kernel mappings are done with one single contiguous chunk of
669 * ram. On small ram machines (classics mainly) we only get
670 * around 8mb mapped for us.
671 */
672
early_pgtable_allocfail(char * type)673 static void __init early_pgtable_allocfail(char *type)
674 {
675 prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
676 prom_halt();
677 }
678
srmmu_early_allocate_ptable_skeleton(unsigned long start,unsigned long end)679 static void __init srmmu_early_allocate_ptable_skeleton(unsigned long start,
680 unsigned long end)
681 {
682 pgd_t *pgdp;
683 p4d_t *p4dp;
684 pud_t *pudp;
685 pmd_t *pmdp;
686 pte_t *ptep;
687
688 while (start < end) {
689 pgdp = pgd_offset_k(start);
690 p4dp = p4d_offset(pgdp, start);
691 pudp = pud_offset(p4dp, start);
692 if (pud_none(*(pud_t *)__nocache_fix(pudp))) {
693 pmdp = __srmmu_get_nocache(
694 SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
695 if (pmdp == NULL)
696 early_pgtable_allocfail("pmd");
697 memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
698 pud_set(__nocache_fix(pudp), pmdp);
699 }
700 pmdp = pmd_offset(__nocache_fix(pudp), start);
701 if (srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
702 ptep = __srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
703 if (ptep == NULL)
704 early_pgtable_allocfail("pte");
705 memset(__nocache_fix(ptep), 0, PTE_SIZE);
706 pmd_set(__nocache_fix(pmdp), ptep);
707 }
708 if (start > (0xffffffffUL - PMD_SIZE))
709 break;
710 start = (start + PMD_SIZE) & PMD_MASK;
711 }
712 }
713
srmmu_allocate_ptable_skeleton(unsigned long start,unsigned long end)714 static void __init srmmu_allocate_ptable_skeleton(unsigned long start,
715 unsigned long end)
716 {
717 pgd_t *pgdp;
718 p4d_t *p4dp;
719 pud_t *pudp;
720 pmd_t *pmdp;
721 pte_t *ptep;
722
723 while (start < end) {
724 pgdp = pgd_offset_k(start);
725 p4dp = p4d_offset(pgdp, start);
726 pudp = pud_offset(p4dp, start);
727 if (pud_none(*pudp)) {
728 pmdp = __srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
729 if (pmdp == NULL)
730 early_pgtable_allocfail("pmd");
731 memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE);
732 pud_set((pud_t *)pgdp, pmdp);
733 }
734 pmdp = pmd_offset(pudp, start);
735 if (srmmu_pmd_none(*pmdp)) {
736 ptep = __srmmu_get_nocache(PTE_SIZE,
737 PTE_SIZE);
738 if (ptep == NULL)
739 early_pgtable_allocfail("pte");
740 memset(ptep, 0, PTE_SIZE);
741 pmd_set(pmdp, ptep);
742 }
743 if (start > (0xffffffffUL - PMD_SIZE))
744 break;
745 start = (start + PMD_SIZE) & PMD_MASK;
746 }
747 }
748
749 /* These flush types are not available on all chips... */
srmmu_probe(unsigned long vaddr)750 static inline unsigned long srmmu_probe(unsigned long vaddr)
751 {
752 unsigned long retval;
753
754 if (sparc_cpu_model != sparc_leon) {
755
756 vaddr &= PAGE_MASK;
757 __asm__ __volatile__("lda [%1] %2, %0\n\t" :
758 "=r" (retval) :
759 "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
760 } else {
761 retval = leon_swprobe(vaddr, NULL);
762 }
763 return retval;
764 }
765
766 /*
767 * This is much cleaner than poking around physical address space
768 * looking at the prom's page table directly which is what most
769 * other OS's do. Yuck... this is much better.
770 */
srmmu_inherit_prom_mappings(unsigned long start,unsigned long end)771 static void __init srmmu_inherit_prom_mappings(unsigned long start,
772 unsigned long end)
773 {
774 unsigned long probed;
775 unsigned long addr;
776 pgd_t *pgdp;
777 p4d_t *p4dp;
778 pud_t *pudp;
779 pmd_t *pmdp;
780 pte_t *ptep;
781 int what; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
782
783 while (start <= end) {
784 if (start == 0)
785 break; /* probably wrap around */
786 if (start == 0xfef00000)
787 start = KADB_DEBUGGER_BEGVM;
788 probed = srmmu_probe(start);
789 if (!probed) {
790 /* continue probing until we find an entry */
791 start += PAGE_SIZE;
792 continue;
793 }
794
795 /* A red snapper, see what it really is. */
796 what = 0;
797 addr = start - PAGE_SIZE;
798
799 if (!(start & ~(PMD_MASK))) {
800 if (srmmu_probe(addr + PMD_SIZE) == probed)
801 what = 1;
802 }
803
804 if (!(start & ~(PGDIR_MASK))) {
805 if (srmmu_probe(addr + PGDIR_SIZE) == probed)
806 what = 2;
807 }
808
809 pgdp = pgd_offset_k(start);
810 p4dp = p4d_offset(pgdp, start);
811 pudp = pud_offset(p4dp, start);
812 if (what == 2) {
813 *(pgd_t *)__nocache_fix(pgdp) = __pgd(probed);
814 start += PGDIR_SIZE;
815 continue;
816 }
817 if (pud_none(*(pud_t *)__nocache_fix(pudp))) {
818 pmdp = __srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE,
819 SRMMU_PMD_TABLE_SIZE);
820 if (pmdp == NULL)
821 early_pgtable_allocfail("pmd");
822 memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
823 pud_set(__nocache_fix(pudp), pmdp);
824 }
825 pmdp = pmd_offset(__nocache_fix(pgdp), start);
826 if (what == 1) {
827 *(pmd_t *)__nocache_fix(pmdp) = __pmd(probed);
828 start += PMD_SIZE;
829 continue;
830 }
831 if (srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
832 ptep = __srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
833 if (ptep == NULL)
834 early_pgtable_allocfail("pte");
835 memset(__nocache_fix(ptep), 0, PTE_SIZE);
836 pmd_set(__nocache_fix(pmdp), ptep);
837 }
838 ptep = pte_offset_kernel(__nocache_fix(pmdp), start);
839 *(pte_t *)__nocache_fix(ptep) = __pte(probed);
840 start += PAGE_SIZE;
841 }
842 }
843
844 #define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID)
845
846 /* Create a third-level SRMMU 16MB page mapping. */
do_large_mapping(unsigned long vaddr,unsigned long phys_base)847 static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base)
848 {
849 pgd_t *pgdp = pgd_offset_k(vaddr);
850 unsigned long big_pte;
851
852 big_pte = KERNEL_PTE(phys_base >> 4);
853 *(pgd_t *)__nocache_fix(pgdp) = __pgd(big_pte);
854 }
855
856 /* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */
map_spbank(unsigned long vbase,int sp_entry)857 static unsigned long __init map_spbank(unsigned long vbase, int sp_entry)
858 {
859 unsigned long pstart = (sp_banks[sp_entry].base_addr & PGDIR_MASK);
860 unsigned long vstart = (vbase & PGDIR_MASK);
861 unsigned long vend = PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes);
862 /* Map "low" memory only */
863 const unsigned long min_vaddr = PAGE_OFFSET;
864 const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM;
865
866 if (vstart < min_vaddr || vstart >= max_vaddr)
867 return vstart;
868
869 if (vend > max_vaddr || vend < min_vaddr)
870 vend = max_vaddr;
871
872 while (vstart < vend) {
873 do_large_mapping(vstart, pstart);
874 vstart += PGDIR_SIZE; pstart += PGDIR_SIZE;
875 }
876 return vstart;
877 }
878
map_kernel(void)879 static void __init map_kernel(void)
880 {
881 int i;
882
883 if (phys_base > 0) {
884 do_large_mapping(PAGE_OFFSET, phys_base);
885 }
886
887 for (i = 0; sp_banks[i].num_bytes != 0; i++) {
888 map_spbank((unsigned long)__va(sp_banks[i].base_addr), i);
889 }
890 }
891
892 void (*poke_srmmu)(void) = NULL;
893
srmmu_paging_init(void)894 void __init srmmu_paging_init(void)
895 {
896 int i;
897 phandle cpunode;
898 char node_str[128];
899 pgd_t *pgd;
900 p4d_t *p4d;
901 pud_t *pud;
902 pmd_t *pmd;
903 pte_t *pte;
904 unsigned long pages_avail;
905
906 init_mm.context = (unsigned long) NO_CONTEXT;
907 sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */
908
909 if (sparc_cpu_model == sun4d)
910 num_contexts = 65536; /* We know it is Viking */
911 else {
912 /* Find the number of contexts on the srmmu. */
913 cpunode = prom_getchild(prom_root_node);
914 num_contexts = 0;
915 while (cpunode != 0) {
916 prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
917 if (!strcmp(node_str, "cpu")) {
918 num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
919 break;
920 }
921 cpunode = prom_getsibling(cpunode);
922 }
923 }
924
925 if (!num_contexts) {
926 prom_printf("Something wrong, can't find cpu node in paging_init.\n");
927 prom_halt();
928 }
929
930 pages_avail = 0;
931 last_valid_pfn = bootmem_init(&pages_avail);
932
933 srmmu_nocache_calcsize();
934 srmmu_nocache_init();
935 srmmu_inherit_prom_mappings(0xfe400000, (LINUX_OPPROM_ENDVM - PAGE_SIZE));
936 map_kernel();
937
938 /* ctx table has to be physically aligned to its size */
939 srmmu_context_table = __srmmu_get_nocache(num_contexts * sizeof(ctxd_t), num_contexts * sizeof(ctxd_t));
940 srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa(srmmu_context_table);
941
942 for (i = 0; i < num_contexts; i++)
943 srmmu_ctxd_set((ctxd_t *)__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir);
944
945 flush_cache_all();
946 srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys);
947 #ifdef CONFIG_SMP
948 /* Stop from hanging here... */
949 local_ops->tlb_all();
950 #else
951 flush_tlb_all();
952 #endif
953 poke_srmmu();
954
955 srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END);
956 srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END);
957
958 srmmu_allocate_ptable_skeleton(
959 __fix_to_virt(__end_of_fixed_addresses - 1), FIXADDR_TOP);
960 srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END);
961
962 pgd = pgd_offset_k(PKMAP_BASE);
963 p4d = p4d_offset(pgd, PKMAP_BASE);
964 pud = pud_offset(p4d, PKMAP_BASE);
965 pmd = pmd_offset(pud, PKMAP_BASE);
966 pte = pte_offset_kernel(pmd, PKMAP_BASE);
967 pkmap_page_table = pte;
968
969 flush_cache_all();
970 flush_tlb_all();
971
972 sparc_context_init(num_contexts);
973
974 kmap_init();
975
976 {
977 unsigned long max_zone_pfn[MAX_NR_ZONES] = { 0 };
978
979 max_zone_pfn[ZONE_DMA] = max_low_pfn;
980 max_zone_pfn[ZONE_NORMAL] = max_low_pfn;
981 max_zone_pfn[ZONE_HIGHMEM] = highend_pfn;
982
983 free_area_init(max_zone_pfn);
984 }
985 }
986
mmu_info(struct seq_file * m)987 void mmu_info(struct seq_file *m)
988 {
989 seq_printf(m,
990 "MMU type\t: %s\n"
991 "contexts\t: %d\n"
992 "nocache total\t: %ld\n"
993 "nocache used\t: %d\n",
994 srmmu_name,
995 num_contexts,
996 srmmu_nocache_size,
997 srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
998 }
999
init_new_context(struct task_struct * tsk,struct mm_struct * mm)1000 int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
1001 {
1002 mm->context = NO_CONTEXT;
1003 return 0;
1004 }
1005
destroy_context(struct mm_struct * mm)1006 void destroy_context(struct mm_struct *mm)
1007 {
1008 unsigned long flags;
1009
1010 if (mm->context != NO_CONTEXT) {
1011 flush_cache_mm(mm);
1012 srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir);
1013 flush_tlb_mm(mm);
1014 spin_lock_irqsave(&srmmu_context_spinlock, flags);
1015 free_context(mm->context);
1016 spin_unlock_irqrestore(&srmmu_context_spinlock, flags);
1017 mm->context = NO_CONTEXT;
1018 }
1019 }
1020
1021 /* Init various srmmu chip types. */
srmmu_is_bad(void)1022 static void __init srmmu_is_bad(void)
1023 {
1024 prom_printf("Could not determine SRMMU chip type.\n");
1025 prom_halt();
1026 }
1027
init_vac_layout(void)1028 static void __init init_vac_layout(void)
1029 {
1030 phandle nd;
1031 int cache_lines;
1032 char node_str[128];
1033 #ifdef CONFIG_SMP
1034 int cpu = 0;
1035 unsigned long max_size = 0;
1036 unsigned long min_line_size = 0x10000000;
1037 #endif
1038
1039 nd = prom_getchild(prom_root_node);
1040 while ((nd = prom_getsibling(nd)) != 0) {
1041 prom_getstring(nd, "device_type", node_str, sizeof(node_str));
1042 if (!strcmp(node_str, "cpu")) {
1043 vac_line_size = prom_getint(nd, "cache-line-size");
1044 if (vac_line_size == -1) {
1045 prom_printf("can't determine cache-line-size, halting.\n");
1046 prom_halt();
1047 }
1048 cache_lines = prom_getint(nd, "cache-nlines");
1049 if (cache_lines == -1) {
1050 prom_printf("can't determine cache-nlines, halting.\n");
1051 prom_halt();
1052 }
1053
1054 vac_cache_size = cache_lines * vac_line_size;
1055 #ifdef CONFIG_SMP
1056 if (vac_cache_size > max_size)
1057 max_size = vac_cache_size;
1058 if (vac_line_size < min_line_size)
1059 min_line_size = vac_line_size;
1060 //FIXME: cpus not contiguous!!
1061 cpu++;
1062 if (cpu >= nr_cpu_ids || !cpu_online(cpu))
1063 break;
1064 #else
1065 break;
1066 #endif
1067 }
1068 }
1069 if (nd == 0) {
1070 prom_printf("No CPU nodes found, halting.\n");
1071 prom_halt();
1072 }
1073 #ifdef CONFIG_SMP
1074 vac_cache_size = max_size;
1075 vac_line_size = min_line_size;
1076 #endif
1077 printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
1078 (int)vac_cache_size, (int)vac_line_size);
1079 }
1080
poke_hypersparc(void)1081 static void poke_hypersparc(void)
1082 {
1083 volatile unsigned long clear;
1084 unsigned long mreg = srmmu_get_mmureg();
1085
1086 hyper_flush_unconditional_combined();
1087
1088 mreg &= ~(HYPERSPARC_CWENABLE);
1089 mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE);
1090 mreg |= (HYPERSPARC_CMODE);
1091
1092 srmmu_set_mmureg(mreg);
1093
1094 #if 0 /* XXX I think this is bad news... -DaveM */
1095 hyper_clear_all_tags();
1096 #endif
1097
1098 put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE);
1099 hyper_flush_whole_icache();
1100 clear = srmmu_get_faddr();
1101 clear = srmmu_get_fstatus();
1102 }
1103
1104 static const struct sparc32_cachetlb_ops hypersparc_ops = {
1105 .cache_all = hypersparc_flush_cache_all,
1106 .cache_mm = hypersparc_flush_cache_mm,
1107 .cache_page = hypersparc_flush_cache_page,
1108 .cache_range = hypersparc_flush_cache_range,
1109 .tlb_all = hypersparc_flush_tlb_all,
1110 .tlb_mm = hypersparc_flush_tlb_mm,
1111 .tlb_page = hypersparc_flush_tlb_page,
1112 .tlb_range = hypersparc_flush_tlb_range,
1113 .page_to_ram = hypersparc_flush_page_to_ram,
1114 .sig_insns = hypersparc_flush_sig_insns,
1115 .page_for_dma = hypersparc_flush_page_for_dma,
1116 };
1117
init_hypersparc(void)1118 static void __init init_hypersparc(void)
1119 {
1120 srmmu_name = "ROSS HyperSparc";
1121 srmmu_modtype = HyperSparc;
1122
1123 init_vac_layout();
1124
1125 is_hypersparc = 1;
1126 sparc32_cachetlb_ops = &hypersparc_ops;
1127
1128 poke_srmmu = poke_hypersparc;
1129
1130 hypersparc_setup_blockops();
1131 }
1132
poke_swift(void)1133 static void poke_swift(void)
1134 {
1135 unsigned long mreg;
1136
1137 /* Clear any crap from the cache or else... */
1138 swift_flush_cache_all();
1139
1140 /* Enable I & D caches */
1141 mreg = srmmu_get_mmureg();
1142 mreg |= (SWIFT_IE | SWIFT_DE);
1143 /*
1144 * The Swift branch folding logic is completely broken. At
1145 * trap time, if things are just right, if can mistakenly
1146 * think that a trap is coming from kernel mode when in fact
1147 * it is coming from user mode (it mis-executes the branch in
1148 * the trap code). So you see things like crashme completely
1149 * hosing your machine which is completely unacceptable. Turn
1150 * this shit off... nice job Fujitsu.
1151 */
1152 mreg &= ~(SWIFT_BF);
1153 srmmu_set_mmureg(mreg);
1154 }
1155
1156 static const struct sparc32_cachetlb_ops swift_ops = {
1157 .cache_all = swift_flush_cache_all,
1158 .cache_mm = swift_flush_cache_mm,
1159 .cache_page = swift_flush_cache_page,
1160 .cache_range = swift_flush_cache_range,
1161 .tlb_all = swift_flush_tlb_all,
1162 .tlb_mm = swift_flush_tlb_mm,
1163 .tlb_page = swift_flush_tlb_page,
1164 .tlb_range = swift_flush_tlb_range,
1165 .page_to_ram = swift_flush_page_to_ram,
1166 .sig_insns = swift_flush_sig_insns,
1167 .page_for_dma = swift_flush_page_for_dma,
1168 };
1169
1170 #define SWIFT_MASKID_ADDR 0x10003018
init_swift(void)1171 static void __init init_swift(void)
1172 {
1173 unsigned long swift_rev;
1174
1175 __asm__ __volatile__("lda [%1] %2, %0\n\t"
1176 "srl %0, 0x18, %0\n\t" :
1177 "=r" (swift_rev) :
1178 "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS));
1179 srmmu_name = "Fujitsu Swift";
1180 switch (swift_rev) {
1181 case 0x11:
1182 case 0x20:
1183 case 0x23:
1184 case 0x30:
1185 srmmu_modtype = Swift_lots_o_bugs;
1186 hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN);
1187 /*
1188 * Gee george, I wonder why Sun is so hush hush about
1189 * this hardware bug... really braindamage stuff going
1190 * on here. However I think we can find a way to avoid
1191 * all of the workaround overhead under Linux. Basically,
1192 * any page fault can cause kernel pages to become user
1193 * accessible (the mmu gets confused and clears some of
1194 * the ACC bits in kernel ptes). Aha, sounds pretty
1195 * horrible eh? But wait, after extensive testing it appears
1196 * that if you use pgd_t level large kernel pte's (like the
1197 * 4MB pages on the Pentium) the bug does not get tripped
1198 * at all. This avoids almost all of the major overhead.
1199 * Welcome to a world where your vendor tells you to,
1200 * "apply this kernel patch" instead of "sorry for the
1201 * broken hardware, send it back and we'll give you
1202 * properly functioning parts"
1203 */
1204 break;
1205 case 0x25:
1206 case 0x31:
1207 srmmu_modtype = Swift_bad_c;
1208 hwbug_bitmask |= HWBUG_KERN_CBITBROKEN;
1209 /*
1210 * You see Sun allude to this hardware bug but never
1211 * admit things directly, they'll say things like,
1212 * "the Swift chip cache problems" or similar.
1213 */
1214 break;
1215 default:
1216 srmmu_modtype = Swift_ok;
1217 break;
1218 }
1219
1220 sparc32_cachetlb_ops = &swift_ops;
1221 flush_page_for_dma_global = 0;
1222
1223 /*
1224 * Are you now convinced that the Swift is one of the
1225 * biggest VLSI abortions of all time? Bravo Fujitsu!
1226 * Fujitsu, the !#?!%$'d up processor people. I bet if
1227 * you examined the microcode of the Swift you'd find
1228 * XXX's all over the place.
1229 */
1230 poke_srmmu = poke_swift;
1231 }
1232
turbosparc_flush_cache_all(void)1233 static void turbosparc_flush_cache_all(void)
1234 {
1235 flush_user_windows();
1236 turbosparc_idflash_clear();
1237 }
1238
turbosparc_flush_cache_mm(struct mm_struct * mm)1239 static void turbosparc_flush_cache_mm(struct mm_struct *mm)
1240 {
1241 FLUSH_BEGIN(mm)
1242 flush_user_windows();
1243 turbosparc_idflash_clear();
1244 FLUSH_END
1245 }
1246
turbosparc_flush_cache_range(struct vm_area_struct * vma,unsigned long start,unsigned long end)1247 static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1248 {
1249 FLUSH_BEGIN(vma->vm_mm)
1250 flush_user_windows();
1251 turbosparc_idflash_clear();
1252 FLUSH_END
1253 }
1254
turbosparc_flush_cache_page(struct vm_area_struct * vma,unsigned long page)1255 static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1256 {
1257 FLUSH_BEGIN(vma->vm_mm)
1258 flush_user_windows();
1259 if (vma->vm_flags & VM_EXEC)
1260 turbosparc_flush_icache();
1261 turbosparc_flush_dcache();
1262 FLUSH_END
1263 }
1264
1265 /* TurboSparc is copy-back, if we turn it on, but this does not work. */
turbosparc_flush_page_to_ram(unsigned long page)1266 static void turbosparc_flush_page_to_ram(unsigned long page)
1267 {
1268 #ifdef TURBOSPARC_WRITEBACK
1269 volatile unsigned long clear;
1270
1271 if (srmmu_probe(page))
1272 turbosparc_flush_page_cache(page);
1273 clear = srmmu_get_fstatus();
1274 #endif
1275 }
1276
turbosparc_flush_sig_insns(struct mm_struct * mm,unsigned long insn_addr)1277 static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1278 {
1279 }
1280
turbosparc_flush_page_for_dma(unsigned long page)1281 static void turbosparc_flush_page_for_dma(unsigned long page)
1282 {
1283 turbosparc_flush_dcache();
1284 }
1285
turbosparc_flush_tlb_all(void)1286 static void turbosparc_flush_tlb_all(void)
1287 {
1288 srmmu_flush_whole_tlb();
1289 }
1290
turbosparc_flush_tlb_mm(struct mm_struct * mm)1291 static void turbosparc_flush_tlb_mm(struct mm_struct *mm)
1292 {
1293 FLUSH_BEGIN(mm)
1294 srmmu_flush_whole_tlb();
1295 FLUSH_END
1296 }
1297
turbosparc_flush_tlb_range(struct vm_area_struct * vma,unsigned long start,unsigned long end)1298 static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1299 {
1300 FLUSH_BEGIN(vma->vm_mm)
1301 srmmu_flush_whole_tlb();
1302 FLUSH_END
1303 }
1304
turbosparc_flush_tlb_page(struct vm_area_struct * vma,unsigned long page)1305 static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1306 {
1307 FLUSH_BEGIN(vma->vm_mm)
1308 srmmu_flush_whole_tlb();
1309 FLUSH_END
1310 }
1311
1312
poke_turbosparc(void)1313 static void poke_turbosparc(void)
1314 {
1315 unsigned long mreg = srmmu_get_mmureg();
1316 unsigned long ccreg;
1317
1318 /* Clear any crap from the cache or else... */
1319 turbosparc_flush_cache_all();
1320 /* Temporarily disable I & D caches */
1321 mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE);
1322 mreg &= ~(TURBOSPARC_PCENABLE); /* Don't check parity */
1323 srmmu_set_mmureg(mreg);
1324
1325 ccreg = turbosparc_get_ccreg();
1326
1327 #ifdef TURBOSPARC_WRITEBACK
1328 ccreg |= (TURBOSPARC_SNENABLE); /* Do DVMA snooping in Dcache */
1329 ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE);
1330 /* Write-back D-cache, emulate VLSI
1331 * abortion number three, not number one */
1332 #else
1333 /* For now let's play safe, optimize later */
1334 ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE);
1335 /* Do DVMA snooping in Dcache, Write-thru D-cache */
1336 ccreg &= ~(TURBOSPARC_uS2);
1337 /* Emulate VLSI abortion number three, not number one */
1338 #endif
1339
1340 switch (ccreg & 7) {
1341 case 0: /* No SE cache */
1342 case 7: /* Test mode */
1343 break;
1344 default:
1345 ccreg |= (TURBOSPARC_SCENABLE);
1346 }
1347 turbosparc_set_ccreg(ccreg);
1348
1349 mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */
1350 mreg |= (TURBOSPARC_ICSNOOP); /* Icache snooping on */
1351 srmmu_set_mmureg(mreg);
1352 }
1353
1354 static const struct sparc32_cachetlb_ops turbosparc_ops = {
1355 .cache_all = turbosparc_flush_cache_all,
1356 .cache_mm = turbosparc_flush_cache_mm,
1357 .cache_page = turbosparc_flush_cache_page,
1358 .cache_range = turbosparc_flush_cache_range,
1359 .tlb_all = turbosparc_flush_tlb_all,
1360 .tlb_mm = turbosparc_flush_tlb_mm,
1361 .tlb_page = turbosparc_flush_tlb_page,
1362 .tlb_range = turbosparc_flush_tlb_range,
1363 .page_to_ram = turbosparc_flush_page_to_ram,
1364 .sig_insns = turbosparc_flush_sig_insns,
1365 .page_for_dma = turbosparc_flush_page_for_dma,
1366 };
1367
init_turbosparc(void)1368 static void __init init_turbosparc(void)
1369 {
1370 srmmu_name = "Fujitsu TurboSparc";
1371 srmmu_modtype = TurboSparc;
1372 sparc32_cachetlb_ops = &turbosparc_ops;
1373 poke_srmmu = poke_turbosparc;
1374 }
1375
poke_tsunami(void)1376 static void poke_tsunami(void)
1377 {
1378 unsigned long mreg = srmmu_get_mmureg();
1379
1380 tsunami_flush_icache();
1381 tsunami_flush_dcache();
1382 mreg &= ~TSUNAMI_ITD;
1383 mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB);
1384 srmmu_set_mmureg(mreg);
1385 }
1386
1387 static const struct sparc32_cachetlb_ops tsunami_ops = {
1388 .cache_all = tsunami_flush_cache_all,
1389 .cache_mm = tsunami_flush_cache_mm,
1390 .cache_page = tsunami_flush_cache_page,
1391 .cache_range = tsunami_flush_cache_range,
1392 .tlb_all = tsunami_flush_tlb_all,
1393 .tlb_mm = tsunami_flush_tlb_mm,
1394 .tlb_page = tsunami_flush_tlb_page,
1395 .tlb_range = tsunami_flush_tlb_range,
1396 .page_to_ram = tsunami_flush_page_to_ram,
1397 .sig_insns = tsunami_flush_sig_insns,
1398 .page_for_dma = tsunami_flush_page_for_dma,
1399 };
1400
init_tsunami(void)1401 static void __init init_tsunami(void)
1402 {
1403 /*
1404 * Tsunami's pretty sane, Sun and TI actually got it
1405 * somewhat right this time. Fujitsu should have
1406 * taken some lessons from them.
1407 */
1408
1409 srmmu_name = "TI Tsunami";
1410 srmmu_modtype = Tsunami;
1411 sparc32_cachetlb_ops = &tsunami_ops;
1412 poke_srmmu = poke_tsunami;
1413
1414 tsunami_setup_blockops();
1415 }
1416
poke_viking(void)1417 static void poke_viking(void)
1418 {
1419 unsigned long mreg = srmmu_get_mmureg();
1420 static int smp_catch;
1421
1422 if (viking_mxcc_present) {
1423 unsigned long mxcc_control = mxcc_get_creg();
1424
1425 mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE);
1426 mxcc_control &= ~(MXCC_CTL_RRC);
1427 mxcc_set_creg(mxcc_control);
1428
1429 /*
1430 * We don't need memory parity checks.
1431 * XXX This is a mess, have to dig out later. ecd.
1432 viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
1433 */
1434
1435 /* We do cache ptables on MXCC. */
1436 mreg |= VIKING_TCENABLE;
1437 } else {
1438 unsigned long bpreg;
1439
1440 mreg &= ~(VIKING_TCENABLE);
1441 if (smp_catch++) {
1442 /* Must disable mixed-cmd mode here for other cpu's. */
1443 bpreg = viking_get_bpreg();
1444 bpreg &= ~(VIKING_ACTION_MIX);
1445 viking_set_bpreg(bpreg);
1446
1447 /* Just in case PROM does something funny. */
1448 msi_set_sync();
1449 }
1450 }
1451
1452 mreg |= VIKING_SPENABLE;
1453 mreg |= (VIKING_ICENABLE | VIKING_DCENABLE);
1454 mreg |= VIKING_SBENABLE;
1455 mreg &= ~(VIKING_ACENABLE);
1456 srmmu_set_mmureg(mreg);
1457 }
1458
1459 static struct sparc32_cachetlb_ops viking_ops __ro_after_init = {
1460 .cache_all = viking_flush_cache_all,
1461 .cache_mm = viking_flush_cache_mm,
1462 .cache_page = viking_flush_cache_page,
1463 .cache_range = viking_flush_cache_range,
1464 .tlb_all = viking_flush_tlb_all,
1465 .tlb_mm = viking_flush_tlb_mm,
1466 .tlb_page = viking_flush_tlb_page,
1467 .tlb_range = viking_flush_tlb_range,
1468 .page_to_ram = viking_flush_page_to_ram,
1469 .sig_insns = viking_flush_sig_insns,
1470 .page_for_dma = viking_flush_page_for_dma,
1471 };
1472
1473 #ifdef CONFIG_SMP
1474 /* On sun4d the cpu broadcasts local TLB flushes, so we can just
1475 * perform the local TLB flush and all the other cpus will see it.
1476 * But, unfortunately, there is a bug in the sun4d XBUS backplane
1477 * that requires that we add some synchronization to these flushes.
1478 *
1479 * The bug is that the fifo which keeps track of all the pending TLB
1480 * broadcasts in the system is an entry or two too small, so if we
1481 * have too many going at once we'll overflow that fifo and lose a TLB
1482 * flush resulting in corruption.
1483 *
1484 * Our workaround is to take a global spinlock around the TLB flushes,
1485 * which guarentees we won't ever have too many pending. It's a big
1486 * hammer, but a semaphore like system to make sure we only have N TLB
1487 * flushes going at once will require SMP locking anyways so there's
1488 * no real value in trying any harder than this.
1489 */
1490 static struct sparc32_cachetlb_ops viking_sun4d_smp_ops __ro_after_init = {
1491 .cache_all = viking_flush_cache_all,
1492 .cache_mm = viking_flush_cache_mm,
1493 .cache_page = viking_flush_cache_page,
1494 .cache_range = viking_flush_cache_range,
1495 .tlb_all = sun4dsmp_flush_tlb_all,
1496 .tlb_mm = sun4dsmp_flush_tlb_mm,
1497 .tlb_page = sun4dsmp_flush_tlb_page,
1498 .tlb_range = sun4dsmp_flush_tlb_range,
1499 .page_to_ram = viking_flush_page_to_ram,
1500 .sig_insns = viking_flush_sig_insns,
1501 .page_for_dma = viking_flush_page_for_dma,
1502 };
1503 #endif
1504
init_viking(void)1505 static void __init init_viking(void)
1506 {
1507 unsigned long mreg = srmmu_get_mmureg();
1508
1509 /* Ahhh, the viking. SRMMU VLSI abortion number two... */
1510 if (mreg & VIKING_MMODE) {
1511 srmmu_name = "TI Viking";
1512 viking_mxcc_present = 0;
1513 msi_set_sync();
1514
1515 /*
1516 * We need this to make sure old viking takes no hits
1517 * on it's cache for dma snoops to workaround the
1518 * "load from non-cacheable memory" interrupt bug.
1519 * This is only necessary because of the new way in
1520 * which we use the IOMMU.
1521 */
1522 viking_ops.page_for_dma = viking_flush_page;
1523 #ifdef CONFIG_SMP
1524 viking_sun4d_smp_ops.page_for_dma = viking_flush_page;
1525 #endif
1526 flush_page_for_dma_global = 0;
1527 } else {
1528 srmmu_name = "TI Viking/MXCC";
1529 viking_mxcc_present = 1;
1530 srmmu_cache_pagetables = 1;
1531 }
1532
1533 sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1534 &viking_ops;
1535 #ifdef CONFIG_SMP
1536 if (sparc_cpu_model == sun4d)
1537 sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1538 &viking_sun4d_smp_ops;
1539 #endif
1540
1541 poke_srmmu = poke_viking;
1542 }
1543
1544 /* Probe for the srmmu chip version. */
get_srmmu_type(void)1545 static void __init get_srmmu_type(void)
1546 {
1547 unsigned long mreg, psr;
1548 unsigned long mod_typ, mod_rev, psr_typ, psr_vers;
1549
1550 srmmu_modtype = SRMMU_INVAL_MOD;
1551 hwbug_bitmask = 0;
1552
1553 mreg = srmmu_get_mmureg(); psr = get_psr();
1554 mod_typ = (mreg & 0xf0000000) >> 28;
1555 mod_rev = (mreg & 0x0f000000) >> 24;
1556 psr_typ = (psr >> 28) & 0xf;
1557 psr_vers = (psr >> 24) & 0xf;
1558
1559 /* First, check for sparc-leon. */
1560 if (sparc_cpu_model == sparc_leon) {
1561 init_leon();
1562 return;
1563 }
1564
1565 /* Second, check for HyperSparc or Cypress. */
1566 if (mod_typ == 1) {
1567 switch (mod_rev) {
1568 case 7:
1569 /* UP or MP Hypersparc */
1570 init_hypersparc();
1571 break;
1572 case 0:
1573 case 2:
1574 case 10:
1575 case 11:
1576 case 12:
1577 case 13:
1578 case 14:
1579 case 15:
1580 default:
1581 prom_printf("Sparc-Linux Cypress support does not longer exit.\n");
1582 prom_halt();
1583 break;
1584 }
1585 return;
1586 }
1587
1588 /* Now Fujitsu TurboSparc. It might happen that it is
1589 * in Swift emulation mode, so we will check later...
1590 */
1591 if (psr_typ == 0 && psr_vers == 5) {
1592 init_turbosparc();
1593 return;
1594 }
1595
1596 /* Next check for Fujitsu Swift. */
1597 if (psr_typ == 0 && psr_vers == 4) {
1598 phandle cpunode;
1599 char node_str[128];
1600
1601 /* Look if it is not a TurboSparc emulating Swift... */
1602 cpunode = prom_getchild(prom_root_node);
1603 while ((cpunode = prom_getsibling(cpunode)) != 0) {
1604 prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
1605 if (!strcmp(node_str, "cpu")) {
1606 if (!prom_getintdefault(cpunode, "psr-implementation", 1) &&
1607 prom_getintdefault(cpunode, "psr-version", 1) == 5) {
1608 init_turbosparc();
1609 return;
1610 }
1611 break;
1612 }
1613 }
1614
1615 init_swift();
1616 return;
1617 }
1618
1619 /* Now the Viking family of srmmu. */
1620 if (psr_typ == 4 &&
1621 ((psr_vers == 0) ||
1622 ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) {
1623 init_viking();
1624 return;
1625 }
1626
1627 /* Finally the Tsunami. */
1628 if (psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) {
1629 init_tsunami();
1630 return;
1631 }
1632
1633 /* Oh well */
1634 srmmu_is_bad();
1635 }
1636
1637 #ifdef CONFIG_SMP
1638 /* Local cross-calls. */
smp_flush_page_for_dma(unsigned long page)1639 static void smp_flush_page_for_dma(unsigned long page)
1640 {
1641 xc1((smpfunc_t) local_ops->page_for_dma, page);
1642 local_ops->page_for_dma(page);
1643 }
1644
smp_flush_cache_all(void)1645 static void smp_flush_cache_all(void)
1646 {
1647 xc0((smpfunc_t) local_ops->cache_all);
1648 local_ops->cache_all();
1649 }
1650
smp_flush_tlb_all(void)1651 static void smp_flush_tlb_all(void)
1652 {
1653 xc0((smpfunc_t) local_ops->tlb_all);
1654 local_ops->tlb_all();
1655 }
1656
smp_flush_cache_mm(struct mm_struct * mm)1657 static void smp_flush_cache_mm(struct mm_struct *mm)
1658 {
1659 if (mm->context != NO_CONTEXT) {
1660 cpumask_t cpu_mask;
1661 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1662 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1663 if (!cpumask_empty(&cpu_mask))
1664 xc1((smpfunc_t) local_ops->cache_mm, (unsigned long) mm);
1665 local_ops->cache_mm(mm);
1666 }
1667 }
1668
smp_flush_tlb_mm(struct mm_struct * mm)1669 static void smp_flush_tlb_mm(struct mm_struct *mm)
1670 {
1671 if (mm->context != NO_CONTEXT) {
1672 cpumask_t cpu_mask;
1673 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1674 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1675 if (!cpumask_empty(&cpu_mask)) {
1676 xc1((smpfunc_t) local_ops->tlb_mm, (unsigned long) mm);
1677 if (atomic_read(&mm->mm_users) == 1 && current->active_mm == mm)
1678 cpumask_copy(mm_cpumask(mm),
1679 cpumask_of(smp_processor_id()));
1680 }
1681 local_ops->tlb_mm(mm);
1682 }
1683 }
1684
smp_flush_cache_range(struct vm_area_struct * vma,unsigned long start,unsigned long end)1685 static void smp_flush_cache_range(struct vm_area_struct *vma,
1686 unsigned long start,
1687 unsigned long end)
1688 {
1689 struct mm_struct *mm = vma->vm_mm;
1690
1691 if (mm->context != NO_CONTEXT) {
1692 cpumask_t cpu_mask;
1693 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1694 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1695 if (!cpumask_empty(&cpu_mask))
1696 xc3((smpfunc_t) local_ops->cache_range,
1697 (unsigned long) vma, start, end);
1698 local_ops->cache_range(vma, start, end);
1699 }
1700 }
1701
smp_flush_tlb_range(struct vm_area_struct * vma,unsigned long start,unsigned long end)1702 static void smp_flush_tlb_range(struct vm_area_struct *vma,
1703 unsigned long start,
1704 unsigned long end)
1705 {
1706 struct mm_struct *mm = vma->vm_mm;
1707
1708 if (mm->context != NO_CONTEXT) {
1709 cpumask_t cpu_mask;
1710 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1711 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1712 if (!cpumask_empty(&cpu_mask))
1713 xc3((smpfunc_t) local_ops->tlb_range,
1714 (unsigned long) vma, start, end);
1715 local_ops->tlb_range(vma, start, end);
1716 }
1717 }
1718
smp_flush_cache_page(struct vm_area_struct * vma,unsigned long page)1719 static void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1720 {
1721 struct mm_struct *mm = vma->vm_mm;
1722
1723 if (mm->context != NO_CONTEXT) {
1724 cpumask_t cpu_mask;
1725 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1726 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1727 if (!cpumask_empty(&cpu_mask))
1728 xc2((smpfunc_t) local_ops->cache_page,
1729 (unsigned long) vma, page);
1730 local_ops->cache_page(vma, page);
1731 }
1732 }
1733
smp_flush_tlb_page(struct vm_area_struct * vma,unsigned long page)1734 static void smp_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1735 {
1736 struct mm_struct *mm = vma->vm_mm;
1737
1738 if (mm->context != NO_CONTEXT) {
1739 cpumask_t cpu_mask;
1740 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1741 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1742 if (!cpumask_empty(&cpu_mask))
1743 xc2((smpfunc_t) local_ops->tlb_page,
1744 (unsigned long) vma, page);
1745 local_ops->tlb_page(vma, page);
1746 }
1747 }
1748
smp_flush_page_to_ram(unsigned long page)1749 static void smp_flush_page_to_ram(unsigned long page)
1750 {
1751 /* Current theory is that those who call this are the one's
1752 * who have just dirtied their cache with the pages contents
1753 * in kernel space, therefore we only run this on local cpu.
1754 *
1755 * XXX This experiment failed, research further... -DaveM
1756 */
1757 #if 1
1758 xc1((smpfunc_t) local_ops->page_to_ram, page);
1759 #endif
1760 local_ops->page_to_ram(page);
1761 }
1762
smp_flush_sig_insns(struct mm_struct * mm,unsigned long insn_addr)1763 static void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1764 {
1765 cpumask_t cpu_mask;
1766 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1767 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1768 if (!cpumask_empty(&cpu_mask))
1769 xc2((smpfunc_t) local_ops->sig_insns,
1770 (unsigned long) mm, insn_addr);
1771 local_ops->sig_insns(mm, insn_addr);
1772 }
1773
1774 static struct sparc32_cachetlb_ops smp_cachetlb_ops __ro_after_init = {
1775 .cache_all = smp_flush_cache_all,
1776 .cache_mm = smp_flush_cache_mm,
1777 .cache_page = smp_flush_cache_page,
1778 .cache_range = smp_flush_cache_range,
1779 .tlb_all = smp_flush_tlb_all,
1780 .tlb_mm = smp_flush_tlb_mm,
1781 .tlb_page = smp_flush_tlb_page,
1782 .tlb_range = smp_flush_tlb_range,
1783 .page_to_ram = smp_flush_page_to_ram,
1784 .sig_insns = smp_flush_sig_insns,
1785 .page_for_dma = smp_flush_page_for_dma,
1786 };
1787 #endif
1788
1789 /* Load up routines and constants for sun4m and sun4d mmu */
load_mmu(void)1790 void __init load_mmu(void)
1791 {
1792 /* Functions */
1793 get_srmmu_type();
1794
1795 #ifdef CONFIG_SMP
1796 /* El switcheroo... */
1797 local_ops = sparc32_cachetlb_ops;
1798
1799 if (sparc_cpu_model == sun4d || sparc_cpu_model == sparc_leon) {
1800 smp_cachetlb_ops.tlb_all = local_ops->tlb_all;
1801 smp_cachetlb_ops.tlb_mm = local_ops->tlb_mm;
1802 smp_cachetlb_ops.tlb_range = local_ops->tlb_range;
1803 smp_cachetlb_ops.tlb_page = local_ops->tlb_page;
1804 }
1805
1806 if (poke_srmmu == poke_viking) {
1807 /* Avoid unnecessary cross calls. */
1808 smp_cachetlb_ops.cache_all = local_ops->cache_all;
1809 smp_cachetlb_ops.cache_mm = local_ops->cache_mm;
1810 smp_cachetlb_ops.cache_range = local_ops->cache_range;
1811 smp_cachetlb_ops.cache_page = local_ops->cache_page;
1812
1813 smp_cachetlb_ops.page_to_ram = local_ops->page_to_ram;
1814 smp_cachetlb_ops.sig_insns = local_ops->sig_insns;
1815 smp_cachetlb_ops.page_for_dma = local_ops->page_for_dma;
1816 }
1817
1818 /* It really is const after this point. */
1819 sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1820 &smp_cachetlb_ops;
1821 #endif
1822
1823 if (sparc_cpu_model != sun4d)
1824 ld_mmu_iommu();
1825 #ifdef CONFIG_SMP
1826 if (sparc_cpu_model == sun4d)
1827 sun4d_init_smp();
1828 else if (sparc_cpu_model == sparc_leon)
1829 leon_init_smp();
1830 else
1831 sun4m_init_smp();
1832 #endif
1833 }
1834
