1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Huang Rui 23 * 24 */ 25 #ifndef __AMDGPU_PSP_H__ 26 #define __AMDGPU_PSP_H__ 27 28 #include "amdgpu.h" 29 #include "psp_gfx_if.h" 30 31 #define PSP_FENCE_BUFFER_SIZE 0x1000 32 #define PSP_CMD_BUFFER_SIZE 0x1000 33 #define PSP_ASD_SHARED_MEM_SIZE 0x4000 34 #define PSP_1_MEG 0x100000 35 36 struct psp_context; 37 38 enum psp_ring_type 39 { 40 PSP_RING_TYPE__INVALID = 0, 41 /* 42 * These values map to the way the PSP kernel identifies the 43 * rings. 44 */ 45 PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */ 46 PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */ 47 }; 48 49 struct psp_ring 50 { 51 enum psp_ring_type ring_type; 52 struct psp_gfx_rb_frame *ring_mem; 53 uint64_t ring_mem_mc_addr; 54 void *ring_mem_handle; 55 uint32_t ring_size; 56 }; 57 58 struct psp_funcs 59 { 60 int (*init_microcode)(struct psp_context *psp); 61 int (*bootloader_load_sysdrv)(struct psp_context *psp); 62 int (*bootloader_load_sos)(struct psp_context *psp); 63 int (*prep_cmd_buf)(struct amdgpu_firmware_info *ucode, 64 struct psp_gfx_cmd_resp *cmd); 65 int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type); 66 int (*ring_create)(struct psp_context *psp, enum psp_ring_type ring_type); 67 int (*ring_stop)(struct psp_context *psp, 68 enum psp_ring_type ring_type); 69 int (*ring_destroy)(struct psp_context *psp, 70 enum psp_ring_type ring_type); 71 int (*cmd_submit)(struct psp_context *psp, struct amdgpu_firmware_info *ucode, 72 uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, int index); 73 bool (*compare_sram_data)(struct psp_context *psp, 74 struct amdgpu_firmware_info *ucode, 75 enum AMDGPU_UCODE_ID ucode_type); 76 bool (*smu_reload_quirk)(struct psp_context *psp); 77 int (*mode1_reset)(struct psp_context *psp); 78 }; 79 80 struct psp_context 81 { 82 struct amdgpu_device *adev; 83 struct psp_ring km_ring; 84 struct psp_gfx_cmd_resp *cmd; 85 86 const struct psp_funcs *funcs; 87 88 /* fence buffer */ 89 struct amdgpu_bo *fw_pri_bo; 90 uint64_t fw_pri_mc_addr; 91 void *fw_pri_buf; 92 93 /* sos firmware */ 94 const struct firmware *sos_fw; 95 uint32_t sos_fw_version; 96 uint32_t sos_feature_version; 97 uint32_t sys_bin_size; 98 uint32_t sos_bin_size; 99 uint8_t *sys_start_addr; 100 uint8_t *sos_start_addr; 101 102 /* tmr buffer */ 103 struct amdgpu_bo *tmr_bo; 104 uint64_t tmr_mc_addr; 105 void *tmr_buf; 106 107 /* asd firmware and buffer */ 108 const struct firmware *asd_fw; 109 uint32_t asd_fw_version; 110 uint32_t asd_feature_version; 111 uint32_t asd_ucode_size; 112 uint8_t *asd_start_addr; 113 struct amdgpu_bo *asd_shared_bo; 114 uint64_t asd_shared_mc_addr; 115 void *asd_shared_buf; 116 117 /* fence buffer */ 118 struct amdgpu_bo *fence_buf_bo; 119 uint64_t fence_buf_mc_addr; 120 void *fence_buf; 121 122 /* cmd buffer */ 123 struct amdgpu_bo *cmd_buf_bo; 124 uint64_t cmd_buf_mc_addr; 125 struct psp_gfx_cmd_resp *cmd_buf_mem; 126 }; 127 128 struct amdgpu_psp_funcs { 129 bool (*check_fw_loading_status)(struct amdgpu_device *adev, 130 enum AMDGPU_UCODE_ID); 131 }; 132 133 #define psp_prep_cmd_buf(ucode, type) (psp)->funcs->prep_cmd_buf((ucode), (type)) 134 #define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type)) 135 #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type)) 136 #define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type)) 137 #define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type))) 138 #define psp_cmd_submit(psp, ucode, cmd_mc, fence_mc, index) \ 139 (psp)->funcs->cmd_submit((psp), (ucode), (cmd_mc), (fence_mc), (index)) 140 #define psp_compare_sram_data(psp, ucode, type) \ 141 (psp)->funcs->compare_sram_data((psp), (ucode), (type)) 142 #define psp_init_microcode(psp) \ 143 ((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0) 144 #define psp_bootloader_load_sysdrv(psp) \ 145 ((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0) 146 #define psp_bootloader_load_sos(psp) \ 147 ((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0) 148 #define psp_smu_reload_quirk(psp) \ 149 ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false) 150 #define psp_mode1_reset(psp) \ 151 ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false) 152 153 extern const struct amd_ip_funcs psp_ip_funcs; 154 155 extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; 156 extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, 157 uint32_t field_val, uint32_t mask, bool check_changed); 158 159 extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; 160 161 int psp_gpu_reset(struct amdgpu_device *adev); 162 163 #endif 164
