1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Atheros AR71XX/AR724X/AR913X common definitions 4 * 5 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 7 * 8 * Parts of this file are based on Atheros' 2.6.15 BSP 9 */ 10 11 #ifndef __ASM_MACH_ATH79_H 12 #define __ASM_MACH_ATH79_H 13 14 #include <linux/types.h> 15 #include <linux/io.h> 16 17 enum ath79_soc_type { 18 ATH79_SOC_UNKNOWN, 19 ATH79_SOC_AR7130, 20 ATH79_SOC_AR7141, 21 ATH79_SOC_AR7161, 22 ATH79_SOC_AR7240, 23 ATH79_SOC_AR7241, 24 ATH79_SOC_AR7242, 25 ATH79_SOC_AR9130, 26 ATH79_SOC_AR9132, 27 ATH79_SOC_AR9330, 28 ATH79_SOC_AR9331, 29 ATH79_SOC_AR9341, 30 ATH79_SOC_AR9342, 31 ATH79_SOC_AR9344, 32 ATH79_SOC_QCA9533, 33 ATH79_SOC_QCA9556, 34 ATH79_SOC_QCA9558, 35 ATH79_SOC_TP9343, 36 ATH79_SOC_QCA956X, 37 }; 38 39 extern enum ath79_soc_type ath79_soc; 40 extern unsigned int ath79_soc_rev; 41 soc_is_ar71xx(void)42 static inline int soc_is_ar71xx(void) 43 { 44 return (ath79_soc == ATH79_SOC_AR7130 || 45 ath79_soc == ATH79_SOC_AR7141 || 46 ath79_soc == ATH79_SOC_AR7161); 47 } 48 soc_is_ar724x(void)49 static inline int soc_is_ar724x(void) 50 { 51 return (ath79_soc == ATH79_SOC_AR7240 || 52 ath79_soc == ATH79_SOC_AR7241 || 53 ath79_soc == ATH79_SOC_AR7242); 54 } 55 soc_is_ar7240(void)56 static inline int soc_is_ar7240(void) 57 { 58 return (ath79_soc == ATH79_SOC_AR7240); 59 } 60 soc_is_ar7241(void)61 static inline int soc_is_ar7241(void) 62 { 63 return (ath79_soc == ATH79_SOC_AR7241); 64 } 65 soc_is_ar7242(void)66 static inline int soc_is_ar7242(void) 67 { 68 return (ath79_soc == ATH79_SOC_AR7242); 69 } 70 soc_is_ar913x(void)71 static inline int soc_is_ar913x(void) 72 { 73 return (ath79_soc == ATH79_SOC_AR9130 || 74 ath79_soc == ATH79_SOC_AR9132); 75 } 76 soc_is_ar933x(void)77 static inline int soc_is_ar933x(void) 78 { 79 return (ath79_soc == ATH79_SOC_AR9330 || 80 ath79_soc == ATH79_SOC_AR9331); 81 } 82 soc_is_ar9341(void)83 static inline int soc_is_ar9341(void) 84 { 85 return (ath79_soc == ATH79_SOC_AR9341); 86 } 87 soc_is_ar9342(void)88 static inline int soc_is_ar9342(void) 89 { 90 return (ath79_soc == ATH79_SOC_AR9342); 91 } 92 soc_is_ar9344(void)93 static inline int soc_is_ar9344(void) 94 { 95 return (ath79_soc == ATH79_SOC_AR9344); 96 } 97 soc_is_ar934x(void)98 static inline int soc_is_ar934x(void) 99 { 100 return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344(); 101 } 102 soc_is_qca9533(void)103 static inline int soc_is_qca9533(void) 104 { 105 return ath79_soc == ATH79_SOC_QCA9533; 106 } 107 soc_is_qca953x(void)108 static inline int soc_is_qca953x(void) 109 { 110 return soc_is_qca9533(); 111 } 112 soc_is_qca9556(void)113 static inline int soc_is_qca9556(void) 114 { 115 return ath79_soc == ATH79_SOC_QCA9556; 116 } 117 soc_is_qca9558(void)118 static inline int soc_is_qca9558(void) 119 { 120 return ath79_soc == ATH79_SOC_QCA9558; 121 } 122 soc_is_qca955x(void)123 static inline int soc_is_qca955x(void) 124 { 125 return soc_is_qca9556() || soc_is_qca9558(); 126 } 127 soc_is_tp9343(void)128 static inline int soc_is_tp9343(void) 129 { 130 return ath79_soc == ATH79_SOC_TP9343; 131 } 132 soc_is_qca9561(void)133 static inline int soc_is_qca9561(void) 134 { 135 return ath79_soc == ATH79_SOC_QCA956X; 136 } 137 soc_is_qca9563(void)138 static inline int soc_is_qca9563(void) 139 { 140 return ath79_soc == ATH79_SOC_QCA956X; 141 } 142 soc_is_qca956x(void)143 static inline int soc_is_qca956x(void) 144 { 145 return soc_is_qca9561() || soc_is_qca9563(); 146 } 147 148 void ath79_ddr_wb_flush(unsigned int reg); 149 void ath79_ddr_set_pci_windows(void); 150 151 extern void __iomem *ath79_pll_base; 152 extern void __iomem *ath79_reset_base; 153 ath79_pll_wr(unsigned reg,u32 val)154 static inline void ath79_pll_wr(unsigned reg, u32 val) 155 { 156 __raw_writel(val, ath79_pll_base + reg); 157 } 158 ath79_pll_rr(unsigned reg)159 static inline u32 ath79_pll_rr(unsigned reg) 160 { 161 return __raw_readl(ath79_pll_base + reg); 162 } 163 ath79_reset_wr(unsigned reg,u32 val)164 static inline void ath79_reset_wr(unsigned reg, u32 val) 165 { 166 __raw_writel(val, ath79_reset_base + reg); 167 (void) __raw_readl(ath79_reset_base + reg); /* flush */ 168 } 169 ath79_reset_rr(unsigned reg)170 static inline u32 ath79_reset_rr(unsigned reg) 171 { 172 return __raw_readl(ath79_reset_base + reg); 173 } 174 175 void ath79_device_reset_set(u32 mask); 176 void ath79_device_reset_clear(u32 mask); 177 178 #endif /* __ASM_MACH_ATH79_H */ 179
