1 /*
2 * HD-audio controller helpers
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/export.h>
8 #include <sound/core.h>
9 #include <sound/hdaudio.h>
10 #include <sound/hda_register.h>
11
12 /* clear CORB read pointer properly */
azx_clear_corbrp(struct hdac_bus * bus)13 static void azx_clear_corbrp(struct hdac_bus *bus)
14 {
15 int timeout;
16
17 for (timeout = 1000; timeout > 0; timeout--) {
18 if (snd_hdac_chip_readw(bus, CORBRP) & AZX_CORBRP_RST)
19 break;
20 udelay(1);
21 }
22 if (timeout <= 0)
23 dev_err(bus->dev, "CORB reset timeout#1, CORBRP = %d\n",
24 snd_hdac_chip_readw(bus, CORBRP));
25
26 snd_hdac_chip_writew(bus, CORBRP, 0);
27 for (timeout = 1000; timeout > 0; timeout--) {
28 if (snd_hdac_chip_readw(bus, CORBRP) == 0)
29 break;
30 udelay(1);
31 }
32 if (timeout <= 0)
33 dev_err(bus->dev, "CORB reset timeout#2, CORBRP = %d\n",
34 snd_hdac_chip_readw(bus, CORBRP));
35 }
36
37 /**
38 * snd_hdac_bus_init_cmd_io - set up CORB/RIRB buffers
39 * @bus: HD-audio core bus
40 */
snd_hdac_bus_init_cmd_io(struct hdac_bus * bus)41 void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus)
42 {
43 WARN_ON_ONCE(!bus->rb.area);
44
45 spin_lock_irq(&bus->reg_lock);
46 /* CORB set up */
47 bus->corb.addr = bus->rb.addr;
48 bus->corb.buf = (__le32 *)bus->rb.area;
49 snd_hdac_chip_writel(bus, CORBLBASE, (u32)bus->corb.addr);
50 snd_hdac_chip_writel(bus, CORBUBASE, upper_32_bits(bus->corb.addr));
51
52 /* set the corb size to 256 entries (ULI requires explicitly) */
53 snd_hdac_chip_writeb(bus, CORBSIZE, 0x02);
54 /* set the corb write pointer to 0 */
55 snd_hdac_chip_writew(bus, CORBWP, 0);
56
57 /* reset the corb hw read pointer */
58 snd_hdac_chip_writew(bus, CORBRP, AZX_CORBRP_RST);
59 if (!bus->corbrp_self_clear)
60 azx_clear_corbrp(bus);
61
62 /* enable corb dma */
63 snd_hdac_chip_writeb(bus, CORBCTL, AZX_CORBCTL_RUN);
64
65 /* RIRB set up */
66 bus->rirb.addr = bus->rb.addr + 2048;
67 bus->rirb.buf = (__le32 *)(bus->rb.area + 2048);
68 bus->rirb.wp = bus->rirb.rp = 0;
69 memset(bus->rirb.cmds, 0, sizeof(bus->rirb.cmds));
70 snd_hdac_chip_writel(bus, RIRBLBASE, (u32)bus->rirb.addr);
71 snd_hdac_chip_writel(bus, RIRBUBASE, upper_32_bits(bus->rirb.addr));
72
73 /* set the rirb size to 256 entries (ULI requires explicitly) */
74 snd_hdac_chip_writeb(bus, RIRBSIZE, 0x02);
75 /* reset the rirb hw write pointer */
76 snd_hdac_chip_writew(bus, RIRBWP, AZX_RIRBWP_RST);
77 /* set N=1, get RIRB response interrupt for new entry */
78 snd_hdac_chip_writew(bus, RINTCNT, 1);
79 /* enable rirb dma and response irq */
80 snd_hdac_chip_writeb(bus, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN);
81 spin_unlock_irq(&bus->reg_lock);
82 }
83 EXPORT_SYMBOL_GPL(snd_hdac_bus_init_cmd_io);
84
85 /* wait for cmd dmas till they are stopped */
hdac_wait_for_cmd_dmas(struct hdac_bus * bus)86 static void hdac_wait_for_cmd_dmas(struct hdac_bus *bus)
87 {
88 unsigned long timeout;
89
90 timeout = jiffies + msecs_to_jiffies(100);
91 while ((snd_hdac_chip_readb(bus, RIRBCTL) & AZX_RBCTL_DMA_EN)
92 && time_before(jiffies, timeout))
93 udelay(10);
94
95 timeout = jiffies + msecs_to_jiffies(100);
96 while ((snd_hdac_chip_readb(bus, CORBCTL) & AZX_CORBCTL_RUN)
97 && time_before(jiffies, timeout))
98 udelay(10);
99 }
100
101 /**
102 * snd_hdac_bus_stop_cmd_io - clean up CORB/RIRB buffers
103 * @bus: HD-audio core bus
104 */
snd_hdac_bus_stop_cmd_io(struct hdac_bus * bus)105 void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus)
106 {
107 spin_lock_irq(&bus->reg_lock);
108 /* disable ringbuffer DMAs */
109 snd_hdac_chip_writeb(bus, RIRBCTL, 0);
110 snd_hdac_chip_writeb(bus, CORBCTL, 0);
111 spin_unlock_irq(&bus->reg_lock);
112
113 hdac_wait_for_cmd_dmas(bus);
114
115 spin_lock_irq(&bus->reg_lock);
116 /* disable unsolicited responses */
117 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, 0);
118 spin_unlock_irq(&bus->reg_lock);
119 }
120 EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_cmd_io);
121
azx_command_addr(u32 cmd)122 static unsigned int azx_command_addr(u32 cmd)
123 {
124 unsigned int addr = cmd >> 28;
125
126 if (snd_BUG_ON(addr >= HDA_MAX_CODECS))
127 addr = 0;
128 return addr;
129 }
130
131 /**
132 * snd_hdac_bus_send_cmd - send a command verb via CORB
133 * @bus: HD-audio core bus
134 * @val: encoded verb value to send
135 *
136 * Returns zero for success or a negative error code.
137 */
snd_hdac_bus_send_cmd(struct hdac_bus * bus,unsigned int val)138 int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val)
139 {
140 unsigned int addr = azx_command_addr(val);
141 unsigned int wp, rp;
142
143 spin_lock_irq(&bus->reg_lock);
144
145 bus->last_cmd[azx_command_addr(val)] = val;
146
147 /* add command to corb */
148 wp = snd_hdac_chip_readw(bus, CORBWP);
149 if (wp == 0xffff) {
150 /* something wrong, controller likely turned to D3 */
151 spin_unlock_irq(&bus->reg_lock);
152 return -EIO;
153 }
154 wp++;
155 wp %= AZX_MAX_CORB_ENTRIES;
156
157 rp = snd_hdac_chip_readw(bus, CORBRP);
158 if (wp == rp) {
159 /* oops, it's full */
160 spin_unlock_irq(&bus->reg_lock);
161 return -EAGAIN;
162 }
163
164 bus->rirb.cmds[addr]++;
165 bus->corb.buf[wp] = cpu_to_le32(val);
166 snd_hdac_chip_writew(bus, CORBWP, wp);
167
168 spin_unlock_irq(&bus->reg_lock);
169
170 return 0;
171 }
172 EXPORT_SYMBOL_GPL(snd_hdac_bus_send_cmd);
173
174 #define AZX_RIRB_EX_UNSOL_EV (1<<4)
175
176 /**
177 * snd_hdac_bus_update_rirb - retrieve RIRB entries
178 * @bus: HD-audio core bus
179 *
180 * Usually called from interrupt handler.
181 */
snd_hdac_bus_update_rirb(struct hdac_bus * bus)182 void snd_hdac_bus_update_rirb(struct hdac_bus *bus)
183 {
184 unsigned int rp, wp;
185 unsigned int addr;
186 u32 res, res_ex;
187
188 wp = snd_hdac_chip_readw(bus, RIRBWP);
189 if (wp == 0xffff) {
190 /* something wrong, controller likely turned to D3 */
191 return;
192 }
193
194 if (wp == bus->rirb.wp)
195 return;
196 bus->rirb.wp = wp;
197
198 while (bus->rirb.rp != wp) {
199 bus->rirb.rp++;
200 bus->rirb.rp %= AZX_MAX_RIRB_ENTRIES;
201
202 rp = bus->rirb.rp << 1; /* an RIRB entry is 8-bytes */
203 res_ex = le32_to_cpu(bus->rirb.buf[rp + 1]);
204 res = le32_to_cpu(bus->rirb.buf[rp]);
205 addr = res_ex & 0xf;
206 if (addr >= HDA_MAX_CODECS) {
207 dev_err(bus->dev,
208 "spurious response %#x:%#x, rp = %d, wp = %d",
209 res, res_ex, bus->rirb.rp, wp);
210 snd_BUG();
211 } else if (res_ex & AZX_RIRB_EX_UNSOL_EV)
212 snd_hdac_bus_queue_event(bus, res, res_ex);
213 else if (bus->rirb.cmds[addr]) {
214 bus->rirb.res[addr] = res;
215 bus->rirb.cmds[addr]--;
216 } else {
217 dev_err_ratelimited(bus->dev,
218 "spurious response %#x:%#x, last cmd=%#08x\n",
219 res, res_ex, bus->last_cmd[addr]);
220 }
221 }
222 }
223 EXPORT_SYMBOL_GPL(snd_hdac_bus_update_rirb);
224
225 /**
226 * snd_hdac_bus_get_response - receive a response via RIRB
227 * @bus: HD-audio core bus
228 * @addr: codec address
229 * @res: pointer to store the value, NULL when not needed
230 *
231 * Returns zero if a value is read, or a negative error code.
232 */
snd_hdac_bus_get_response(struct hdac_bus * bus,unsigned int addr,unsigned int * res)233 int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
234 unsigned int *res)
235 {
236 unsigned long timeout;
237 unsigned long loopcounter;
238
239 timeout = jiffies + msecs_to_jiffies(1000);
240
241 for (loopcounter = 0;; loopcounter++) {
242 spin_lock_irq(&bus->reg_lock);
243 if (!bus->rirb.cmds[addr]) {
244 if (res)
245 *res = bus->rirb.res[addr]; /* the last value */
246 spin_unlock_irq(&bus->reg_lock);
247 return 0;
248 }
249 spin_unlock_irq(&bus->reg_lock);
250 if (time_after(jiffies, timeout))
251 break;
252 if (loopcounter > 3000)
253 msleep(2); /* temporary workaround */
254 else {
255 udelay(10);
256 cond_resched();
257 }
258 }
259
260 return -EIO;
261 }
262 EXPORT_SYMBOL_GPL(snd_hdac_bus_get_response);
263
264 #define HDAC_MAX_CAPS 10
265 /**
266 * snd_hdac_bus_parse_capabilities - parse capability structure
267 * @bus: the pointer to bus object
268 *
269 * Returns 0 if successful, or a negative error code.
270 */
snd_hdac_bus_parse_capabilities(struct hdac_bus * bus)271 int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus)
272 {
273 unsigned int cur_cap;
274 unsigned int offset;
275 unsigned int counter = 0;
276
277 offset = snd_hdac_chip_readw(bus, LLCH);
278
279 /* Lets walk the linked capabilities list */
280 do {
281 cur_cap = _snd_hdac_chip_readl(bus, offset);
282
283 dev_dbg(bus->dev, "Capability version: 0x%x\n",
284 (cur_cap & AZX_CAP_HDR_VER_MASK) >> AZX_CAP_HDR_VER_OFF);
285
286 dev_dbg(bus->dev, "HDA capability ID: 0x%x\n",
287 (cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF);
288
289 if (cur_cap == -1) {
290 dev_dbg(bus->dev, "Invalid capability reg read\n");
291 break;
292 }
293
294 switch ((cur_cap & AZX_CAP_HDR_ID_MASK) >> AZX_CAP_HDR_ID_OFF) {
295 case AZX_ML_CAP_ID:
296 dev_dbg(bus->dev, "Found ML capability\n");
297 bus->mlcap = bus->remap_addr + offset;
298 break;
299
300 case AZX_GTS_CAP_ID:
301 dev_dbg(bus->dev, "Found GTS capability offset=%x\n", offset);
302 bus->gtscap = bus->remap_addr + offset;
303 break;
304
305 case AZX_PP_CAP_ID:
306 /* PP capability found, the Audio DSP is present */
307 dev_dbg(bus->dev, "Found PP capability offset=%x\n", offset);
308 bus->ppcap = bus->remap_addr + offset;
309 break;
310
311 case AZX_SPB_CAP_ID:
312 /* SPIB capability found, handler function */
313 dev_dbg(bus->dev, "Found SPB capability\n");
314 bus->spbcap = bus->remap_addr + offset;
315 break;
316
317 case AZX_DRSM_CAP_ID:
318 /* DMA resume capability found, handler function */
319 dev_dbg(bus->dev, "Found DRSM capability\n");
320 bus->drsmcap = bus->remap_addr + offset;
321 break;
322
323 default:
324 dev_err(bus->dev, "Unknown capability %d\n", cur_cap);
325 cur_cap = 0;
326 break;
327 }
328
329 counter++;
330
331 if (counter > HDAC_MAX_CAPS) {
332 dev_err(bus->dev, "We exceeded HDAC capabilities!!!\n");
333 break;
334 }
335
336 /* read the offset of next capability */
337 offset = cur_cap & AZX_CAP_HDR_NXT_PTR_MASK;
338
339 } while (offset);
340
341 return 0;
342 }
343 EXPORT_SYMBOL_GPL(snd_hdac_bus_parse_capabilities);
344
345 /*
346 * Lowlevel interface
347 */
348
349 /**
350 * snd_hdac_bus_enter_link_reset - enter link reset
351 * @bus: HD-audio core bus
352 *
353 * Enter to the link reset state.
354 */
snd_hdac_bus_enter_link_reset(struct hdac_bus * bus)355 void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus)
356 {
357 unsigned long timeout;
358
359 /* reset controller */
360 snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_RESET, 0);
361
362 timeout = jiffies + msecs_to_jiffies(100);
363 while ((snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET) &&
364 time_before(jiffies, timeout))
365 usleep_range(500, 1000);
366 }
367 EXPORT_SYMBOL_GPL(snd_hdac_bus_enter_link_reset);
368
369 /**
370 * snd_hdac_bus_exit_link_reset - exit link reset
371 * @bus: HD-audio core bus
372 *
373 * Exit from the link reset state.
374 */
snd_hdac_bus_exit_link_reset(struct hdac_bus * bus)375 void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus)
376 {
377 unsigned long timeout;
378
379 snd_hdac_chip_updateb(bus, GCTL, 0, AZX_GCTL_RESET);
380
381 timeout = jiffies + msecs_to_jiffies(100);
382 while (!snd_hdac_chip_readb(bus, GCTL) && time_before(jiffies, timeout))
383 usleep_range(500, 1000);
384 }
385 EXPORT_SYMBOL_GPL(snd_hdac_bus_exit_link_reset);
386
387 /* reset codec link */
snd_hdac_bus_reset_link(struct hdac_bus * bus,bool full_reset)388 int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset)
389 {
390 if (!full_reset)
391 goto skip_reset;
392
393 /* clear STATESTS */
394 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
395
396 /* reset controller */
397 snd_hdac_bus_enter_link_reset(bus);
398
399 /* delay for >= 100us for codec PLL to settle per spec
400 * Rev 0.9 section 5.5.1
401 */
402 usleep_range(500, 1000);
403
404 /* Bring controller out of reset */
405 snd_hdac_bus_exit_link_reset(bus);
406
407 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
408 usleep_range(1000, 1200);
409
410 skip_reset:
411 /* check to see if controller is ready */
412 if (!snd_hdac_chip_readb(bus, GCTL)) {
413 dev_dbg(bus->dev, "controller not ready!\n");
414 return -EBUSY;
415 }
416
417 /* Accept unsolicited responses */
418 snd_hdac_chip_updatel(bus, GCTL, 0, AZX_GCTL_UNSOL);
419
420 /* detect codecs */
421 if (!bus->codec_mask) {
422 bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS);
423 dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask);
424 }
425
426 return 0;
427 }
428 EXPORT_SYMBOL_GPL(snd_hdac_bus_reset_link);
429
430 /* enable interrupts */
azx_int_enable(struct hdac_bus * bus)431 static void azx_int_enable(struct hdac_bus *bus)
432 {
433 /* enable controller CIE and GIE */
434 snd_hdac_chip_updatel(bus, INTCTL, 0, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN);
435 }
436
437 /* disable interrupts */
azx_int_disable(struct hdac_bus * bus)438 static void azx_int_disable(struct hdac_bus *bus)
439 {
440 struct hdac_stream *azx_dev;
441
442 /* disable interrupts in stream descriptor */
443 list_for_each_entry(azx_dev, &bus->stream_list, list)
444 snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_INT_MASK, 0);
445
446 /* disable SIE for all streams */
447 snd_hdac_chip_writeb(bus, INTCTL, 0);
448
449 /* disable controller CIE and GIE */
450 snd_hdac_chip_updatel(bus, INTCTL, AZX_INT_CTRL_EN | AZX_INT_GLOBAL_EN, 0);
451 }
452
453 /* clear interrupts */
azx_int_clear(struct hdac_bus * bus)454 static void azx_int_clear(struct hdac_bus *bus)
455 {
456 struct hdac_stream *azx_dev;
457
458 /* clear stream status */
459 list_for_each_entry(azx_dev, &bus->stream_list, list)
460 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
461
462 /* clear STATESTS */
463 snd_hdac_chip_writew(bus, STATESTS, STATESTS_INT_MASK);
464
465 /* clear rirb status */
466 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
467
468 /* clear int status */
469 snd_hdac_chip_writel(bus, INTSTS, AZX_INT_CTRL_EN | AZX_INT_ALL_STREAM);
470 }
471
472 /**
473 * snd_hdac_bus_init_chip - reset and start the controller registers
474 * @bus: HD-audio core bus
475 * @full_reset: Do full reset
476 */
snd_hdac_bus_init_chip(struct hdac_bus * bus,bool full_reset)477 bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset)
478 {
479 if (bus->chip_init)
480 return false;
481
482 /* reset controller */
483 snd_hdac_bus_reset_link(bus, full_reset);
484
485 /* clear interrupts */
486 azx_int_clear(bus);
487
488 /* initialize the codec command I/O */
489 snd_hdac_bus_init_cmd_io(bus);
490
491 /* enable interrupts after CORB/RIRB buffers are initialized above */
492 azx_int_enable(bus);
493
494 /* program the position buffer */
495 if (bus->use_posbuf && bus->posbuf.addr) {
496 snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr);
497 snd_hdac_chip_writel(bus, DPUBASE, upper_32_bits(bus->posbuf.addr));
498 }
499
500 bus->chip_init = true;
501 return true;
502 }
503 EXPORT_SYMBOL_GPL(snd_hdac_bus_init_chip);
504
505 /**
506 * snd_hdac_bus_stop_chip - disable the whole IRQ and I/Os
507 * @bus: HD-audio core bus
508 */
snd_hdac_bus_stop_chip(struct hdac_bus * bus)509 void snd_hdac_bus_stop_chip(struct hdac_bus *bus)
510 {
511 if (!bus->chip_init)
512 return;
513
514 /* disable interrupts */
515 azx_int_disable(bus);
516 azx_int_clear(bus);
517
518 /* disable CORB/RIRB */
519 snd_hdac_bus_stop_cmd_io(bus);
520
521 /* disable position buffer */
522 if (bus->posbuf.addr) {
523 snd_hdac_chip_writel(bus, DPLBASE, 0);
524 snd_hdac_chip_writel(bus, DPUBASE, 0);
525 }
526
527 bus->chip_init = false;
528 }
529 EXPORT_SYMBOL_GPL(snd_hdac_bus_stop_chip);
530
531 /**
532 * snd_hdac_bus_handle_stream_irq - interrupt handler for streams
533 * @bus: HD-audio core bus
534 * @status: INTSTS register value
535 * @ask: callback to be called for woken streams
536 *
537 * Returns the bits of handled streams, or zero if no stream is handled.
538 */
snd_hdac_bus_handle_stream_irq(struct hdac_bus * bus,unsigned int status,void (* ack)(struct hdac_bus *,struct hdac_stream *))539 int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
540 void (*ack)(struct hdac_bus *,
541 struct hdac_stream *))
542 {
543 struct hdac_stream *azx_dev;
544 u8 sd_status;
545 int handled = 0;
546
547 list_for_each_entry(azx_dev, &bus->stream_list, list) {
548 if (status & azx_dev->sd_int_sta_mask) {
549 sd_status = snd_hdac_stream_readb(azx_dev, SD_STS);
550 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK);
551 handled |= 1 << azx_dev->index;
552 if (!azx_dev->substream || !azx_dev->running ||
553 !(sd_status & SD_INT_COMPLETE))
554 continue;
555 if (ack)
556 ack(bus, azx_dev);
557 }
558 }
559 return handled;
560 }
561 EXPORT_SYMBOL_GPL(snd_hdac_bus_handle_stream_irq);
562
563 /**
564 * snd_hdac_bus_alloc_stream_pages - allocate BDL and other buffers
565 * @bus: HD-audio core bus
566 *
567 * Call this after assigning the all streams.
568 * Returns zero for success, or a negative error code.
569 */
snd_hdac_bus_alloc_stream_pages(struct hdac_bus * bus)570 int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus)
571 {
572 struct hdac_stream *s;
573 int num_streams = 0;
574 int err;
575
576 list_for_each_entry(s, &bus->stream_list, list) {
577 /* allocate memory for the BDL for each stream */
578 err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV,
579 BDL_SIZE, &s->bdl);
580 num_streams++;
581 if (err < 0)
582 return -ENOMEM;
583 }
584
585 if (WARN_ON(!num_streams))
586 return -EINVAL;
587 /* allocate memory for the position buffer */
588 err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV,
589 num_streams * 8, &bus->posbuf);
590 if (err < 0)
591 return -ENOMEM;
592 list_for_each_entry(s, &bus->stream_list, list)
593 s->posbuf = (__le32 *)(bus->posbuf.area + s->index * 8);
594
595 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
596 return bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV,
597 PAGE_SIZE, &bus->rb);
598 }
599 EXPORT_SYMBOL_GPL(snd_hdac_bus_alloc_stream_pages);
600
601 /**
602 * snd_hdac_bus_free_stream_pages - release BDL and other buffers
603 * @bus: HD-audio core bus
604 */
snd_hdac_bus_free_stream_pages(struct hdac_bus * bus)605 void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus)
606 {
607 struct hdac_stream *s;
608
609 list_for_each_entry(s, &bus->stream_list, list) {
610 if (s->bdl.area)
611 bus->io_ops->dma_free_pages(bus, &s->bdl);
612 }
613
614 if (bus->rb.area)
615 bus->io_ops->dma_free_pages(bus, &bus->rb);
616 if (bus->posbuf.area)
617 bus->io_ops->dma_free_pages(bus, &bus->posbuf);
618 }
619 EXPORT_SYMBOL_GPL(snd_hdac_bus_free_stream_pages);
620
