1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include <linux/pci.h>
28 #include <linux/i2c.h>
29 #include "amdgpu.h"
30 #include "amdgpu_smu.h"
31 #include "atomfirmware.h"
32 #include "amdgpu_atomfirmware.h"
33 #include "amdgpu_atombios.h"
34 #include "smu_v13_0.h"
35 #include "smu13_driver_if_v13_0_7.h"
36 #include "soc15_common.h"
37 #include "atom.h"
38 #include "smu_v13_0_7_ppt.h"
39 #include "smu_v13_0_7_pptable.h"
40 #include "smu_v13_0_7_ppsmc.h"
41 #include "nbio/nbio_4_3_0_offset.h"
42 #include "nbio/nbio_4_3_0_sh_mask.h"
43 #include "mp/mp_13_0_0_offset.h"
44 #include "mp/mp_13_0_0_sh_mask.h"
45
46 #include "asic_reg/mp/mp_13_0_0_sh_mask.h"
47 #include "smu_cmn.h"
48 #include "amdgpu_ras.h"
49
50 /*
51 * DO NOT use these for err/warn/info/debug messages.
52 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
53 * They are more MGPU friendly.
54 */
55 #undef pr_err
56 #undef pr_warn
57 #undef pr_info
58 #undef pr_debug
59
60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
61
62 #define FEATURE_MASK(feature) (1ULL << feature)
63 #define SMC_DPM_FEATURE ( \
64 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
65 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
66 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
67 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
68 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
69 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
70
71 #define smnMP1_FIRMWARE_FLAGS_SMU_13_0_7 0x3b10028
72
73 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000
74
75 static struct cmn2asic_msg_mapping smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] = {
76 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
77 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
78 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
79 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
80 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
81 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
82 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
83 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
84 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
85 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
86 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
87 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
88 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
89 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
90 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
91 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
92 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
93 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
94 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
95 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
96 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
97 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
98 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
99 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
100 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
101 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
102 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
103 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
104 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
105 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
106 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
107 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
108 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
109 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
110 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
111 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
112 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
113 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
114 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
115 MSG_MAP(AllowIHHostInterrupt, PPSMC_MSG_AllowIHHostInterrupt, 0),
116 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
117 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
118 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
119 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
120 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
121 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
122 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
123 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
124 MSG_MAP(DFCstateControl, PPSMC_MSG_SetExternalClientDfCstateAllow, 0),
125 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
126 };
127
128 static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] = {
129 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
130 CLK_MAP(SCLK, PPCLK_GFXCLK),
131 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
132 CLK_MAP(FCLK, PPCLK_FCLK),
133 CLK_MAP(UCLK, PPCLK_UCLK),
134 CLK_MAP(MCLK, PPCLK_UCLK),
135 CLK_MAP(VCLK, PPCLK_VCLK_0),
136 CLK_MAP(VCLK1, PPCLK_VCLK_1),
137 CLK_MAP(DCLK, PPCLK_DCLK_0),
138 CLK_MAP(DCLK1, PPCLK_DCLK_1),
139 };
140
141 static struct cmn2asic_mapping smu_v13_0_7_feature_mask_map[SMU_FEATURE_COUNT] = {
142 FEA_MAP(FW_DATA_READ),
143 FEA_MAP(DPM_GFXCLK),
144 FEA_MAP(DPM_GFX_POWER_OPTIMIZER),
145 FEA_MAP(DPM_UCLK),
146 FEA_MAP(DPM_FCLK),
147 FEA_MAP(DPM_SOCCLK),
148 FEA_MAP(DPM_MP0CLK),
149 FEA_MAP(DPM_LINK),
150 FEA_MAP(DPM_DCN),
151 FEA_MAP(VMEMP_SCALING),
152 FEA_MAP(VDDIO_MEM_SCALING),
153 FEA_MAP(DS_GFXCLK),
154 FEA_MAP(DS_SOCCLK),
155 FEA_MAP(DS_FCLK),
156 FEA_MAP(DS_LCLK),
157 FEA_MAP(DS_DCFCLK),
158 FEA_MAP(DS_UCLK),
159 FEA_MAP(GFX_ULV),
160 FEA_MAP(FW_DSTATE),
161 FEA_MAP(GFXOFF),
162 FEA_MAP(BACO),
163 FEA_MAP(MM_DPM),
164 FEA_MAP(SOC_MPCLK_DS),
165 FEA_MAP(BACO_MPCLK_DS),
166 FEA_MAP(THROTTLERS),
167 FEA_MAP(SMARTSHIFT),
168 FEA_MAP(GTHR),
169 FEA_MAP(ACDC),
170 FEA_MAP(VR0HOT),
171 FEA_MAP(FW_CTF),
172 FEA_MAP(FAN_CONTROL),
173 FEA_MAP(GFX_DCS),
174 FEA_MAP(GFX_READ_MARGIN),
175 FEA_MAP(LED_DISPLAY),
176 FEA_MAP(GFXCLK_SPREAD_SPECTRUM),
177 FEA_MAP(OUT_OF_BAND_MONITOR),
178 FEA_MAP(OPTIMIZED_VMIN),
179 FEA_MAP(GFX_IMU),
180 FEA_MAP(BOOT_TIME_CAL),
181 FEA_MAP(GFX_PCC_DFLL),
182 FEA_MAP(SOC_CG),
183 FEA_MAP(DF_CSTATE),
184 FEA_MAP(GFX_EDC),
185 FEA_MAP(BOOT_POWER_OPT),
186 FEA_MAP(CLOCK_POWER_DOWN_BYPASS),
187 FEA_MAP(DS_VCN),
188 FEA_MAP(BACO_CG),
189 FEA_MAP(MEM_TEMP_READ),
190 FEA_MAP(ATHUB_MMHUB_PG),
191 FEA_MAP(SOC_PCC),
192 };
193
194 static struct cmn2asic_mapping smu_v13_0_7_table_map[SMU_TABLE_COUNT] = {
195 TAB_MAP(PPTABLE),
196 TAB_MAP(WATERMARKS),
197 TAB_MAP(AVFS_PSM_DEBUG),
198 TAB_MAP(PMSTATUSLOG),
199 TAB_MAP(SMU_METRICS),
200 TAB_MAP(DRIVER_SMU_CONFIG),
201 TAB_MAP(ACTIVITY_MONITOR_COEFF),
202 [SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE},
203 };
204
205 static struct cmn2asic_mapping smu_v13_0_7_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
206 PWR_MAP(AC),
207 PWR_MAP(DC),
208 };
209
210 static struct cmn2asic_mapping smu_v13_0_7_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
211 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
212 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
213 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
214 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
215 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
216 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
217 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
218 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_WINDOW3D, WORKLOAD_PPLIB_WINDOW_3D_BIT),
219 };
220
221 static const uint8_t smu_v13_0_7_throttler_map[] = {
222 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
223 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
224 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
225 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
226 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
227 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
228 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
229 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
230 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
231 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
232 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
233 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
234 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
235 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
236 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
237 [THROTTLER_GFX_APCC_PLUS_BIT] = (SMU_THROTTLER_APCC_BIT),
238 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
239 };
240
241 static int
smu_v13_0_7_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)242 smu_v13_0_7_get_allowed_feature_mask(struct smu_context *smu,
243 uint32_t *feature_mask, uint32_t num)
244 {
245 struct amdgpu_device *adev = smu->adev;
246
247 if (num > 2)
248 return -EINVAL;
249
250 memset(feature_mask, 0, sizeof(uint32_t) * num);
251
252 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DATA_READ_BIT);
253
254 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
255 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
256 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT);
257 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT);
258 }
259
260 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
261 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
262
263 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) {
264 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
265 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT);
266 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT);
267 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT);
268 }
269
270 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
271
272 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
273 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
274
275 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
276 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
277
278 if (adev->pm.pp_feature & PP_ULV_MASK)
279 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
280
281 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
282 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT);
283 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_BIT);
284 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_VCN_BIT);
285 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_FCLK_BIT);
286 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DF_CSTATE_BIT);
287 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_THROTTLERS_BIT);
288 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VR0HOT_BIT);
289 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_CTF_BIT);
290 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FAN_CONTROL_BIT);
291 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
292 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXCLK_SPREAD_SPECTRUM_BIT);
293 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MEM_TEMP_READ_BIT);
294 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
295 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_MPCLK_DS_BIT);
296 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_MPCLK_DS_BIT);
297 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_PCC_DFLL_BIT);
298 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_CG_BIT);
299 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_BIT);
300
301 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
302 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCN_BIT);
303
304 if ((adev->pg_flags & AMD_PG_SUPPORT_ATHUB) &&
305 (adev->pg_flags & AMD_PG_SUPPORT_MMHUB))
306 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT);
307
308 return 0;
309 }
310
smu_v13_0_7_check_powerplay_table(struct smu_context * smu)311 static int smu_v13_0_7_check_powerplay_table(struct smu_context *smu)
312 {
313 struct smu_table_context *table_context = &smu->smu_table;
314 struct smu_13_0_7_powerplay_table *powerplay_table =
315 table_context->power_play_table;
316 struct smu_baco_context *smu_baco = &smu->smu_baco;
317 PPTable_t *smc_pptable = table_context->driver_pptable;
318 BoardTable_t *BoardTable = &smc_pptable->BoardTable;
319
320 if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_HARDWAREDC)
321 smu->dc_controlled_by_gpio = true;
322
323 if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_BACO ||
324 powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_MACO)
325 smu_baco->platform_support = true;
326
327 if (smu_baco->platform_support && (BoardTable->HsrEnabled || BoardTable->VddqOffEnabled))
328 smu_baco->maco_support = true;
329
330 table_context->thermal_controller_type =
331 powerplay_table->thermal_controller_type;
332
333 /*
334 * Instead of having its own buffer space and get overdrive_table copied,
335 * smu->od_settings just points to the actual overdrive_table
336 */
337 smu->od_settings = &powerplay_table->overdrive_table;
338
339 return 0;
340 }
341
smu_v13_0_7_store_powerplay_table(struct smu_context * smu)342 static int smu_v13_0_7_store_powerplay_table(struct smu_context *smu)
343 {
344 struct smu_table_context *table_context = &smu->smu_table;
345 struct smu_13_0_7_powerplay_table *powerplay_table =
346 table_context->power_play_table;
347 struct amdgpu_device *adev = smu->adev;
348
349 if (adev->pdev->device == 0x51)
350 powerplay_table->smc_pptable.SkuTable.DebugOverrides |= 0x00000080;
351
352 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
353 sizeof(PPTable_t));
354
355 return 0;
356 }
357
smu_v13_0_7_check_fw_status(struct smu_context * smu)358 static int smu_v13_0_7_check_fw_status(struct smu_context *smu)
359 {
360 struct amdgpu_device *adev = smu->adev;
361 uint32_t mp1_fw_flags;
362
363 mp1_fw_flags = RREG32_PCIE(MP1_Public |
364 (smnMP1_FIRMWARE_FLAGS_SMU_13_0_7 & 0xffffffff));
365
366 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
367 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
368 return 0;
369
370 return -EIO;
371 }
372
373 #ifndef atom_smc_dpm_info_table_13_0_7
374 struct atom_smc_dpm_info_table_13_0_7
375 {
376 struct atom_common_table_header table_header;
377 BoardTable_t BoardTable;
378 };
379 #endif
380
smu_v13_0_7_append_powerplay_table(struct smu_context * smu)381 static int smu_v13_0_7_append_powerplay_table(struct smu_context *smu)
382 {
383 struct smu_table_context *table_context = &smu->smu_table;
384
385 PPTable_t *smc_pptable = table_context->driver_pptable;
386
387 struct atom_smc_dpm_info_table_13_0_7 *smc_dpm_table;
388
389 BoardTable_t *BoardTable = &smc_pptable->BoardTable;
390
391 int index, ret;
392
393 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
394 smc_dpm_info);
395
396 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
397 (uint8_t **)&smc_dpm_table);
398 if (ret)
399 return ret;
400
401 memcpy(BoardTable, &smc_dpm_table->BoardTable, sizeof(BoardTable_t));
402
403 return 0;
404 }
405
smu_v13_0_7_get_pptable_from_pmfw(struct smu_context * smu,void ** table,uint32_t * size)406 static int smu_v13_0_7_get_pptable_from_pmfw(struct smu_context *smu,
407 void **table,
408 uint32_t *size)
409 {
410 struct smu_table_context *smu_table = &smu->smu_table;
411 void *combo_pptable = smu_table->combo_pptable;
412 int ret = 0;
413
414 ret = smu_cmn_get_combo_pptable(smu);
415 if (ret)
416 return ret;
417
418 *table = combo_pptable;
419 *size = sizeof(struct smu_13_0_7_powerplay_table);
420
421 return 0;
422 }
423
smu_v13_0_7_setup_pptable(struct smu_context * smu)424 static int smu_v13_0_7_setup_pptable(struct smu_context *smu)
425 {
426 struct smu_table_context *smu_table = &smu->smu_table;
427 struct amdgpu_device *adev = smu->adev;
428 int ret = 0;
429
430 /*
431 * With SCPM enabled, the pptable used will be signed. It cannot
432 * be used directly by driver. To get the raw pptable, we need to
433 * rely on the combo pptable(and its revelant SMU message).
434 */
435 ret = smu_v13_0_7_get_pptable_from_pmfw(smu,
436 &smu_table->power_play_table,
437 &smu_table->power_play_table_size);
438 if (ret)
439 return ret;
440
441 ret = smu_v13_0_7_store_powerplay_table(smu);
442 if (ret)
443 return ret;
444
445 /*
446 * With SCPM enabled, the operation below will be handled
447 * by PSP. Driver involvment is unnecessary and useless.
448 */
449 if (!adev->scpm_enabled) {
450 ret = smu_v13_0_7_append_powerplay_table(smu);
451 if (ret)
452 return ret;
453 }
454
455 ret = smu_v13_0_7_check_powerplay_table(smu);
456 if (ret)
457 return ret;
458
459 return ret;
460 }
461
smu_v13_0_7_tables_init(struct smu_context * smu)462 static int smu_v13_0_7_tables_init(struct smu_context *smu)
463 {
464 struct smu_table_context *smu_table = &smu->smu_table;
465 struct smu_table *tables = smu_table->tables;
466
467 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
468 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
469
470 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
471 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
472 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
473 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
474 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
475 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
476 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
477 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
478 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
479 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
480 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
481 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
482 AMDGPU_GEM_DOMAIN_VRAM);
483 SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE,
484 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
485
486 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
487 if (!smu_table->metrics_table)
488 goto err0_out;
489 smu_table->metrics_time = 0;
490
491 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
492 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
493 if (!smu_table->gpu_metrics_table)
494 goto err1_out;
495
496 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
497 if (!smu_table->watermarks_table)
498 goto err2_out;
499
500 return 0;
501
502 err2_out:
503 kfree(smu_table->gpu_metrics_table);
504 err1_out:
505 kfree(smu_table->metrics_table);
506 err0_out:
507 return -ENOMEM;
508 }
509
smu_v13_0_7_allocate_dpm_context(struct smu_context * smu)510 static int smu_v13_0_7_allocate_dpm_context(struct smu_context *smu)
511 {
512 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
513
514 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
515 GFP_KERNEL);
516 if (!smu_dpm->dpm_context)
517 return -ENOMEM;
518
519 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
520
521 return 0;
522 }
523
smu_v13_0_7_init_smc_tables(struct smu_context * smu)524 static int smu_v13_0_7_init_smc_tables(struct smu_context *smu)
525 {
526 int ret = 0;
527
528 ret = smu_v13_0_7_tables_init(smu);
529 if (ret)
530 return ret;
531
532 ret = smu_v13_0_7_allocate_dpm_context(smu);
533 if (ret)
534 return ret;
535
536 return smu_v13_0_init_smc_tables(smu);
537 }
538
smu_v13_0_7_set_default_dpm_table(struct smu_context * smu)539 static int smu_v13_0_7_set_default_dpm_table(struct smu_context *smu)
540 {
541 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
542 PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
543 SkuTable_t *skutable = &driver_ppt->SkuTable;
544 struct smu_13_0_dpm_table *dpm_table;
545 struct smu_13_0_pcie_table *pcie_table;
546 uint32_t link_level;
547 int ret = 0;
548
549 /* socclk dpm table setup */
550 dpm_table = &dpm_context->dpm_tables.soc_table;
551 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
552 ret = smu_v13_0_set_single_dpm_table(smu,
553 SMU_SOCCLK,
554 dpm_table);
555 if (ret)
556 return ret;
557 } else {
558 dpm_table->count = 1;
559 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
560 dpm_table->dpm_levels[0].enabled = true;
561 dpm_table->min = dpm_table->dpm_levels[0].value;
562 dpm_table->max = dpm_table->dpm_levels[0].value;
563 }
564
565 /* gfxclk dpm table setup */
566 dpm_table = &dpm_context->dpm_tables.gfx_table;
567 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
568 ret = smu_v13_0_set_single_dpm_table(smu,
569 SMU_GFXCLK,
570 dpm_table);
571 if (ret)
572 return ret;
573 } else {
574 dpm_table->count = 1;
575 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
576 dpm_table->dpm_levels[0].enabled = true;
577 dpm_table->min = dpm_table->dpm_levels[0].value;
578 dpm_table->max = dpm_table->dpm_levels[0].value;
579 }
580
581 /* uclk dpm table setup */
582 dpm_table = &dpm_context->dpm_tables.uclk_table;
583 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
584 ret = smu_v13_0_set_single_dpm_table(smu,
585 SMU_UCLK,
586 dpm_table);
587 if (ret)
588 return ret;
589 } else {
590 dpm_table->count = 1;
591 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
592 dpm_table->dpm_levels[0].enabled = true;
593 dpm_table->min = dpm_table->dpm_levels[0].value;
594 dpm_table->max = dpm_table->dpm_levels[0].value;
595 }
596
597 /* fclk dpm table setup */
598 dpm_table = &dpm_context->dpm_tables.fclk_table;
599 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
600 ret = smu_v13_0_set_single_dpm_table(smu,
601 SMU_FCLK,
602 dpm_table);
603 if (ret)
604 return ret;
605 } else {
606 dpm_table->count = 1;
607 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
608 dpm_table->dpm_levels[0].enabled = true;
609 dpm_table->min = dpm_table->dpm_levels[0].value;
610 dpm_table->max = dpm_table->dpm_levels[0].value;
611 }
612
613 /* vclk dpm table setup */
614 dpm_table = &dpm_context->dpm_tables.vclk_table;
615 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) {
616 ret = smu_v13_0_set_single_dpm_table(smu,
617 SMU_VCLK,
618 dpm_table);
619 if (ret)
620 return ret;
621 } else {
622 dpm_table->count = 1;
623 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
624 dpm_table->dpm_levels[0].enabled = true;
625 dpm_table->min = dpm_table->dpm_levels[0].value;
626 dpm_table->max = dpm_table->dpm_levels[0].value;
627 }
628
629 /* dclk dpm table setup */
630 dpm_table = &dpm_context->dpm_tables.dclk_table;
631 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) {
632 ret = smu_v13_0_set_single_dpm_table(smu,
633 SMU_DCLK,
634 dpm_table);
635 if (ret)
636 return ret;
637 } else {
638 dpm_table->count = 1;
639 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
640 dpm_table->dpm_levels[0].enabled = true;
641 dpm_table->min = dpm_table->dpm_levels[0].value;
642 dpm_table->max = dpm_table->dpm_levels[0].value;
643 }
644
645 /* lclk dpm table setup */
646 pcie_table = &dpm_context->dpm_tables.pcie_table;
647 pcie_table->num_of_link_levels = 0;
648 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) {
649 if (!skutable->PcieGenSpeed[link_level] &&
650 !skutable->PcieLaneCount[link_level] &&
651 !skutable->LclkFreq[link_level])
652 continue;
653
654 pcie_table->pcie_gen[pcie_table->num_of_link_levels] =
655 skutable->PcieGenSpeed[link_level];
656 pcie_table->pcie_lane[pcie_table->num_of_link_levels] =
657 skutable->PcieLaneCount[link_level];
658 pcie_table->clk_freq[pcie_table->num_of_link_levels] =
659 skutable->LclkFreq[link_level];
660 pcie_table->num_of_link_levels++;
661 }
662
663 return 0;
664 }
665
smu_v13_0_7_is_dpm_running(struct smu_context * smu)666 static bool smu_v13_0_7_is_dpm_running(struct smu_context *smu)
667 {
668 int ret = 0;
669 uint64_t feature_enabled;
670
671 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
672 if (ret)
673 return false;
674
675 return !!(feature_enabled & SMC_DPM_FEATURE);
676 }
677
smu_v13_0_7_dump_pptable(struct smu_context * smu)678 static void smu_v13_0_7_dump_pptable(struct smu_context *smu)
679 {
680 struct smu_table_context *table_context = &smu->smu_table;
681 PPTable_t *pptable = table_context->driver_pptable;
682 SkuTable_t *skutable = &pptable->SkuTable;
683
684 dev_info(smu->adev->dev, "Dumped PPTable:\n");
685
686 dev_info(smu->adev->dev, "Version = 0x%08x\n", skutable->Version);
687 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", skutable->FeaturesToRun[0]);
688 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", skutable->FeaturesToRun[1]);
689 }
690
smu_v13_0_7_get_throttler_status(SmuMetrics_t * metrics)691 static uint32_t smu_v13_0_7_get_throttler_status(SmuMetrics_t *metrics)
692 {
693 uint32_t throttler_status = 0;
694 int i;
695
696 for (i = 0; i < THROTTLER_COUNT; i++)
697 throttler_status |=
698 (metrics->ThrottlingPercentage[i] ? 1U << i : 0);
699
700 return throttler_status;
701 }
702
703 #define SMU_13_0_7_BUSY_THRESHOLD 15
smu_v13_0_7_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)704 static int smu_v13_0_7_get_smu_metrics_data(struct smu_context *smu,
705 MetricsMember_t member,
706 uint32_t *value)
707 {
708 struct smu_table_context *smu_table= &smu->smu_table;
709 SmuMetrics_t *metrics =
710 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
711 int ret = 0;
712
713 ret = smu_cmn_get_metrics_table(smu,
714 NULL,
715 false);
716 if (ret)
717 return ret;
718
719 switch (member) {
720 case METRICS_CURR_GFXCLK:
721 *value = metrics->CurrClock[PPCLK_GFXCLK];
722 break;
723 case METRICS_CURR_SOCCLK:
724 *value = metrics->CurrClock[PPCLK_SOCCLK];
725 break;
726 case METRICS_CURR_UCLK:
727 *value = metrics->CurrClock[PPCLK_UCLK];
728 break;
729 case METRICS_CURR_VCLK:
730 *value = metrics->CurrClock[PPCLK_VCLK_0];
731 break;
732 case METRICS_CURR_VCLK1:
733 *value = metrics->CurrClock[PPCLK_VCLK_1];
734 break;
735 case METRICS_CURR_DCLK:
736 *value = metrics->CurrClock[PPCLK_DCLK_0];
737 break;
738 case METRICS_CURR_DCLK1:
739 *value = metrics->CurrClock[PPCLK_DCLK_1];
740 break;
741 case METRICS_CURR_FCLK:
742 *value = metrics->CurrClock[PPCLK_FCLK];
743 break;
744 case METRICS_AVERAGE_GFXCLK:
745 *value = metrics->AverageGfxclkFrequencyPreDs;
746 break;
747 case METRICS_AVERAGE_FCLK:
748 if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD)
749 *value = metrics->AverageFclkFrequencyPostDs;
750 else
751 *value = metrics->AverageFclkFrequencyPreDs;
752 break;
753 case METRICS_AVERAGE_UCLK:
754 if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD)
755 *value = metrics->AverageMemclkFrequencyPostDs;
756 else
757 *value = metrics->AverageMemclkFrequencyPreDs;
758 break;
759 case METRICS_AVERAGE_VCLK:
760 *value = metrics->AverageVclk0Frequency;
761 break;
762 case METRICS_AVERAGE_DCLK:
763 *value = metrics->AverageDclk0Frequency;
764 break;
765 case METRICS_AVERAGE_VCLK1:
766 *value = metrics->AverageVclk1Frequency;
767 break;
768 case METRICS_AVERAGE_DCLK1:
769 *value = metrics->AverageDclk1Frequency;
770 break;
771 case METRICS_AVERAGE_GFXACTIVITY:
772 *value = metrics->AverageGfxActivity;
773 break;
774 case METRICS_AVERAGE_MEMACTIVITY:
775 *value = metrics->AverageUclkActivity;
776 break;
777 case METRICS_AVERAGE_SOCKETPOWER:
778 *value = metrics->AverageSocketPower << 8;
779 break;
780 case METRICS_TEMPERATURE_EDGE:
781 *value = metrics->AvgTemperature[TEMP_EDGE] *
782 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
783 break;
784 case METRICS_TEMPERATURE_HOTSPOT:
785 *value = metrics->AvgTemperature[TEMP_HOTSPOT] *
786 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
787 break;
788 case METRICS_TEMPERATURE_MEM:
789 *value = metrics->AvgTemperature[TEMP_MEM] *
790 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
791 break;
792 case METRICS_TEMPERATURE_VRGFX:
793 *value = metrics->AvgTemperature[TEMP_VR_GFX] *
794 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
795 break;
796 case METRICS_TEMPERATURE_VRSOC:
797 *value = metrics->AvgTemperature[TEMP_VR_SOC] *
798 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
799 break;
800 case METRICS_THROTTLER_STATUS:
801 *value = smu_v13_0_7_get_throttler_status(metrics);
802 break;
803 case METRICS_CURR_FANSPEED:
804 *value = metrics->AvgFanRpm;
805 break;
806 case METRICS_CURR_FANPWM:
807 *value = metrics->AvgFanPwm;
808 break;
809 case METRICS_VOLTAGE_VDDGFX:
810 *value = metrics->AvgVoltage[SVI_PLANE_GFX];
811 break;
812 case METRICS_PCIE_RATE:
813 *value = metrics->PcieRate;
814 break;
815 case METRICS_PCIE_WIDTH:
816 *value = metrics->PcieWidth;
817 break;
818 default:
819 *value = UINT_MAX;
820 break;
821 }
822
823 return ret;
824 }
825
smu_v13_0_7_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)826 static int smu_v13_0_7_read_sensor(struct smu_context *smu,
827 enum amd_pp_sensors sensor,
828 void *data,
829 uint32_t *size)
830 {
831 struct smu_table_context *table_context = &smu->smu_table;
832 PPTable_t *smc_pptable = table_context->driver_pptable;
833 int ret = 0;
834
835 switch (sensor) {
836 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
837 *(uint16_t *)data = smc_pptable->SkuTable.FanMaximumRpm;
838 *size = 4;
839 break;
840 case AMDGPU_PP_SENSOR_MEM_LOAD:
841 ret = smu_v13_0_7_get_smu_metrics_data(smu,
842 METRICS_AVERAGE_MEMACTIVITY,
843 (uint32_t *)data);
844 *size = 4;
845 break;
846 case AMDGPU_PP_SENSOR_GPU_LOAD:
847 ret = smu_v13_0_7_get_smu_metrics_data(smu,
848 METRICS_AVERAGE_GFXACTIVITY,
849 (uint32_t *)data);
850 *size = 4;
851 break;
852 case AMDGPU_PP_SENSOR_GPU_POWER:
853 ret = smu_v13_0_7_get_smu_metrics_data(smu,
854 METRICS_AVERAGE_SOCKETPOWER,
855 (uint32_t *)data);
856 *size = 4;
857 break;
858 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
859 ret = smu_v13_0_7_get_smu_metrics_data(smu,
860 METRICS_TEMPERATURE_HOTSPOT,
861 (uint32_t *)data);
862 *size = 4;
863 break;
864 case AMDGPU_PP_SENSOR_EDGE_TEMP:
865 ret = smu_v13_0_7_get_smu_metrics_data(smu,
866 METRICS_TEMPERATURE_EDGE,
867 (uint32_t *)data);
868 *size = 4;
869 break;
870 case AMDGPU_PP_SENSOR_MEM_TEMP:
871 ret = smu_v13_0_7_get_smu_metrics_data(smu,
872 METRICS_TEMPERATURE_MEM,
873 (uint32_t *)data);
874 *size = 4;
875 break;
876 case AMDGPU_PP_SENSOR_GFX_MCLK:
877 ret = smu_v13_0_7_get_smu_metrics_data(smu,
878 METRICS_AVERAGE_UCLK,
879 (uint32_t *)data);
880 *(uint32_t *)data *= 100;
881 *size = 4;
882 break;
883 case AMDGPU_PP_SENSOR_GFX_SCLK:
884 ret = smu_v13_0_7_get_smu_metrics_data(smu,
885 METRICS_AVERAGE_GFXCLK,
886 (uint32_t *)data);
887 *(uint32_t *)data *= 100;
888 *size = 4;
889 break;
890 case AMDGPU_PP_SENSOR_VDDGFX:
891 ret = smu_v13_0_7_get_smu_metrics_data(smu,
892 METRICS_VOLTAGE_VDDGFX,
893 (uint32_t *)data);
894 *size = 4;
895 break;
896 default:
897 ret = -EOPNOTSUPP;
898 break;
899 }
900
901 return ret;
902 }
903
smu_v13_0_7_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)904 static int smu_v13_0_7_get_current_clk_freq_by_table(struct smu_context *smu,
905 enum smu_clk_type clk_type,
906 uint32_t *value)
907 {
908 MetricsMember_t member_type;
909 int clk_id = 0;
910
911 clk_id = smu_cmn_to_asic_specific_index(smu,
912 CMN2ASIC_MAPPING_CLK,
913 clk_type);
914 if (clk_id < 0)
915 return -EINVAL;
916
917 switch (clk_id) {
918 case PPCLK_GFXCLK:
919 member_type = METRICS_AVERAGE_GFXCLK;
920 break;
921 case PPCLK_UCLK:
922 member_type = METRICS_CURR_UCLK;
923 break;
924 case PPCLK_FCLK:
925 member_type = METRICS_CURR_FCLK;
926 break;
927 case PPCLK_SOCCLK:
928 member_type = METRICS_CURR_SOCCLK;
929 break;
930 case PPCLK_VCLK_0:
931 member_type = METRICS_CURR_VCLK;
932 break;
933 case PPCLK_DCLK_0:
934 member_type = METRICS_CURR_DCLK;
935 break;
936 case PPCLK_VCLK_1:
937 member_type = METRICS_CURR_VCLK1;
938 break;
939 case PPCLK_DCLK_1:
940 member_type = METRICS_CURR_DCLK1;
941 break;
942 default:
943 return -EINVAL;
944 }
945
946 return smu_v13_0_7_get_smu_metrics_data(smu,
947 member_type,
948 value);
949 }
950
smu_v13_0_7_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)951 static int smu_v13_0_7_print_clk_levels(struct smu_context *smu,
952 enum smu_clk_type clk_type,
953 char *buf)
954 {
955 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
956 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
957 struct smu_13_0_dpm_table *single_dpm_table;
958 struct smu_13_0_pcie_table *pcie_table;
959 uint32_t gen_speed, lane_width;
960 int i, curr_freq, size = 0;
961 int ret = 0;
962
963 smu_cmn_get_sysfs_buf(&buf, &size);
964
965 if (amdgpu_ras_intr_triggered()) {
966 size += sysfs_emit_at(buf, size, "unavailable\n");
967 return size;
968 }
969
970 switch (clk_type) {
971 case SMU_SCLK:
972 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
973 break;
974 case SMU_MCLK:
975 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
976 break;
977 case SMU_SOCCLK:
978 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
979 break;
980 case SMU_FCLK:
981 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
982 break;
983 case SMU_VCLK:
984 case SMU_VCLK1:
985 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
986 break;
987 case SMU_DCLK:
988 case SMU_DCLK1:
989 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
990 break;
991 default:
992 break;
993 }
994
995 switch (clk_type) {
996 case SMU_SCLK:
997 case SMU_MCLK:
998 case SMU_SOCCLK:
999 case SMU_FCLK:
1000 case SMU_VCLK:
1001 case SMU_VCLK1:
1002 case SMU_DCLK:
1003 case SMU_DCLK1:
1004 ret = smu_v13_0_7_get_current_clk_freq_by_table(smu, clk_type, &curr_freq);
1005 if (ret) {
1006 dev_err(smu->adev->dev, "Failed to get current clock freq!");
1007 return ret;
1008 }
1009
1010 if (single_dpm_table->is_fine_grained) {
1011 /*
1012 * For fine grained dpms, there are only two dpm levels:
1013 * - level 0 -> min clock freq
1014 * - level 1 -> max clock freq
1015 * And the current clock frequency can be any value between them.
1016 * So, if the current clock frequency is not at level 0 or level 1,
1017 * we will fake it as three dpm levels:
1018 * - level 0 -> min clock freq
1019 * - level 1 -> current actual clock freq
1020 * - level 2 -> max clock freq
1021 */
1022 if ((single_dpm_table->dpm_levels[0].value != curr_freq) &&
1023 (single_dpm_table->dpm_levels[1].value != curr_freq)) {
1024 size += sysfs_emit_at(buf, size, "0: %uMhz\n",
1025 single_dpm_table->dpm_levels[0].value);
1026 size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
1027 curr_freq);
1028 size += sysfs_emit_at(buf, size, "2: %uMhz\n",
1029 single_dpm_table->dpm_levels[1].value);
1030 } else {
1031 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n",
1032 single_dpm_table->dpm_levels[0].value,
1033 single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : "");
1034 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
1035 single_dpm_table->dpm_levels[1].value,
1036 single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : "");
1037 }
1038 } else {
1039 for (i = 0; i < single_dpm_table->count; i++)
1040 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
1041 i, single_dpm_table->dpm_levels[i].value,
1042 single_dpm_table->dpm_levels[i].value == curr_freq ? "*" : "");
1043 }
1044 break;
1045 case SMU_PCIE:
1046 ret = smu_v13_0_7_get_smu_metrics_data(smu,
1047 METRICS_PCIE_RATE,
1048 &gen_speed);
1049 if (ret)
1050 return ret;
1051
1052 ret = smu_v13_0_7_get_smu_metrics_data(smu,
1053 METRICS_PCIE_WIDTH,
1054 &lane_width);
1055 if (ret)
1056 return ret;
1057
1058 pcie_table = &(dpm_context->dpm_tables.pcie_table);
1059 for (i = 0; i < pcie_table->num_of_link_levels; i++)
1060 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1061 (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," :
1062 (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," :
1063 (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," :
1064 (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "",
1065 (pcie_table->pcie_lane[i] == 1) ? "x1" :
1066 (pcie_table->pcie_lane[i] == 2) ? "x2" :
1067 (pcie_table->pcie_lane[i] == 3) ? "x4" :
1068 (pcie_table->pcie_lane[i] == 4) ? "x8" :
1069 (pcie_table->pcie_lane[i] == 5) ? "x12" :
1070 (pcie_table->pcie_lane[i] == 6) ? "x16" : "",
1071 pcie_table->clk_freq[i],
1072 (gen_speed == pcie_table->pcie_gen[i]) &&
1073 (lane_width == pcie_table->pcie_lane[i]) ?
1074 "*" : "");
1075 break;
1076
1077 default:
1078 break;
1079 }
1080
1081 return size;
1082 }
1083
smu_v13_0_7_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1084 static int smu_v13_0_7_force_clk_levels(struct smu_context *smu,
1085 enum smu_clk_type clk_type,
1086 uint32_t mask)
1087 {
1088 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1089 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1090 struct smu_13_0_dpm_table *single_dpm_table;
1091 uint32_t soft_min_level, soft_max_level;
1092 uint32_t min_freq, max_freq;
1093 int ret = 0;
1094
1095 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1096 soft_max_level = mask ? (fls(mask) - 1) : 0;
1097
1098 switch (clk_type) {
1099 case SMU_GFXCLK:
1100 case SMU_SCLK:
1101 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1102 break;
1103 case SMU_MCLK:
1104 case SMU_UCLK:
1105 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1106 break;
1107 case SMU_SOCCLK:
1108 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1109 break;
1110 case SMU_FCLK:
1111 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1112 break;
1113 case SMU_VCLK:
1114 case SMU_VCLK1:
1115 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1116 break;
1117 case SMU_DCLK:
1118 case SMU_DCLK1:
1119 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1120 break;
1121 default:
1122 break;
1123 }
1124
1125 switch (clk_type) {
1126 case SMU_GFXCLK:
1127 case SMU_SCLK:
1128 case SMU_MCLK:
1129 case SMU_UCLK:
1130 case SMU_SOCCLK:
1131 case SMU_FCLK:
1132 case SMU_VCLK:
1133 case SMU_VCLK1:
1134 case SMU_DCLK:
1135 case SMU_DCLK1:
1136 if (single_dpm_table->is_fine_grained) {
1137 /* There is only 2 levels for fine grained DPM */
1138 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1139 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1140 } else {
1141 if ((soft_max_level >= single_dpm_table->count) ||
1142 (soft_min_level >= single_dpm_table->count))
1143 return -EINVAL;
1144 }
1145
1146 min_freq = single_dpm_table->dpm_levels[soft_min_level].value;
1147 max_freq = single_dpm_table->dpm_levels[soft_max_level].value;
1148
1149 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1150 clk_type,
1151 min_freq,
1152 max_freq);
1153 break;
1154 case SMU_DCEFCLK:
1155 case SMU_PCIE:
1156 default:
1157 break;
1158 }
1159
1160 return ret;
1161 }
1162
smu_v13_0_7_update_pcie_parameters(struct smu_context * smu,uint32_t pcie_gen_cap,uint32_t pcie_width_cap)1163 static int smu_v13_0_7_update_pcie_parameters(struct smu_context *smu,
1164 uint32_t pcie_gen_cap,
1165 uint32_t pcie_width_cap)
1166 {
1167 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1168 struct smu_13_0_pcie_table *pcie_table =
1169 &dpm_context->dpm_tables.pcie_table;
1170 uint32_t smu_pcie_arg;
1171 int ret, i;
1172
1173 for (i = 0; i < pcie_table->num_of_link_levels; i++) {
1174 if (pcie_table->pcie_gen[i] > pcie_gen_cap)
1175 pcie_table->pcie_gen[i] = pcie_gen_cap;
1176 if (pcie_table->pcie_lane[i] > pcie_width_cap)
1177 pcie_table->pcie_lane[i] = pcie_width_cap;
1178
1179 smu_pcie_arg = i << 16;
1180 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
1181 smu_pcie_arg |= pcie_table->pcie_lane[i];
1182
1183 ret = smu_cmn_send_smc_msg_with_param(smu,
1184 SMU_MSG_OverridePcieParameters,
1185 smu_pcie_arg,
1186 NULL);
1187 if (ret)
1188 return ret;
1189 }
1190
1191 return 0;
1192 }
1193
1194 static const struct smu_temperature_range smu13_thermal_policy[] =
1195 {
1196 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
1197 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
1198 };
1199
smu_v13_0_7_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)1200 static int smu_v13_0_7_get_thermal_temperature_range(struct smu_context *smu,
1201 struct smu_temperature_range *range)
1202 {
1203 struct smu_table_context *table_context = &smu->smu_table;
1204 struct smu_13_0_7_powerplay_table *powerplay_table =
1205 table_context->power_play_table;
1206 PPTable_t *pptable = smu->smu_table.driver_pptable;
1207
1208 if (!range)
1209 return -EINVAL;
1210
1211 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range));
1212
1213 range->max = pptable->SkuTable.TemperatureLimit[TEMP_EDGE] *
1214 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1215 range->edge_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
1216 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1217 range->hotspot_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] *
1218 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1219 range->hotspot_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
1220 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1221 range->mem_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_MEM] *
1222 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1223 range->mem_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
1224 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1225 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1226
1227 return 0;
1228 }
1229
1230 #define MAX(a, b) ((a) > (b) ? (a) : (b))
smu_v13_0_7_get_gpu_metrics(struct smu_context * smu,void ** table)1231 static ssize_t smu_v13_0_7_get_gpu_metrics(struct smu_context *smu,
1232 void **table)
1233 {
1234 struct smu_table_context *smu_table = &smu->smu_table;
1235 struct gpu_metrics_v1_3 *gpu_metrics =
1236 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
1237 SmuMetricsExternal_t metrics_ext;
1238 SmuMetrics_t *metrics = &metrics_ext.SmuMetrics;
1239 int ret = 0;
1240
1241 ret = smu_cmn_get_metrics_table(smu,
1242 &metrics_ext,
1243 true);
1244 if (ret)
1245 return ret;
1246
1247 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
1248
1249 gpu_metrics->temperature_edge = metrics->AvgTemperature[TEMP_EDGE];
1250 gpu_metrics->temperature_hotspot = metrics->AvgTemperature[TEMP_HOTSPOT];
1251 gpu_metrics->temperature_mem = metrics->AvgTemperature[TEMP_MEM];
1252 gpu_metrics->temperature_vrgfx = metrics->AvgTemperature[TEMP_VR_GFX];
1253 gpu_metrics->temperature_vrsoc = metrics->AvgTemperature[TEMP_VR_SOC];
1254 gpu_metrics->temperature_vrmem = MAX(metrics->AvgTemperature[TEMP_VR_MEM0],
1255 metrics->AvgTemperature[TEMP_VR_MEM1]);
1256
1257 gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity;
1258 gpu_metrics->average_umc_activity = metrics->AverageUclkActivity;
1259 gpu_metrics->average_mm_activity = MAX(metrics->Vcn0ActivityPercentage,
1260 metrics->Vcn1ActivityPercentage);
1261
1262 gpu_metrics->average_socket_power = metrics->AverageSocketPower;
1263 gpu_metrics->energy_accumulator = metrics->EnergyAccumulator;
1264
1265 if (metrics->AverageGfxActivity <= SMU_13_0_7_BUSY_THRESHOLD)
1266 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs;
1267 else
1268 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs;
1269
1270 if (metrics->AverageUclkActivity <= SMU_13_0_7_BUSY_THRESHOLD)
1271 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs;
1272 else
1273 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs;
1274
1275 gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency;
1276 gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency;
1277 gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency;
1278 gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency;
1279
1280 gpu_metrics->current_gfxclk = metrics->CurrClock[PPCLK_GFXCLK];
1281 gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0];
1282 gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0];
1283 gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1];
1284 gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1];
1285
1286 gpu_metrics->throttle_status =
1287 smu_v13_0_7_get_throttler_status(metrics);
1288 gpu_metrics->indep_throttle_status =
1289 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
1290 smu_v13_0_7_throttler_map);
1291
1292 gpu_metrics->current_fan_speed = metrics->AvgFanRpm;
1293
1294 gpu_metrics->pcie_link_width = metrics->PcieWidth;
1295 gpu_metrics->pcie_link_speed = metrics->PcieRate;
1296
1297 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1298
1299 gpu_metrics->voltage_gfx = metrics->AvgVoltage[SVI_PLANE_GFX];
1300 gpu_metrics->voltage_soc = metrics->AvgVoltage[SVI_PLANE_SOC];
1301 gpu_metrics->voltage_mem = metrics->AvgVoltage[SVI_PLANE_VMEMP];
1302
1303 *table = (void *)gpu_metrics;
1304
1305 return sizeof(struct gpu_metrics_v1_3);
1306 }
1307
smu_v13_0_7_populate_umd_state_clk(struct smu_context * smu)1308 static int smu_v13_0_7_populate_umd_state_clk(struct smu_context *smu)
1309 {
1310 struct smu_13_0_dpm_context *dpm_context =
1311 smu->smu_dpm.dpm_context;
1312 struct smu_13_0_dpm_table *gfx_table =
1313 &dpm_context->dpm_tables.gfx_table;
1314 struct smu_13_0_dpm_table *mem_table =
1315 &dpm_context->dpm_tables.uclk_table;
1316 struct smu_13_0_dpm_table *soc_table =
1317 &dpm_context->dpm_tables.soc_table;
1318 struct smu_13_0_dpm_table *vclk_table =
1319 &dpm_context->dpm_tables.vclk_table;
1320 struct smu_13_0_dpm_table *dclk_table =
1321 &dpm_context->dpm_tables.dclk_table;
1322 struct smu_13_0_dpm_table *fclk_table =
1323 &dpm_context->dpm_tables.fclk_table;
1324 struct smu_umd_pstate_table *pstate_table =
1325 &smu->pstate_table;
1326
1327 pstate_table->gfxclk_pstate.min = gfx_table->min;
1328 pstate_table->gfxclk_pstate.peak = gfx_table->max;
1329
1330 pstate_table->uclk_pstate.min = mem_table->min;
1331 pstate_table->uclk_pstate.peak = mem_table->max;
1332
1333 pstate_table->socclk_pstate.min = soc_table->min;
1334 pstate_table->socclk_pstate.peak = soc_table->max;
1335
1336 pstate_table->vclk_pstate.min = vclk_table->min;
1337 pstate_table->vclk_pstate.peak = vclk_table->max;
1338
1339 pstate_table->dclk_pstate.min = dclk_table->min;
1340 pstate_table->dclk_pstate.peak = dclk_table->max;
1341
1342 pstate_table->fclk_pstate.min = fclk_table->min;
1343 pstate_table->fclk_pstate.peak = fclk_table->max;
1344
1345 /*
1346 * For now, just use the mininum clock frequency.
1347 * TODO: update them when the real pstate settings available
1348 */
1349 pstate_table->gfxclk_pstate.standard = gfx_table->min;
1350 pstate_table->uclk_pstate.standard = mem_table->min;
1351 pstate_table->socclk_pstate.standard = soc_table->min;
1352 pstate_table->vclk_pstate.standard = vclk_table->min;
1353 pstate_table->dclk_pstate.standard = dclk_table->min;
1354 pstate_table->fclk_pstate.standard = fclk_table->min;
1355
1356 return 0;
1357 }
1358
smu_v13_0_7_get_fan_speed_pwm(struct smu_context * smu,uint32_t * speed)1359 static int smu_v13_0_7_get_fan_speed_pwm(struct smu_context *smu,
1360 uint32_t *speed)
1361 {
1362 if (!speed)
1363 return -EINVAL;
1364
1365 return smu_v13_0_7_get_smu_metrics_data(smu,
1366 METRICS_CURR_FANPWM,
1367 speed);
1368 }
1369
smu_v13_0_7_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)1370 static int smu_v13_0_7_get_fan_speed_rpm(struct smu_context *smu,
1371 uint32_t *speed)
1372 {
1373 if (!speed)
1374 return -EINVAL;
1375
1376 return smu_v13_0_7_get_smu_metrics_data(smu,
1377 METRICS_CURR_FANSPEED,
1378 speed);
1379 }
1380
smu_v13_0_7_enable_mgpu_fan_boost(struct smu_context * smu)1381 static int smu_v13_0_7_enable_mgpu_fan_boost(struct smu_context *smu)
1382 {
1383 struct smu_table_context *table_context = &smu->smu_table;
1384 PPTable_t *pptable = table_context->driver_pptable;
1385 SkuTable_t *skutable = &pptable->SkuTable;
1386
1387 /*
1388 * Skip the MGpuFanBoost setting for those ASICs
1389 * which do not support it
1390 */
1391 if (skutable->MGpuAcousticLimitRpmThreshold == 0)
1392 return 0;
1393
1394 return smu_cmn_send_smc_msg_with_param(smu,
1395 SMU_MSG_SetMGpuFanBoostLimitRpm,
1396 0,
1397 NULL);
1398 }
1399
smu_v13_0_7_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit)1400 static int smu_v13_0_7_get_power_limit(struct smu_context *smu,
1401 uint32_t *current_power_limit,
1402 uint32_t *default_power_limit,
1403 uint32_t *max_power_limit)
1404 {
1405 struct smu_table_context *table_context = &smu->smu_table;
1406 struct smu_13_0_7_powerplay_table *powerplay_table =
1407 (struct smu_13_0_7_powerplay_table *)table_context->power_play_table;
1408 PPTable_t *pptable = table_context->driver_pptable;
1409 SkuTable_t *skutable = &pptable->SkuTable;
1410 uint32_t power_limit, od_percent;
1411
1412 if (smu_v13_0_get_current_power_limit(smu, &power_limit))
1413 power_limit = smu->adev->pm.ac_power ?
1414 skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] :
1415 skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0];
1416
1417 if (current_power_limit)
1418 *current_power_limit = power_limit;
1419 if (default_power_limit)
1420 *default_power_limit = power_limit;
1421
1422 if (max_power_limit) {
1423 if (smu->od_enabled) {
1424 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_13_0_7_ODSETTING_POWERPERCENTAGE]);
1425
1426 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1427
1428 power_limit *= (100 + od_percent);
1429 power_limit /= 100;
1430 }
1431 *max_power_limit = power_limit;
1432 }
1433
1434 return 0;
1435 }
1436
smu_v13_0_7_get_power_profile_mode(struct smu_context * smu,char * buf)1437 static int smu_v13_0_7_get_power_profile_mode(struct smu_context *smu, char *buf)
1438 {
1439 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external[PP_SMC_POWER_PROFILE_COUNT];
1440 uint32_t i, j, size = 0;
1441 int16_t workload_type = 0;
1442 int result = 0;
1443
1444 if (!buf)
1445 return -EINVAL;
1446
1447 size += sysfs_emit_at(buf, size, " ");
1448 for (i = 0; i <= PP_SMC_POWER_PROFILE_WINDOW3D; i++)
1449 size += sysfs_emit_at(buf, size, "%-14s%s", amdgpu_pp_profile_name[i],
1450 (i == smu->power_profile_mode) ? "* " : " ");
1451
1452 size += sysfs_emit_at(buf, size, "\n");
1453
1454 for (i = 0; i <= PP_SMC_POWER_PROFILE_WINDOW3D; i++) {
1455 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1456 workload_type = smu_cmn_to_asic_specific_index(smu,
1457 CMN2ASIC_MAPPING_WORKLOAD,
1458 i);
1459 if (workload_type < 0)
1460 return -EINVAL;
1461
1462 result = smu_cmn_update_table(smu,
1463 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1464 (void *)(&activity_monitor_external[i]), false);
1465 if (result) {
1466 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1467 return result;
1468 }
1469 }
1470
1471 #define PRINT_DPM_MONITOR(field) \
1472 do { \
1473 size += sysfs_emit_at(buf, size, "%-30s", #field); \
1474 for (j = 0; j <= PP_SMC_POWER_PROFILE_WINDOW3D; j++) \
1475 size += sysfs_emit_at(buf, size, "%-16d", activity_monitor_external[j].DpmActivityMonitorCoeffInt.field); \
1476 size += sysfs_emit_at(buf, size, "\n"); \
1477 } while (0)
1478
1479 PRINT_DPM_MONITOR(Gfx_ActiveHystLimit);
1480 PRINT_DPM_MONITOR(Gfx_IdleHystLimit);
1481 PRINT_DPM_MONITOR(Gfx_FPS);
1482 PRINT_DPM_MONITOR(Gfx_MinActiveFreqType);
1483 PRINT_DPM_MONITOR(Gfx_BoosterFreqType);
1484 PRINT_DPM_MONITOR(Gfx_MinActiveFreq);
1485 PRINT_DPM_MONITOR(Gfx_BoosterFreq);
1486 PRINT_DPM_MONITOR(Fclk_ActiveHystLimit);
1487 PRINT_DPM_MONITOR(Fclk_IdleHystLimit);
1488 PRINT_DPM_MONITOR(Fclk_FPS);
1489 PRINT_DPM_MONITOR(Fclk_MinActiveFreqType);
1490 PRINT_DPM_MONITOR(Fclk_BoosterFreqType);
1491 PRINT_DPM_MONITOR(Fclk_MinActiveFreq);
1492 PRINT_DPM_MONITOR(Fclk_BoosterFreq);
1493 #undef PRINT_DPM_MONITOR
1494
1495 return size;
1496 }
1497
smu_v13_0_7_set_power_profile_mode(struct smu_context * smu,long * input,uint32_t size)1498 static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1499 {
1500
1501 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1502 DpmActivityMonitorCoeffInt_t *activity_monitor =
1503 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1504 int workload_type, ret = 0;
1505
1506 smu->power_profile_mode = input[size];
1507
1508 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_WINDOW3D) {
1509 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1510 return -EINVAL;
1511 }
1512
1513 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1514
1515 ret = smu_cmn_update_table(smu,
1516 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1517 (void *)(&activity_monitor_external), false);
1518 if (ret) {
1519 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1520 return ret;
1521 }
1522
1523 switch (input[0]) {
1524 case 0: /* Gfxclk */
1525 activity_monitor->Gfx_ActiveHystLimit = input[1];
1526 activity_monitor->Gfx_IdleHystLimit = input[2];
1527 activity_monitor->Gfx_FPS = input[3];
1528 activity_monitor->Gfx_MinActiveFreqType = input[4];
1529 activity_monitor->Gfx_BoosterFreqType = input[5];
1530 activity_monitor->Gfx_MinActiveFreq = input[6];
1531 activity_monitor->Gfx_BoosterFreq = input[7];
1532 break;
1533 case 1: /* Fclk */
1534 activity_monitor->Fclk_ActiveHystLimit = input[1];
1535 activity_monitor->Fclk_IdleHystLimit = input[2];
1536 activity_monitor->Fclk_FPS = input[3];
1537 activity_monitor->Fclk_MinActiveFreqType = input[4];
1538 activity_monitor->Fclk_BoosterFreqType = input[5];
1539 activity_monitor->Fclk_MinActiveFreq = input[6];
1540 activity_monitor->Fclk_BoosterFreq = input[7];
1541 break;
1542 }
1543
1544 ret = smu_cmn_update_table(smu,
1545 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1546 (void *)(&activity_monitor_external), true);
1547 if (ret) {
1548 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1549 return ret;
1550 }
1551 }
1552
1553 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1554 workload_type = smu_cmn_to_asic_specific_index(smu,
1555 CMN2ASIC_MAPPING_WORKLOAD,
1556 smu->power_profile_mode);
1557 if (workload_type < 0)
1558 return -EINVAL;
1559 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1560 1 << workload_type, NULL);
1561
1562 return ret;
1563 }
1564
smu_v13_0_7_set_mp1_state(struct smu_context * smu,enum pp_mp1_state mp1_state)1565 static int smu_v13_0_7_set_mp1_state(struct smu_context *smu,
1566 enum pp_mp1_state mp1_state)
1567 {
1568 int ret;
1569
1570 switch (mp1_state) {
1571 case PP_MP1_STATE_UNLOAD:
1572 ret = smu_cmn_set_mp1_state(smu, mp1_state);
1573 break;
1574 default:
1575 /* Ignore others */
1576 ret = 0;
1577 }
1578
1579 return ret;
1580 }
1581
smu_v13_0_7_baco_enter(struct smu_context * smu)1582 static int smu_v13_0_7_baco_enter(struct smu_context *smu)
1583 {
1584 struct smu_baco_context *smu_baco = &smu->smu_baco;
1585 struct amdgpu_device *adev = smu->adev;
1586
1587 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
1588 return smu_v13_0_baco_set_armd3_sequence(smu,
1589 smu_baco->maco_support ? BACO_SEQ_BAMACO : BACO_SEQ_BACO);
1590 else
1591 return smu_v13_0_baco_enter(smu);
1592 }
1593
smu_v13_0_7_baco_exit(struct smu_context * smu)1594 static int smu_v13_0_7_baco_exit(struct smu_context *smu)
1595 {
1596 struct amdgpu_device *adev = smu->adev;
1597
1598 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
1599 /* Wait for PMFW handling for the Dstate change */
1600 usleep_range(10000, 11000);
1601 return smu_v13_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
1602 } else {
1603 return smu_v13_0_baco_exit(smu);
1604 }
1605 }
1606
smu_v13_0_7_is_mode1_reset_supported(struct smu_context * smu)1607 static bool smu_v13_0_7_is_mode1_reset_supported(struct smu_context *smu)
1608 {
1609 struct amdgpu_device *adev = smu->adev;
1610
1611 /* SRIOV does not support SMU mode1 reset */
1612 if (amdgpu_sriov_vf(adev))
1613 return false;
1614
1615 return true;
1616 }
1617
smu_v13_0_7_set_df_cstate(struct smu_context * smu,enum pp_df_cstate state)1618 static int smu_v13_0_7_set_df_cstate(struct smu_context *smu,
1619 enum pp_df_cstate state)
1620 {
1621 return smu_cmn_send_smc_msg_with_param(smu,
1622 SMU_MSG_DFCstateControl,
1623 state,
1624 NULL);
1625 }
1626
1627 static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
1628 .get_allowed_feature_mask = smu_v13_0_7_get_allowed_feature_mask,
1629 .set_default_dpm_table = smu_v13_0_7_set_default_dpm_table,
1630 .is_dpm_running = smu_v13_0_7_is_dpm_running,
1631 .dump_pptable = smu_v13_0_7_dump_pptable,
1632 .init_microcode = smu_v13_0_init_microcode,
1633 .load_microcode = smu_v13_0_load_microcode,
1634 .fini_microcode = smu_v13_0_fini_microcode,
1635 .init_smc_tables = smu_v13_0_7_init_smc_tables,
1636 .fini_smc_tables = smu_v13_0_fini_smc_tables,
1637 .init_power = smu_v13_0_init_power,
1638 .fini_power = smu_v13_0_fini_power,
1639 .check_fw_status = smu_v13_0_7_check_fw_status,
1640 .setup_pptable = smu_v13_0_7_setup_pptable,
1641 .check_fw_version = smu_v13_0_check_fw_version,
1642 .write_pptable = smu_cmn_write_pptable,
1643 .set_driver_table_location = smu_v13_0_set_driver_table_location,
1644 .system_features_control = smu_v13_0_system_features_control,
1645 .set_allowed_mask = smu_v13_0_set_allowed_mask,
1646 .get_enabled_mask = smu_cmn_get_enabled_mask,
1647 .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable,
1648 .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable,
1649 .init_pptable_microcode = smu_v13_0_init_pptable_microcode,
1650 .populate_umd_state_clk = smu_v13_0_7_populate_umd_state_clk,
1651 .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq,
1652 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
1653 .read_sensor = smu_v13_0_7_read_sensor,
1654 .feature_is_enabled = smu_cmn_feature_is_enabled,
1655 .print_clk_levels = smu_v13_0_7_print_clk_levels,
1656 .force_clk_levels = smu_v13_0_7_force_clk_levels,
1657 .update_pcie_parameters = smu_v13_0_7_update_pcie_parameters,
1658 .get_thermal_temperature_range = smu_v13_0_7_get_thermal_temperature_range,
1659 .register_irq_handler = smu_v13_0_register_irq_handler,
1660 .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
1661 .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
1662 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
1663 .get_gpu_metrics = smu_v13_0_7_get_gpu_metrics,
1664 .set_soft_freq_limited_range = smu_v13_0_set_soft_freq_limited_range,
1665 .set_performance_level = smu_v13_0_set_performance_level,
1666 .gfx_off_control = smu_v13_0_gfx_off_control,
1667 .get_fan_speed_pwm = smu_v13_0_7_get_fan_speed_pwm,
1668 .get_fan_speed_rpm = smu_v13_0_7_get_fan_speed_rpm,
1669 .set_fan_speed_pwm = smu_v13_0_set_fan_speed_pwm,
1670 .set_fan_speed_rpm = smu_v13_0_set_fan_speed_rpm,
1671 .get_fan_control_mode = smu_v13_0_get_fan_control_mode,
1672 .set_fan_control_mode = smu_v13_0_set_fan_control_mode,
1673 .enable_mgpu_fan_boost = smu_v13_0_7_enable_mgpu_fan_boost,
1674 .get_power_limit = smu_v13_0_7_get_power_limit,
1675 .set_power_limit = smu_v13_0_set_power_limit,
1676 .get_power_profile_mode = smu_v13_0_7_get_power_profile_mode,
1677 .set_power_profile_mode = smu_v13_0_7_set_power_profile_mode,
1678 .set_tool_table_location = smu_v13_0_set_tool_table_location,
1679 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1680 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
1681 .baco_is_support = smu_v13_0_baco_is_support,
1682 .baco_get_state = smu_v13_0_baco_get_state,
1683 .baco_set_state = smu_v13_0_baco_set_state,
1684 .baco_enter = smu_v13_0_7_baco_enter,
1685 .baco_exit = smu_v13_0_7_baco_exit,
1686 .mode1_reset_is_support = smu_v13_0_7_is_mode1_reset_supported,
1687 .mode1_reset = smu_v13_0_mode1_reset,
1688 .set_mp1_state = smu_v13_0_7_set_mp1_state,
1689 .set_df_cstate = smu_v13_0_7_set_df_cstate,
1690 };
1691
smu_v13_0_7_set_ppt_funcs(struct smu_context * smu)1692 void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu)
1693 {
1694 smu->ppt_funcs = &smu_v13_0_7_ppt_funcs;
1695 smu->message_map = smu_v13_0_7_message_map;
1696 smu->clock_map = smu_v13_0_7_clk_map;
1697 smu->feature_map = smu_v13_0_7_feature_mask_map;
1698 smu->table_map = smu_v13_0_7_table_map;
1699 smu->pwr_src_map = smu_v13_0_7_pwr_src_map;
1700 smu->workload_map = smu_v13_0_7_workload_map;
1701 smu_v13_0_set_smu_mailbox_registers(smu);
1702 }
1703
