1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include <linux/pci.h>
28 #include <linux/i2c.h>
29 #include "amdgpu.h"
30 #include "amdgpu_smu.h"
31 #include "atomfirmware.h"
32 #include "amdgpu_atomfirmware.h"
33 #include "amdgpu_atombios.h"
34 #include "smu_v13_0.h"
35 #include "smu13_driver_if_v13_0_0.h"
36 #include "soc15_common.h"
37 #include "atom.h"
38 #include "smu_v13_0_0_ppt.h"
39 #include "smu_v13_0_0_pptable.h"
40 #include "smu_v13_0_0_ppsmc.h"
41 #include "nbio/nbio_4_3_0_offset.h"
42 #include "nbio/nbio_4_3_0_sh_mask.h"
43 #include "mp/mp_13_0_0_offset.h"
44 #include "mp/mp_13_0_0_sh_mask.h"
45
46 #include "asic_reg/mp/mp_13_0_0_sh_mask.h"
47 #include "smu_cmn.h"
48 #include "amdgpu_ras.h"
49
50 /*
51 * DO NOT use these for err/warn/info/debug messages.
52 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
53 * They are more MGPU friendly.
54 */
55 #undef pr_err
56 #undef pr_warn
57 #undef pr_info
58 #undef pr_debug
59
60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
61
62 #define FEATURE_MASK(feature) (1ULL << feature)
63 #define SMC_DPM_FEATURE ( \
64 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
65 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
66 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
67 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
68 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
69 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
70
71 #define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000
72
73 static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] = {
74 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
75 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
76 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
77 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
78 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
79 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
80 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
81 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
82 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
83 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
84 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
85 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
86 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
87 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
88 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
89 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
90 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
91 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
92 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
93 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
94 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
95 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
96 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
97 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
98 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
99 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
100 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
101 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
102 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
103 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
104 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
105 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
106 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
107 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
108 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
109 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
110 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
111 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
112 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
113 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
114 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
115 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
116 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
117 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
118 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
119 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
120 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
121 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
122 MSG_MAP(DFCstateControl, PPSMC_MSG_SetExternalClientDfCstateAllow, 0),
123 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
124 };
125
126 static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = {
127 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
128 CLK_MAP(SCLK, PPCLK_GFXCLK),
129 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
130 CLK_MAP(FCLK, PPCLK_FCLK),
131 CLK_MAP(UCLK, PPCLK_UCLK),
132 CLK_MAP(MCLK, PPCLK_UCLK),
133 CLK_MAP(VCLK, PPCLK_VCLK_0),
134 CLK_MAP(VCLK1, PPCLK_VCLK_1),
135 CLK_MAP(DCLK, PPCLK_DCLK_0),
136 CLK_MAP(DCLK1, PPCLK_DCLK_1),
137 };
138
139 static struct cmn2asic_mapping smu_v13_0_0_feature_mask_map[SMU_FEATURE_COUNT] = {
140 FEA_MAP(FW_DATA_READ),
141 FEA_MAP(DPM_GFXCLK),
142 FEA_MAP(DPM_GFX_POWER_OPTIMIZER),
143 FEA_MAP(DPM_UCLK),
144 FEA_MAP(DPM_FCLK),
145 FEA_MAP(DPM_SOCCLK),
146 FEA_MAP(DPM_MP0CLK),
147 FEA_MAP(DPM_LINK),
148 FEA_MAP(DPM_DCN),
149 FEA_MAP(VMEMP_SCALING),
150 FEA_MAP(VDDIO_MEM_SCALING),
151 FEA_MAP(DS_GFXCLK),
152 FEA_MAP(DS_SOCCLK),
153 FEA_MAP(DS_FCLK),
154 FEA_MAP(DS_LCLK),
155 FEA_MAP(DS_DCFCLK),
156 FEA_MAP(DS_UCLK),
157 FEA_MAP(GFX_ULV),
158 FEA_MAP(FW_DSTATE),
159 FEA_MAP(GFXOFF),
160 FEA_MAP(BACO),
161 FEA_MAP(MM_DPM),
162 FEA_MAP(SOC_MPCLK_DS),
163 FEA_MAP(BACO_MPCLK_DS),
164 FEA_MAP(THROTTLERS),
165 FEA_MAP(SMARTSHIFT),
166 FEA_MAP(GTHR),
167 FEA_MAP(ACDC),
168 FEA_MAP(VR0HOT),
169 FEA_MAP(FW_CTF),
170 FEA_MAP(FAN_CONTROL),
171 FEA_MAP(GFX_DCS),
172 FEA_MAP(GFX_READ_MARGIN),
173 FEA_MAP(LED_DISPLAY),
174 FEA_MAP(GFXCLK_SPREAD_SPECTRUM),
175 FEA_MAP(OUT_OF_BAND_MONITOR),
176 FEA_MAP(OPTIMIZED_VMIN),
177 FEA_MAP(GFX_IMU),
178 FEA_MAP(BOOT_TIME_CAL),
179 FEA_MAP(GFX_PCC_DFLL),
180 FEA_MAP(SOC_CG),
181 FEA_MAP(DF_CSTATE),
182 FEA_MAP(GFX_EDC),
183 FEA_MAP(BOOT_POWER_OPT),
184 FEA_MAP(CLOCK_POWER_DOWN_BYPASS),
185 FEA_MAP(DS_VCN),
186 FEA_MAP(BACO_CG),
187 FEA_MAP(MEM_TEMP_READ),
188 FEA_MAP(ATHUB_MMHUB_PG),
189 FEA_MAP(SOC_PCC),
190 };
191
192 static struct cmn2asic_mapping smu_v13_0_0_table_map[SMU_TABLE_COUNT] = {
193 TAB_MAP(PPTABLE),
194 TAB_MAP(WATERMARKS),
195 TAB_MAP(AVFS_PSM_DEBUG),
196 TAB_MAP(PMSTATUSLOG),
197 TAB_MAP(SMU_METRICS),
198 TAB_MAP(DRIVER_SMU_CONFIG),
199 TAB_MAP(ACTIVITY_MONITOR_COEFF),
200 [SMU_TABLE_COMBO_PPTABLE] = {1, TABLE_COMBO_PPTABLE},
201 TAB_MAP(I2C_COMMANDS),
202 };
203
204 static struct cmn2asic_mapping smu_v13_0_0_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
205 PWR_MAP(AC),
206 PWR_MAP(DC),
207 };
208
209 static struct cmn2asic_mapping smu_v13_0_0_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
210 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
211 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
212 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
213 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
214 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
215 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
216 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
217 };
218
219 static const uint8_t smu_v13_0_0_throttler_map[] = {
220 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
221 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
222 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
223 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
224 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
225 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
226 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
227 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
228 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
229 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
230 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
231 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
232 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
233 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
234 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
235 [THROTTLER_GFX_APCC_PLUS_BIT] = (SMU_THROTTLER_APCC_BIT),
236 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
237 };
238
239 static int
smu_v13_0_0_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)240 smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu,
241 uint32_t *feature_mask, uint32_t num)
242 {
243 struct amdgpu_device *adev = smu->adev;
244 u32 smu_version;
245
246 if (num > 2)
247 return -EINVAL;
248
249 memset(feature_mask, 0xff, sizeof(uint32_t) * num);
250
251 if (!(adev->pm.pp_feature & PP_SCLK_DPM_MASK)) {
252 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
253 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_IMU_BIT);
254 }
255
256 if (!(adev->pg_flags & AMD_PG_SUPPORT_ATHUB) ||
257 !(adev->pg_flags & AMD_PG_SUPPORT_MMHUB))
258 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_ATHUB_MMHUB_PG_BIT);
259
260 if (!(adev->pm.pp_feature & PP_SOCCLK_DPM_MASK))
261 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
262
263 /* PMFW 78.58 contains a critical fix for gfxoff feature */
264 smu_cmn_get_smc_version(smu, NULL, &smu_version);
265 if ((smu_version < 0x004e3a00) ||
266 !(adev->pm.pp_feature & PP_GFXOFF_MASK))
267 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFXOFF_BIT);
268
269 if (!(adev->pm.pp_feature & PP_MCLK_DPM_MASK)) {
270 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
271 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT);
272 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT);
273 }
274
275 if (!(adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK))
276 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
277
278 if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
279 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DPM_LINK_BIT);
280 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_LCLK_BIT);
281 }
282
283 if (!(adev->pm.pp_feature & PP_ULV_MASK))
284 *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_GFX_ULV_BIT);
285
286 return 0;
287 }
288
smu_v13_0_0_check_powerplay_table(struct smu_context * smu)289 static int smu_v13_0_0_check_powerplay_table(struct smu_context *smu)
290 {
291 struct smu_table_context *table_context = &smu->smu_table;
292 struct smu_13_0_0_powerplay_table *powerplay_table =
293 table_context->power_play_table;
294 struct smu_baco_context *smu_baco = &smu->smu_baco;
295
296 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_HARDWAREDC)
297 smu->dc_controlled_by_gpio = true;
298
299 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_BACO ||
300 powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO)
301 smu_baco->platform_support = true;
302
303 if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO)
304 smu_baco->maco_support = true;
305
306 table_context->thermal_controller_type =
307 powerplay_table->thermal_controller_type;
308
309 /*
310 * Instead of having its own buffer space and get overdrive_table copied,
311 * smu->od_settings just points to the actual overdrive_table
312 */
313 smu->od_settings = &powerplay_table->overdrive_table;
314
315 return 0;
316 }
317
smu_v13_0_0_store_powerplay_table(struct smu_context * smu)318 static int smu_v13_0_0_store_powerplay_table(struct smu_context *smu)
319 {
320 struct smu_table_context *table_context = &smu->smu_table;
321 struct smu_13_0_0_powerplay_table *powerplay_table =
322 table_context->power_play_table;
323
324 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
325 sizeof(PPTable_t));
326
327 return 0;
328 }
329
330 #ifndef atom_smc_dpm_info_table_13_0_0
331 struct atom_smc_dpm_info_table_13_0_0 {
332 struct atom_common_table_header table_header;
333 BoardTable_t BoardTable;
334 };
335 #endif
336
smu_v13_0_0_append_powerplay_table(struct smu_context * smu)337 static int smu_v13_0_0_append_powerplay_table(struct smu_context *smu)
338 {
339 struct smu_table_context *table_context = &smu->smu_table;
340 PPTable_t *smc_pptable = table_context->driver_pptable;
341 struct atom_smc_dpm_info_table_13_0_0 *smc_dpm_table;
342 BoardTable_t *BoardTable = &smc_pptable->BoardTable;
343 int index, ret;
344
345 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
346 smc_dpm_info);
347
348 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
349 (uint8_t **)&smc_dpm_table);
350 if (ret)
351 return ret;
352
353 memcpy(BoardTable, &smc_dpm_table->BoardTable, sizeof(BoardTable_t));
354
355 return 0;
356 }
357
smu_v13_0_0_get_pptable_from_pmfw(struct smu_context * smu,void ** table,uint32_t * size)358 static int smu_v13_0_0_get_pptable_from_pmfw(struct smu_context *smu,
359 void **table,
360 uint32_t *size)
361 {
362 struct smu_table_context *smu_table = &smu->smu_table;
363 void *combo_pptable = smu_table->combo_pptable;
364 int ret = 0;
365
366 ret = smu_cmn_get_combo_pptable(smu);
367 if (ret)
368 return ret;
369
370 *table = combo_pptable;
371 *size = sizeof(struct smu_13_0_0_powerplay_table);
372
373 return 0;
374 }
375
smu_v13_0_0_setup_pptable(struct smu_context * smu)376 static int smu_v13_0_0_setup_pptable(struct smu_context *smu)
377 {
378 struct smu_table_context *smu_table = &smu->smu_table;
379 struct amdgpu_device *adev = smu->adev;
380 int ret = 0;
381
382 ret = smu_v13_0_0_get_pptable_from_pmfw(smu,
383 &smu_table->power_play_table,
384 &smu_table->power_play_table_size);
385 if (ret)
386 return ret;
387
388 ret = smu_v13_0_0_store_powerplay_table(smu);
389 if (ret)
390 return ret;
391
392 /*
393 * With SCPM enabled, the operation below will be handled
394 * by PSP. Driver involvment is unnecessary and useless.
395 */
396 if (!adev->scpm_enabled) {
397 ret = smu_v13_0_0_append_powerplay_table(smu);
398 if (ret)
399 return ret;
400 }
401
402 ret = smu_v13_0_0_check_powerplay_table(smu);
403 if (ret)
404 return ret;
405
406 return ret;
407 }
408
smu_v13_0_0_tables_init(struct smu_context * smu)409 static int smu_v13_0_0_tables_init(struct smu_context *smu)
410 {
411 struct smu_table_context *smu_table = &smu->smu_table;
412 struct smu_table *tables = smu_table->tables;
413
414 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
415 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
416 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
417 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
418 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
419 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
420 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
421 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
422 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
423 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
424 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
425 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
426 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
427 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
428 AMDGPU_GEM_DOMAIN_VRAM);
429 SMU_TABLE_INIT(tables, SMU_TABLE_COMBO_PPTABLE, MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE,
430 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
431
432 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
433 if (!smu_table->metrics_table)
434 goto err0_out;
435 smu_table->metrics_time = 0;
436
437 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
438 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
439 if (!smu_table->gpu_metrics_table)
440 goto err1_out;
441
442 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
443 if (!smu_table->watermarks_table)
444 goto err2_out;
445
446 return 0;
447
448 err2_out:
449 kfree(smu_table->gpu_metrics_table);
450 err1_out:
451 kfree(smu_table->metrics_table);
452 err0_out:
453 return -ENOMEM;
454 }
455
smu_v13_0_0_allocate_dpm_context(struct smu_context * smu)456 static int smu_v13_0_0_allocate_dpm_context(struct smu_context *smu)
457 {
458 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
459
460 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
461 GFP_KERNEL);
462 if (!smu_dpm->dpm_context)
463 return -ENOMEM;
464
465 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
466
467 return 0;
468 }
469
smu_v13_0_0_init_smc_tables(struct smu_context * smu)470 static int smu_v13_0_0_init_smc_tables(struct smu_context *smu)
471 {
472 int ret = 0;
473
474 ret = smu_v13_0_0_tables_init(smu);
475 if (ret)
476 return ret;
477
478 ret = smu_v13_0_0_allocate_dpm_context(smu);
479 if (ret)
480 return ret;
481
482 return smu_v13_0_init_smc_tables(smu);
483 }
484
smu_v13_0_0_set_default_dpm_table(struct smu_context * smu)485 static int smu_v13_0_0_set_default_dpm_table(struct smu_context *smu)
486 {
487 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
488 struct smu_table_context *table_context = &smu->smu_table;
489 PPTable_t *pptable = table_context->driver_pptable;
490 SkuTable_t *skutable = &pptable->SkuTable;
491 struct smu_13_0_dpm_table *dpm_table;
492 struct smu_13_0_pcie_table *pcie_table;
493 uint32_t link_level;
494 int ret = 0;
495
496 /* socclk dpm table setup */
497 dpm_table = &dpm_context->dpm_tables.soc_table;
498 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
499 ret = smu_v13_0_set_single_dpm_table(smu,
500 SMU_SOCCLK,
501 dpm_table);
502 if (ret)
503 return ret;
504 } else {
505 dpm_table->count = 1;
506 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
507 dpm_table->dpm_levels[0].enabled = true;
508 dpm_table->min = dpm_table->dpm_levels[0].value;
509 dpm_table->max = dpm_table->dpm_levels[0].value;
510 }
511
512 /* gfxclk dpm table setup */
513 dpm_table = &dpm_context->dpm_tables.gfx_table;
514 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
515 ret = smu_v13_0_set_single_dpm_table(smu,
516 SMU_GFXCLK,
517 dpm_table);
518 if (ret)
519 return ret;
520 } else {
521 dpm_table->count = 1;
522 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
523 dpm_table->dpm_levels[0].enabled = true;
524 dpm_table->min = dpm_table->dpm_levels[0].value;
525 dpm_table->max = dpm_table->dpm_levels[0].value;
526 }
527
528 /* uclk dpm table setup */
529 dpm_table = &dpm_context->dpm_tables.uclk_table;
530 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
531 ret = smu_v13_0_set_single_dpm_table(smu,
532 SMU_UCLK,
533 dpm_table);
534 if (ret)
535 return ret;
536 } else {
537 dpm_table->count = 1;
538 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
539 dpm_table->dpm_levels[0].enabled = true;
540 dpm_table->min = dpm_table->dpm_levels[0].value;
541 dpm_table->max = dpm_table->dpm_levels[0].value;
542 }
543
544 /* fclk dpm table setup */
545 dpm_table = &dpm_context->dpm_tables.fclk_table;
546 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
547 ret = smu_v13_0_set_single_dpm_table(smu,
548 SMU_FCLK,
549 dpm_table);
550 if (ret)
551 return ret;
552 } else {
553 dpm_table->count = 1;
554 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
555 dpm_table->dpm_levels[0].enabled = true;
556 dpm_table->min = dpm_table->dpm_levels[0].value;
557 dpm_table->max = dpm_table->dpm_levels[0].value;
558 }
559
560 /* vclk dpm table setup */
561 dpm_table = &dpm_context->dpm_tables.vclk_table;
562 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_VCLK_BIT)) {
563 ret = smu_v13_0_set_single_dpm_table(smu,
564 SMU_VCLK,
565 dpm_table);
566 if (ret)
567 return ret;
568 } else {
569 dpm_table->count = 1;
570 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
571 dpm_table->dpm_levels[0].enabled = true;
572 dpm_table->min = dpm_table->dpm_levels[0].value;
573 dpm_table->max = dpm_table->dpm_levels[0].value;
574 }
575
576 /* dclk dpm table setup */
577 dpm_table = &dpm_context->dpm_tables.dclk_table;
578 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCLK_BIT)) {
579 ret = smu_v13_0_set_single_dpm_table(smu,
580 SMU_DCLK,
581 dpm_table);
582 if (ret)
583 return ret;
584 } else {
585 dpm_table->count = 1;
586 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
587 dpm_table->dpm_levels[0].enabled = true;
588 dpm_table->min = dpm_table->dpm_levels[0].value;
589 dpm_table->max = dpm_table->dpm_levels[0].value;
590 }
591
592 /* lclk dpm table setup */
593 pcie_table = &dpm_context->dpm_tables.pcie_table;
594 pcie_table->num_of_link_levels = 0;
595 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) {
596 if (!skutable->PcieGenSpeed[link_level] &&
597 !skutable->PcieLaneCount[link_level] &&
598 !skutable->LclkFreq[link_level])
599 continue;
600
601 pcie_table->pcie_gen[pcie_table->num_of_link_levels] =
602 skutable->PcieGenSpeed[link_level];
603 pcie_table->pcie_lane[pcie_table->num_of_link_levels] =
604 skutable->PcieLaneCount[link_level];
605 pcie_table->clk_freq[pcie_table->num_of_link_levels] =
606 skutable->LclkFreq[link_level];
607 pcie_table->num_of_link_levels++;
608 }
609
610 return 0;
611 }
612
smu_v13_0_0_is_dpm_running(struct smu_context * smu)613 static bool smu_v13_0_0_is_dpm_running(struct smu_context *smu)
614 {
615 int ret = 0;
616 uint64_t feature_enabled;
617
618 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
619 if (ret)
620 return false;
621
622 return !!(feature_enabled & SMC_DPM_FEATURE);
623 }
624
smu_v13_0_0_dump_pptable(struct smu_context * smu)625 static void smu_v13_0_0_dump_pptable(struct smu_context *smu)
626 {
627 struct smu_table_context *table_context = &smu->smu_table;
628 PPTable_t *pptable = table_context->driver_pptable;
629 SkuTable_t *skutable = &pptable->SkuTable;
630
631 dev_info(smu->adev->dev, "Dumped PPTable:\n");
632
633 dev_info(smu->adev->dev, "Version = 0x%08x\n", skutable->Version);
634 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", skutable->FeaturesToRun[0]);
635 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", skutable->FeaturesToRun[1]);
636 }
637
smu_v13_0_0_system_features_control(struct smu_context * smu,bool en)638 static int smu_v13_0_0_system_features_control(struct smu_context *smu,
639 bool en)
640 {
641 return smu_v13_0_system_features_control(smu, en);
642 }
643
smu_v13_0_get_throttler_status(SmuMetrics_t * metrics)644 static uint32_t smu_v13_0_get_throttler_status(SmuMetrics_t *metrics)
645 {
646 uint32_t throttler_status = 0;
647 int i;
648
649 for (i = 0; i < THROTTLER_COUNT; i++)
650 throttler_status |=
651 (metrics->ThrottlingPercentage[i] ? 1U << i : 0);
652
653 return throttler_status;
654 }
655
656 #define SMU_13_0_0_BUSY_THRESHOLD 15
smu_v13_0_0_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)657 static int smu_v13_0_0_get_smu_metrics_data(struct smu_context *smu,
658 MetricsMember_t member,
659 uint32_t *value)
660 {
661 struct smu_table_context *smu_table = &smu->smu_table;
662 SmuMetrics_t *metrics =
663 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
664 int ret = 0;
665
666 ret = smu_cmn_get_metrics_table(smu,
667 NULL,
668 false);
669 if (ret)
670 return ret;
671
672 switch (member) {
673 case METRICS_CURR_GFXCLK:
674 *value = metrics->CurrClock[PPCLK_GFXCLK];
675 break;
676 case METRICS_CURR_SOCCLK:
677 *value = metrics->CurrClock[PPCLK_SOCCLK];
678 break;
679 case METRICS_CURR_UCLK:
680 *value = metrics->CurrClock[PPCLK_UCLK];
681 break;
682 case METRICS_CURR_VCLK:
683 *value = metrics->CurrClock[PPCLK_VCLK_0];
684 break;
685 case METRICS_CURR_VCLK1:
686 *value = metrics->CurrClock[PPCLK_VCLK_1];
687 break;
688 case METRICS_CURR_DCLK:
689 *value = metrics->CurrClock[PPCLK_DCLK_0];
690 break;
691 case METRICS_CURR_DCLK1:
692 *value = metrics->CurrClock[PPCLK_DCLK_1];
693 break;
694 case METRICS_CURR_FCLK:
695 *value = metrics->CurrClock[PPCLK_FCLK];
696 break;
697 case METRICS_AVERAGE_GFXCLK:
698 if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD)
699 *value = metrics->AverageGfxclkFrequencyPostDs;
700 else
701 *value = metrics->AverageGfxclkFrequencyPreDs;
702 break;
703 case METRICS_AVERAGE_FCLK:
704 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD)
705 *value = metrics->AverageFclkFrequencyPostDs;
706 else
707 *value = metrics->AverageFclkFrequencyPreDs;
708 break;
709 case METRICS_AVERAGE_UCLK:
710 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD)
711 *value = metrics->AverageMemclkFrequencyPostDs;
712 else
713 *value = metrics->AverageMemclkFrequencyPreDs;
714 break;
715 case METRICS_AVERAGE_VCLK:
716 *value = metrics->AverageVclk0Frequency;
717 break;
718 case METRICS_AVERAGE_DCLK:
719 *value = metrics->AverageDclk0Frequency;
720 break;
721 case METRICS_AVERAGE_VCLK1:
722 *value = metrics->AverageVclk1Frequency;
723 break;
724 case METRICS_AVERAGE_DCLK1:
725 *value = metrics->AverageDclk1Frequency;
726 break;
727 case METRICS_AVERAGE_GFXACTIVITY:
728 *value = metrics->AverageGfxActivity;
729 break;
730 case METRICS_AVERAGE_MEMACTIVITY:
731 *value = metrics->AverageUclkActivity;
732 break;
733 case METRICS_AVERAGE_SOCKETPOWER:
734 *value = metrics->AverageSocketPower << 8;
735 break;
736 case METRICS_TEMPERATURE_EDGE:
737 *value = metrics->AvgTemperature[TEMP_EDGE] *
738 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
739 break;
740 case METRICS_TEMPERATURE_HOTSPOT:
741 *value = metrics->AvgTemperature[TEMP_HOTSPOT] *
742 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
743 break;
744 case METRICS_TEMPERATURE_MEM:
745 *value = metrics->AvgTemperature[TEMP_MEM] *
746 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
747 break;
748 case METRICS_TEMPERATURE_VRGFX:
749 *value = metrics->AvgTemperature[TEMP_VR_GFX] *
750 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
751 break;
752 case METRICS_TEMPERATURE_VRSOC:
753 *value = metrics->AvgTemperature[TEMP_VR_SOC] *
754 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
755 break;
756 case METRICS_THROTTLER_STATUS:
757 *value = smu_v13_0_get_throttler_status(metrics);
758 break;
759 case METRICS_CURR_FANSPEED:
760 *value = metrics->AvgFanRpm;
761 break;
762 case METRICS_CURR_FANPWM:
763 *value = metrics->AvgFanPwm;
764 break;
765 case METRICS_VOLTAGE_VDDGFX:
766 *value = metrics->AvgVoltage[SVI_PLANE_GFX];
767 break;
768 case METRICS_PCIE_RATE:
769 *value = metrics->PcieRate;
770 break;
771 case METRICS_PCIE_WIDTH:
772 *value = metrics->PcieWidth;
773 break;
774 default:
775 *value = UINT_MAX;
776 break;
777 }
778
779 return ret;
780 }
781
smu_v13_0_0_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)782 static int smu_v13_0_0_read_sensor(struct smu_context *smu,
783 enum amd_pp_sensors sensor,
784 void *data,
785 uint32_t *size)
786 {
787 struct smu_table_context *table_context = &smu->smu_table;
788 PPTable_t *smc_pptable = table_context->driver_pptable;
789 int ret = 0;
790
791 switch (sensor) {
792 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
793 *(uint16_t *)data = smc_pptable->SkuTable.FanMaximumRpm;
794 *size = 4;
795 break;
796 case AMDGPU_PP_SENSOR_MEM_LOAD:
797 ret = smu_v13_0_0_get_smu_metrics_data(smu,
798 METRICS_AVERAGE_MEMACTIVITY,
799 (uint32_t *)data);
800 *size = 4;
801 break;
802 case AMDGPU_PP_SENSOR_GPU_LOAD:
803 ret = smu_v13_0_0_get_smu_metrics_data(smu,
804 METRICS_AVERAGE_GFXACTIVITY,
805 (uint32_t *)data);
806 *size = 4;
807 break;
808 case AMDGPU_PP_SENSOR_GPU_POWER:
809 ret = smu_v13_0_0_get_smu_metrics_data(smu,
810 METRICS_AVERAGE_SOCKETPOWER,
811 (uint32_t *)data);
812 *size = 4;
813 break;
814 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
815 ret = smu_v13_0_0_get_smu_metrics_data(smu,
816 METRICS_TEMPERATURE_HOTSPOT,
817 (uint32_t *)data);
818 *size = 4;
819 break;
820 case AMDGPU_PP_SENSOR_EDGE_TEMP:
821 ret = smu_v13_0_0_get_smu_metrics_data(smu,
822 METRICS_TEMPERATURE_EDGE,
823 (uint32_t *)data);
824 *size = 4;
825 break;
826 case AMDGPU_PP_SENSOR_MEM_TEMP:
827 ret = smu_v13_0_0_get_smu_metrics_data(smu,
828 METRICS_TEMPERATURE_MEM,
829 (uint32_t *)data);
830 *size = 4;
831 break;
832 case AMDGPU_PP_SENSOR_GFX_MCLK:
833 ret = smu_v13_0_0_get_smu_metrics_data(smu,
834 METRICS_CURR_UCLK,
835 (uint32_t *)data);
836 *(uint32_t *)data *= 100;
837 *size = 4;
838 break;
839 case AMDGPU_PP_SENSOR_GFX_SCLK:
840 ret = smu_v13_0_0_get_smu_metrics_data(smu,
841 METRICS_AVERAGE_GFXCLK,
842 (uint32_t *)data);
843 *(uint32_t *)data *= 100;
844 *size = 4;
845 break;
846 case AMDGPU_PP_SENSOR_VDDGFX:
847 ret = smu_v13_0_0_get_smu_metrics_data(smu,
848 METRICS_VOLTAGE_VDDGFX,
849 (uint32_t *)data);
850 *size = 4;
851 break;
852 default:
853 ret = -EOPNOTSUPP;
854 break;
855 }
856
857 return ret;
858 }
859
smu_v13_0_0_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)860 static int smu_v13_0_0_get_current_clk_freq_by_table(struct smu_context *smu,
861 enum smu_clk_type clk_type,
862 uint32_t *value)
863 {
864 MetricsMember_t member_type;
865 int clk_id = 0;
866
867 clk_id = smu_cmn_to_asic_specific_index(smu,
868 CMN2ASIC_MAPPING_CLK,
869 clk_type);
870 if (clk_id < 0)
871 return -EINVAL;
872
873 switch (clk_id) {
874 case PPCLK_GFXCLK:
875 member_type = METRICS_AVERAGE_GFXCLK;
876 break;
877 case PPCLK_UCLK:
878 member_type = METRICS_CURR_UCLK;
879 break;
880 case PPCLK_FCLK:
881 member_type = METRICS_CURR_FCLK;
882 break;
883 case PPCLK_SOCCLK:
884 member_type = METRICS_CURR_SOCCLK;
885 break;
886 case PPCLK_VCLK_0:
887 member_type = METRICS_AVERAGE_VCLK;
888 break;
889 case PPCLK_DCLK_0:
890 member_type = METRICS_AVERAGE_DCLK;
891 break;
892 case PPCLK_VCLK_1:
893 member_type = METRICS_AVERAGE_VCLK1;
894 break;
895 case PPCLK_DCLK_1:
896 member_type = METRICS_AVERAGE_DCLK1;
897 break;
898 default:
899 return -EINVAL;
900 }
901
902 return smu_v13_0_0_get_smu_metrics_data(smu,
903 member_type,
904 value);
905 }
906
smu_v13_0_0_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)907 static int smu_v13_0_0_print_clk_levels(struct smu_context *smu,
908 enum smu_clk_type clk_type,
909 char *buf)
910 {
911 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
912 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
913 struct smu_13_0_dpm_table *single_dpm_table;
914 struct smu_13_0_pcie_table *pcie_table;
915 const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
916 uint32_t gen_speed, lane_width;
917 int i, curr_freq, size = 0;
918 int ret = 0;
919
920 smu_cmn_get_sysfs_buf(&buf, &size);
921
922 if (amdgpu_ras_intr_triggered()) {
923 size += sysfs_emit_at(buf, size, "unavailable\n");
924 return size;
925 }
926
927 switch (clk_type) {
928 case SMU_SCLK:
929 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
930 break;
931 case SMU_MCLK:
932 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
933 break;
934 case SMU_SOCCLK:
935 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
936 break;
937 case SMU_FCLK:
938 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
939 break;
940 case SMU_VCLK:
941 case SMU_VCLK1:
942 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
943 break;
944 case SMU_DCLK:
945 case SMU_DCLK1:
946 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
947 break;
948 default:
949 break;
950 }
951
952 switch (clk_type) {
953 case SMU_SCLK:
954 case SMU_MCLK:
955 case SMU_SOCCLK:
956 case SMU_FCLK:
957 case SMU_VCLK:
958 case SMU_VCLK1:
959 case SMU_DCLK:
960 case SMU_DCLK1:
961 ret = smu_v13_0_0_get_current_clk_freq_by_table(smu, clk_type, &curr_freq);
962 if (ret) {
963 dev_err(smu->adev->dev, "Failed to get current clock freq!");
964 return ret;
965 }
966
967 if (single_dpm_table->is_fine_grained) {
968 /*
969 * For fine grained dpms, there are only two dpm levels:
970 * - level 0 -> min clock freq
971 * - level 1 -> max clock freq
972 * And the current clock frequency can be any value between them.
973 * So, if the current clock frequency is not at level 0 or level 1,
974 * we will fake it as three dpm levels:
975 * - level 0 -> min clock freq
976 * - level 1 -> current actual clock freq
977 * - level 2 -> max clock freq
978 */
979 if ((single_dpm_table->dpm_levels[0].value != curr_freq) &&
980 (single_dpm_table->dpm_levels[1].value != curr_freq)) {
981 size += sysfs_emit_at(buf, size, "0: %uMhz\n",
982 single_dpm_table->dpm_levels[0].value);
983 size += sysfs_emit_at(buf, size, "1: %uMhz *\n",
984 curr_freq);
985 size += sysfs_emit_at(buf, size, "2: %uMhz\n",
986 single_dpm_table->dpm_levels[1].value);
987 } else {
988 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n",
989 single_dpm_table->dpm_levels[0].value,
990 single_dpm_table->dpm_levels[0].value == curr_freq ? "*" : "");
991 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
992 single_dpm_table->dpm_levels[1].value,
993 single_dpm_table->dpm_levels[1].value == curr_freq ? "*" : "");
994 }
995 } else {
996 for (i = 0; i < single_dpm_table->count; i++)
997 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
998 i, single_dpm_table->dpm_levels[i].value,
999 single_dpm_table->dpm_levels[i].value == curr_freq ? "*" : "");
1000 }
1001 break;
1002 case SMU_PCIE:
1003 ret = smu_v13_0_0_get_smu_metrics_data(smu,
1004 METRICS_PCIE_RATE,
1005 &gen_speed);
1006 if (ret)
1007 return ret;
1008
1009 ret = smu_v13_0_0_get_smu_metrics_data(smu,
1010 METRICS_PCIE_WIDTH,
1011 &lane_width);
1012 if (ret)
1013 return ret;
1014
1015 pcie_table = &(dpm_context->dpm_tables.pcie_table);
1016 for (i = 0; i < pcie_table->num_of_link_levels; i++)
1017 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1018 (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," :
1019 (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," :
1020 (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," :
1021 (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "",
1022 (pcie_table->pcie_lane[i] == 1) ? "x1" :
1023 (pcie_table->pcie_lane[i] == 2) ? "x2" :
1024 (pcie_table->pcie_lane[i] == 3) ? "x4" :
1025 (pcie_table->pcie_lane[i] == 4) ? "x8" :
1026 (pcie_table->pcie_lane[i] == 5) ? "x12" :
1027 (pcie_table->pcie_lane[i] == 6) ? "x16" : "",
1028 pcie_table->clk_freq[i],
1029 ((gen_speed - 1) == pcie_table->pcie_gen[i]) &&
1030 (lane_width == link_width[pcie_table->pcie_lane[i]]) ?
1031 "*" : "");
1032 break;
1033
1034 default:
1035 break;
1036 }
1037
1038 return size;
1039 }
1040
smu_v13_0_0_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1041 static int smu_v13_0_0_force_clk_levels(struct smu_context *smu,
1042 enum smu_clk_type clk_type,
1043 uint32_t mask)
1044 {
1045 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1046 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1047 struct smu_13_0_dpm_table *single_dpm_table;
1048 uint32_t soft_min_level, soft_max_level;
1049 uint32_t min_freq, max_freq;
1050 int ret = 0;
1051
1052 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1053 soft_max_level = mask ? (fls(mask) - 1) : 0;
1054
1055 switch (clk_type) {
1056 case SMU_GFXCLK:
1057 case SMU_SCLK:
1058 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1059 break;
1060 case SMU_MCLK:
1061 case SMU_UCLK:
1062 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1063 break;
1064 case SMU_SOCCLK:
1065 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1066 break;
1067 case SMU_FCLK:
1068 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1069 break;
1070 case SMU_VCLK:
1071 case SMU_VCLK1:
1072 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1073 break;
1074 case SMU_DCLK:
1075 case SMU_DCLK1:
1076 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1077 break;
1078 default:
1079 break;
1080 }
1081
1082 switch (clk_type) {
1083 case SMU_GFXCLK:
1084 case SMU_SCLK:
1085 case SMU_MCLK:
1086 case SMU_UCLK:
1087 case SMU_SOCCLK:
1088 case SMU_FCLK:
1089 case SMU_VCLK:
1090 case SMU_VCLK1:
1091 case SMU_DCLK:
1092 case SMU_DCLK1:
1093 if (single_dpm_table->is_fine_grained) {
1094 /* There is only 2 levels for fine grained DPM */
1095 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1096 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1097 } else {
1098 if ((soft_max_level >= single_dpm_table->count) ||
1099 (soft_min_level >= single_dpm_table->count))
1100 return -EINVAL;
1101 }
1102
1103 min_freq = single_dpm_table->dpm_levels[soft_min_level].value;
1104 max_freq = single_dpm_table->dpm_levels[soft_max_level].value;
1105
1106 ret = smu_v13_0_set_soft_freq_limited_range(smu,
1107 clk_type,
1108 min_freq,
1109 max_freq);
1110 break;
1111 case SMU_DCEFCLK:
1112 case SMU_PCIE:
1113 default:
1114 break;
1115 }
1116
1117 return ret;
1118 }
1119
smu_v13_0_0_update_pcie_parameters(struct smu_context * smu,uint32_t pcie_gen_cap,uint32_t pcie_width_cap)1120 static int smu_v13_0_0_update_pcie_parameters(struct smu_context *smu,
1121 uint32_t pcie_gen_cap,
1122 uint32_t pcie_width_cap)
1123 {
1124 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1125 struct smu_13_0_pcie_table *pcie_table =
1126 &dpm_context->dpm_tables.pcie_table;
1127 uint32_t smu_pcie_arg;
1128 int ret, i;
1129
1130 for (i = 0; i < pcie_table->num_of_link_levels; i++) {
1131 if (pcie_table->pcie_gen[i] > pcie_gen_cap)
1132 pcie_table->pcie_gen[i] = pcie_gen_cap;
1133 if (pcie_table->pcie_lane[i] > pcie_width_cap)
1134 pcie_table->pcie_lane[i] = pcie_width_cap;
1135
1136 smu_pcie_arg = i << 16;
1137 smu_pcie_arg |= pcie_table->pcie_gen[i] << 8;
1138 smu_pcie_arg |= pcie_table->pcie_lane[i];
1139
1140 ret = smu_cmn_send_smc_msg_with_param(smu,
1141 SMU_MSG_OverridePcieParameters,
1142 smu_pcie_arg,
1143 NULL);
1144 if (ret)
1145 return ret;
1146 }
1147
1148 return 0;
1149 }
1150
1151 static const struct smu_temperature_range smu13_thermal_policy[] = {
1152 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
1153 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
1154 };
1155
smu_v13_0_0_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)1156 static int smu_v13_0_0_get_thermal_temperature_range(struct smu_context *smu,
1157 struct smu_temperature_range *range)
1158 {
1159 struct smu_table_context *table_context = &smu->smu_table;
1160 struct smu_13_0_0_powerplay_table *powerplay_table =
1161 table_context->power_play_table;
1162 PPTable_t *pptable = smu->smu_table.driver_pptable;
1163
1164 if (!range)
1165 return -EINVAL;
1166
1167 memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range));
1168
1169 range->max = pptable->SkuTable.TemperatureLimit[TEMP_EDGE] *
1170 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1171 range->edge_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_EDGE] + CTF_OFFSET_EDGE) *
1172 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1173 range->hotspot_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] *
1174 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1175 range->hotspot_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_HOTSPOT] + CTF_OFFSET_HOTSPOT) *
1176 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1177 range->mem_crit_max = pptable->SkuTable.TemperatureLimit[TEMP_MEM] *
1178 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1179 range->mem_emergency_max = (pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
1180 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1181 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1182
1183 return 0;
1184 }
1185
1186 #define MAX(a, b) ((a) > (b) ? (a) : (b))
smu_v13_0_0_get_gpu_metrics(struct smu_context * smu,void ** table)1187 static ssize_t smu_v13_0_0_get_gpu_metrics(struct smu_context *smu,
1188 void **table)
1189 {
1190 struct smu_table_context *smu_table = &smu->smu_table;
1191 struct gpu_metrics_v1_3 *gpu_metrics =
1192 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
1193 SmuMetricsExternal_t metrics_ext;
1194 SmuMetrics_t *metrics = &metrics_ext.SmuMetrics;
1195 int ret = 0;
1196
1197 ret = smu_cmn_get_metrics_table(smu,
1198 &metrics_ext,
1199 true);
1200 if (ret)
1201 return ret;
1202
1203 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
1204
1205 gpu_metrics->temperature_edge = metrics->AvgTemperature[TEMP_EDGE];
1206 gpu_metrics->temperature_hotspot = metrics->AvgTemperature[TEMP_HOTSPOT];
1207 gpu_metrics->temperature_mem = metrics->AvgTemperature[TEMP_MEM];
1208 gpu_metrics->temperature_vrgfx = metrics->AvgTemperature[TEMP_VR_GFX];
1209 gpu_metrics->temperature_vrsoc = metrics->AvgTemperature[TEMP_VR_SOC];
1210 gpu_metrics->temperature_vrmem = MAX(metrics->AvgTemperature[TEMP_VR_MEM0],
1211 metrics->AvgTemperature[TEMP_VR_MEM1]);
1212
1213 gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity;
1214 gpu_metrics->average_umc_activity = metrics->AverageUclkActivity;
1215 gpu_metrics->average_mm_activity = MAX(metrics->Vcn0ActivityPercentage,
1216 metrics->Vcn1ActivityPercentage);
1217
1218 gpu_metrics->average_socket_power = metrics->AverageSocketPower;
1219 gpu_metrics->energy_accumulator = metrics->EnergyAccumulator;
1220
1221 if (metrics->AverageGfxActivity <= SMU_13_0_0_BUSY_THRESHOLD)
1222 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs;
1223 else
1224 gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs;
1225
1226 if (metrics->AverageUclkActivity <= SMU_13_0_0_BUSY_THRESHOLD)
1227 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs;
1228 else
1229 gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs;
1230
1231 gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency;
1232 gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency;
1233 gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency;
1234 gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency;
1235
1236 gpu_metrics->current_gfxclk = metrics->CurrClock[PPCLK_GFXCLK];
1237 gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK];
1238 gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK];
1239 gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0];
1240 gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0];
1241 gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_1];
1242 gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_1];
1243
1244 gpu_metrics->throttle_status =
1245 smu_v13_0_get_throttler_status(metrics);
1246 gpu_metrics->indep_throttle_status =
1247 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
1248 smu_v13_0_0_throttler_map);
1249
1250 gpu_metrics->current_fan_speed = metrics->AvgFanRpm;
1251
1252 gpu_metrics->pcie_link_width = metrics->PcieWidth;
1253 gpu_metrics->pcie_link_speed = metrics->PcieRate;
1254
1255 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1256
1257 gpu_metrics->voltage_gfx = metrics->AvgVoltage[SVI_PLANE_GFX];
1258 gpu_metrics->voltage_soc = metrics->AvgVoltage[SVI_PLANE_SOC];
1259 gpu_metrics->voltage_mem = metrics->AvgVoltage[SVI_PLANE_VMEMP];
1260
1261 *table = (void *)gpu_metrics;
1262
1263 return sizeof(struct gpu_metrics_v1_3);
1264 }
1265
smu_v13_0_0_populate_umd_state_clk(struct smu_context * smu)1266 static int smu_v13_0_0_populate_umd_state_clk(struct smu_context *smu)
1267 {
1268 struct smu_13_0_dpm_context *dpm_context =
1269 smu->smu_dpm.dpm_context;
1270 struct smu_13_0_dpm_table *gfx_table =
1271 &dpm_context->dpm_tables.gfx_table;
1272 struct smu_13_0_dpm_table *mem_table =
1273 &dpm_context->dpm_tables.uclk_table;
1274 struct smu_13_0_dpm_table *soc_table =
1275 &dpm_context->dpm_tables.soc_table;
1276 struct smu_13_0_dpm_table *vclk_table =
1277 &dpm_context->dpm_tables.vclk_table;
1278 struct smu_13_0_dpm_table *dclk_table =
1279 &dpm_context->dpm_tables.dclk_table;
1280 struct smu_13_0_dpm_table *fclk_table =
1281 &dpm_context->dpm_tables.fclk_table;
1282 struct smu_umd_pstate_table *pstate_table =
1283 &smu->pstate_table;
1284
1285 pstate_table->gfxclk_pstate.min = gfx_table->min;
1286 pstate_table->gfxclk_pstate.peak = gfx_table->max;
1287
1288 pstate_table->uclk_pstate.min = mem_table->min;
1289 pstate_table->uclk_pstate.peak = mem_table->max;
1290
1291 pstate_table->socclk_pstate.min = soc_table->min;
1292 pstate_table->socclk_pstate.peak = soc_table->max;
1293
1294 pstate_table->vclk_pstate.min = vclk_table->min;
1295 pstate_table->vclk_pstate.peak = vclk_table->max;
1296
1297 pstate_table->dclk_pstate.min = dclk_table->min;
1298 pstate_table->dclk_pstate.peak = dclk_table->max;
1299
1300 pstate_table->fclk_pstate.min = fclk_table->min;
1301 pstate_table->fclk_pstate.peak = fclk_table->max;
1302
1303 /*
1304 * For now, just use the mininum clock frequency.
1305 * TODO: update them when the real pstate settings available
1306 */
1307 pstate_table->gfxclk_pstate.standard = gfx_table->min;
1308 pstate_table->uclk_pstate.standard = mem_table->min;
1309 pstate_table->socclk_pstate.standard = soc_table->min;
1310 pstate_table->vclk_pstate.standard = vclk_table->min;
1311 pstate_table->dclk_pstate.standard = dclk_table->min;
1312 pstate_table->fclk_pstate.standard = fclk_table->min;
1313
1314 return 0;
1315 }
1316
smu_v13_0_0_get_unique_id(struct smu_context * smu)1317 static void smu_v13_0_0_get_unique_id(struct smu_context *smu)
1318 {
1319 struct smu_table_context *smu_table = &smu->smu_table;
1320 SmuMetrics_t *metrics =
1321 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
1322 struct amdgpu_device *adev = smu->adev;
1323 uint32_t upper32 = 0, lower32 = 0;
1324 int ret;
1325
1326 ret = smu_cmn_get_metrics_table(smu, NULL, false);
1327 if (ret)
1328 goto out;
1329
1330 upper32 = metrics->PublicSerialNumberUpper;
1331 lower32 = metrics->PublicSerialNumberLower;
1332
1333 out:
1334 adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1335 if (adev->serial[0] == '\0')
1336 sprintf(adev->serial, "%016llx", adev->unique_id);
1337 }
1338
smu_v13_0_0_get_fan_speed_pwm(struct smu_context * smu,uint32_t * speed)1339 static int smu_v13_0_0_get_fan_speed_pwm(struct smu_context *smu,
1340 uint32_t *speed)
1341 {
1342 if (!speed)
1343 return -EINVAL;
1344
1345 return smu_v13_0_0_get_smu_metrics_data(smu,
1346 METRICS_CURR_FANPWM,
1347 speed);
1348 }
1349
smu_v13_0_0_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)1350 static int smu_v13_0_0_get_fan_speed_rpm(struct smu_context *smu,
1351 uint32_t *speed)
1352 {
1353 if (!speed)
1354 return -EINVAL;
1355
1356 return smu_v13_0_0_get_smu_metrics_data(smu,
1357 METRICS_CURR_FANSPEED,
1358 speed);
1359 }
1360
smu_v13_0_0_enable_mgpu_fan_boost(struct smu_context * smu)1361 static int smu_v13_0_0_enable_mgpu_fan_boost(struct smu_context *smu)
1362 {
1363 struct smu_table_context *table_context = &smu->smu_table;
1364 PPTable_t *pptable = table_context->driver_pptable;
1365 SkuTable_t *skutable = &pptable->SkuTable;
1366
1367 /*
1368 * Skip the MGpuFanBoost setting for those ASICs
1369 * which do not support it
1370 */
1371 if (skutable->MGpuAcousticLimitRpmThreshold == 0)
1372 return 0;
1373
1374 return smu_cmn_send_smc_msg_with_param(smu,
1375 SMU_MSG_SetMGpuFanBoostLimitRpm,
1376 0,
1377 NULL);
1378 }
1379
smu_v13_0_0_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit)1380 static int smu_v13_0_0_get_power_limit(struct smu_context *smu,
1381 uint32_t *current_power_limit,
1382 uint32_t *default_power_limit,
1383 uint32_t *max_power_limit)
1384 {
1385 struct smu_table_context *table_context = &smu->smu_table;
1386 struct smu_13_0_0_powerplay_table *powerplay_table =
1387 (struct smu_13_0_0_powerplay_table *)table_context->power_play_table;
1388 PPTable_t *pptable = table_context->driver_pptable;
1389 SkuTable_t *skutable = &pptable->SkuTable;
1390 uint32_t power_limit, od_percent;
1391
1392 if (smu_v13_0_get_current_power_limit(smu, &power_limit))
1393 power_limit = smu->adev->pm.ac_power ?
1394 skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] :
1395 skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0];
1396
1397 if (current_power_limit)
1398 *current_power_limit = power_limit;
1399 if (default_power_limit)
1400 *default_power_limit = power_limit;
1401
1402 if (max_power_limit) {
1403 if (smu->od_enabled) {
1404 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_13_0_0_ODSETTING_POWERPERCENTAGE]);
1405
1406 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1407
1408 power_limit *= (100 + od_percent);
1409 power_limit /= 100;
1410 }
1411 *max_power_limit = power_limit;
1412 }
1413
1414 return 0;
1415 }
1416
smu_v13_0_0_get_power_profile_mode(struct smu_context * smu,char * buf)1417 static int smu_v13_0_0_get_power_profile_mode(struct smu_context *smu,
1418 char *buf)
1419 {
1420 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1421 DpmActivityMonitorCoeffInt_t *activity_monitor =
1422 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1423 static const char *title[] = {
1424 "PROFILE_INDEX(NAME)",
1425 "CLOCK_TYPE(NAME)",
1426 "FPS",
1427 "MinActiveFreqType",
1428 "MinActiveFreq",
1429 "BoosterFreqType",
1430 "BoosterFreq",
1431 "PD_Data_limit_c",
1432 "PD_Data_error_coeff",
1433 "PD_Data_error_rate_coeff"};
1434 int16_t workload_type = 0;
1435 uint32_t i, size = 0;
1436 int result = 0;
1437
1438 if (!buf)
1439 return -EINVAL;
1440
1441 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s\n",
1442 title[0], title[1], title[2], title[3], title[4], title[5],
1443 title[6], title[7], title[8], title[9]);
1444
1445 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1446 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1447 workload_type = smu_cmn_to_asic_specific_index(smu,
1448 CMN2ASIC_MAPPING_WORKLOAD,
1449 i);
1450 if (workload_type < 0)
1451 return -EINVAL;
1452
1453 result = smu_cmn_update_table(smu,
1454 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1455 workload_type,
1456 (void *)(&activity_monitor_external),
1457 false);
1458 if (result) {
1459 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1460 return result;
1461 }
1462
1463 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
1464 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1465
1466 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n",
1467 " ",
1468 0,
1469 "GFXCLK",
1470 activity_monitor->Gfx_FPS,
1471 activity_monitor->Gfx_MinActiveFreqType,
1472 activity_monitor->Gfx_MinActiveFreq,
1473 activity_monitor->Gfx_BoosterFreqType,
1474 activity_monitor->Gfx_BoosterFreq,
1475 activity_monitor->Gfx_PD_Data_limit_c,
1476 activity_monitor->Gfx_PD_Data_error_coeff,
1477 activity_monitor->Gfx_PD_Data_error_rate_coeff);
1478
1479 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n",
1480 " ",
1481 1,
1482 "FCLK",
1483 activity_monitor->Fclk_FPS,
1484 activity_monitor->Fclk_MinActiveFreqType,
1485 activity_monitor->Fclk_MinActiveFreq,
1486 activity_monitor->Fclk_BoosterFreqType,
1487 activity_monitor->Fclk_BoosterFreq,
1488 activity_monitor->Fclk_PD_Data_limit_c,
1489 activity_monitor->Fclk_PD_Data_error_coeff,
1490 activity_monitor->Fclk_PD_Data_error_rate_coeff);
1491 }
1492
1493 return size;
1494 }
1495
smu_v13_0_0_set_power_profile_mode(struct smu_context * smu,long * input,uint32_t size)1496 static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu,
1497 long *input,
1498 uint32_t size)
1499 {
1500 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1501 DpmActivityMonitorCoeffInt_t *activity_monitor =
1502 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1503 int workload_type, ret = 0;
1504
1505 smu->power_profile_mode = input[size];
1506
1507 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1508 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1509 return -EINVAL;
1510 }
1511
1512 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1513 ret = smu_cmn_update_table(smu,
1514 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1515 WORKLOAD_PPLIB_CUSTOM_BIT,
1516 (void *)(&activity_monitor_external),
1517 false);
1518 if (ret) {
1519 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1520 return ret;
1521 }
1522
1523 switch (input[0]) {
1524 case 0: /* Gfxclk */
1525 activity_monitor->Gfx_FPS = input[1];
1526 activity_monitor->Gfx_MinActiveFreqType = input[2];
1527 activity_monitor->Gfx_MinActiveFreq = input[3];
1528 activity_monitor->Gfx_BoosterFreqType = input[4];
1529 activity_monitor->Gfx_BoosterFreq = input[5];
1530 activity_monitor->Gfx_PD_Data_limit_c = input[6];
1531 activity_monitor->Gfx_PD_Data_error_coeff = input[7];
1532 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[8];
1533 break;
1534 case 1: /* Fclk */
1535 activity_monitor->Fclk_FPS = input[1];
1536 activity_monitor->Fclk_MinActiveFreqType = input[2];
1537 activity_monitor->Fclk_MinActiveFreq = input[3];
1538 activity_monitor->Fclk_BoosterFreqType = input[4];
1539 activity_monitor->Fclk_BoosterFreq = input[5];
1540 activity_monitor->Fclk_PD_Data_limit_c = input[6];
1541 activity_monitor->Fclk_PD_Data_error_coeff = input[7];
1542 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[8];
1543 break;
1544 }
1545
1546 ret = smu_cmn_update_table(smu,
1547 SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1548 WORKLOAD_PPLIB_CUSTOM_BIT,
1549 (void *)(&activity_monitor_external),
1550 true);
1551 if (ret) {
1552 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1553 return ret;
1554 }
1555 }
1556
1557 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1558 workload_type = smu_cmn_to_asic_specific_index(smu,
1559 CMN2ASIC_MAPPING_WORKLOAD,
1560 smu->power_profile_mode);
1561 if (workload_type < 0)
1562 return -EINVAL;
1563
1564 return smu_cmn_send_smc_msg_with_param(smu,
1565 SMU_MSG_SetWorkloadMask,
1566 1 << workload_type,
1567 NULL);
1568 }
1569
smu_v13_0_0_baco_enter(struct smu_context * smu)1570 static int smu_v13_0_0_baco_enter(struct smu_context *smu)
1571 {
1572 struct smu_baco_context *smu_baco = &smu->smu_baco;
1573 struct amdgpu_device *adev = smu->adev;
1574
1575 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
1576 return smu_v13_0_baco_set_armd3_sequence(smu,
1577 smu_baco->maco_support ? BACO_SEQ_BAMACO : BACO_SEQ_BACO);
1578 else
1579 return smu_v13_0_baco_enter(smu);
1580 }
1581
smu_v13_0_0_baco_exit(struct smu_context * smu)1582 static int smu_v13_0_0_baco_exit(struct smu_context *smu)
1583 {
1584 struct amdgpu_device *adev = smu->adev;
1585
1586 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
1587 /* Wait for PMFW handling for the Dstate change */
1588 usleep_range(10000, 11000);
1589 return smu_v13_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
1590 } else {
1591 return smu_v13_0_baco_exit(smu);
1592 }
1593 }
1594
smu_v13_0_0_is_mode1_reset_supported(struct smu_context * smu)1595 static bool smu_v13_0_0_is_mode1_reset_supported(struct smu_context *smu)
1596 {
1597 struct amdgpu_device *adev = smu->adev;
1598 u32 smu_version;
1599
1600 /* SRIOV does not support SMU mode1 reset */
1601 if (amdgpu_sriov_vf(adev))
1602 return false;
1603
1604 /* PMFW support is available since 78.41 */
1605 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1606 if (smu_version < 0x004e2900)
1607 return false;
1608
1609 return true;
1610 }
1611
smu_v13_0_0_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msg,int num_msgs)1612 static int smu_v13_0_0_i2c_xfer(struct i2c_adapter *i2c_adap,
1613 struct i2c_msg *msg, int num_msgs)
1614 {
1615 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
1616 struct amdgpu_device *adev = smu_i2c->adev;
1617 struct smu_context *smu = adev->powerplay.pp_handle;
1618 struct smu_table_context *smu_table = &smu->smu_table;
1619 struct smu_table *table = &smu_table->driver_table;
1620 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
1621 int i, j, r, c;
1622 u16 dir;
1623
1624 if (!adev->pm.dpm_enabled)
1625 return -EBUSY;
1626
1627 req = kzalloc(sizeof(*req), GFP_KERNEL);
1628 if (!req)
1629 return -ENOMEM;
1630
1631 req->I2CcontrollerPort = smu_i2c->port;
1632 req->I2CSpeed = I2C_SPEED_FAST_400K;
1633 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
1634 dir = msg[0].flags & I2C_M_RD;
1635
1636 for (c = i = 0; i < num_msgs; i++) {
1637 for (j = 0; j < msg[i].len; j++, c++) {
1638 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
1639
1640 if (!(msg[i].flags & I2C_M_RD)) {
1641 /* write */
1642 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
1643 cmd->ReadWriteData = msg[i].buf[j];
1644 }
1645
1646 if ((dir ^ msg[i].flags) & I2C_M_RD) {
1647 /* The direction changes.
1648 */
1649 dir = msg[i].flags & I2C_M_RD;
1650 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
1651 }
1652
1653 req->NumCmds++;
1654
1655 /*
1656 * Insert STOP if we are at the last byte of either last
1657 * message for the transaction or the client explicitly
1658 * requires a STOP at this particular message.
1659 */
1660 if ((j == msg[i].len - 1) &&
1661 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
1662 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
1663 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
1664 }
1665 }
1666 }
1667 mutex_lock(&adev->pm.mutex);
1668 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
1669 mutex_unlock(&adev->pm.mutex);
1670 if (r)
1671 goto fail;
1672
1673 for (c = i = 0; i < num_msgs; i++) {
1674 if (!(msg[i].flags & I2C_M_RD)) {
1675 c += msg[i].len;
1676 continue;
1677 }
1678 for (j = 0; j < msg[i].len; j++, c++) {
1679 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
1680
1681 msg[i].buf[j] = cmd->ReadWriteData;
1682 }
1683 }
1684 r = num_msgs;
1685 fail:
1686 kfree(req);
1687 return r;
1688 }
1689
smu_v13_0_0_i2c_func(struct i2c_adapter * adap)1690 static u32 smu_v13_0_0_i2c_func(struct i2c_adapter *adap)
1691 {
1692 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1693 }
1694
1695 static const struct i2c_algorithm smu_v13_0_0_i2c_algo = {
1696 .master_xfer = smu_v13_0_0_i2c_xfer,
1697 .functionality = smu_v13_0_0_i2c_func,
1698 };
1699
1700 static const struct i2c_adapter_quirks smu_v13_0_0_i2c_control_quirks = {
1701 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
1702 .max_read_len = MAX_SW_I2C_COMMANDS,
1703 .max_write_len = MAX_SW_I2C_COMMANDS,
1704 .max_comb_1st_msg_len = 2,
1705 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
1706 };
1707
smu_v13_0_0_i2c_control_init(struct smu_context * smu)1708 static int smu_v13_0_0_i2c_control_init(struct smu_context *smu)
1709 {
1710 struct amdgpu_device *adev = smu->adev;
1711 int res, i;
1712
1713 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
1714 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
1715 struct i2c_adapter *control = &smu_i2c->adapter;
1716
1717 smu_i2c->adev = adev;
1718 smu_i2c->port = i;
1719 mutex_init(&smu_i2c->mutex);
1720 control->owner = THIS_MODULE;
1721 control->class = I2C_CLASS_SPD;
1722 control->dev.parent = &adev->pdev->dev;
1723 control->algo = &smu_v13_0_0_i2c_algo;
1724 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
1725 control->quirks = &smu_v13_0_0_i2c_control_quirks;
1726 i2c_set_adapdata(control, smu_i2c);
1727
1728 res = i2c_add_adapter(control);
1729 if (res) {
1730 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
1731 goto Out_err;
1732 }
1733 }
1734
1735 /* assign the buses used for the FRU EEPROM and RAS EEPROM */
1736 /* XXX ideally this would be something in a vbios data table */
1737 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
1738 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
1739
1740 return 0;
1741 Out_err:
1742 for ( ; i >= 0; i--) {
1743 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
1744 struct i2c_adapter *control = &smu_i2c->adapter;
1745
1746 i2c_del_adapter(control);
1747 }
1748 return res;
1749 }
1750
smu_v13_0_0_i2c_control_fini(struct smu_context * smu)1751 static void smu_v13_0_0_i2c_control_fini(struct smu_context *smu)
1752 {
1753 struct amdgpu_device *adev = smu->adev;
1754 int i;
1755
1756 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
1757 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
1758 struct i2c_adapter *control = &smu_i2c->adapter;
1759
1760 i2c_del_adapter(control);
1761 }
1762 adev->pm.ras_eeprom_i2c_bus = NULL;
1763 adev->pm.fru_eeprom_i2c_bus = NULL;
1764 }
1765
smu_v13_0_0_set_mp1_state(struct smu_context * smu,enum pp_mp1_state mp1_state)1766 static int smu_v13_0_0_set_mp1_state(struct smu_context *smu,
1767 enum pp_mp1_state mp1_state)
1768 {
1769 int ret;
1770
1771 switch (mp1_state) {
1772 case PP_MP1_STATE_UNLOAD:
1773 ret = smu_cmn_set_mp1_state(smu, mp1_state);
1774 break;
1775 default:
1776 /* Ignore others */
1777 ret = 0;
1778 }
1779
1780 return ret;
1781 }
1782
smu_v13_0_0_set_df_cstate(struct smu_context * smu,enum pp_df_cstate state)1783 static int smu_v13_0_0_set_df_cstate(struct smu_context *smu,
1784 enum pp_df_cstate state)
1785 {
1786 return smu_cmn_send_smc_msg_with_param(smu,
1787 SMU_MSG_DFCstateControl,
1788 state,
1789 NULL);
1790 }
1791
1792 static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
1793 .get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask,
1794 .set_default_dpm_table = smu_v13_0_0_set_default_dpm_table,
1795 .i2c_init = smu_v13_0_0_i2c_control_init,
1796 .i2c_fini = smu_v13_0_0_i2c_control_fini,
1797 .is_dpm_running = smu_v13_0_0_is_dpm_running,
1798 .dump_pptable = smu_v13_0_0_dump_pptable,
1799 .init_microcode = smu_v13_0_init_microcode,
1800 .load_microcode = smu_v13_0_load_microcode,
1801 .fini_microcode = smu_v13_0_fini_microcode,
1802 .init_smc_tables = smu_v13_0_0_init_smc_tables,
1803 .fini_smc_tables = smu_v13_0_fini_smc_tables,
1804 .init_power = smu_v13_0_init_power,
1805 .fini_power = smu_v13_0_fini_power,
1806 .check_fw_status = smu_v13_0_check_fw_status,
1807 .setup_pptable = smu_v13_0_0_setup_pptable,
1808 .check_fw_version = smu_v13_0_check_fw_version,
1809 .write_pptable = smu_cmn_write_pptable,
1810 .set_driver_table_location = smu_v13_0_set_driver_table_location,
1811 .system_features_control = smu_v13_0_0_system_features_control,
1812 .set_allowed_mask = smu_v13_0_set_allowed_mask,
1813 .get_enabled_mask = smu_cmn_get_enabled_mask,
1814 .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable,
1815 .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable,
1816 .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq,
1817 .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
1818 .read_sensor = smu_v13_0_0_read_sensor,
1819 .feature_is_enabled = smu_cmn_feature_is_enabled,
1820 .print_clk_levels = smu_v13_0_0_print_clk_levels,
1821 .force_clk_levels = smu_v13_0_0_force_clk_levels,
1822 .update_pcie_parameters = smu_v13_0_0_update_pcie_parameters,
1823 .get_thermal_temperature_range = smu_v13_0_0_get_thermal_temperature_range,
1824 .register_irq_handler = smu_v13_0_register_irq_handler,
1825 .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
1826 .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
1827 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
1828 .get_gpu_metrics = smu_v13_0_0_get_gpu_metrics,
1829 .set_soft_freq_limited_range = smu_v13_0_set_soft_freq_limited_range,
1830 .init_pptable_microcode = smu_v13_0_init_pptable_microcode,
1831 .populate_umd_state_clk = smu_v13_0_0_populate_umd_state_clk,
1832 .set_performance_level = smu_v13_0_set_performance_level,
1833 .gfx_off_control = smu_v13_0_gfx_off_control,
1834 .get_unique_id = smu_v13_0_0_get_unique_id,
1835 .get_fan_speed_pwm = smu_v13_0_0_get_fan_speed_pwm,
1836 .get_fan_speed_rpm = smu_v13_0_0_get_fan_speed_rpm,
1837 .set_fan_speed_pwm = smu_v13_0_set_fan_speed_pwm,
1838 .set_fan_speed_rpm = smu_v13_0_set_fan_speed_rpm,
1839 .get_fan_control_mode = smu_v13_0_get_fan_control_mode,
1840 .set_fan_control_mode = smu_v13_0_set_fan_control_mode,
1841 .enable_mgpu_fan_boost = smu_v13_0_0_enable_mgpu_fan_boost,
1842 .get_power_limit = smu_v13_0_0_get_power_limit,
1843 .set_power_limit = smu_v13_0_set_power_limit,
1844 .set_power_source = smu_v13_0_set_power_source,
1845 .get_power_profile_mode = smu_v13_0_0_get_power_profile_mode,
1846 .set_power_profile_mode = smu_v13_0_0_set_power_profile_mode,
1847 .run_btc = smu_v13_0_run_btc,
1848 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1849 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
1850 .set_tool_table_location = smu_v13_0_set_tool_table_location,
1851 .deep_sleep_control = smu_v13_0_deep_sleep_control,
1852 .gfx_ulv_control = smu_v13_0_gfx_ulv_control,
1853 .baco_is_support = smu_v13_0_baco_is_support,
1854 .baco_get_state = smu_v13_0_baco_get_state,
1855 .baco_set_state = smu_v13_0_baco_set_state,
1856 .baco_enter = smu_v13_0_0_baco_enter,
1857 .baco_exit = smu_v13_0_0_baco_exit,
1858 .mode1_reset_is_support = smu_v13_0_0_is_mode1_reset_supported,
1859 .mode1_reset = smu_v13_0_mode1_reset,
1860 .set_mp1_state = smu_v13_0_0_set_mp1_state,
1861 .set_df_cstate = smu_v13_0_0_set_df_cstate,
1862 };
1863
smu_v13_0_0_set_ppt_funcs(struct smu_context * smu)1864 void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
1865 {
1866 smu->ppt_funcs = &smu_v13_0_0_ppt_funcs;
1867 smu->message_map = smu_v13_0_0_message_map;
1868 smu->clock_map = smu_v13_0_0_clk_map;
1869 smu->feature_map = smu_v13_0_0_feature_mask_map;
1870 smu->table_map = smu_v13_0_0_table_map;
1871 smu->pwr_src_map = smu_v13_0_0_pwr_src_map;
1872 smu->workload_map = smu_v13_0_0_workload_map;
1873 smu_v13_0_set_smu_mailbox_registers(smu);
1874 }
1875