1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #define SWSMU_CODE_LAYER_L1
24
25 #include <linux/firmware.h>
26 #include <linux/pci.h>
27 #include <linux/reboot.h>
28
29 #include "amdgpu.h"
30 #include "amdgpu_smu.h"
31 #include "smu_internal.h"
32 #include "atom.h"
33 #include "arcturus_ppt.h"
34 #include "navi10_ppt.h"
35 #include "sienna_cichlid_ppt.h"
36 #include "renoir_ppt.h"
37 #include "vangogh_ppt.h"
38 #include "aldebaran_ppt.h"
39 #include "yellow_carp_ppt.h"
40 #include "cyan_skillfish_ppt.h"
41 #include "smu_v13_0_0_ppt.h"
42 #include "smu_v13_0_4_ppt.h"
43 #include "smu_v13_0_5_ppt.h"
44 #include "smu_v13_0_6_ppt.h"
45 #include "smu_v13_0_7_ppt.h"
46 #include "amd_pcie.h"
47
48 /*
49 * DO NOT use these for err/warn/info/debug messages.
50 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
51 * They are more MGPU friendly.
52 */
53 #undef pr_err
54 #undef pr_warn
55 #undef pr_info
56 #undef pr_debug
57
58 static const struct amd_pm_funcs swsmu_pm_funcs;
59 static int smu_force_smuclk_levels(struct smu_context *smu,
60 enum smu_clk_type clk_type,
61 uint32_t mask);
62 static int smu_handle_task(struct smu_context *smu,
63 enum amd_dpm_forced_level level,
64 enum amd_pp_task task_id);
65 static int smu_reset(struct smu_context *smu);
66 static int smu_set_fan_speed_pwm(void *handle, u32 speed);
67 static int smu_set_fan_control_mode(void *handle, u32 value);
68 static int smu_set_power_limit(void *handle, uint32_t limit);
69 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed);
70 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
71 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state);
72
smu_sys_get_pp_feature_mask(void * handle,char * buf)73 static int smu_sys_get_pp_feature_mask(void *handle,
74 char *buf)
75 {
76 struct smu_context *smu = handle;
77
78 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
79 return -EOPNOTSUPP;
80
81 return smu_get_pp_feature_mask(smu, buf);
82 }
83
smu_sys_set_pp_feature_mask(void * handle,uint64_t new_mask)84 static int smu_sys_set_pp_feature_mask(void *handle,
85 uint64_t new_mask)
86 {
87 struct smu_context *smu = handle;
88
89 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
90 return -EOPNOTSUPP;
91
92 return smu_set_pp_feature_mask(smu, new_mask);
93 }
94
smu_set_residency_gfxoff(struct smu_context * smu,bool value)95 int smu_set_residency_gfxoff(struct smu_context *smu, bool value)
96 {
97 if (!smu->ppt_funcs->set_gfx_off_residency)
98 return -EINVAL;
99
100 return smu_set_gfx_off_residency(smu, value);
101 }
102
smu_get_residency_gfxoff(struct smu_context * smu,u32 * value)103 int smu_get_residency_gfxoff(struct smu_context *smu, u32 *value)
104 {
105 if (!smu->ppt_funcs->get_gfx_off_residency)
106 return -EINVAL;
107
108 return smu_get_gfx_off_residency(smu, value);
109 }
110
smu_get_entrycount_gfxoff(struct smu_context * smu,u64 * value)111 int smu_get_entrycount_gfxoff(struct smu_context *smu, u64 *value)
112 {
113 if (!smu->ppt_funcs->get_gfx_off_entrycount)
114 return -EINVAL;
115
116 return smu_get_gfx_off_entrycount(smu, value);
117 }
118
smu_get_status_gfxoff(struct smu_context * smu,uint32_t * value)119 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value)
120 {
121 if (!smu->ppt_funcs->get_gfx_off_status)
122 return -EINVAL;
123
124 *value = smu_get_gfx_off_status(smu);
125
126 return 0;
127 }
128
smu_set_soft_freq_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)129 int smu_set_soft_freq_range(struct smu_context *smu,
130 enum smu_clk_type clk_type,
131 uint32_t min,
132 uint32_t max)
133 {
134 int ret = 0;
135
136 if (smu->ppt_funcs->set_soft_freq_limited_range)
137 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu,
138 clk_type,
139 min,
140 max);
141
142 return ret;
143 }
144
smu_get_dpm_freq_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)145 int smu_get_dpm_freq_range(struct smu_context *smu,
146 enum smu_clk_type clk_type,
147 uint32_t *min,
148 uint32_t *max)
149 {
150 int ret = -ENOTSUPP;
151
152 if (!min && !max)
153 return -EINVAL;
154
155 if (smu->ppt_funcs->get_dpm_ultimate_freq)
156 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu,
157 clk_type,
158 min,
159 max);
160
161 return ret;
162 }
163
smu_set_gfx_power_up_by_imu(struct smu_context * smu)164 int smu_set_gfx_power_up_by_imu(struct smu_context *smu)
165 {
166 int ret = 0;
167 struct amdgpu_device *adev = smu->adev;
168
169 if (smu->ppt_funcs->set_gfx_power_up_by_imu) {
170 ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
171 if (ret)
172 dev_err(adev->dev, "Failed to enable gfx imu!\n");
173 }
174 return ret;
175 }
176
smu_get_mclk(void * handle,bool low)177 static u32 smu_get_mclk(void *handle, bool low)
178 {
179 struct smu_context *smu = handle;
180 uint32_t clk_freq;
181 int ret = 0;
182
183 ret = smu_get_dpm_freq_range(smu, SMU_UCLK,
184 low ? &clk_freq : NULL,
185 !low ? &clk_freq : NULL);
186 if (ret)
187 return 0;
188 return clk_freq * 100;
189 }
190
smu_get_sclk(void * handle,bool low)191 static u32 smu_get_sclk(void *handle, bool low)
192 {
193 struct smu_context *smu = handle;
194 uint32_t clk_freq;
195 int ret = 0;
196
197 ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK,
198 low ? &clk_freq : NULL,
199 !low ? &clk_freq : NULL);
200 if (ret)
201 return 0;
202 return clk_freq * 100;
203 }
204
smu_set_gfx_imu_enable(struct smu_context * smu)205 static int smu_set_gfx_imu_enable(struct smu_context *smu)
206 {
207 struct amdgpu_device *adev = smu->adev;
208
209 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
210 return 0;
211
212 if (amdgpu_in_reset(smu->adev) || adev->in_s0ix)
213 return 0;
214
215 return smu_set_gfx_power_up_by_imu(smu);
216 }
217
smu_dpm_set_vcn_enable(struct smu_context * smu,bool enable)218 static int smu_dpm_set_vcn_enable(struct smu_context *smu,
219 bool enable)
220 {
221 struct smu_power_context *smu_power = &smu->smu_power;
222 struct smu_power_gate *power_gate = &smu_power->power_gate;
223 int ret = 0;
224
225 if (!smu->ppt_funcs->dpm_set_vcn_enable)
226 return 0;
227
228 if (atomic_read(&power_gate->vcn_gated) ^ enable)
229 return 0;
230
231 ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
232 if (!ret)
233 atomic_set(&power_gate->vcn_gated, !enable);
234
235 return ret;
236 }
237
smu_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)238 static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
239 bool enable)
240 {
241 struct smu_power_context *smu_power = &smu->smu_power;
242 struct smu_power_gate *power_gate = &smu_power->power_gate;
243 int ret = 0;
244
245 if (!smu->ppt_funcs->dpm_set_jpeg_enable)
246 return 0;
247
248 if (atomic_read(&power_gate->jpeg_gated) ^ enable)
249 return 0;
250
251 ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
252 if (!ret)
253 atomic_set(&power_gate->jpeg_gated, !enable);
254
255 return ret;
256 }
257
258 /**
259 * smu_dpm_set_power_gate - power gate/ungate the specific IP block
260 *
261 * @handle: smu_context pointer
262 * @block_type: the IP block to power gate/ungate
263 * @gate: to power gate if true, ungate otherwise
264 *
265 * This API uses no smu->mutex lock protection due to:
266 * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
267 * This is guarded to be race condition free by the caller.
268 * 2. Or get called on user setting request of power_dpm_force_performance_level.
269 * Under this case, the smu->mutex lock protection is already enforced on
270 * the parent API smu_force_performance_level of the call path.
271 */
smu_dpm_set_power_gate(void * handle,uint32_t block_type,bool gate)272 static int smu_dpm_set_power_gate(void *handle,
273 uint32_t block_type,
274 bool gate)
275 {
276 struct smu_context *smu = handle;
277 int ret = 0;
278
279 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) {
280 dev_WARN(smu->adev->dev,
281 "SMU uninitialized but power %s requested for %u!\n",
282 gate ? "gate" : "ungate", block_type);
283 return -EOPNOTSUPP;
284 }
285
286 switch (block_type) {
287 /*
288 * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
289 * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
290 */
291 case AMD_IP_BLOCK_TYPE_UVD:
292 case AMD_IP_BLOCK_TYPE_VCN:
293 ret = smu_dpm_set_vcn_enable(smu, !gate);
294 if (ret)
295 dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
296 gate ? "gate" : "ungate");
297 break;
298 case AMD_IP_BLOCK_TYPE_GFX:
299 ret = smu_gfx_off_control(smu, gate);
300 if (ret)
301 dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
302 gate ? "enable" : "disable");
303 break;
304 case AMD_IP_BLOCK_TYPE_SDMA:
305 ret = smu_powergate_sdma(smu, gate);
306 if (ret)
307 dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
308 gate ? "gate" : "ungate");
309 break;
310 case AMD_IP_BLOCK_TYPE_JPEG:
311 ret = smu_dpm_set_jpeg_enable(smu, !gate);
312 if (ret)
313 dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
314 gate ? "gate" : "ungate");
315 break;
316 default:
317 dev_err(smu->adev->dev, "Unsupported block type!\n");
318 return -EINVAL;
319 }
320
321 return ret;
322 }
323
324 /**
325 * smu_set_user_clk_dependencies - set user profile clock dependencies
326 *
327 * @smu: smu_context pointer
328 * @clk: enum smu_clk_type type
329 *
330 * Enable/Disable the clock dependency for the @clk type.
331 */
smu_set_user_clk_dependencies(struct smu_context * smu,enum smu_clk_type clk)332 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk)
333 {
334 if (smu->adev->in_suspend)
335 return;
336
337 if (clk == SMU_MCLK) {
338 smu->user_dpm_profile.clk_dependency = 0;
339 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK);
340 } else if (clk == SMU_FCLK) {
341 /* MCLK takes precedence over FCLK */
342 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
343 return;
344
345 smu->user_dpm_profile.clk_dependency = 0;
346 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK);
347 } else if (clk == SMU_SOCCLK) {
348 /* MCLK takes precedence over SOCCLK */
349 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
350 return;
351
352 smu->user_dpm_profile.clk_dependency = 0;
353 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK);
354 } else
355 /* Add clk dependencies here, if any */
356 return;
357 }
358
359 /**
360 * smu_restore_dpm_user_profile - reinstate user dpm profile
361 *
362 * @smu: smu_context pointer
363 *
364 * Restore the saved user power configurations include power limit,
365 * clock frequencies, fan control mode and fan speed.
366 */
smu_restore_dpm_user_profile(struct smu_context * smu)367 static void smu_restore_dpm_user_profile(struct smu_context *smu)
368 {
369 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
370 int ret = 0;
371
372 if (!smu->adev->in_suspend)
373 return;
374
375 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
376 return;
377
378 /* Enable restore flag */
379 smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE;
380
381 /* set the user dpm power limit */
382 if (smu->user_dpm_profile.power_limit) {
383 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit);
384 if (ret)
385 dev_err(smu->adev->dev, "Failed to set power limit value\n");
386 }
387
388 /* set the user dpm clock configurations */
389 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
390 enum smu_clk_type clk_type;
391
392 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) {
393 /*
394 * Iterate over smu clk type and force the saved user clk
395 * configs, skip if clock dependency is enabled
396 */
397 if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) &&
398 smu->user_dpm_profile.clk_mask[clk_type]) {
399 ret = smu_force_smuclk_levels(smu, clk_type,
400 smu->user_dpm_profile.clk_mask[clk_type]);
401 if (ret)
402 dev_err(smu->adev->dev,
403 "Failed to set clock type = %d\n", clk_type);
404 }
405 }
406 }
407
408 /* set the user dpm fan configurations */
409 if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL ||
410 smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) {
411 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode);
412 if (ret != -EOPNOTSUPP) {
413 smu->user_dpm_profile.fan_speed_pwm = 0;
414 smu->user_dpm_profile.fan_speed_rpm = 0;
415 smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO;
416 dev_err(smu->adev->dev, "Failed to set manual fan control mode\n");
417 }
418
419 if (smu->user_dpm_profile.fan_speed_pwm) {
420 ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm);
421 if (ret != -EOPNOTSUPP)
422 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n");
423 }
424
425 if (smu->user_dpm_profile.fan_speed_rpm) {
426 ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm);
427 if (ret != -EOPNOTSUPP)
428 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n");
429 }
430 }
431
432 /* Restore user customized OD settings */
433 if (smu->user_dpm_profile.user_od) {
434 if (smu->ppt_funcs->restore_user_od_settings) {
435 ret = smu->ppt_funcs->restore_user_od_settings(smu);
436 if (ret)
437 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n");
438 }
439 }
440
441 /* Disable restore flag */
442 smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE;
443 }
444
smu_get_power_num_states(void * handle,struct pp_states_info * state_info)445 static int smu_get_power_num_states(void *handle,
446 struct pp_states_info *state_info)
447 {
448 if (!state_info)
449 return -EINVAL;
450
451 /* not support power state */
452 memset(state_info, 0, sizeof(struct pp_states_info));
453 state_info->nums = 1;
454 state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
455
456 return 0;
457 }
458
is_support_sw_smu(struct amdgpu_device * adev)459 bool is_support_sw_smu(struct amdgpu_device *adev)
460 {
461 /* vega20 is 11.0.2, but it's supported via the powerplay code */
462 if (adev->asic_type == CHIP_VEGA20)
463 return false;
464
465 if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0))
466 return true;
467
468 return false;
469 }
470
is_support_cclk_dpm(struct amdgpu_device * adev)471 bool is_support_cclk_dpm(struct amdgpu_device *adev)
472 {
473 struct smu_context *smu = adev->powerplay.pp_handle;
474
475 if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT))
476 return false;
477
478 return true;
479 }
480
481
smu_sys_get_pp_table(void * handle,char ** table)482 static int smu_sys_get_pp_table(void *handle,
483 char **table)
484 {
485 struct smu_context *smu = handle;
486 struct smu_table_context *smu_table = &smu->smu_table;
487
488 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
489 return -EOPNOTSUPP;
490
491 if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
492 return -EINVAL;
493
494 if (smu_table->hardcode_pptable)
495 *table = smu_table->hardcode_pptable;
496 else
497 *table = smu_table->power_play_table;
498
499 return smu_table->power_play_table_size;
500 }
501
smu_sys_set_pp_table(void * handle,const char * buf,size_t size)502 static int smu_sys_set_pp_table(void *handle,
503 const char *buf,
504 size_t size)
505 {
506 struct smu_context *smu = handle;
507 struct smu_table_context *smu_table = &smu->smu_table;
508 ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
509 int ret = 0;
510
511 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
512 return -EOPNOTSUPP;
513
514 if (header->usStructureSize != size) {
515 dev_err(smu->adev->dev, "pp table size not matched !\n");
516 return -EIO;
517 }
518
519 if (!smu_table->hardcode_pptable) {
520 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
521 if (!smu_table->hardcode_pptable)
522 return -ENOMEM;
523 }
524
525 memcpy(smu_table->hardcode_pptable, buf, size);
526 smu_table->power_play_table = smu_table->hardcode_pptable;
527 smu_table->power_play_table_size = size;
528
529 /*
530 * Special hw_fini action(for Navi1x, the DPMs disablement will be
531 * skipped) may be needed for custom pptable uploading.
532 */
533 smu->uploading_custom_pp_table = true;
534
535 ret = smu_reset(smu);
536 if (ret)
537 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret);
538
539 smu->uploading_custom_pp_table = false;
540
541 return ret;
542 }
543
smu_get_driver_allowed_feature_mask(struct smu_context * smu)544 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
545 {
546 struct smu_feature *feature = &smu->smu_feature;
547 uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
548 int ret = 0;
549
550 /*
551 * With SCPM enabled, the allowed featuremasks setting(via
552 * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted.
553 * That means there is no way to let PMFW knows the settings below.
554 * Thus, we just assume all the features are allowed under
555 * such scenario.
556 */
557 if (smu->adev->scpm_enabled) {
558 bitmap_fill(feature->allowed, SMU_FEATURE_MAX);
559 return 0;
560 }
561
562 bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
563
564 ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
565 SMU_FEATURE_MAX/32);
566 if (ret)
567 return ret;
568
569 bitmap_or(feature->allowed, feature->allowed,
570 (unsigned long *)allowed_feature_mask,
571 feature->feature_num);
572
573 return ret;
574 }
575
smu_set_funcs(struct amdgpu_device * adev)576 static int smu_set_funcs(struct amdgpu_device *adev)
577 {
578 struct smu_context *smu = adev->powerplay.pp_handle;
579
580 if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
581 smu->od_enabled = true;
582
583 switch (adev->ip_versions[MP1_HWIP][0]) {
584 case IP_VERSION(11, 0, 0):
585 case IP_VERSION(11, 0, 5):
586 case IP_VERSION(11, 0, 9):
587 navi10_set_ppt_funcs(smu);
588 break;
589 case IP_VERSION(11, 0, 7):
590 case IP_VERSION(11, 0, 11):
591 case IP_VERSION(11, 0, 12):
592 case IP_VERSION(11, 0, 13):
593 sienna_cichlid_set_ppt_funcs(smu);
594 break;
595 case IP_VERSION(12, 0, 0):
596 case IP_VERSION(12, 0, 1):
597 renoir_set_ppt_funcs(smu);
598 break;
599 case IP_VERSION(11, 5, 0):
600 vangogh_set_ppt_funcs(smu);
601 break;
602 case IP_VERSION(13, 0, 1):
603 case IP_VERSION(13, 0, 3):
604 case IP_VERSION(13, 0, 8):
605 yellow_carp_set_ppt_funcs(smu);
606 break;
607 case IP_VERSION(13, 0, 4):
608 case IP_VERSION(13, 0, 11):
609 smu_v13_0_4_set_ppt_funcs(smu);
610 break;
611 case IP_VERSION(13, 0, 5):
612 smu_v13_0_5_set_ppt_funcs(smu);
613 break;
614 case IP_VERSION(11, 0, 8):
615 cyan_skillfish_set_ppt_funcs(smu);
616 break;
617 case IP_VERSION(11, 0, 2):
618 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
619 arcturus_set_ppt_funcs(smu);
620 /* OD is not supported on Arcturus */
621 smu->od_enabled = false;
622 break;
623 case IP_VERSION(13, 0, 2):
624 aldebaran_set_ppt_funcs(smu);
625 /* Enable pp_od_clk_voltage node */
626 smu->od_enabled = true;
627 break;
628 case IP_VERSION(13, 0, 0):
629 case IP_VERSION(13, 0, 10):
630 smu_v13_0_0_set_ppt_funcs(smu);
631 break;
632 case IP_VERSION(13, 0, 6):
633 smu_v13_0_6_set_ppt_funcs(smu);
634 /* Enable pp_od_clk_voltage node */
635 smu->od_enabled = true;
636 break;
637 case IP_VERSION(13, 0, 7):
638 smu_v13_0_7_set_ppt_funcs(smu);
639 break;
640 default:
641 return -EINVAL;
642 }
643
644 return 0;
645 }
646
smu_early_init(void * handle)647 static int smu_early_init(void *handle)
648 {
649 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
650 struct smu_context *smu;
651 int r;
652
653 smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL);
654 if (!smu)
655 return -ENOMEM;
656
657 smu->adev = adev;
658 smu->pm_enabled = !!amdgpu_dpm;
659 smu->is_apu = false;
660 smu->smu_baco.state = SMU_BACO_STATE_EXIT;
661 smu->smu_baco.platform_support = false;
662 smu->user_dpm_profile.fan_mode = -1;
663
664 mutex_init(&smu->message_lock);
665
666 adev->powerplay.pp_handle = smu;
667 adev->powerplay.pp_funcs = &swsmu_pm_funcs;
668
669 r = smu_set_funcs(adev);
670 if (r)
671 return r;
672 return smu_init_microcode(smu);
673 }
674
smu_set_default_dpm_table(struct smu_context * smu)675 static int smu_set_default_dpm_table(struct smu_context *smu)
676 {
677 struct smu_power_context *smu_power = &smu->smu_power;
678 struct smu_power_gate *power_gate = &smu_power->power_gate;
679 int vcn_gate, jpeg_gate;
680 int ret = 0;
681
682 if (!smu->ppt_funcs->set_default_dpm_table)
683 return 0;
684
685 vcn_gate = atomic_read(&power_gate->vcn_gated);
686 jpeg_gate = atomic_read(&power_gate->jpeg_gated);
687
688 ret = smu_dpm_set_vcn_enable(smu, true);
689 if (ret)
690 return ret;
691
692 ret = smu_dpm_set_jpeg_enable(smu, true);
693 if (ret)
694 goto err_out;
695
696 ret = smu->ppt_funcs->set_default_dpm_table(smu);
697 if (ret)
698 dev_err(smu->adev->dev,
699 "Failed to setup default dpm clock tables!\n");
700
701 smu_dpm_set_jpeg_enable(smu, !jpeg_gate);
702 err_out:
703 smu_dpm_set_vcn_enable(smu, !vcn_gate);
704 return ret;
705 }
706
smu_apply_default_config_table_settings(struct smu_context * smu)707 static int smu_apply_default_config_table_settings(struct smu_context *smu)
708 {
709 struct amdgpu_device *adev = smu->adev;
710 int ret = 0;
711
712 ret = smu_get_default_config_table_settings(smu,
713 &adev->pm.config_table);
714 if (ret)
715 return ret;
716
717 return smu_set_config_table(smu, &adev->pm.config_table);
718 }
719
smu_late_init(void * handle)720 static int smu_late_init(void *handle)
721 {
722 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
723 struct smu_context *smu = adev->powerplay.pp_handle;
724 int ret = 0;
725
726 smu_set_fine_grain_gfx_freq_parameters(smu);
727
728 if (!smu->pm_enabled)
729 return 0;
730
731 ret = smu_post_init(smu);
732 if (ret) {
733 dev_err(adev->dev, "Failed to post smu init!\n");
734 return ret;
735 }
736
737 /*
738 * Explicitly notify PMFW the power mode the system in. Since
739 * the PMFW may boot the ASIC with a different mode.
740 * For those supporting ACDC switch via gpio, PMFW will
741 * handle the switch automatically. Driver involvement
742 * is unnecessary.
743 */
744 if (!smu->dc_controlled_by_gpio) {
745 ret = smu_set_power_source(smu,
746 adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
747 SMU_POWER_SOURCE_DC);
748 if (ret) {
749 dev_err(adev->dev, "Failed to switch to %s mode!\n",
750 adev->pm.ac_power ? "AC" : "DC");
751 return ret;
752 }
753 }
754
755 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) ||
756 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3)))
757 return 0;
758
759 if (!amdgpu_sriov_vf(adev) || smu->od_enabled) {
760 ret = smu_set_default_od_settings(smu);
761 if (ret) {
762 dev_err(adev->dev, "Failed to setup default OD settings!\n");
763 return ret;
764 }
765 }
766
767 ret = smu_populate_umd_state_clk(smu);
768 if (ret) {
769 dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
770 return ret;
771 }
772
773 ret = smu_get_asic_power_limits(smu,
774 &smu->current_power_limit,
775 &smu->default_power_limit,
776 &smu->max_power_limit);
777 if (ret) {
778 dev_err(adev->dev, "Failed to get asic power limits!\n");
779 return ret;
780 }
781
782 if (!amdgpu_sriov_vf(adev))
783 smu_get_unique_id(smu);
784
785 smu_get_fan_parameters(smu);
786
787 smu_handle_task(smu,
788 smu->smu_dpm.dpm_level,
789 AMD_PP_TASK_COMPLETE_INIT);
790
791 ret = smu_apply_default_config_table_settings(smu);
792 if (ret && (ret != -EOPNOTSUPP)) {
793 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n");
794 return ret;
795 }
796
797 smu_restore_dpm_user_profile(smu);
798
799 return 0;
800 }
801
smu_init_fb_allocations(struct smu_context * smu)802 static int smu_init_fb_allocations(struct smu_context *smu)
803 {
804 struct amdgpu_device *adev = smu->adev;
805 struct smu_table_context *smu_table = &smu->smu_table;
806 struct smu_table *tables = smu_table->tables;
807 struct smu_table *driver_table = &(smu_table->driver_table);
808 uint32_t max_table_size = 0;
809 int ret, i;
810
811 /* VRAM allocation for tool table */
812 if (tables[SMU_TABLE_PMSTATUSLOG].size) {
813 ret = amdgpu_bo_create_kernel(adev,
814 tables[SMU_TABLE_PMSTATUSLOG].size,
815 tables[SMU_TABLE_PMSTATUSLOG].align,
816 tables[SMU_TABLE_PMSTATUSLOG].domain,
817 &tables[SMU_TABLE_PMSTATUSLOG].bo,
818 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
819 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
820 if (ret) {
821 dev_err(adev->dev, "VRAM allocation for tool table failed!\n");
822 return ret;
823 }
824 }
825
826 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT;
827 /* VRAM allocation for driver table */
828 for (i = 0; i < SMU_TABLE_COUNT; i++) {
829 if (tables[i].size == 0)
830 continue;
831
832 /* If one of the tables has VRAM domain restriction, keep it in
833 * VRAM
834 */
835 if ((tables[i].domain &
836 (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) ==
837 AMDGPU_GEM_DOMAIN_VRAM)
838 driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
839
840 if (i == SMU_TABLE_PMSTATUSLOG)
841 continue;
842
843 if (max_table_size < tables[i].size)
844 max_table_size = tables[i].size;
845 }
846
847 driver_table->size = max_table_size;
848 driver_table->align = PAGE_SIZE;
849
850 ret = amdgpu_bo_create_kernel(adev,
851 driver_table->size,
852 driver_table->align,
853 driver_table->domain,
854 &driver_table->bo,
855 &driver_table->mc_address,
856 &driver_table->cpu_addr);
857 if (ret) {
858 dev_err(adev->dev, "VRAM allocation for driver table failed!\n");
859 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
860 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
861 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
862 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
863 }
864
865 return ret;
866 }
867
smu_fini_fb_allocations(struct smu_context * smu)868 static int smu_fini_fb_allocations(struct smu_context *smu)
869 {
870 struct smu_table_context *smu_table = &smu->smu_table;
871 struct smu_table *tables = smu_table->tables;
872 struct smu_table *driver_table = &(smu_table->driver_table);
873
874 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
875 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
876 &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
877 &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
878
879 amdgpu_bo_free_kernel(&driver_table->bo,
880 &driver_table->mc_address,
881 &driver_table->cpu_addr);
882
883 return 0;
884 }
885
886 /**
887 * smu_alloc_memory_pool - allocate memory pool in the system memory
888 *
889 * @smu: amdgpu_device pointer
890 *
891 * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
892 * and DramLogSetDramAddr can notify it changed.
893 *
894 * Returns 0 on success, error on failure.
895 */
smu_alloc_memory_pool(struct smu_context * smu)896 static int smu_alloc_memory_pool(struct smu_context *smu)
897 {
898 struct amdgpu_device *adev = smu->adev;
899 struct smu_table_context *smu_table = &smu->smu_table;
900 struct smu_table *memory_pool = &smu_table->memory_pool;
901 uint64_t pool_size = smu->pool_size;
902 int ret = 0;
903
904 if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
905 return ret;
906
907 memory_pool->size = pool_size;
908 memory_pool->align = PAGE_SIZE;
909 memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
910
911 switch (pool_size) {
912 case SMU_MEMORY_POOL_SIZE_256_MB:
913 case SMU_MEMORY_POOL_SIZE_512_MB:
914 case SMU_MEMORY_POOL_SIZE_1_GB:
915 case SMU_MEMORY_POOL_SIZE_2_GB:
916 ret = amdgpu_bo_create_kernel(adev,
917 memory_pool->size,
918 memory_pool->align,
919 memory_pool->domain,
920 &memory_pool->bo,
921 &memory_pool->mc_address,
922 &memory_pool->cpu_addr);
923 if (ret)
924 dev_err(adev->dev, "VRAM allocation for dramlog failed!\n");
925 break;
926 default:
927 break;
928 }
929
930 return ret;
931 }
932
smu_free_memory_pool(struct smu_context * smu)933 static int smu_free_memory_pool(struct smu_context *smu)
934 {
935 struct smu_table_context *smu_table = &smu->smu_table;
936 struct smu_table *memory_pool = &smu_table->memory_pool;
937
938 if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
939 return 0;
940
941 amdgpu_bo_free_kernel(&memory_pool->bo,
942 &memory_pool->mc_address,
943 &memory_pool->cpu_addr);
944
945 memset(memory_pool, 0, sizeof(struct smu_table));
946
947 return 0;
948 }
949
smu_alloc_dummy_read_table(struct smu_context * smu)950 static int smu_alloc_dummy_read_table(struct smu_context *smu)
951 {
952 struct smu_table_context *smu_table = &smu->smu_table;
953 struct smu_table *dummy_read_1_table =
954 &smu_table->dummy_read_1_table;
955 struct amdgpu_device *adev = smu->adev;
956 int ret = 0;
957
958 if (!dummy_read_1_table->size)
959 return 0;
960
961 ret = amdgpu_bo_create_kernel(adev,
962 dummy_read_1_table->size,
963 dummy_read_1_table->align,
964 dummy_read_1_table->domain,
965 &dummy_read_1_table->bo,
966 &dummy_read_1_table->mc_address,
967 &dummy_read_1_table->cpu_addr);
968 if (ret)
969 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n");
970
971 return ret;
972 }
973
smu_free_dummy_read_table(struct smu_context * smu)974 static void smu_free_dummy_read_table(struct smu_context *smu)
975 {
976 struct smu_table_context *smu_table = &smu->smu_table;
977 struct smu_table *dummy_read_1_table =
978 &smu_table->dummy_read_1_table;
979
980
981 amdgpu_bo_free_kernel(&dummy_read_1_table->bo,
982 &dummy_read_1_table->mc_address,
983 &dummy_read_1_table->cpu_addr);
984
985 memset(dummy_read_1_table, 0, sizeof(struct smu_table));
986 }
987
smu_smc_table_sw_init(struct smu_context * smu)988 static int smu_smc_table_sw_init(struct smu_context *smu)
989 {
990 int ret;
991
992 /**
993 * Create smu_table structure, and init smc tables such as
994 * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
995 */
996 ret = smu_init_smc_tables(smu);
997 if (ret) {
998 dev_err(smu->adev->dev, "Failed to init smc tables!\n");
999 return ret;
1000 }
1001
1002 /**
1003 * Create smu_power_context structure, and allocate smu_dpm_context and
1004 * context size to fill the smu_power_context data.
1005 */
1006 ret = smu_init_power(smu);
1007 if (ret) {
1008 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n");
1009 return ret;
1010 }
1011
1012 /*
1013 * allocate vram bos to store smc table contents.
1014 */
1015 ret = smu_init_fb_allocations(smu);
1016 if (ret)
1017 return ret;
1018
1019 ret = smu_alloc_memory_pool(smu);
1020 if (ret)
1021 return ret;
1022
1023 ret = smu_alloc_dummy_read_table(smu);
1024 if (ret)
1025 return ret;
1026
1027 ret = smu_i2c_init(smu);
1028 if (ret)
1029 return ret;
1030
1031 return 0;
1032 }
1033
smu_smc_table_sw_fini(struct smu_context * smu)1034 static int smu_smc_table_sw_fini(struct smu_context *smu)
1035 {
1036 int ret;
1037
1038 smu_i2c_fini(smu);
1039
1040 smu_free_dummy_read_table(smu);
1041
1042 ret = smu_free_memory_pool(smu);
1043 if (ret)
1044 return ret;
1045
1046 ret = smu_fini_fb_allocations(smu);
1047 if (ret)
1048 return ret;
1049
1050 ret = smu_fini_power(smu);
1051 if (ret) {
1052 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n");
1053 return ret;
1054 }
1055
1056 ret = smu_fini_smc_tables(smu);
1057 if (ret) {
1058 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n");
1059 return ret;
1060 }
1061
1062 return 0;
1063 }
1064
smu_throttling_logging_work_fn(struct work_struct * work)1065 static void smu_throttling_logging_work_fn(struct work_struct *work)
1066 {
1067 struct smu_context *smu = container_of(work, struct smu_context,
1068 throttling_logging_work);
1069
1070 smu_log_thermal_throttling(smu);
1071 }
1072
smu_interrupt_work_fn(struct work_struct * work)1073 static void smu_interrupt_work_fn(struct work_struct *work)
1074 {
1075 struct smu_context *smu = container_of(work, struct smu_context,
1076 interrupt_work);
1077
1078 if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work)
1079 smu->ppt_funcs->interrupt_work(smu);
1080 }
1081
smu_swctf_delayed_work_handler(struct work_struct * work)1082 static void smu_swctf_delayed_work_handler(struct work_struct *work)
1083 {
1084 struct smu_context *smu =
1085 container_of(work, struct smu_context, swctf_delayed_work.work);
1086 struct smu_temperature_range *range =
1087 &smu->thermal_range;
1088 struct amdgpu_device *adev = smu->adev;
1089 uint32_t hotspot_tmp, size;
1090
1091 /*
1092 * If the hotspot temperature is confirmed as below SW CTF setting point
1093 * after the delay enforced, nothing will be done.
1094 * Otherwise, a graceful shutdown will be performed to prevent further damage.
1095 */
1096 if (range->software_shutdown_temp &&
1097 smu->ppt_funcs->read_sensor &&
1098 !smu->ppt_funcs->read_sensor(smu,
1099 AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
1100 &hotspot_tmp,
1101 &size) &&
1102 hotspot_tmp / 1000 < range->software_shutdown_temp)
1103 return;
1104
1105 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1106 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1107 orderly_poweroff(true);
1108 }
1109
smu_sw_init(void * handle)1110 static int smu_sw_init(void *handle)
1111 {
1112 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1113 struct smu_context *smu = adev->powerplay.pp_handle;
1114 int ret;
1115
1116 smu->pool_size = adev->pm.smu_prv_buffer_size;
1117 smu->smu_feature.feature_num = SMU_FEATURE_MAX;
1118 bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
1119 bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
1120
1121 INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
1122 INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn);
1123 atomic64_set(&smu->throttle_int_counter, 0);
1124 smu->watermarks_bitmap = 0;
1125 smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1126 smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1127
1128 atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
1129 atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
1130
1131 smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
1132 smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
1133 smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
1134 smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
1135 smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
1136 smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
1137 smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
1138 smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
1139
1140 smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1141 smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1142 smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
1143 smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
1144 smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
1145 smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
1146 smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
1147 smu->display_config = &adev->pm.pm_display_cfg;
1148
1149 smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1150 smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1151
1152 INIT_DELAYED_WORK(&smu->swctf_delayed_work,
1153 smu_swctf_delayed_work_handler);
1154
1155 ret = smu_smc_table_sw_init(smu);
1156 if (ret) {
1157 dev_err(adev->dev, "Failed to sw init smc table!\n");
1158 return ret;
1159 }
1160
1161 /* get boot_values from vbios to set revision, gfxclk, and etc. */
1162 ret = smu_get_vbios_bootup_values(smu);
1163 if (ret) {
1164 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n");
1165 return ret;
1166 }
1167
1168 ret = smu_init_pptable_microcode(smu);
1169 if (ret) {
1170 dev_err(adev->dev, "Failed to setup pptable firmware!\n");
1171 return ret;
1172 }
1173
1174 ret = smu_register_irq_handler(smu);
1175 if (ret) {
1176 dev_err(adev->dev, "Failed to register smc irq handler!\n");
1177 return ret;
1178 }
1179
1180 /* If there is no way to query fan control mode, fan control is not supported */
1181 if (!smu->ppt_funcs->get_fan_control_mode)
1182 smu->adev->pm.no_fan = true;
1183
1184 return 0;
1185 }
1186
smu_sw_fini(void * handle)1187 static int smu_sw_fini(void *handle)
1188 {
1189 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1190 struct smu_context *smu = adev->powerplay.pp_handle;
1191 int ret;
1192
1193 ret = smu_smc_table_sw_fini(smu);
1194 if (ret) {
1195 dev_err(adev->dev, "Failed to sw fini smc table!\n");
1196 return ret;
1197 }
1198
1199 smu_fini_microcode(smu);
1200
1201 return 0;
1202 }
1203
smu_get_thermal_temperature_range(struct smu_context * smu)1204 static int smu_get_thermal_temperature_range(struct smu_context *smu)
1205 {
1206 struct amdgpu_device *adev = smu->adev;
1207 struct smu_temperature_range *range =
1208 &smu->thermal_range;
1209 int ret = 0;
1210
1211 if (!smu->ppt_funcs->get_thermal_temperature_range)
1212 return 0;
1213
1214 ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range);
1215 if (ret)
1216 return ret;
1217
1218 adev->pm.dpm.thermal.min_temp = range->min;
1219 adev->pm.dpm.thermal.max_temp = range->max;
1220 adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max;
1221 adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min;
1222 adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max;
1223 adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max;
1224 adev->pm.dpm.thermal.min_mem_temp = range->mem_min;
1225 adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max;
1226 adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max;
1227
1228 return ret;
1229 }
1230
smu_smc_hw_setup(struct smu_context * smu)1231 static int smu_smc_hw_setup(struct smu_context *smu)
1232 {
1233 struct smu_feature *feature = &smu->smu_feature;
1234 struct amdgpu_device *adev = smu->adev;
1235 uint32_t pcie_gen = 0, pcie_width = 0;
1236 uint64_t features_supported;
1237 int ret = 0;
1238
1239 switch (adev->ip_versions[MP1_HWIP][0]) {
1240 case IP_VERSION(11, 0, 7):
1241 case IP_VERSION(11, 0, 11):
1242 case IP_VERSION(11, 5, 0):
1243 case IP_VERSION(11, 0, 12):
1244 if (adev->in_suspend && smu_is_dpm_running(smu)) {
1245 dev_info(adev->dev, "dpm has been enabled\n");
1246 ret = smu_system_features_control(smu, true);
1247 if (ret)
1248 dev_err(adev->dev, "Failed system features control!\n");
1249 return ret;
1250 }
1251 break;
1252 default:
1253 break;
1254 }
1255
1256 ret = smu_init_display_count(smu, 0);
1257 if (ret) {
1258 dev_info(adev->dev, "Failed to pre-set display count as 0!\n");
1259 return ret;
1260 }
1261
1262 ret = smu_set_driver_table_location(smu);
1263 if (ret) {
1264 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n");
1265 return ret;
1266 }
1267
1268 /*
1269 * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
1270 */
1271 ret = smu_set_tool_table_location(smu);
1272 if (ret) {
1273 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n");
1274 return ret;
1275 }
1276
1277 /*
1278 * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1279 * pool location.
1280 */
1281 ret = smu_notify_memory_pool_location(smu);
1282 if (ret) {
1283 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n");
1284 return ret;
1285 }
1286
1287 /*
1288 * It is assumed the pptable used before runpm is same as
1289 * the one used afterwards. Thus, we can reuse the stored
1290 * copy and do not need to resetup the pptable again.
1291 */
1292 if (!adev->in_runpm) {
1293 ret = smu_setup_pptable(smu);
1294 if (ret) {
1295 dev_err(adev->dev, "Failed to setup pptable!\n");
1296 return ret;
1297 }
1298 }
1299
1300 /* smu_dump_pptable(smu); */
1301
1302 /*
1303 * With SCPM enabled, PSP is responsible for the PPTable transferring
1304 * (to SMU). Driver involvement is not needed and permitted.
1305 */
1306 if (!adev->scpm_enabled) {
1307 /*
1308 * Copy pptable bo in the vram to smc with SMU MSGs such as
1309 * SetDriverDramAddr and TransferTableDram2Smu.
1310 */
1311 ret = smu_write_pptable(smu);
1312 if (ret) {
1313 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n");
1314 return ret;
1315 }
1316 }
1317
1318 /* issue Run*Btc msg */
1319 ret = smu_run_btc(smu);
1320 if (ret)
1321 return ret;
1322
1323 /*
1324 * With SCPM enabled, these actions(and relevant messages) are
1325 * not needed and permitted.
1326 */
1327 if (!adev->scpm_enabled) {
1328 ret = smu_feature_set_allowed_mask(smu);
1329 if (ret) {
1330 dev_err(adev->dev, "Failed to set driver allowed features mask!\n");
1331 return ret;
1332 }
1333 }
1334
1335 ret = smu_system_features_control(smu, true);
1336 if (ret) {
1337 dev_err(adev->dev, "Failed to enable requested dpm features!\n");
1338 return ret;
1339 }
1340
1341 ret = smu_feature_get_enabled_mask(smu, &features_supported);
1342 if (ret) {
1343 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n");
1344 return ret;
1345 }
1346 bitmap_copy(feature->supported,
1347 (unsigned long *)&features_supported,
1348 feature->feature_num);
1349
1350 if (!smu_is_dpm_running(smu))
1351 dev_info(adev->dev, "dpm has been disabled\n");
1352
1353 /*
1354 * Set initialized values (get from vbios) to dpm tables context such as
1355 * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1356 * type of clks.
1357 */
1358 ret = smu_set_default_dpm_table(smu);
1359 if (ret) {
1360 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
1361 return ret;
1362 }
1363
1364 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1365 pcie_gen = 3;
1366 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1367 pcie_gen = 2;
1368 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1369 pcie_gen = 1;
1370 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1371 pcie_gen = 0;
1372
1373 /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
1374 * Bit 15:8: PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
1375 * Bit 7:0: PCIE lane width, 1 to 7 corresponds is x1 to x32
1376 */
1377 if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1378 pcie_width = 6;
1379 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1380 pcie_width = 5;
1381 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1382 pcie_width = 4;
1383 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1384 pcie_width = 3;
1385 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1386 pcie_width = 2;
1387 else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1388 pcie_width = 1;
1389 ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
1390 if (ret) {
1391 dev_err(adev->dev, "Attempt to override pcie params failed!\n");
1392 return ret;
1393 }
1394
1395 ret = smu_get_thermal_temperature_range(smu);
1396 if (ret) {
1397 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n");
1398 return ret;
1399 }
1400
1401 ret = smu_enable_thermal_alert(smu);
1402 if (ret) {
1403 dev_err(adev->dev, "Failed to enable thermal alert!\n");
1404 return ret;
1405 }
1406
1407 ret = smu_notify_display_change(smu);
1408 if (ret) {
1409 dev_err(adev->dev, "Failed to notify display change!\n");
1410 return ret;
1411 }
1412
1413 /*
1414 * Set min deep sleep dce fclk with bootup value from vbios via
1415 * SetMinDeepSleepDcefclk MSG.
1416 */
1417 ret = smu_set_min_dcef_deep_sleep(smu,
1418 smu->smu_table.boot_values.dcefclk / 100);
1419
1420 return ret;
1421 }
1422
smu_start_smc_engine(struct smu_context * smu)1423 static int smu_start_smc_engine(struct smu_context *smu)
1424 {
1425 struct amdgpu_device *adev = smu->adev;
1426 int ret = 0;
1427
1428 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1429 if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) {
1430 if (smu->ppt_funcs->load_microcode) {
1431 ret = smu->ppt_funcs->load_microcode(smu);
1432 if (ret)
1433 return ret;
1434 }
1435 }
1436 }
1437
1438 if (smu->ppt_funcs->check_fw_status) {
1439 ret = smu->ppt_funcs->check_fw_status(smu);
1440 if (ret) {
1441 dev_err(adev->dev, "SMC is not ready\n");
1442 return ret;
1443 }
1444 }
1445
1446 /*
1447 * Send msg GetDriverIfVersion to check if the return value is equal
1448 * with DRIVER_IF_VERSION of smc header.
1449 */
1450 ret = smu_check_fw_version(smu);
1451 if (ret)
1452 return ret;
1453
1454 return ret;
1455 }
1456
smu_hw_init(void * handle)1457 static int smu_hw_init(void *handle)
1458 {
1459 int ret;
1460 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1461 struct smu_context *smu = adev->powerplay.pp_handle;
1462
1463 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
1464 smu->pm_enabled = false;
1465 return 0;
1466 }
1467
1468 ret = smu_start_smc_engine(smu);
1469 if (ret) {
1470 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1471 return ret;
1472 }
1473
1474 if (smu->is_apu) {
1475 ret = smu_set_gfx_imu_enable(smu);
1476 if (ret)
1477 return ret;
1478 smu_dpm_set_vcn_enable(smu, true);
1479 smu_dpm_set_jpeg_enable(smu, true);
1480 smu_set_gfx_cgpg(smu, true);
1481 }
1482
1483 if (!smu->pm_enabled)
1484 return 0;
1485
1486 ret = smu_get_driver_allowed_feature_mask(smu);
1487 if (ret)
1488 return ret;
1489
1490 ret = smu_smc_hw_setup(smu);
1491 if (ret) {
1492 dev_err(adev->dev, "Failed to setup smc hw!\n");
1493 return ret;
1494 }
1495
1496 /*
1497 * Move maximum sustainable clock retrieving here considering
1498 * 1. It is not needed on resume(from S3).
1499 * 2. DAL settings come between .hw_init and .late_init of SMU.
1500 * And DAL needs to know the maximum sustainable clocks. Thus
1501 * it cannot be put in .late_init().
1502 */
1503 ret = smu_init_max_sustainable_clocks(smu);
1504 if (ret) {
1505 dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
1506 return ret;
1507 }
1508
1509 adev->pm.dpm_enabled = true;
1510
1511 dev_info(adev->dev, "SMU is initialized successfully!\n");
1512
1513 return 0;
1514 }
1515
smu_disable_dpms(struct smu_context * smu)1516 static int smu_disable_dpms(struct smu_context *smu)
1517 {
1518 struct amdgpu_device *adev = smu->adev;
1519 int ret = 0;
1520 bool use_baco = !smu->is_apu &&
1521 ((amdgpu_in_reset(adev) &&
1522 (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
1523 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev)));
1524
1525 /*
1526 * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others)
1527 * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues.
1528 */
1529 switch (adev->ip_versions[MP1_HWIP][0]) {
1530 case IP_VERSION(13, 0, 0):
1531 case IP_VERSION(13, 0, 7):
1532 case IP_VERSION(13, 0, 10):
1533 return 0;
1534 default:
1535 break;
1536 }
1537
1538 /*
1539 * For custom pptable uploading, skip the DPM features
1540 * disable process on Navi1x ASICs.
1541 * - As the gfx related features are under control of
1542 * RLC on those ASICs. RLC reinitialization will be
1543 * needed to reenable them. That will cost much more
1544 * efforts.
1545 *
1546 * - SMU firmware can handle the DPM reenablement
1547 * properly.
1548 */
1549 if (smu->uploading_custom_pp_table) {
1550 switch (adev->ip_versions[MP1_HWIP][0]) {
1551 case IP_VERSION(11, 0, 0):
1552 case IP_VERSION(11, 0, 5):
1553 case IP_VERSION(11, 0, 9):
1554 case IP_VERSION(11, 0, 7):
1555 case IP_VERSION(11, 0, 11):
1556 case IP_VERSION(11, 5, 0):
1557 case IP_VERSION(11, 0, 12):
1558 case IP_VERSION(11, 0, 13):
1559 return 0;
1560 default:
1561 break;
1562 }
1563 }
1564
1565 /*
1566 * For Sienna_Cichlid, PMFW will handle the features disablement properly
1567 * on BACO in. Driver involvement is unnecessary.
1568 */
1569 if (use_baco) {
1570 switch (adev->ip_versions[MP1_HWIP][0]) {
1571 case IP_VERSION(11, 0, 7):
1572 case IP_VERSION(11, 0, 0):
1573 case IP_VERSION(11, 0, 5):
1574 case IP_VERSION(11, 0, 9):
1575 case IP_VERSION(13, 0, 7):
1576 return 0;
1577 default:
1578 break;
1579 }
1580 }
1581
1582 /*
1583 * For SMU 13.0.4/11, PMFW will handle the features disablement properly
1584 * for gpu reset and S0i3 cases. Driver involvement is unnecessary.
1585 */
1586 if (amdgpu_in_reset(adev) || adev->in_s0ix) {
1587 switch (adev->ip_versions[MP1_HWIP][0]) {
1588 case IP_VERSION(13, 0, 4):
1589 case IP_VERSION(13, 0, 11):
1590 return 0;
1591 default:
1592 break;
1593 }
1594 }
1595
1596 /*
1597 * For gpu reset, runpm and hibernation through BACO,
1598 * BACO feature has to be kept enabled.
1599 */
1600 if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
1601 ret = smu_disable_all_features_with_exception(smu,
1602 SMU_FEATURE_BACO_BIT);
1603 if (ret)
1604 dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
1605 } else {
1606 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */
1607 if (!adev->scpm_enabled) {
1608 ret = smu_system_features_control(smu, false);
1609 if (ret)
1610 dev_err(adev->dev, "Failed to disable smu features.\n");
1611 }
1612 }
1613
1614 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) &&
1615 !amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->stop)
1616 adev->gfx.rlc.funcs->stop(adev);
1617
1618 return ret;
1619 }
1620
smu_smc_hw_cleanup(struct smu_context * smu)1621 static int smu_smc_hw_cleanup(struct smu_context *smu)
1622 {
1623 struct amdgpu_device *adev = smu->adev;
1624 int ret = 0;
1625
1626 cancel_work_sync(&smu->throttling_logging_work);
1627 cancel_work_sync(&smu->interrupt_work);
1628
1629 ret = smu_disable_thermal_alert(smu);
1630 if (ret) {
1631 dev_err(adev->dev, "Fail to disable thermal alert!\n");
1632 return ret;
1633 }
1634
1635 cancel_delayed_work_sync(&smu->swctf_delayed_work);
1636
1637 ret = smu_disable_dpms(smu);
1638 if (ret) {
1639 dev_err(adev->dev, "Fail to disable dpm features!\n");
1640 return ret;
1641 }
1642
1643 return 0;
1644 }
1645
smu_hw_fini(void * handle)1646 static int smu_hw_fini(void *handle)
1647 {
1648 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1649 struct smu_context *smu = adev->powerplay.pp_handle;
1650
1651 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1652 return 0;
1653
1654 smu_dpm_set_vcn_enable(smu, false);
1655 smu_dpm_set_jpeg_enable(smu, false);
1656
1657 adev->vcn.cur_state = AMD_PG_STATE_GATE;
1658 adev->jpeg.cur_state = AMD_PG_STATE_GATE;
1659
1660 if (!smu->pm_enabled)
1661 return 0;
1662
1663 adev->pm.dpm_enabled = false;
1664
1665 return smu_smc_hw_cleanup(smu);
1666 }
1667
smu_late_fini(void * handle)1668 static void smu_late_fini(void *handle)
1669 {
1670 struct amdgpu_device *adev = handle;
1671 struct smu_context *smu = adev->powerplay.pp_handle;
1672
1673 kfree(smu);
1674 }
1675
smu_reset(struct smu_context * smu)1676 static int smu_reset(struct smu_context *smu)
1677 {
1678 struct amdgpu_device *adev = smu->adev;
1679 int ret;
1680
1681 ret = smu_hw_fini(adev);
1682 if (ret)
1683 return ret;
1684
1685 ret = smu_hw_init(adev);
1686 if (ret)
1687 return ret;
1688
1689 ret = smu_late_init(adev);
1690 if (ret)
1691 return ret;
1692
1693 return 0;
1694 }
1695
smu_suspend(void * handle)1696 static int smu_suspend(void *handle)
1697 {
1698 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1699 struct smu_context *smu = adev->powerplay.pp_handle;
1700 int ret;
1701 uint64_t count;
1702
1703 if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
1704 return 0;
1705
1706 if (!smu->pm_enabled)
1707 return 0;
1708
1709 adev->pm.dpm_enabled = false;
1710
1711 ret = smu_smc_hw_cleanup(smu);
1712 if (ret)
1713 return ret;
1714
1715 smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1716
1717 smu_set_gfx_cgpg(smu, false);
1718
1719 /*
1720 * pwfw resets entrycount when device is suspended, so we save the
1721 * last value to be used when we resume to keep it consistent
1722 */
1723 ret = smu_get_entrycount_gfxoff(smu, &count);
1724 if (!ret)
1725 adev->gfx.gfx_off_entrycount = count;
1726
1727 return 0;
1728 }
1729
smu_resume(void * handle)1730 static int smu_resume(void *handle)
1731 {
1732 int ret;
1733 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1734 struct smu_context *smu = adev->powerplay.pp_handle;
1735
1736 if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1737 return 0;
1738
1739 if (!smu->pm_enabled)
1740 return 0;
1741
1742 dev_info(adev->dev, "SMU is resuming...\n");
1743
1744 ret = smu_start_smc_engine(smu);
1745 if (ret) {
1746 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1747 return ret;
1748 }
1749
1750 ret = smu_smc_hw_setup(smu);
1751 if (ret) {
1752 dev_err(adev->dev, "Failed to setup smc hw!\n");
1753 return ret;
1754 }
1755
1756 ret = smu_set_gfx_imu_enable(smu);
1757 if (ret)
1758 return ret;
1759
1760 smu_set_gfx_cgpg(smu, true);
1761
1762 smu->disable_uclk_switch = 0;
1763
1764 adev->pm.dpm_enabled = true;
1765
1766 dev_info(adev->dev, "SMU is resumed successfully!\n");
1767
1768 return 0;
1769 }
1770
smu_display_configuration_change(void * handle,const struct amd_pp_display_configuration * display_config)1771 static int smu_display_configuration_change(void *handle,
1772 const struct amd_pp_display_configuration *display_config)
1773 {
1774 struct smu_context *smu = handle;
1775
1776 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1777 return -EOPNOTSUPP;
1778
1779 if (!display_config)
1780 return -EINVAL;
1781
1782 smu_set_min_dcef_deep_sleep(smu,
1783 display_config->min_dcef_deep_sleep_set_clk / 100);
1784
1785 return 0;
1786 }
1787
smu_set_clockgating_state(void * handle,enum amd_clockgating_state state)1788 static int smu_set_clockgating_state(void *handle,
1789 enum amd_clockgating_state state)
1790 {
1791 return 0;
1792 }
1793
smu_set_powergating_state(void * handle,enum amd_powergating_state state)1794 static int smu_set_powergating_state(void *handle,
1795 enum amd_powergating_state state)
1796 {
1797 return 0;
1798 }
1799
smu_enable_umd_pstate(void * handle,enum amd_dpm_forced_level * level)1800 static int smu_enable_umd_pstate(void *handle,
1801 enum amd_dpm_forced_level *level)
1802 {
1803 uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1804 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1805 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1806 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1807
1808 struct smu_context *smu = (struct smu_context*)(handle);
1809 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1810
1811 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1812 return -EINVAL;
1813
1814 if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1815 /* enter umd pstate, save current level, disable gfx cg*/
1816 if (*level & profile_mode_mask) {
1817 smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1818 smu_gpo_control(smu, false);
1819 smu_gfx_ulv_control(smu, false);
1820 smu_deep_sleep_control(smu, false);
1821 amdgpu_asic_update_umd_stable_pstate(smu->adev, true);
1822 }
1823 } else {
1824 /* exit umd pstate, restore level, enable gfx cg*/
1825 if (!(*level & profile_mode_mask)) {
1826 if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1827 *level = smu_dpm_ctx->saved_dpm_level;
1828 amdgpu_asic_update_umd_stable_pstate(smu->adev, false);
1829 smu_deep_sleep_control(smu, true);
1830 smu_gfx_ulv_control(smu, true);
1831 smu_gpo_control(smu, true);
1832 }
1833 }
1834
1835 return 0;
1836 }
1837
smu_bump_power_profile_mode(struct smu_context * smu,long * param,uint32_t param_size)1838 static int smu_bump_power_profile_mode(struct smu_context *smu,
1839 long *param,
1840 uint32_t param_size)
1841 {
1842 int ret = 0;
1843
1844 if (smu->ppt_funcs->set_power_profile_mode)
1845 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
1846
1847 return ret;
1848 }
1849
smu_adjust_power_state_dynamic(struct smu_context * smu,enum amd_dpm_forced_level level,bool skip_display_settings)1850 static int smu_adjust_power_state_dynamic(struct smu_context *smu,
1851 enum amd_dpm_forced_level level,
1852 bool skip_display_settings)
1853 {
1854 int ret = 0;
1855 int index = 0;
1856 long workload;
1857 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1858
1859 if (!skip_display_settings) {
1860 ret = smu_display_config_changed(smu);
1861 if (ret) {
1862 dev_err(smu->adev->dev, "Failed to change display config!");
1863 return ret;
1864 }
1865 }
1866
1867 ret = smu_apply_clocks_adjust_rules(smu);
1868 if (ret) {
1869 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!");
1870 return ret;
1871 }
1872
1873 if (!skip_display_settings) {
1874 ret = smu_notify_smc_display_config(smu);
1875 if (ret) {
1876 dev_err(smu->adev->dev, "Failed to notify smc display config!");
1877 return ret;
1878 }
1879 }
1880
1881 if (smu_dpm_ctx->dpm_level != level) {
1882 ret = smu_asic_set_performance_level(smu, level);
1883 if (ret) {
1884 dev_err(smu->adev->dev, "Failed to set performance level!");
1885 return ret;
1886 }
1887
1888 /* update the saved copy */
1889 smu_dpm_ctx->dpm_level = level;
1890 }
1891
1892 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
1893 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
1894 index = fls(smu->workload_mask);
1895 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1896 workload = smu->workload_setting[index];
1897
1898 if (smu->power_profile_mode != workload)
1899 smu_bump_power_profile_mode(smu, &workload, 0);
1900 }
1901
1902 return ret;
1903 }
1904
smu_handle_task(struct smu_context * smu,enum amd_dpm_forced_level level,enum amd_pp_task task_id)1905 static int smu_handle_task(struct smu_context *smu,
1906 enum amd_dpm_forced_level level,
1907 enum amd_pp_task task_id)
1908 {
1909 int ret = 0;
1910
1911 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1912 return -EOPNOTSUPP;
1913
1914 switch (task_id) {
1915 case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1916 ret = smu_pre_display_config_changed(smu);
1917 if (ret)
1918 return ret;
1919 ret = smu_adjust_power_state_dynamic(smu, level, false);
1920 break;
1921 case AMD_PP_TASK_COMPLETE_INIT:
1922 case AMD_PP_TASK_READJUST_POWER_STATE:
1923 ret = smu_adjust_power_state_dynamic(smu, level, true);
1924 break;
1925 default:
1926 break;
1927 }
1928
1929 return ret;
1930 }
1931
smu_handle_dpm_task(void * handle,enum amd_pp_task task_id,enum amd_pm_state_type * user_state)1932 static int smu_handle_dpm_task(void *handle,
1933 enum amd_pp_task task_id,
1934 enum amd_pm_state_type *user_state)
1935 {
1936 struct smu_context *smu = handle;
1937 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1938
1939 return smu_handle_task(smu, smu_dpm->dpm_level, task_id);
1940
1941 }
1942
smu_switch_power_profile(void * handle,enum PP_SMC_POWER_PROFILE type,bool en)1943 static int smu_switch_power_profile(void *handle,
1944 enum PP_SMC_POWER_PROFILE type,
1945 bool en)
1946 {
1947 struct smu_context *smu = handle;
1948 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1949 long workload;
1950 uint32_t index;
1951
1952 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1953 return -EOPNOTSUPP;
1954
1955 if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1956 return -EINVAL;
1957
1958 if (!en) {
1959 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1960 index = fls(smu->workload_mask);
1961 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1962 workload = smu->workload_setting[index];
1963 } else {
1964 smu->workload_mask |= (1 << smu->workload_prority[type]);
1965 index = fls(smu->workload_mask);
1966 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1967 workload = smu->workload_setting[index];
1968 }
1969
1970 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
1971 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
1972 smu_bump_power_profile_mode(smu, &workload, 0);
1973
1974 return 0;
1975 }
1976
smu_get_performance_level(void * handle)1977 static enum amd_dpm_forced_level smu_get_performance_level(void *handle)
1978 {
1979 struct smu_context *smu = handle;
1980 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1981
1982 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1983 return -EOPNOTSUPP;
1984
1985 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1986 return -EINVAL;
1987
1988 return smu_dpm_ctx->dpm_level;
1989 }
1990
smu_force_performance_level(void * handle,enum amd_dpm_forced_level level)1991 static int smu_force_performance_level(void *handle,
1992 enum amd_dpm_forced_level level)
1993 {
1994 struct smu_context *smu = handle;
1995 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1996 int ret = 0;
1997
1998 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1999 return -EOPNOTSUPP;
2000
2001 if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
2002 return -EINVAL;
2003
2004 ret = smu_enable_umd_pstate(smu, &level);
2005 if (ret)
2006 return ret;
2007
2008 ret = smu_handle_task(smu, level,
2009 AMD_PP_TASK_READJUST_POWER_STATE);
2010
2011 /* reset user dpm clock state */
2012 if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
2013 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask));
2014 smu->user_dpm_profile.clk_dependency = 0;
2015 }
2016
2017 return ret;
2018 }
2019
smu_set_display_count(void * handle,uint32_t count)2020 static int smu_set_display_count(void *handle, uint32_t count)
2021 {
2022 struct smu_context *smu = handle;
2023
2024 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2025 return -EOPNOTSUPP;
2026
2027 return smu_init_display_count(smu, count);
2028 }
2029
smu_force_smuclk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)2030 static int smu_force_smuclk_levels(struct smu_context *smu,
2031 enum smu_clk_type clk_type,
2032 uint32_t mask)
2033 {
2034 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2035 int ret = 0;
2036
2037 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2038 return -EOPNOTSUPP;
2039
2040 if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
2041 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n");
2042 return -EINVAL;
2043 }
2044
2045 if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) {
2046 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
2047 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2048 smu->user_dpm_profile.clk_mask[clk_type] = mask;
2049 smu_set_user_clk_dependencies(smu, clk_type);
2050 }
2051 }
2052
2053 return ret;
2054 }
2055
smu_force_ppclk_levels(void * handle,enum pp_clock_type type,uint32_t mask)2056 static int smu_force_ppclk_levels(void *handle,
2057 enum pp_clock_type type,
2058 uint32_t mask)
2059 {
2060 struct smu_context *smu = handle;
2061 enum smu_clk_type clk_type;
2062
2063 switch (type) {
2064 case PP_SCLK:
2065 clk_type = SMU_SCLK; break;
2066 case PP_MCLK:
2067 clk_type = SMU_MCLK; break;
2068 case PP_PCIE:
2069 clk_type = SMU_PCIE; break;
2070 case PP_SOCCLK:
2071 clk_type = SMU_SOCCLK; break;
2072 case PP_FCLK:
2073 clk_type = SMU_FCLK; break;
2074 case PP_DCEFCLK:
2075 clk_type = SMU_DCEFCLK; break;
2076 case PP_VCLK:
2077 clk_type = SMU_VCLK; break;
2078 case PP_VCLK1:
2079 clk_type = SMU_VCLK1; break;
2080 case PP_DCLK:
2081 clk_type = SMU_DCLK; break;
2082 case PP_DCLK1:
2083 clk_type = SMU_DCLK1; break;
2084 case OD_SCLK:
2085 clk_type = SMU_OD_SCLK; break;
2086 case OD_MCLK:
2087 clk_type = SMU_OD_MCLK; break;
2088 case OD_VDDC_CURVE:
2089 clk_type = SMU_OD_VDDC_CURVE; break;
2090 case OD_RANGE:
2091 clk_type = SMU_OD_RANGE; break;
2092 default:
2093 return -EINVAL;
2094 }
2095
2096 return smu_force_smuclk_levels(smu, clk_type, mask);
2097 }
2098
2099 /*
2100 * On system suspending or resetting, the dpm_enabled
2101 * flag will be cleared. So that those SMU services which
2102 * are not supported will be gated.
2103 * However, the mp1 state setting should still be granted
2104 * even if the dpm_enabled cleared.
2105 */
smu_set_mp1_state(void * handle,enum pp_mp1_state mp1_state)2106 static int smu_set_mp1_state(void *handle,
2107 enum pp_mp1_state mp1_state)
2108 {
2109 struct smu_context *smu = handle;
2110 int ret = 0;
2111
2112 if (!smu->pm_enabled)
2113 return -EOPNOTSUPP;
2114
2115 if (smu->ppt_funcs &&
2116 smu->ppt_funcs->set_mp1_state)
2117 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state);
2118
2119 return ret;
2120 }
2121
smu_set_df_cstate(void * handle,enum pp_df_cstate state)2122 static int smu_set_df_cstate(void *handle,
2123 enum pp_df_cstate state)
2124 {
2125 struct smu_context *smu = handle;
2126 int ret = 0;
2127
2128 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2129 return -EOPNOTSUPP;
2130
2131 if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
2132 return 0;
2133
2134 ret = smu->ppt_funcs->set_df_cstate(smu, state);
2135 if (ret)
2136 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n");
2137
2138 return ret;
2139 }
2140
smu_allow_xgmi_power_down(struct smu_context * smu,bool en)2141 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en)
2142 {
2143 int ret = 0;
2144
2145 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2146 return -EOPNOTSUPP;
2147
2148 if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down)
2149 return 0;
2150
2151 ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en);
2152 if (ret)
2153 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n");
2154
2155 return ret;
2156 }
2157
smu_write_watermarks_table(struct smu_context * smu)2158 int smu_write_watermarks_table(struct smu_context *smu)
2159 {
2160 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2161 return -EOPNOTSUPP;
2162
2163 return smu_set_watermarks_table(smu, NULL);
2164 }
2165
smu_set_watermarks_for_clock_ranges(void * handle,struct pp_smu_wm_range_sets * clock_ranges)2166 static int smu_set_watermarks_for_clock_ranges(void *handle,
2167 struct pp_smu_wm_range_sets *clock_ranges)
2168 {
2169 struct smu_context *smu = handle;
2170
2171 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2172 return -EOPNOTSUPP;
2173
2174 if (smu->disable_watermark)
2175 return 0;
2176
2177 return smu_set_watermarks_table(smu, clock_ranges);
2178 }
2179
smu_set_ac_dc(struct smu_context * smu)2180 int smu_set_ac_dc(struct smu_context *smu)
2181 {
2182 int ret = 0;
2183
2184 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2185 return -EOPNOTSUPP;
2186
2187 /* controlled by firmware */
2188 if (smu->dc_controlled_by_gpio)
2189 return 0;
2190
2191 ret = smu_set_power_source(smu,
2192 smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
2193 SMU_POWER_SOURCE_DC);
2194 if (ret)
2195 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n",
2196 smu->adev->pm.ac_power ? "AC" : "DC");
2197
2198 return ret;
2199 }
2200
2201 const struct amd_ip_funcs smu_ip_funcs = {
2202 .name = "smu",
2203 .early_init = smu_early_init,
2204 .late_init = smu_late_init,
2205 .sw_init = smu_sw_init,
2206 .sw_fini = smu_sw_fini,
2207 .hw_init = smu_hw_init,
2208 .hw_fini = smu_hw_fini,
2209 .late_fini = smu_late_fini,
2210 .suspend = smu_suspend,
2211 .resume = smu_resume,
2212 .is_idle = NULL,
2213 .check_soft_reset = NULL,
2214 .wait_for_idle = NULL,
2215 .soft_reset = NULL,
2216 .set_clockgating_state = smu_set_clockgating_state,
2217 .set_powergating_state = smu_set_powergating_state,
2218 };
2219
2220 const struct amdgpu_ip_block_version smu_v11_0_ip_block = {
2221 .type = AMD_IP_BLOCK_TYPE_SMC,
2222 .major = 11,
2223 .minor = 0,
2224 .rev = 0,
2225 .funcs = &smu_ip_funcs,
2226 };
2227
2228 const struct amdgpu_ip_block_version smu_v12_0_ip_block = {
2229 .type = AMD_IP_BLOCK_TYPE_SMC,
2230 .major = 12,
2231 .minor = 0,
2232 .rev = 0,
2233 .funcs = &smu_ip_funcs,
2234 };
2235
2236 const struct amdgpu_ip_block_version smu_v13_0_ip_block = {
2237 .type = AMD_IP_BLOCK_TYPE_SMC,
2238 .major = 13,
2239 .minor = 0,
2240 .rev = 0,
2241 .funcs = &smu_ip_funcs,
2242 };
2243
smu_load_microcode(void * handle)2244 static int smu_load_microcode(void *handle)
2245 {
2246 struct smu_context *smu = handle;
2247 struct amdgpu_device *adev = smu->adev;
2248 int ret = 0;
2249
2250 if (!smu->pm_enabled)
2251 return -EOPNOTSUPP;
2252
2253 /* This should be used for non PSP loading */
2254 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
2255 return 0;
2256
2257 if (smu->ppt_funcs->load_microcode) {
2258 ret = smu->ppt_funcs->load_microcode(smu);
2259 if (ret) {
2260 dev_err(adev->dev, "Load microcode failed\n");
2261 return ret;
2262 }
2263 }
2264
2265 if (smu->ppt_funcs->check_fw_status) {
2266 ret = smu->ppt_funcs->check_fw_status(smu);
2267 if (ret) {
2268 dev_err(adev->dev, "SMC is not ready\n");
2269 return ret;
2270 }
2271 }
2272
2273 return ret;
2274 }
2275
smu_set_gfx_cgpg(struct smu_context * smu,bool enabled)2276 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
2277 {
2278 int ret = 0;
2279
2280 if (smu->ppt_funcs->set_gfx_cgpg)
2281 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
2282
2283 return ret;
2284 }
2285
smu_set_fan_speed_rpm(void * handle,uint32_t speed)2286 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
2287 {
2288 struct smu_context *smu = handle;
2289 int ret = 0;
2290
2291 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2292 return -EOPNOTSUPP;
2293
2294 if (!smu->ppt_funcs->set_fan_speed_rpm)
2295 return -EOPNOTSUPP;
2296
2297 if (speed == U32_MAX)
2298 return -EINVAL;
2299
2300 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
2301 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2302 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM;
2303 smu->user_dpm_profile.fan_speed_rpm = speed;
2304
2305 /* Override custom PWM setting as they cannot co-exist */
2306 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM;
2307 smu->user_dpm_profile.fan_speed_pwm = 0;
2308 }
2309
2310 return ret;
2311 }
2312
2313 /**
2314 * smu_get_power_limit - Request one of the SMU Power Limits
2315 *
2316 * @handle: pointer to smu context
2317 * @limit: requested limit is written back to this variable
2318 * @pp_limit_level: &pp_power_limit_level which limit of the power to return
2319 * @pp_power_type: &pp_power_type type of power
2320 * Return: 0 on success, <0 on error
2321 *
2322 */
smu_get_power_limit(void * handle,uint32_t * limit,enum pp_power_limit_level pp_limit_level,enum pp_power_type pp_power_type)2323 int smu_get_power_limit(void *handle,
2324 uint32_t *limit,
2325 enum pp_power_limit_level pp_limit_level,
2326 enum pp_power_type pp_power_type)
2327 {
2328 struct smu_context *smu = handle;
2329 struct amdgpu_device *adev = smu->adev;
2330 enum smu_ppt_limit_level limit_level;
2331 uint32_t limit_type;
2332 int ret = 0;
2333
2334 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2335 return -EOPNOTSUPP;
2336
2337 switch (pp_power_type) {
2338 case PP_PWR_TYPE_SUSTAINED:
2339 limit_type = SMU_DEFAULT_PPT_LIMIT;
2340 break;
2341 case PP_PWR_TYPE_FAST:
2342 limit_type = SMU_FAST_PPT_LIMIT;
2343 break;
2344 default:
2345 return -EOPNOTSUPP;
2346 break;
2347 }
2348
2349 switch (pp_limit_level) {
2350 case PP_PWR_LIMIT_CURRENT:
2351 limit_level = SMU_PPT_LIMIT_CURRENT;
2352 break;
2353 case PP_PWR_LIMIT_DEFAULT:
2354 limit_level = SMU_PPT_LIMIT_DEFAULT;
2355 break;
2356 case PP_PWR_LIMIT_MAX:
2357 limit_level = SMU_PPT_LIMIT_MAX;
2358 break;
2359 case PP_PWR_LIMIT_MIN:
2360 default:
2361 return -EOPNOTSUPP;
2362 break;
2363 }
2364
2365 if (limit_type != SMU_DEFAULT_PPT_LIMIT) {
2366 if (smu->ppt_funcs->get_ppt_limit)
2367 ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level);
2368 } else {
2369 switch (limit_level) {
2370 case SMU_PPT_LIMIT_CURRENT:
2371 switch (adev->ip_versions[MP1_HWIP][0]) {
2372 case IP_VERSION(13, 0, 2):
2373 case IP_VERSION(11, 0, 7):
2374 case IP_VERSION(11, 0, 11):
2375 case IP_VERSION(11, 0, 12):
2376 case IP_VERSION(11, 0, 13):
2377 ret = smu_get_asic_power_limits(smu,
2378 &smu->current_power_limit,
2379 NULL,
2380 NULL);
2381 break;
2382 default:
2383 break;
2384 }
2385 *limit = smu->current_power_limit;
2386 break;
2387 case SMU_PPT_LIMIT_DEFAULT:
2388 *limit = smu->default_power_limit;
2389 break;
2390 case SMU_PPT_LIMIT_MAX:
2391 *limit = smu->max_power_limit;
2392 break;
2393 default:
2394 break;
2395 }
2396 }
2397
2398 return ret;
2399 }
2400
smu_set_power_limit(void * handle,uint32_t limit)2401 static int smu_set_power_limit(void *handle, uint32_t limit)
2402 {
2403 struct smu_context *smu = handle;
2404 uint32_t limit_type = limit >> 24;
2405 int ret = 0;
2406
2407 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2408 return -EOPNOTSUPP;
2409
2410 limit &= (1<<24)-1;
2411 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
2412 if (smu->ppt_funcs->set_power_limit)
2413 return smu->ppt_funcs->set_power_limit(smu, limit_type, limit);
2414
2415 if (limit > smu->max_power_limit) {
2416 dev_err(smu->adev->dev,
2417 "New power limit (%d) is over the max allowed %d\n",
2418 limit, smu->max_power_limit);
2419 return -EINVAL;
2420 }
2421
2422 if (!limit)
2423 limit = smu->current_power_limit;
2424
2425 if (smu->ppt_funcs->set_power_limit) {
2426 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit);
2427 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
2428 smu->user_dpm_profile.power_limit = limit;
2429 }
2430
2431 return ret;
2432 }
2433
smu_print_smuclk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)2434 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2435 {
2436 int ret = 0;
2437
2438 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2439 return -EOPNOTSUPP;
2440
2441 if (smu->ppt_funcs->print_clk_levels)
2442 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2443
2444 return ret;
2445 }
2446
smu_convert_to_smuclk(enum pp_clock_type type)2447 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type)
2448 {
2449 enum smu_clk_type clk_type;
2450
2451 switch (type) {
2452 case PP_SCLK:
2453 clk_type = SMU_SCLK; break;
2454 case PP_MCLK:
2455 clk_type = SMU_MCLK; break;
2456 case PP_PCIE:
2457 clk_type = SMU_PCIE; break;
2458 case PP_SOCCLK:
2459 clk_type = SMU_SOCCLK; break;
2460 case PP_FCLK:
2461 clk_type = SMU_FCLK; break;
2462 case PP_DCEFCLK:
2463 clk_type = SMU_DCEFCLK; break;
2464 case PP_VCLK:
2465 clk_type = SMU_VCLK; break;
2466 case PP_VCLK1:
2467 clk_type = SMU_VCLK1; break;
2468 case PP_DCLK:
2469 clk_type = SMU_DCLK; break;
2470 case PP_DCLK1:
2471 clk_type = SMU_DCLK1; break;
2472 case OD_SCLK:
2473 clk_type = SMU_OD_SCLK; break;
2474 case OD_MCLK:
2475 clk_type = SMU_OD_MCLK; break;
2476 case OD_VDDC_CURVE:
2477 clk_type = SMU_OD_VDDC_CURVE; break;
2478 case OD_RANGE:
2479 clk_type = SMU_OD_RANGE; break;
2480 case OD_VDDGFX_OFFSET:
2481 clk_type = SMU_OD_VDDGFX_OFFSET; break;
2482 case OD_CCLK:
2483 clk_type = SMU_OD_CCLK; break;
2484 default:
2485 clk_type = SMU_CLK_COUNT; break;
2486 }
2487
2488 return clk_type;
2489 }
2490
smu_print_ppclk_levels(void * handle,enum pp_clock_type type,char * buf)2491 static int smu_print_ppclk_levels(void *handle,
2492 enum pp_clock_type type,
2493 char *buf)
2494 {
2495 struct smu_context *smu = handle;
2496 enum smu_clk_type clk_type;
2497
2498 clk_type = smu_convert_to_smuclk(type);
2499 if (clk_type == SMU_CLK_COUNT)
2500 return -EINVAL;
2501
2502 return smu_print_smuclk_levels(smu, clk_type, buf);
2503 }
2504
smu_emit_ppclk_levels(void * handle,enum pp_clock_type type,char * buf,int * offset)2505 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset)
2506 {
2507 struct smu_context *smu = handle;
2508 enum smu_clk_type clk_type;
2509
2510 clk_type = smu_convert_to_smuclk(type);
2511 if (clk_type == SMU_CLK_COUNT)
2512 return -EINVAL;
2513
2514 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2515 return -EOPNOTSUPP;
2516
2517 if (!smu->ppt_funcs->emit_clk_levels)
2518 return -ENOENT;
2519
2520 return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset);
2521
2522 }
2523
smu_od_edit_dpm_table(void * handle,enum PP_OD_DPM_TABLE_COMMAND type,long * input,uint32_t size)2524 static int smu_od_edit_dpm_table(void *handle,
2525 enum PP_OD_DPM_TABLE_COMMAND type,
2526 long *input, uint32_t size)
2527 {
2528 struct smu_context *smu = handle;
2529 int ret = 0;
2530
2531 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2532 return -EOPNOTSUPP;
2533
2534 if (smu->ppt_funcs->od_edit_dpm_table) {
2535 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2536 }
2537
2538 return ret;
2539 }
2540
smu_read_sensor(void * handle,int sensor,void * data,int * size_arg)2541 static int smu_read_sensor(void *handle,
2542 int sensor,
2543 void *data,
2544 int *size_arg)
2545 {
2546 struct smu_context *smu = handle;
2547 struct smu_umd_pstate_table *pstate_table =
2548 &smu->pstate_table;
2549 int ret = 0;
2550 uint32_t *size, size_val;
2551
2552 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2553 return -EOPNOTSUPP;
2554
2555 if (!data || !size_arg)
2556 return -EINVAL;
2557
2558 size_val = *size_arg;
2559 size = &size_val;
2560
2561 if (smu->ppt_funcs->read_sensor)
2562 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size))
2563 goto unlock;
2564
2565 switch (sensor) {
2566 case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
2567 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100;
2568 *size = 4;
2569 break;
2570 case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
2571 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100;
2572 *size = 4;
2573 break;
2574 case AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK:
2575 *((uint32_t *)data) = pstate_table->gfxclk_pstate.peak * 100;
2576 *size = 4;
2577 break;
2578 case AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK:
2579 *((uint32_t *)data) = pstate_table->uclk_pstate.peak * 100;
2580 *size = 4;
2581 break;
2582 case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2583 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data);
2584 *size = 8;
2585 break;
2586 case AMDGPU_PP_SENSOR_UVD_POWER:
2587 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
2588 *size = 4;
2589 break;
2590 case AMDGPU_PP_SENSOR_VCE_POWER:
2591 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
2592 *size = 4;
2593 break;
2594 case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
2595 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0 : 1;
2596 *size = 4;
2597 break;
2598 case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
2599 *(uint32_t *)data = 0;
2600 *size = 4;
2601 break;
2602 default:
2603 *size = 0;
2604 ret = -EOPNOTSUPP;
2605 break;
2606 }
2607
2608 unlock:
2609 // assign uint32_t to int
2610 *size_arg = size_val;
2611
2612 return ret;
2613 }
2614
smu_get_apu_thermal_limit(void * handle,uint32_t * limit)2615 static int smu_get_apu_thermal_limit(void *handle, uint32_t *limit)
2616 {
2617 int ret = -EINVAL;
2618 struct smu_context *smu = handle;
2619
2620 if (smu->ppt_funcs && smu->ppt_funcs->get_apu_thermal_limit)
2621 ret = smu->ppt_funcs->get_apu_thermal_limit(smu, limit);
2622
2623 return ret;
2624 }
2625
smu_set_apu_thermal_limit(void * handle,uint32_t limit)2626 static int smu_set_apu_thermal_limit(void *handle, uint32_t limit)
2627 {
2628 int ret = -EINVAL;
2629 struct smu_context *smu = handle;
2630
2631 if (smu->ppt_funcs && smu->ppt_funcs->set_apu_thermal_limit)
2632 ret = smu->ppt_funcs->set_apu_thermal_limit(smu, limit);
2633
2634 return ret;
2635 }
2636
smu_get_power_profile_mode(void * handle,char * buf)2637 static int smu_get_power_profile_mode(void *handle, char *buf)
2638 {
2639 struct smu_context *smu = handle;
2640
2641 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled ||
2642 !smu->ppt_funcs->get_power_profile_mode)
2643 return -EOPNOTSUPP;
2644 if (!buf)
2645 return -EINVAL;
2646
2647 return smu->ppt_funcs->get_power_profile_mode(smu, buf);
2648 }
2649
smu_set_power_profile_mode(void * handle,long * param,uint32_t param_size)2650 static int smu_set_power_profile_mode(void *handle,
2651 long *param,
2652 uint32_t param_size)
2653 {
2654 struct smu_context *smu = handle;
2655
2656 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled ||
2657 !smu->ppt_funcs->set_power_profile_mode)
2658 return -EOPNOTSUPP;
2659
2660 return smu_bump_power_profile_mode(smu, param, param_size);
2661 }
2662
smu_get_fan_control_mode(void * handle,u32 * fan_mode)2663 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode)
2664 {
2665 struct smu_context *smu = handle;
2666
2667 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2668 return -EOPNOTSUPP;
2669
2670 if (!smu->ppt_funcs->get_fan_control_mode)
2671 return -EOPNOTSUPP;
2672
2673 if (!fan_mode)
2674 return -EINVAL;
2675
2676 *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu);
2677
2678 return 0;
2679 }
2680
smu_set_fan_control_mode(void * handle,u32 value)2681 static int smu_set_fan_control_mode(void *handle, u32 value)
2682 {
2683 struct smu_context *smu = handle;
2684 int ret = 0;
2685
2686 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2687 return -EOPNOTSUPP;
2688
2689 if (!smu->ppt_funcs->set_fan_control_mode)
2690 return -EOPNOTSUPP;
2691
2692 if (value == U32_MAX)
2693 return -EINVAL;
2694
2695 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2696 if (ret)
2697 goto out;
2698
2699 if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2700 smu->user_dpm_profile.fan_mode = value;
2701
2702 /* reset user dpm fan speed */
2703 if (value != AMD_FAN_CTRL_MANUAL) {
2704 smu->user_dpm_profile.fan_speed_pwm = 0;
2705 smu->user_dpm_profile.fan_speed_rpm = 0;
2706 smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM);
2707 }
2708 }
2709
2710 out:
2711 return ret;
2712 }
2713
smu_get_fan_speed_pwm(void * handle,u32 * speed)2714 static int smu_get_fan_speed_pwm(void *handle, u32 *speed)
2715 {
2716 struct smu_context *smu = handle;
2717 int ret = 0;
2718
2719 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2720 return -EOPNOTSUPP;
2721
2722 if (!smu->ppt_funcs->get_fan_speed_pwm)
2723 return -EOPNOTSUPP;
2724
2725 if (!speed)
2726 return -EINVAL;
2727
2728 ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed);
2729
2730 return ret;
2731 }
2732
smu_set_fan_speed_pwm(void * handle,u32 speed)2733 static int smu_set_fan_speed_pwm(void *handle, u32 speed)
2734 {
2735 struct smu_context *smu = handle;
2736 int ret = 0;
2737
2738 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2739 return -EOPNOTSUPP;
2740
2741 if (!smu->ppt_funcs->set_fan_speed_pwm)
2742 return -EOPNOTSUPP;
2743
2744 if (speed == U32_MAX)
2745 return -EINVAL;
2746
2747 ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed);
2748 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2749 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM;
2750 smu->user_dpm_profile.fan_speed_pwm = speed;
2751
2752 /* Override custom RPM setting as they cannot co-exist */
2753 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM;
2754 smu->user_dpm_profile.fan_speed_rpm = 0;
2755 }
2756
2757 return ret;
2758 }
2759
smu_get_fan_speed_rpm(void * handle,uint32_t * speed)2760 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed)
2761 {
2762 struct smu_context *smu = handle;
2763 int ret = 0;
2764
2765 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2766 return -EOPNOTSUPP;
2767
2768 if (!smu->ppt_funcs->get_fan_speed_rpm)
2769 return -EOPNOTSUPP;
2770
2771 if (!speed)
2772 return -EINVAL;
2773
2774 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
2775
2776 return ret;
2777 }
2778
smu_set_deep_sleep_dcefclk(void * handle,uint32_t clk)2779 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk)
2780 {
2781 struct smu_context *smu = handle;
2782
2783 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2784 return -EOPNOTSUPP;
2785
2786 return smu_set_min_dcef_deep_sleep(smu, clk);
2787 }
2788
smu_get_clock_by_type_with_latency(void * handle,enum amd_pp_clock_type type,struct pp_clock_levels_with_latency * clocks)2789 static int smu_get_clock_by_type_with_latency(void *handle,
2790 enum amd_pp_clock_type type,
2791 struct pp_clock_levels_with_latency *clocks)
2792 {
2793 struct smu_context *smu = handle;
2794 enum smu_clk_type clk_type;
2795 int ret = 0;
2796
2797 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2798 return -EOPNOTSUPP;
2799
2800 if (smu->ppt_funcs->get_clock_by_type_with_latency) {
2801 switch (type) {
2802 case amd_pp_sys_clock:
2803 clk_type = SMU_GFXCLK;
2804 break;
2805 case amd_pp_mem_clock:
2806 clk_type = SMU_MCLK;
2807 break;
2808 case amd_pp_dcef_clock:
2809 clk_type = SMU_DCEFCLK;
2810 break;
2811 case amd_pp_disp_clock:
2812 clk_type = SMU_DISPCLK;
2813 break;
2814 default:
2815 dev_err(smu->adev->dev, "Invalid clock type!\n");
2816 return -EINVAL;
2817 }
2818
2819 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2820 }
2821
2822 return ret;
2823 }
2824
smu_display_clock_voltage_request(void * handle,struct pp_display_clock_request * clock_req)2825 static int smu_display_clock_voltage_request(void *handle,
2826 struct pp_display_clock_request *clock_req)
2827 {
2828 struct smu_context *smu = handle;
2829 int ret = 0;
2830
2831 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2832 return -EOPNOTSUPP;
2833
2834 if (smu->ppt_funcs->display_clock_voltage_request)
2835 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2836
2837 return ret;
2838 }
2839
2840
smu_display_disable_memory_clock_switch(void * handle,bool disable_memory_clock_switch)2841 static int smu_display_disable_memory_clock_switch(void *handle,
2842 bool disable_memory_clock_switch)
2843 {
2844 struct smu_context *smu = handle;
2845 int ret = -EINVAL;
2846
2847 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2848 return -EOPNOTSUPP;
2849
2850 if (smu->ppt_funcs->display_disable_memory_clock_switch)
2851 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2852
2853 return ret;
2854 }
2855
smu_set_xgmi_pstate(void * handle,uint32_t pstate)2856 static int smu_set_xgmi_pstate(void *handle,
2857 uint32_t pstate)
2858 {
2859 struct smu_context *smu = handle;
2860 int ret = 0;
2861
2862 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2863 return -EOPNOTSUPP;
2864
2865 if (smu->ppt_funcs->set_xgmi_pstate)
2866 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2867
2868 if (ret)
2869 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n");
2870
2871 return ret;
2872 }
2873
smu_get_baco_capability(void * handle,bool * cap)2874 static int smu_get_baco_capability(void *handle, bool *cap)
2875 {
2876 struct smu_context *smu = handle;
2877
2878 *cap = false;
2879
2880 if (!smu->pm_enabled)
2881 return 0;
2882
2883 if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
2884 *cap = smu->ppt_funcs->baco_is_support(smu);
2885
2886 return 0;
2887 }
2888
smu_baco_set_state(void * handle,int state)2889 static int smu_baco_set_state(void *handle, int state)
2890 {
2891 struct smu_context *smu = handle;
2892 int ret = 0;
2893
2894 if (!smu->pm_enabled)
2895 return -EOPNOTSUPP;
2896
2897 if (state == 0) {
2898 if (smu->ppt_funcs->baco_exit)
2899 ret = smu->ppt_funcs->baco_exit(smu);
2900 } else if (state == 1) {
2901 if (smu->ppt_funcs->baco_enter)
2902 ret = smu->ppt_funcs->baco_enter(smu);
2903 } else {
2904 return -EINVAL;
2905 }
2906
2907 if (ret)
2908 dev_err(smu->adev->dev, "Failed to %s BACO state!\n",
2909 (state)?"enter":"exit");
2910
2911 return ret;
2912 }
2913
smu_mode1_reset_is_support(struct smu_context * smu)2914 bool smu_mode1_reset_is_support(struct smu_context *smu)
2915 {
2916 bool ret = false;
2917
2918 if (!smu->pm_enabled)
2919 return false;
2920
2921 if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support)
2922 ret = smu->ppt_funcs->mode1_reset_is_support(smu);
2923
2924 return ret;
2925 }
2926
smu_mode2_reset_is_support(struct smu_context * smu)2927 bool smu_mode2_reset_is_support(struct smu_context *smu)
2928 {
2929 bool ret = false;
2930
2931 if (!smu->pm_enabled)
2932 return false;
2933
2934 if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support)
2935 ret = smu->ppt_funcs->mode2_reset_is_support(smu);
2936
2937 return ret;
2938 }
2939
smu_mode1_reset(struct smu_context * smu)2940 int smu_mode1_reset(struct smu_context *smu)
2941 {
2942 int ret = 0;
2943
2944 if (!smu->pm_enabled)
2945 return -EOPNOTSUPP;
2946
2947 if (smu->ppt_funcs->mode1_reset)
2948 ret = smu->ppt_funcs->mode1_reset(smu);
2949
2950 return ret;
2951 }
2952
smu_mode2_reset(void * handle)2953 static int smu_mode2_reset(void *handle)
2954 {
2955 struct smu_context *smu = handle;
2956 int ret = 0;
2957
2958 if (!smu->pm_enabled)
2959 return -EOPNOTSUPP;
2960
2961 if (smu->ppt_funcs->mode2_reset)
2962 ret = smu->ppt_funcs->mode2_reset(smu);
2963
2964 if (ret)
2965 dev_err(smu->adev->dev, "Mode2 reset failed!\n");
2966
2967 return ret;
2968 }
2969
smu_enable_gfx_features(void * handle)2970 static int smu_enable_gfx_features(void *handle)
2971 {
2972 struct smu_context *smu = handle;
2973 int ret = 0;
2974
2975 if (!smu->pm_enabled)
2976 return -EOPNOTSUPP;
2977
2978 if (smu->ppt_funcs->enable_gfx_features)
2979 ret = smu->ppt_funcs->enable_gfx_features(smu);
2980
2981 if (ret)
2982 dev_err(smu->adev->dev, "enable gfx features failed!\n");
2983
2984 return ret;
2985 }
2986
smu_get_max_sustainable_clocks_by_dc(void * handle,struct pp_smu_nv_clock_table * max_clocks)2987 static int smu_get_max_sustainable_clocks_by_dc(void *handle,
2988 struct pp_smu_nv_clock_table *max_clocks)
2989 {
2990 struct smu_context *smu = handle;
2991 int ret = 0;
2992
2993 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2994 return -EOPNOTSUPP;
2995
2996 if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2997 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2998
2999 return ret;
3000 }
3001
smu_get_uclk_dpm_states(void * handle,unsigned int * clock_values_in_khz,unsigned int * num_states)3002 static int smu_get_uclk_dpm_states(void *handle,
3003 unsigned int *clock_values_in_khz,
3004 unsigned int *num_states)
3005 {
3006 struct smu_context *smu = handle;
3007 int ret = 0;
3008
3009 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3010 return -EOPNOTSUPP;
3011
3012 if (smu->ppt_funcs->get_uclk_dpm_states)
3013 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
3014
3015 return ret;
3016 }
3017
smu_get_current_power_state(void * handle)3018 static enum amd_pm_state_type smu_get_current_power_state(void *handle)
3019 {
3020 struct smu_context *smu = handle;
3021 enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
3022
3023 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3024 return -EOPNOTSUPP;
3025
3026 if (smu->ppt_funcs->get_current_power_state)
3027 pm_state = smu->ppt_funcs->get_current_power_state(smu);
3028
3029 return pm_state;
3030 }
3031
smu_get_dpm_clock_table(void * handle,struct dpm_clocks * clock_table)3032 static int smu_get_dpm_clock_table(void *handle,
3033 struct dpm_clocks *clock_table)
3034 {
3035 struct smu_context *smu = handle;
3036 int ret = 0;
3037
3038 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3039 return -EOPNOTSUPP;
3040
3041 if (smu->ppt_funcs->get_dpm_clock_table)
3042 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
3043
3044 return ret;
3045 }
3046
smu_sys_get_gpu_metrics(void * handle,void ** table)3047 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table)
3048 {
3049 struct smu_context *smu = handle;
3050
3051 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3052 return -EOPNOTSUPP;
3053
3054 if (!smu->ppt_funcs->get_gpu_metrics)
3055 return -EOPNOTSUPP;
3056
3057 return smu->ppt_funcs->get_gpu_metrics(smu, table);
3058 }
3059
smu_enable_mgpu_fan_boost(void * handle)3060 static int smu_enable_mgpu_fan_boost(void *handle)
3061 {
3062 struct smu_context *smu = handle;
3063 int ret = 0;
3064
3065 if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
3066 return -EOPNOTSUPP;
3067
3068 if (smu->ppt_funcs->enable_mgpu_fan_boost)
3069 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu);
3070
3071 return ret;
3072 }
3073
smu_gfx_state_change_set(void * handle,uint32_t state)3074 static int smu_gfx_state_change_set(void *handle,
3075 uint32_t state)
3076 {
3077 struct smu_context *smu = handle;
3078 int ret = 0;
3079
3080 if (smu->ppt_funcs->gfx_state_change_set)
3081 ret = smu->ppt_funcs->gfx_state_change_set(smu, state);
3082
3083 return ret;
3084 }
3085
smu_handle_passthrough_sbr(struct smu_context * smu,bool enable)3086 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable)
3087 {
3088 int ret = 0;
3089
3090 if (smu->ppt_funcs->smu_handle_passthrough_sbr)
3091 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable);
3092
3093 return ret;
3094 }
3095
smu_get_ecc_info(struct smu_context * smu,void * umc_ecc)3096 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc)
3097 {
3098 int ret = -EOPNOTSUPP;
3099
3100 if (smu->ppt_funcs &&
3101 smu->ppt_funcs->get_ecc_info)
3102 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc);
3103
3104 return ret;
3105
3106 }
3107
smu_get_prv_buffer_details(void * handle,void ** addr,size_t * size)3108 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size)
3109 {
3110 struct smu_context *smu = handle;
3111 struct smu_table_context *smu_table = &smu->smu_table;
3112 struct smu_table *memory_pool = &smu_table->memory_pool;
3113
3114 if (!addr || !size)
3115 return -EINVAL;
3116
3117 *addr = NULL;
3118 *size = 0;
3119 if (memory_pool->bo) {
3120 *addr = memory_pool->cpu_addr;
3121 *size = memory_pool->size;
3122 }
3123
3124 return 0;
3125 }
3126
3127 static const struct amd_pm_funcs swsmu_pm_funcs = {
3128 /* export for sysfs */
3129 .set_fan_control_mode = smu_set_fan_control_mode,
3130 .get_fan_control_mode = smu_get_fan_control_mode,
3131 .set_fan_speed_pwm = smu_set_fan_speed_pwm,
3132 .get_fan_speed_pwm = smu_get_fan_speed_pwm,
3133 .force_clock_level = smu_force_ppclk_levels,
3134 .print_clock_levels = smu_print_ppclk_levels,
3135 .emit_clock_levels = smu_emit_ppclk_levels,
3136 .force_performance_level = smu_force_performance_level,
3137 .read_sensor = smu_read_sensor,
3138 .get_apu_thermal_limit = smu_get_apu_thermal_limit,
3139 .set_apu_thermal_limit = smu_set_apu_thermal_limit,
3140 .get_performance_level = smu_get_performance_level,
3141 .get_current_power_state = smu_get_current_power_state,
3142 .get_fan_speed_rpm = smu_get_fan_speed_rpm,
3143 .set_fan_speed_rpm = smu_set_fan_speed_rpm,
3144 .get_pp_num_states = smu_get_power_num_states,
3145 .get_pp_table = smu_sys_get_pp_table,
3146 .set_pp_table = smu_sys_set_pp_table,
3147 .switch_power_profile = smu_switch_power_profile,
3148 /* export to amdgpu */
3149 .dispatch_tasks = smu_handle_dpm_task,
3150 .load_firmware = smu_load_microcode,
3151 .set_powergating_by_smu = smu_dpm_set_power_gate,
3152 .set_power_limit = smu_set_power_limit,
3153 .get_power_limit = smu_get_power_limit,
3154 .get_power_profile_mode = smu_get_power_profile_mode,
3155 .set_power_profile_mode = smu_set_power_profile_mode,
3156 .odn_edit_dpm_table = smu_od_edit_dpm_table,
3157 .set_mp1_state = smu_set_mp1_state,
3158 .gfx_state_change_set = smu_gfx_state_change_set,
3159 /* export to DC */
3160 .get_sclk = smu_get_sclk,
3161 .get_mclk = smu_get_mclk,
3162 .display_configuration_change = smu_display_configuration_change,
3163 .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency,
3164 .display_clock_voltage_request = smu_display_clock_voltage_request,
3165 .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost,
3166 .set_active_display_count = smu_set_display_count,
3167 .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk,
3168 .get_asic_baco_capability = smu_get_baco_capability,
3169 .set_asic_baco_state = smu_baco_set_state,
3170 .get_ppfeature_status = smu_sys_get_pp_feature_mask,
3171 .set_ppfeature_status = smu_sys_set_pp_feature_mask,
3172 .asic_reset_mode_2 = smu_mode2_reset,
3173 .asic_reset_enable_gfx_features = smu_enable_gfx_features,
3174 .set_df_cstate = smu_set_df_cstate,
3175 .set_xgmi_pstate = smu_set_xgmi_pstate,
3176 .get_gpu_metrics = smu_sys_get_gpu_metrics,
3177 .set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges,
3178 .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch,
3179 .get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc,
3180 .get_uclk_dpm_states = smu_get_uclk_dpm_states,
3181 .get_dpm_clock_table = smu_get_dpm_clock_table,
3182 .get_smu_prv_buf_details = smu_get_prv_buffer_details,
3183 };
3184
smu_wait_for_event(struct smu_context * smu,enum smu_event_type event,uint64_t event_arg)3185 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event,
3186 uint64_t event_arg)
3187 {
3188 int ret = -EINVAL;
3189
3190 if (smu->ppt_funcs->wait_for_event)
3191 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg);
3192
3193 return ret;
3194 }
3195
smu_stb_collect_info(struct smu_context * smu,void * buf,uint32_t size)3196 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size)
3197 {
3198
3199 if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled)
3200 return -EOPNOTSUPP;
3201
3202 /* Confirm the buffer allocated is of correct size */
3203 if (size != smu->stb_context.stb_buf_size)
3204 return -EINVAL;
3205
3206 /*
3207 * No need to lock smu mutex as we access STB directly through MMIO
3208 * and not going through SMU messaging route (for now at least).
3209 * For registers access rely on implementation internal locking.
3210 */
3211 return smu->ppt_funcs->stb_collect_info(smu, buf, size);
3212 }
3213
3214 #if defined(CONFIG_DEBUG_FS)
3215
smu_stb_debugfs_open(struct inode * inode,struct file * filp)3216 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp)
3217 {
3218 struct amdgpu_device *adev = filp->f_inode->i_private;
3219 struct smu_context *smu = adev->powerplay.pp_handle;
3220 unsigned char *buf;
3221 int r;
3222
3223 buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL);
3224 if (!buf)
3225 return -ENOMEM;
3226
3227 r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size);
3228 if (r)
3229 goto out;
3230
3231 filp->private_data = buf;
3232
3233 return 0;
3234
3235 out:
3236 kvfree(buf);
3237 return r;
3238 }
3239
smu_stb_debugfs_read(struct file * filp,char __user * buf,size_t size,loff_t * pos)3240 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
3241 loff_t *pos)
3242 {
3243 struct amdgpu_device *adev = filp->f_inode->i_private;
3244 struct smu_context *smu = adev->powerplay.pp_handle;
3245
3246
3247 if (!filp->private_data)
3248 return -EINVAL;
3249
3250 return simple_read_from_buffer(buf,
3251 size,
3252 pos, filp->private_data,
3253 smu->stb_context.stb_buf_size);
3254 }
3255
smu_stb_debugfs_release(struct inode * inode,struct file * filp)3256 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp)
3257 {
3258 kvfree(filp->private_data);
3259 filp->private_data = NULL;
3260
3261 return 0;
3262 }
3263
3264 /*
3265 * We have to define not only read method but also
3266 * open and release because .read takes up to PAGE_SIZE
3267 * data each time so and so is invoked multiple times.
3268 * We allocate the STB buffer in .open and release it
3269 * in .release
3270 */
3271 static const struct file_operations smu_stb_debugfs_fops = {
3272 .owner = THIS_MODULE,
3273 .open = smu_stb_debugfs_open,
3274 .read = smu_stb_debugfs_read,
3275 .release = smu_stb_debugfs_release,
3276 .llseek = default_llseek,
3277 };
3278
3279 #endif
3280
amdgpu_smu_stb_debug_fs_init(struct amdgpu_device * adev)3281 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev)
3282 {
3283 #if defined(CONFIG_DEBUG_FS)
3284
3285 struct smu_context *smu = adev->powerplay.pp_handle;
3286
3287 if (!smu || (!smu->stb_context.stb_buf_size))
3288 return;
3289
3290 debugfs_create_file_size("amdgpu_smu_stb_dump",
3291 S_IRUSR,
3292 adev_to_drm(adev)->primary->debugfs_root,
3293 adev,
3294 &smu_stb_debugfs_fops,
3295 smu->stb_context.stb_buf_size);
3296 #endif
3297 }
3298
smu_send_hbm_bad_pages_num(struct smu_context * smu,uint32_t size)3299 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size)
3300 {
3301 int ret = 0;
3302
3303 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num)
3304 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size);
3305
3306 return ret;
3307 }
3308
smu_send_hbm_bad_channel_flag(struct smu_context * smu,uint32_t size)3309 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size)
3310 {
3311 int ret = 0;
3312
3313 if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag)
3314 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size);
3315
3316 return ret;
3317 }
3318
