1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef __AMDGPU_DPM_H__ 24 #define __AMDGPU_DPM_H__ 25 26 enum amdgpu_int_thermal_type { 27 THERMAL_TYPE_NONE, 28 THERMAL_TYPE_EXTERNAL, 29 THERMAL_TYPE_EXTERNAL_GPIO, 30 THERMAL_TYPE_RV6XX, 31 THERMAL_TYPE_RV770, 32 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 33 THERMAL_TYPE_EVERGREEN, 34 THERMAL_TYPE_SUMO, 35 THERMAL_TYPE_NI, 36 THERMAL_TYPE_SI, 37 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 38 THERMAL_TYPE_CI, 39 THERMAL_TYPE_KV, 40 }; 41 42 enum amdgpu_dpm_auto_throttle_src { 43 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, 44 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL 45 }; 46 47 enum amdgpu_dpm_event_src { 48 AMDGPU_DPM_EVENT_SRC_ANALOG = 0, 49 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1, 50 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2, 51 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 52 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 53 }; 54 55 struct amdgpu_ps { 56 u32 caps; /* vbios flags */ 57 u32 class; /* vbios flags */ 58 u32 class2; /* vbios flags */ 59 /* UVD clocks */ 60 u32 vclk; 61 u32 dclk; 62 /* VCE clocks */ 63 u32 evclk; 64 u32 ecclk; 65 bool vce_active; 66 enum amd_vce_level vce_level; 67 /* asic priv */ 68 void *ps_priv; 69 }; 70 71 struct amdgpu_dpm_thermal { 72 /* thermal interrupt work */ 73 struct work_struct work; 74 /* low temperature threshold */ 75 int min_temp; 76 /* high temperature threshold */ 77 int max_temp; 78 /* edge max emergency(shutdown) temp */ 79 int max_edge_emergency_temp; 80 /* hotspot low temperature threshold */ 81 int min_hotspot_temp; 82 /* hotspot high temperature critical threshold */ 83 int max_hotspot_crit_temp; 84 /* hotspot max emergency(shutdown) temp */ 85 int max_hotspot_emergency_temp; 86 /* memory low temperature threshold */ 87 int min_mem_temp; 88 /* memory high temperature critical threshold */ 89 int max_mem_crit_temp; 90 /* memory max emergency(shutdown) temp */ 91 int max_mem_emergency_temp; 92 /* was last interrupt low to high or high to low */ 93 bool high_to_low; 94 /* interrupt source */ 95 struct amdgpu_irq_src irq; 96 }; 97 98 enum amdgpu_clk_action 99 { 100 AMDGPU_SCLK_UP = 1, 101 AMDGPU_SCLK_DOWN 102 }; 103 104 struct amdgpu_blacklist_clocks 105 { 106 u32 sclk; 107 u32 mclk; 108 enum amdgpu_clk_action action; 109 }; 110 111 struct amdgpu_clock_and_voltage_limits { 112 u32 sclk; 113 u32 mclk; 114 u16 vddc; 115 u16 vddci; 116 }; 117 118 struct amdgpu_clock_array { 119 u32 count; 120 u32 *values; 121 }; 122 123 struct amdgpu_clock_voltage_dependency_entry { 124 u32 clk; 125 u16 v; 126 }; 127 128 struct amdgpu_clock_voltage_dependency_table { 129 u32 count; 130 struct amdgpu_clock_voltage_dependency_entry *entries; 131 }; 132 133 union amdgpu_cac_leakage_entry { 134 struct { 135 u16 vddc; 136 u32 leakage; 137 }; 138 struct { 139 u16 vddc1; 140 u16 vddc2; 141 u16 vddc3; 142 }; 143 }; 144 145 struct amdgpu_cac_leakage_table { 146 u32 count; 147 union amdgpu_cac_leakage_entry *entries; 148 }; 149 150 struct amdgpu_phase_shedding_limits_entry { 151 u16 voltage; 152 u32 sclk; 153 u32 mclk; 154 }; 155 156 struct amdgpu_phase_shedding_limits_table { 157 u32 count; 158 struct amdgpu_phase_shedding_limits_entry *entries; 159 }; 160 161 struct amdgpu_uvd_clock_voltage_dependency_entry { 162 u32 vclk; 163 u32 dclk; 164 u16 v; 165 }; 166 167 struct amdgpu_uvd_clock_voltage_dependency_table { 168 u8 count; 169 struct amdgpu_uvd_clock_voltage_dependency_entry *entries; 170 }; 171 172 struct amdgpu_vce_clock_voltage_dependency_entry { 173 u32 ecclk; 174 u32 evclk; 175 u16 v; 176 }; 177 178 struct amdgpu_vce_clock_voltage_dependency_table { 179 u8 count; 180 struct amdgpu_vce_clock_voltage_dependency_entry *entries; 181 }; 182 183 struct amdgpu_ppm_table { 184 u8 ppm_design; 185 u16 cpu_core_number; 186 u32 platform_tdp; 187 u32 small_ac_platform_tdp; 188 u32 platform_tdc; 189 u32 small_ac_platform_tdc; 190 u32 apu_tdp; 191 u32 dgpu_tdp; 192 u32 dgpu_ulv_power; 193 u32 tj_max; 194 }; 195 196 struct amdgpu_cac_tdp_table { 197 u16 tdp; 198 u16 configurable_tdp; 199 u16 tdc; 200 u16 battery_power_limit; 201 u16 small_power_limit; 202 u16 low_cac_leakage; 203 u16 high_cac_leakage; 204 u16 maximum_power_delivery_limit; 205 }; 206 207 struct amdgpu_dpm_dynamic_state { 208 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; 209 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; 210 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; 211 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; 212 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; 213 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 214 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 215 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 216 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 217 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; 218 struct amdgpu_clock_array valid_sclk_values; 219 struct amdgpu_clock_array valid_mclk_values; 220 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; 221 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; 222 u32 mclk_sclk_ratio; 223 u32 sclk_mclk_delta; 224 u16 vddc_vddci_delta; 225 u16 min_vddc_for_pcie_gen2; 226 struct amdgpu_cac_leakage_table cac_leakage_table; 227 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; 228 struct amdgpu_ppm_table *ppm_table; 229 struct amdgpu_cac_tdp_table *cac_tdp_table; 230 }; 231 232 struct amdgpu_dpm_fan { 233 u16 t_min; 234 u16 t_med; 235 u16 t_high; 236 u16 pwm_min; 237 u16 pwm_med; 238 u16 pwm_high; 239 u8 t_hyst; 240 u32 cycle_delay; 241 u16 t_max; 242 u8 control_mode; 243 u16 default_max_fan_pwm; 244 u16 default_fan_output_sensitivity; 245 u16 fan_output_sensitivity; 246 bool ucode_fan_control; 247 }; 248 249 enum amdgpu_pcie_gen { 250 AMDGPU_PCIE_GEN1 = 0, 251 AMDGPU_PCIE_GEN2 = 1, 252 AMDGPU_PCIE_GEN3 = 2, 253 AMDGPU_PCIE_GEN_INVALID = 0xffff 254 }; 255 256 #define amdgpu_dpm_pre_set_power_state(adev) \ 257 ((adev)->powerplay.pp_funcs->pre_set_power_state((adev)->powerplay.pp_handle)) 258 259 #define amdgpu_dpm_set_power_state(adev) \ 260 ((adev)->powerplay.pp_funcs->set_power_state((adev)->powerplay.pp_handle)) 261 262 #define amdgpu_dpm_post_set_power_state(adev) \ 263 ((adev)->powerplay.pp_funcs->post_set_power_state((adev)->powerplay.pp_handle)) 264 265 #define amdgpu_dpm_display_configuration_changed(adev) \ 266 ((adev)->powerplay.pp_funcs->display_configuration_changed((adev)->powerplay.pp_handle)) 267 268 #define amdgpu_dpm_print_power_state(adev, ps) \ 269 ((adev)->powerplay.pp_funcs->print_power_state((adev)->powerplay.pp_handle, (ps))) 270 271 #define amdgpu_dpm_vblank_too_short(adev) \ 272 ((adev)->powerplay.pp_funcs->vblank_too_short((adev)->powerplay.pp_handle)) 273 274 #define amdgpu_dpm_enable_bapm(adev, e) \ 275 ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e))) 276 277 #define amdgpu_dpm_set_fan_control_mode(adev, m) \ 278 ((adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m))) 279 280 #define amdgpu_dpm_get_fan_control_mode(adev) \ 281 ((adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle)) 282 283 #define amdgpu_dpm_set_fan_speed_percent(adev, s) \ 284 ((adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s))) 285 286 #define amdgpu_dpm_get_fan_speed_percent(adev, s) \ 287 ((adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s))) 288 289 #define amdgpu_dpm_get_fan_speed_rpm(adev, s) \ 290 ((adev)->powerplay.pp_funcs->get_fan_speed_rpm)((adev)->powerplay.pp_handle, (s)) 291 292 #define amdgpu_dpm_set_fan_speed_rpm(adev, s) \ 293 ((adev)->powerplay.pp_funcs->set_fan_speed_rpm)((adev)->powerplay.pp_handle, (s)) 294 295 #define amdgpu_dpm_force_performance_level(adev, l) \ 296 ((adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l))) 297 298 #define amdgpu_dpm_get_current_power_state(adev) \ 299 ((adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)) 300 301 #define amdgpu_smu_get_current_power_state(adev) \ 302 ((adev)->smu.ppt_funcs->get_current_power_state(&((adev)->smu))) 303 304 #define amdgpu_smu_set_power_state(adev) \ 305 ((adev)->smu.ppt_funcs->set_power_state(&((adev)->smu))) 306 307 #define amdgpu_dpm_get_pp_num_states(adev, data) \ 308 ((adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)) 309 310 #define amdgpu_dpm_get_pp_table(adev, table) \ 311 ((adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)) 312 313 #define amdgpu_dpm_set_pp_table(adev, buf, size) \ 314 ((adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)) 315 316 #define amdgpu_dpm_print_clock_levels(adev, type, buf) \ 317 ((adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)) 318 319 #define amdgpu_dpm_force_clock_level(adev, type, level) \ 320 ((adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)) 321 322 #define amdgpu_dpm_get_sclk_od(adev) \ 323 ((adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle)) 324 325 #define amdgpu_dpm_set_sclk_od(adev, value) \ 326 ((adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value)) 327 328 #define amdgpu_dpm_get_mclk_od(adev) \ 329 ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle)) 330 331 #define amdgpu_dpm_set_mclk_od(adev, value) \ 332 ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value)) 333 334 #define amdgpu_dpm_dispatch_task(adev, task_id, user_state) \ 335 ((adev)->powerplay.pp_funcs->dispatch_tasks)((adev)->powerplay.pp_handle, (task_id), (user_state)) 336 337 #define amdgpu_dpm_check_state_equal(adev, cps, rps, equal) \ 338 ((adev)->powerplay.pp_funcs->check_state_equal((adev)->powerplay.pp_handle, (cps), (rps), (equal))) 339 340 #define amdgpu_dpm_get_vce_clock_state(adev, i) \ 341 ((adev)->powerplay.pp_funcs->get_vce_clock_state((adev)->powerplay.pp_handle, (i))) 342 343 #define amdgpu_dpm_get_performance_level(adev) \ 344 ((adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)) 345 346 #define amdgpu_dpm_reset_power_profile_state(adev, request) \ 347 ((adev)->powerplay.pp_funcs->reset_power_profile_state(\ 348 (adev)->powerplay.pp_handle, request)) 349 350 #define amdgpu_dpm_switch_power_profile(adev, type, en) \ 351 ((adev)->powerplay.pp_funcs->switch_power_profile(\ 352 (adev)->powerplay.pp_handle, type, en)) 353 354 #define amdgpu_dpm_set_clockgating_by_smu(adev, msg_id) \ 355 ((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\ 356 (adev)->powerplay.pp_handle, msg_id)) 357 358 #define amdgpu_dpm_get_power_profile_mode(adev, buf) \ 359 ((adev)->powerplay.pp_funcs->get_power_profile_mode(\ 360 (adev)->powerplay.pp_handle, buf)) 361 362 #define amdgpu_dpm_set_power_profile_mode(adev, parameter, size) \ 363 ((adev)->powerplay.pp_funcs->set_power_profile_mode(\ 364 (adev)->powerplay.pp_handle, parameter, size)) 365 366 #define amdgpu_dpm_odn_edit_dpm_table(adev, type, parameter, size) \ 367 ((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\ 368 (adev)->powerplay.pp_handle, type, parameter, size)) 369 370 #define amdgpu_dpm_enable_mgpu_fan_boost(adev) \ 371 ((adev)->powerplay.pp_funcs->enable_mgpu_fan_boost(\ 372 (adev)->powerplay.pp_handle)) 373 374 #define amdgpu_dpm_get_ppfeature_status(adev, buf) \ 375 ((adev)->powerplay.pp_funcs->get_ppfeature_status(\ 376 (adev)->powerplay.pp_handle, (buf))) 377 378 #define amdgpu_dpm_set_ppfeature_status(adev, ppfeatures) \ 379 ((adev)->powerplay.pp_funcs->set_ppfeature_status(\ 380 (adev)->powerplay.pp_handle, (ppfeatures))) 381 382 struct amdgpu_dpm { 383 struct amdgpu_ps *ps; 384 /* number of valid power states */ 385 int num_ps; 386 /* current power state that is active */ 387 struct amdgpu_ps *current_ps; 388 /* requested power state */ 389 struct amdgpu_ps *requested_ps; 390 /* boot up power state */ 391 struct amdgpu_ps *boot_ps; 392 /* default uvd power state */ 393 struct amdgpu_ps *uvd_ps; 394 /* vce requirements */ 395 u32 num_of_vce_states; 396 struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS]; 397 enum amd_vce_level vce_level; 398 enum amd_pm_state_type state; 399 enum amd_pm_state_type user_state; 400 enum amd_pm_state_type last_state; 401 enum amd_pm_state_type last_user_state; 402 u32 platform_caps; 403 u32 voltage_response_time; 404 u32 backbias_response_time; 405 void *priv; 406 u32 new_active_crtcs; 407 int new_active_crtc_count; 408 u32 current_active_crtcs; 409 int current_active_crtc_count; 410 struct amdgpu_dpm_dynamic_state dyn_state; 411 struct amdgpu_dpm_fan fan; 412 u32 tdp_limit; 413 u32 near_tdp_limit; 414 u32 near_tdp_limit_adjusted; 415 u32 sq_ramping_threshold; 416 u32 cac_leakage; 417 u16 tdp_od_limit; 418 u32 tdp_adjustment; 419 u16 load_line_slope; 420 bool power_control; 421 /* special states active */ 422 bool thermal_active; 423 bool uvd_active; 424 bool vce_active; 425 /* thermal handling */ 426 struct amdgpu_dpm_thermal thermal; 427 /* forced levels */ 428 enum amd_dpm_forced_level forced_level; 429 }; 430 431 struct amdgpu_pm { 432 struct mutex mutex; 433 u32 current_sclk; 434 u32 current_mclk; 435 u32 default_sclk; 436 u32 default_mclk; 437 struct amdgpu_i2c_chan *i2c_bus; 438 /* internal thermal controller on rv6xx+ */ 439 enum amdgpu_int_thermal_type int_thermal_type; 440 struct device *int_hwmon_dev; 441 /* fan control parameters */ 442 bool no_fan; 443 u8 fan_pulses_per_revolution; 444 u8 fan_min_rpm; 445 u8 fan_max_rpm; 446 /* dpm */ 447 bool dpm_enabled; 448 bool sysfs_initialized; 449 struct amdgpu_dpm dpm; 450 const struct firmware *fw; /* SMC firmware */ 451 uint32_t fw_version; 452 uint32_t pcie_gen_mask; 453 uint32_t pcie_mlw_mask; 454 struct amd_pp_display_configuration pm_display_cfg;/* set by dc */ 455 uint32_t smu_prv_buffer_size; 456 struct amdgpu_bo *smu_prv_buffer; 457 bool ac_power; 458 /* powerplay feature */ 459 uint32_t pp_feature; 460 461 }; 462 463 #define R600_SSTU_DFLT 0 464 #define R600_SST_DFLT 0x00C8 465 466 /* XXX are these ok? */ 467 #define R600_TEMP_RANGE_MIN (90 * 1000) 468 #define R600_TEMP_RANGE_MAX (120 * 1000) 469 470 #define FDO_PWM_MODE_STATIC 1 471 #define FDO_PWM_MODE_STATIC_RPM 5 472 473 enum amdgpu_td { 474 AMDGPU_TD_AUTO, 475 AMDGPU_TD_UP, 476 AMDGPU_TD_DOWN, 477 }; 478 479 enum amdgpu_display_watermark { 480 AMDGPU_DISPLAY_WATERMARK_LOW = 0, 481 AMDGPU_DISPLAY_WATERMARK_HIGH = 1, 482 }; 483 484 enum amdgpu_display_gap 485 { 486 AMDGPU_PM_DISPLAY_GAP_VBLANK_OR_WM = 0, 487 AMDGPU_PM_DISPLAY_GAP_VBLANK = 1, 488 AMDGPU_PM_DISPLAY_GAP_WATERMARK = 2, 489 AMDGPU_PM_DISPLAY_GAP_IGNORE = 3, 490 }; 491 492 void amdgpu_dpm_print_class_info(u32 class, u32 class2); 493 void amdgpu_dpm_print_cap_info(u32 caps); 494 void amdgpu_dpm_print_ps_status(struct amdgpu_device *adev, 495 struct amdgpu_ps *rps); 496 u32 amdgpu_dpm_get_vblank_time(struct amdgpu_device *adev); 497 u32 amdgpu_dpm_get_vrefresh(struct amdgpu_device *adev); 498 void amdgpu_dpm_get_active_displays(struct amdgpu_device *adev); 499 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor, 500 void *data, uint32_t *size); 501 502 bool amdgpu_is_internal_thermal_sensor(enum amdgpu_int_thermal_type sensor); 503 504 int amdgpu_get_platform_caps(struct amdgpu_device *adev); 505 506 int amdgpu_parse_extended_power_table(struct amdgpu_device *adev); 507 void amdgpu_free_extended_power_table(struct amdgpu_device *adev); 508 509 void amdgpu_add_thermal_controller(struct amdgpu_device *adev); 510 511 enum amdgpu_pcie_gen amdgpu_get_pcie_gen_support(struct amdgpu_device *adev, 512 u32 sys_mask, 513 enum amdgpu_pcie_gen asic_gen, 514 enum amdgpu_pcie_gen default_gen); 515 516 struct amd_vce_state* 517 amdgpu_get_vce_clock_state(void *handle, u32 idx); 518 519 int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, 520 uint32_t block_type, bool gate); 521 522 extern int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low); 523 524 extern int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low); 525 526 #endif 527
