1 /*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <linux/export.h>
38 #include <linux/pci.h>
39 #include <linux/errno.h>
40
41 #include <linux/mlx4/cmd.h>
42 #include <linux/mlx4/device.h>
43 #include <linux/semaphore.h>
44 #include <rdma/ib_smi.h>
45 #include <linux/delay.h>
46 #include <linux/etherdevice.h>
47
48 #include <asm/io.h>
49
50 #include "mlx4.h"
51 #include "fw.h"
52 #include "fw_qos.h"
53 #include "mlx4_stats.h"
54
55 #define CMD_POLL_TOKEN 0xffff
56 #define INBOX_MASK 0xffffffffffffff00ULL
57
58 #define CMD_CHAN_VER 1
59 #define CMD_CHAN_IF_REV 1
60
61 enum {
62 /* command completed successfully: */
63 CMD_STAT_OK = 0x00,
64 /* Internal error (such as a bus error) occurred while processing command: */
65 CMD_STAT_INTERNAL_ERR = 0x01,
66 /* Operation/command not supported or opcode modifier not supported: */
67 CMD_STAT_BAD_OP = 0x02,
68 /* Parameter not supported or parameter out of range: */
69 CMD_STAT_BAD_PARAM = 0x03,
70 /* System not enabled or bad system state: */
71 CMD_STAT_BAD_SYS_STATE = 0x04,
72 /* Attempt to access reserved or unallocaterd resource: */
73 CMD_STAT_BAD_RESOURCE = 0x05,
74 /* Requested resource is currently executing a command, or is otherwise busy: */
75 CMD_STAT_RESOURCE_BUSY = 0x06,
76 /* Required capability exceeds device limits: */
77 CMD_STAT_EXCEED_LIM = 0x08,
78 /* Resource is not in the appropriate state or ownership: */
79 CMD_STAT_BAD_RES_STATE = 0x09,
80 /* Index out of range: */
81 CMD_STAT_BAD_INDEX = 0x0a,
82 /* FW image corrupted: */
83 CMD_STAT_BAD_NVMEM = 0x0b,
84 /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
85 CMD_STAT_ICM_ERROR = 0x0c,
86 /* Attempt to modify a QP/EE which is not in the presumed state: */
87 CMD_STAT_BAD_QP_STATE = 0x10,
88 /* Bad segment parameters (Address/Size): */
89 CMD_STAT_BAD_SEG_PARAM = 0x20,
90 /* Memory Region has Memory Windows bound to: */
91 CMD_STAT_REG_BOUND = 0x21,
92 /* HCA local attached memory not present: */
93 CMD_STAT_LAM_NOT_PRE = 0x22,
94 /* Bad management packet (silently discarded): */
95 CMD_STAT_BAD_PKT = 0x30,
96 /* More outstanding CQEs in CQ than new CQ size: */
97 CMD_STAT_BAD_SIZE = 0x40,
98 /* Multi Function device support required: */
99 CMD_STAT_MULTI_FUNC_REQ = 0x50,
100 };
101
102 enum {
103 HCR_IN_PARAM_OFFSET = 0x00,
104 HCR_IN_MODIFIER_OFFSET = 0x08,
105 HCR_OUT_PARAM_OFFSET = 0x0c,
106 HCR_TOKEN_OFFSET = 0x14,
107 HCR_STATUS_OFFSET = 0x18,
108
109 HCR_OPMOD_SHIFT = 12,
110 HCR_T_BIT = 21,
111 HCR_E_BIT = 22,
112 HCR_GO_BIT = 23
113 };
114
115 enum {
116 GO_BIT_TIMEOUT_MSECS = 10000
117 };
118
119 enum mlx4_vlan_transition {
120 MLX4_VLAN_TRANSITION_VST_VST = 0,
121 MLX4_VLAN_TRANSITION_VST_VGT = 1,
122 MLX4_VLAN_TRANSITION_VGT_VST = 2,
123 MLX4_VLAN_TRANSITION_VGT_VGT = 3,
124 };
125
126
127 struct mlx4_cmd_context {
128 struct completion done;
129 int result;
130 int next;
131 u64 out_param;
132 u16 token;
133 u8 fw_status;
134 };
135
136 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
137 struct mlx4_vhcr_cmd *in_vhcr);
138
mlx4_status_to_errno(u8 status)139 static int mlx4_status_to_errno(u8 status)
140 {
141 static const int trans_table[] = {
142 [CMD_STAT_INTERNAL_ERR] = -EIO,
143 [CMD_STAT_BAD_OP] = -EPERM,
144 [CMD_STAT_BAD_PARAM] = -EINVAL,
145 [CMD_STAT_BAD_SYS_STATE] = -ENXIO,
146 [CMD_STAT_BAD_RESOURCE] = -EBADF,
147 [CMD_STAT_RESOURCE_BUSY] = -EBUSY,
148 [CMD_STAT_EXCEED_LIM] = -ENOMEM,
149 [CMD_STAT_BAD_RES_STATE] = -EBADF,
150 [CMD_STAT_BAD_INDEX] = -EBADF,
151 [CMD_STAT_BAD_NVMEM] = -EFAULT,
152 [CMD_STAT_ICM_ERROR] = -ENFILE,
153 [CMD_STAT_BAD_QP_STATE] = -EINVAL,
154 [CMD_STAT_BAD_SEG_PARAM] = -EFAULT,
155 [CMD_STAT_REG_BOUND] = -EBUSY,
156 [CMD_STAT_LAM_NOT_PRE] = -EAGAIN,
157 [CMD_STAT_BAD_PKT] = -EINVAL,
158 [CMD_STAT_BAD_SIZE] = -ENOMEM,
159 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
160 };
161
162 if (status >= ARRAY_SIZE(trans_table) ||
163 (status != CMD_STAT_OK && trans_table[status] == 0))
164 return -EIO;
165
166 return trans_table[status];
167 }
168
mlx4_errno_to_status(int errno)169 static u8 mlx4_errno_to_status(int errno)
170 {
171 switch (errno) {
172 case -EPERM:
173 return CMD_STAT_BAD_OP;
174 case -EINVAL:
175 return CMD_STAT_BAD_PARAM;
176 case -ENXIO:
177 return CMD_STAT_BAD_SYS_STATE;
178 case -EBUSY:
179 return CMD_STAT_RESOURCE_BUSY;
180 case -ENOMEM:
181 return CMD_STAT_EXCEED_LIM;
182 case -ENFILE:
183 return CMD_STAT_ICM_ERROR;
184 default:
185 return CMD_STAT_INTERNAL_ERR;
186 }
187 }
188
mlx4_internal_err_ret_value(struct mlx4_dev * dev,u16 op,u8 op_modifier)189 static int mlx4_internal_err_ret_value(struct mlx4_dev *dev, u16 op,
190 u8 op_modifier)
191 {
192 switch (op) {
193 case MLX4_CMD_UNMAP_ICM:
194 case MLX4_CMD_UNMAP_ICM_AUX:
195 case MLX4_CMD_UNMAP_FA:
196 case MLX4_CMD_2RST_QP:
197 case MLX4_CMD_HW2SW_EQ:
198 case MLX4_CMD_HW2SW_CQ:
199 case MLX4_CMD_HW2SW_SRQ:
200 case MLX4_CMD_HW2SW_MPT:
201 case MLX4_CMD_CLOSE_HCA:
202 case MLX4_QP_FLOW_STEERING_DETACH:
203 case MLX4_CMD_FREE_RES:
204 case MLX4_CMD_CLOSE_PORT:
205 return CMD_STAT_OK;
206
207 case MLX4_CMD_QP_ATTACH:
208 /* On Detach case return success */
209 if (op_modifier == 0)
210 return CMD_STAT_OK;
211 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
212
213 default:
214 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
215 }
216 }
217
mlx4_closing_cmd_fatal_error(u16 op,u8 fw_status)218 static int mlx4_closing_cmd_fatal_error(u16 op, u8 fw_status)
219 {
220 /* Any error during the closing commands below is considered fatal */
221 if (op == MLX4_CMD_CLOSE_HCA ||
222 op == MLX4_CMD_HW2SW_EQ ||
223 op == MLX4_CMD_HW2SW_CQ ||
224 op == MLX4_CMD_2RST_QP ||
225 op == MLX4_CMD_HW2SW_SRQ ||
226 op == MLX4_CMD_SYNC_TPT ||
227 op == MLX4_CMD_UNMAP_ICM ||
228 op == MLX4_CMD_UNMAP_ICM_AUX ||
229 op == MLX4_CMD_UNMAP_FA)
230 return 1;
231 /* Error on MLX4_CMD_HW2SW_MPT is fatal except when fw status equals
232 * CMD_STAT_REG_BOUND.
233 * This status indicates that memory region has memory windows bound to it
234 * which may result from invalid user space usage and is not fatal.
235 */
236 if (op == MLX4_CMD_HW2SW_MPT && fw_status != CMD_STAT_REG_BOUND)
237 return 1;
238 return 0;
239 }
240
mlx4_cmd_reset_flow(struct mlx4_dev * dev,u16 op,u8 op_modifier,int err)241 static int mlx4_cmd_reset_flow(struct mlx4_dev *dev, u16 op, u8 op_modifier,
242 int err)
243 {
244 /* Only if reset flow is really active return code is based on
245 * command, otherwise current error code is returned.
246 */
247 if (mlx4_internal_err_reset) {
248 mlx4_enter_error_state(dev->persist);
249 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
250 }
251
252 return err;
253 }
254
comm_pending(struct mlx4_dev * dev)255 static int comm_pending(struct mlx4_dev *dev)
256 {
257 struct mlx4_priv *priv = mlx4_priv(dev);
258 u32 status = readl(&priv->mfunc.comm->slave_read);
259
260 return (swab32(status) >> 31) != priv->cmd.comm_toggle;
261 }
262
mlx4_comm_cmd_post(struct mlx4_dev * dev,u8 cmd,u16 param)263 static int mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
264 {
265 struct mlx4_priv *priv = mlx4_priv(dev);
266 u32 val;
267
268 /* To avoid writing to unknown addresses after the device state was
269 * changed to internal error and the function was rest,
270 * check the INTERNAL_ERROR flag which is updated under
271 * device_state_mutex lock.
272 */
273 mutex_lock(&dev->persist->device_state_mutex);
274
275 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
276 mutex_unlock(&dev->persist->device_state_mutex);
277 return -EIO;
278 }
279
280 priv->cmd.comm_toggle ^= 1;
281 val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
282 __raw_writel((__force u32) cpu_to_be32(val),
283 &priv->mfunc.comm->slave_write);
284 mmiowb();
285 mutex_unlock(&dev->persist->device_state_mutex);
286 return 0;
287 }
288
mlx4_comm_cmd_poll(struct mlx4_dev * dev,u8 cmd,u16 param,unsigned long timeout)289 static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
290 unsigned long timeout)
291 {
292 struct mlx4_priv *priv = mlx4_priv(dev);
293 unsigned long end;
294 int err = 0;
295 int ret_from_pending = 0;
296
297 /* First, verify that the master reports correct status */
298 if (comm_pending(dev)) {
299 mlx4_warn(dev, "Communication channel is not idle - my toggle is %d (cmd:0x%x)\n",
300 priv->cmd.comm_toggle, cmd);
301 return -EAGAIN;
302 }
303
304 /* Write command */
305 down(&priv->cmd.poll_sem);
306 if (mlx4_comm_cmd_post(dev, cmd, param)) {
307 /* Only in case the device state is INTERNAL_ERROR,
308 * mlx4_comm_cmd_post returns with an error
309 */
310 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
311 goto out;
312 }
313
314 end = msecs_to_jiffies(timeout) + jiffies;
315 while (comm_pending(dev) && time_before(jiffies, end))
316 cond_resched();
317 ret_from_pending = comm_pending(dev);
318 if (ret_from_pending) {
319 /* check if the slave is trying to boot in the middle of
320 * FLR process. The only non-zero result in the RESET command
321 * is MLX4_DELAY_RESET_SLAVE*/
322 if ((MLX4_COMM_CMD_RESET == cmd)) {
323 err = MLX4_DELAY_RESET_SLAVE;
324 goto out;
325 } else {
326 mlx4_warn(dev, "Communication channel command 0x%x timed out\n",
327 cmd);
328 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
329 }
330 }
331
332 if (err)
333 mlx4_enter_error_state(dev->persist);
334 out:
335 up(&priv->cmd.poll_sem);
336 return err;
337 }
338
mlx4_comm_cmd_wait(struct mlx4_dev * dev,u8 vhcr_cmd,u16 param,u16 op,unsigned long timeout)339 static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 vhcr_cmd,
340 u16 param, u16 op, unsigned long timeout)
341 {
342 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
343 struct mlx4_cmd_context *context;
344 unsigned long end;
345 int err = 0;
346
347 down(&cmd->event_sem);
348
349 spin_lock(&cmd->context_lock);
350 BUG_ON(cmd->free_head < 0);
351 context = &cmd->context[cmd->free_head];
352 context->token += cmd->token_mask + 1;
353 cmd->free_head = context->next;
354 spin_unlock(&cmd->context_lock);
355
356 reinit_completion(&context->done);
357
358 if (mlx4_comm_cmd_post(dev, vhcr_cmd, param)) {
359 /* Only in case the device state is INTERNAL_ERROR,
360 * mlx4_comm_cmd_post returns with an error
361 */
362 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
363 goto out;
364 }
365
366 if (!wait_for_completion_timeout(&context->done,
367 msecs_to_jiffies(timeout))) {
368 mlx4_warn(dev, "communication channel command 0x%x (op=0x%x) timed out\n",
369 vhcr_cmd, op);
370 goto out_reset;
371 }
372
373 err = context->result;
374 if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
375 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
376 vhcr_cmd, context->fw_status);
377 if (mlx4_closing_cmd_fatal_error(op, context->fw_status))
378 goto out_reset;
379 }
380
381 /* wait for comm channel ready
382 * this is necessary for prevention the race
383 * when switching between event to polling mode
384 * Skipping this section in case the device is in FATAL_ERROR state,
385 * In this state, no commands are sent via the comm channel until
386 * the device has returned from reset.
387 */
388 if (!(dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)) {
389 end = msecs_to_jiffies(timeout) + jiffies;
390 while (comm_pending(dev) && time_before(jiffies, end))
391 cond_resched();
392 }
393 goto out;
394
395 out_reset:
396 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
397 mlx4_enter_error_state(dev->persist);
398 out:
399 spin_lock(&cmd->context_lock);
400 context->next = cmd->free_head;
401 cmd->free_head = context - cmd->context;
402 spin_unlock(&cmd->context_lock);
403
404 up(&cmd->event_sem);
405 return err;
406 }
407
mlx4_comm_cmd(struct mlx4_dev * dev,u8 cmd,u16 param,u16 op,unsigned long timeout)408 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
409 u16 op, unsigned long timeout)
410 {
411 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
412 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
413
414 if (mlx4_priv(dev)->cmd.use_events)
415 return mlx4_comm_cmd_wait(dev, cmd, param, op, timeout);
416 return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
417 }
418
cmd_pending(struct mlx4_dev * dev)419 static int cmd_pending(struct mlx4_dev *dev)
420 {
421 u32 status;
422
423 if (pci_channel_offline(dev->persist->pdev))
424 return -EIO;
425
426 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
427
428 return (status & swab32(1 << HCR_GO_BIT)) ||
429 (mlx4_priv(dev)->cmd.toggle ==
430 !!(status & swab32(1 << HCR_T_BIT)));
431 }
432
mlx4_cmd_post(struct mlx4_dev * dev,u64 in_param,u64 out_param,u32 in_modifier,u8 op_modifier,u16 op,u16 token,int event)433 static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
434 u32 in_modifier, u8 op_modifier, u16 op, u16 token,
435 int event)
436 {
437 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
438 u32 __iomem *hcr = cmd->hcr;
439 int ret = -EIO;
440 unsigned long end;
441
442 mutex_lock(&dev->persist->device_state_mutex);
443 /* To avoid writing to unknown addresses after the device state was
444 * changed to internal error and the chip was reset,
445 * check the INTERNAL_ERROR flag which is updated under
446 * device_state_mutex lock.
447 */
448 if (pci_channel_offline(dev->persist->pdev) ||
449 (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)) {
450 /*
451 * Device is going through error recovery
452 * and cannot accept commands.
453 */
454 goto out;
455 }
456
457 end = jiffies;
458 if (event)
459 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
460
461 while (cmd_pending(dev)) {
462 if (pci_channel_offline(dev->persist->pdev)) {
463 /*
464 * Device is going through error recovery
465 * and cannot accept commands.
466 */
467 goto out;
468 }
469
470 if (time_after_eq(jiffies, end)) {
471 mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
472 goto out;
473 }
474 cond_resched();
475 }
476
477 /*
478 * We use writel (instead of something like memcpy_toio)
479 * because writes of less than 32 bits to the HCR don't work
480 * (and some architectures such as ia64 implement memcpy_toio
481 * in terms of writeb).
482 */
483 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0);
484 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1);
485 __raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2);
486 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3);
487 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
488 __raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5);
489
490 /* __raw_writel may not order writes. */
491 wmb();
492
493 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
494 (cmd->toggle << HCR_T_BIT) |
495 (event ? (1 << HCR_E_BIT) : 0) |
496 (op_modifier << HCR_OPMOD_SHIFT) |
497 op), hcr + 6);
498
499 /*
500 * Make sure that our HCR writes don't get mixed in with
501 * writes from another CPU starting a FW command.
502 */
503 mmiowb();
504
505 cmd->toggle = cmd->toggle ^ 1;
506
507 ret = 0;
508
509 out:
510 if (ret)
511 mlx4_warn(dev, "Could not post command 0x%x: ret=%d, in_param=0x%llx, in_mod=0x%x, op_mod=0x%x\n",
512 op, ret, in_param, in_modifier, op_modifier);
513 mutex_unlock(&dev->persist->device_state_mutex);
514
515 return ret;
516 }
517
mlx4_slave_cmd(struct mlx4_dev * dev,u64 in_param,u64 * out_param,int out_is_imm,u32 in_modifier,u8 op_modifier,u16 op,unsigned long timeout)518 static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
519 int out_is_imm, u32 in_modifier, u8 op_modifier,
520 u16 op, unsigned long timeout)
521 {
522 struct mlx4_priv *priv = mlx4_priv(dev);
523 struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
524 int ret;
525
526 mutex_lock(&priv->cmd.slave_cmd_mutex);
527
528 vhcr->in_param = cpu_to_be64(in_param);
529 vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
530 vhcr->in_modifier = cpu_to_be32(in_modifier);
531 vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
532 vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
533 vhcr->status = 0;
534 vhcr->flags = !!(priv->cmd.use_events) << 6;
535
536 if (mlx4_is_master(dev)) {
537 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
538 if (!ret) {
539 if (out_is_imm) {
540 if (out_param)
541 *out_param =
542 be64_to_cpu(vhcr->out_param);
543 else {
544 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
545 op);
546 vhcr->status = CMD_STAT_BAD_PARAM;
547 }
548 }
549 ret = mlx4_status_to_errno(vhcr->status);
550 }
551 if (ret &&
552 dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
553 ret = mlx4_internal_err_ret_value(dev, op, op_modifier);
554 } else {
555 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0, op,
556 MLX4_COMM_TIME + timeout);
557 if (!ret) {
558 if (out_is_imm) {
559 if (out_param)
560 *out_param =
561 be64_to_cpu(vhcr->out_param);
562 else {
563 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
564 op);
565 vhcr->status = CMD_STAT_BAD_PARAM;
566 }
567 }
568 ret = mlx4_status_to_errno(vhcr->status);
569 } else {
570 if (dev->persist->state &
571 MLX4_DEVICE_STATE_INTERNAL_ERROR)
572 ret = mlx4_internal_err_ret_value(dev, op,
573 op_modifier);
574 else
575 mlx4_err(dev, "failed execution of VHCR_POST command opcode 0x%x\n", op);
576 }
577 }
578
579 mutex_unlock(&priv->cmd.slave_cmd_mutex);
580 return ret;
581 }
582
mlx4_cmd_poll(struct mlx4_dev * dev,u64 in_param,u64 * out_param,int out_is_imm,u32 in_modifier,u8 op_modifier,u16 op,unsigned long timeout)583 static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
584 int out_is_imm, u32 in_modifier, u8 op_modifier,
585 u16 op, unsigned long timeout)
586 {
587 struct mlx4_priv *priv = mlx4_priv(dev);
588 void __iomem *hcr = priv->cmd.hcr;
589 int err = 0;
590 unsigned long end;
591 u32 stat;
592
593 down(&priv->cmd.poll_sem);
594
595 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
596 /*
597 * Device is going through error recovery
598 * and cannot accept commands.
599 */
600 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
601 goto out;
602 }
603
604 if (out_is_imm && !out_param) {
605 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
606 op);
607 err = -EINVAL;
608 goto out;
609 }
610
611 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
612 in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
613 if (err)
614 goto out_reset;
615
616 end = msecs_to_jiffies(timeout) + jiffies;
617 while (cmd_pending(dev) && time_before(jiffies, end)) {
618 if (pci_channel_offline(dev->persist->pdev)) {
619 /*
620 * Device is going through error recovery
621 * and cannot accept commands.
622 */
623 err = -EIO;
624 goto out_reset;
625 }
626
627 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
628 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
629 goto out;
630 }
631
632 cond_resched();
633 }
634
635 if (cmd_pending(dev)) {
636 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
637 op);
638 err = -EIO;
639 goto out_reset;
640 }
641
642 if (out_is_imm)
643 *out_param =
644 (u64) be32_to_cpu((__force __be32)
645 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
646 (u64) be32_to_cpu((__force __be32)
647 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
648 stat = be32_to_cpu((__force __be32)
649 __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
650 err = mlx4_status_to_errno(stat);
651 if (err) {
652 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
653 op, stat);
654 if (mlx4_closing_cmd_fatal_error(op, stat))
655 goto out_reset;
656 goto out;
657 }
658
659 out_reset:
660 if (err)
661 err = mlx4_cmd_reset_flow(dev, op, op_modifier, err);
662 out:
663 up(&priv->cmd.poll_sem);
664 return err;
665 }
666
mlx4_cmd_event(struct mlx4_dev * dev,u16 token,u8 status,u64 out_param)667 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
668 {
669 struct mlx4_priv *priv = mlx4_priv(dev);
670 struct mlx4_cmd_context *context =
671 &priv->cmd.context[token & priv->cmd.token_mask];
672
673 /* previously timed out command completing at long last */
674 if (token != context->token)
675 return;
676
677 context->fw_status = status;
678 context->result = mlx4_status_to_errno(status);
679 context->out_param = out_param;
680
681 complete(&context->done);
682 }
683
mlx4_cmd_wait(struct mlx4_dev * dev,u64 in_param,u64 * out_param,int out_is_imm,u32 in_modifier,u8 op_modifier,u16 op,unsigned long timeout)684 static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
685 int out_is_imm, u32 in_modifier, u8 op_modifier,
686 u16 op, unsigned long timeout)
687 {
688 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
689 struct mlx4_cmd_context *context;
690 long ret_wait;
691 int err = 0;
692
693 down(&cmd->event_sem);
694
695 spin_lock(&cmd->context_lock);
696 BUG_ON(cmd->free_head < 0);
697 context = &cmd->context[cmd->free_head];
698 context->token += cmd->token_mask + 1;
699 cmd->free_head = context->next;
700 spin_unlock(&cmd->context_lock);
701
702 if (out_is_imm && !out_param) {
703 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
704 op);
705 err = -EINVAL;
706 goto out;
707 }
708
709 reinit_completion(&context->done);
710
711 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
712 in_modifier, op_modifier, op, context->token, 1);
713 if (err)
714 goto out_reset;
715
716 if (op == MLX4_CMD_SENSE_PORT) {
717 ret_wait =
718 wait_for_completion_interruptible_timeout(&context->done,
719 msecs_to_jiffies(timeout));
720 if (ret_wait < 0) {
721 context->fw_status = 0;
722 context->out_param = 0;
723 context->result = 0;
724 }
725 } else {
726 ret_wait = (long)wait_for_completion_timeout(&context->done,
727 msecs_to_jiffies(timeout));
728 }
729 if (!ret_wait) {
730 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
731 op);
732 if (op == MLX4_CMD_NOP) {
733 err = -EBUSY;
734 goto out;
735 } else {
736 err = -EIO;
737 goto out_reset;
738 }
739 }
740
741 err = context->result;
742 if (err) {
743 /* Since we do not want to have this error message always
744 * displayed at driver start when there are ConnectX2 HCAs
745 * on the host, we deprecate the error message for this
746 * specific command/input_mod/opcode_mod/fw-status to be debug.
747 */
748 if (op == MLX4_CMD_SET_PORT &&
749 (in_modifier == 1 || in_modifier == 2) &&
750 op_modifier == MLX4_SET_PORT_IB_OPCODE &&
751 context->fw_status == CMD_STAT_BAD_SIZE)
752 mlx4_dbg(dev, "command 0x%x failed: fw status = 0x%x\n",
753 op, context->fw_status);
754 else
755 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
756 op, context->fw_status);
757 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
758 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
759 else if (mlx4_closing_cmd_fatal_error(op, context->fw_status))
760 goto out_reset;
761
762 goto out;
763 }
764
765 if (out_is_imm)
766 *out_param = context->out_param;
767
768 out_reset:
769 if (err)
770 err = mlx4_cmd_reset_flow(dev, op, op_modifier, err);
771 out:
772 spin_lock(&cmd->context_lock);
773 context->next = cmd->free_head;
774 cmd->free_head = context - cmd->context;
775 spin_unlock(&cmd->context_lock);
776
777 up(&cmd->event_sem);
778 return err;
779 }
780
__mlx4_cmd(struct mlx4_dev * dev,u64 in_param,u64 * out_param,int out_is_imm,u32 in_modifier,u8 op_modifier,u16 op,unsigned long timeout,int native)781 int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
782 int out_is_imm, u32 in_modifier, u8 op_modifier,
783 u16 op, unsigned long timeout, int native)
784 {
785 if (pci_channel_offline(dev->persist->pdev))
786 return mlx4_cmd_reset_flow(dev, op, op_modifier, -EIO);
787
788 if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
789 int ret;
790
791 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
792 return mlx4_internal_err_ret_value(dev, op,
793 op_modifier);
794 down_read(&mlx4_priv(dev)->cmd.switch_sem);
795 if (mlx4_priv(dev)->cmd.use_events)
796 ret = mlx4_cmd_wait(dev, in_param, out_param,
797 out_is_imm, in_modifier,
798 op_modifier, op, timeout);
799 else
800 ret = mlx4_cmd_poll(dev, in_param, out_param,
801 out_is_imm, in_modifier,
802 op_modifier, op, timeout);
803
804 up_read(&mlx4_priv(dev)->cmd.switch_sem);
805 return ret;
806 }
807 return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
808 in_modifier, op_modifier, op, timeout);
809 }
810 EXPORT_SYMBOL_GPL(__mlx4_cmd);
811
812
mlx4_ARM_COMM_CHANNEL(struct mlx4_dev * dev)813 int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
814 {
815 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
816 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
817 }
818
mlx4_ACCESS_MEM(struct mlx4_dev * dev,u64 master_addr,int slave,u64 slave_addr,int size,int is_read)819 static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
820 int slave, u64 slave_addr,
821 int size, int is_read)
822 {
823 u64 in_param;
824 u64 out_param;
825
826 if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
827 (slave & ~0x7f) | (size & 0xff)) {
828 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx master_addr:0x%llx slave_id:%d size:%d\n",
829 slave_addr, master_addr, slave, size);
830 return -EINVAL;
831 }
832
833 if (is_read) {
834 in_param = (u64) slave | slave_addr;
835 out_param = (u64) dev->caps.function | master_addr;
836 } else {
837 in_param = (u64) dev->caps.function | master_addr;
838 out_param = (u64) slave | slave_addr;
839 }
840
841 return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
842 MLX4_CMD_ACCESS_MEM,
843 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
844 }
845
query_pkey_block(struct mlx4_dev * dev,u8 port,u16 index,u16 * pkey,struct mlx4_cmd_mailbox * inbox,struct mlx4_cmd_mailbox * outbox)846 static int query_pkey_block(struct mlx4_dev *dev, u8 port, u16 index, u16 *pkey,
847 struct mlx4_cmd_mailbox *inbox,
848 struct mlx4_cmd_mailbox *outbox)
849 {
850 struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf);
851 struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf);
852 int err;
853 int i;
854
855 if (index & 0x1f)
856 return -EINVAL;
857
858 in_mad->attr_mod = cpu_to_be32(index / 32);
859
860 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
861 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
862 MLX4_CMD_NATIVE);
863 if (err)
864 return err;
865
866 for (i = 0; i < 32; ++i)
867 pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]);
868
869 return err;
870 }
871
get_full_pkey_table(struct mlx4_dev * dev,u8 port,u16 * table,struct mlx4_cmd_mailbox * inbox,struct mlx4_cmd_mailbox * outbox)872 static int get_full_pkey_table(struct mlx4_dev *dev, u8 port, u16 *table,
873 struct mlx4_cmd_mailbox *inbox,
874 struct mlx4_cmd_mailbox *outbox)
875 {
876 int i;
877 int err;
878
879 for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) {
880 err = query_pkey_block(dev, port, i, table + i, inbox, outbox);
881 if (err)
882 return err;
883 }
884
885 return 0;
886 }
887 #define PORT_CAPABILITY_LOCATION_IN_SMP 20
888 #define PORT_STATE_OFFSET 32
889
vf_port_state(struct mlx4_dev * dev,int port,int vf)890 static enum ib_port_state vf_port_state(struct mlx4_dev *dev, int port, int vf)
891 {
892 if (mlx4_get_slave_port_state(dev, vf, port) == SLAVE_PORT_UP)
893 return IB_PORT_ACTIVE;
894 else
895 return IB_PORT_DOWN;
896 }
897
mlx4_MAD_IFC_wrapper(struct mlx4_dev * dev,int slave,struct mlx4_vhcr * vhcr,struct mlx4_cmd_mailbox * inbox,struct mlx4_cmd_mailbox * outbox,struct mlx4_cmd_info * cmd)898 static int mlx4_MAD_IFC_wrapper(struct mlx4_dev *dev, int slave,
899 struct mlx4_vhcr *vhcr,
900 struct mlx4_cmd_mailbox *inbox,
901 struct mlx4_cmd_mailbox *outbox,
902 struct mlx4_cmd_info *cmd)
903 {
904 struct ib_smp *smp = inbox->buf;
905 u32 index;
906 u8 port, slave_port;
907 u8 opcode_modifier;
908 u16 *table;
909 int err;
910 int vidx, pidx;
911 int network_view;
912 struct mlx4_priv *priv = mlx4_priv(dev);
913 struct ib_smp *outsmp = outbox->buf;
914 __be16 *outtab = (__be16 *)(outsmp->data);
915 __be32 slave_cap_mask;
916 __be64 slave_node_guid;
917
918 slave_port = vhcr->in_modifier;
919 port = mlx4_slave_convert_port(dev, slave, slave_port);
920
921 /* network-view bit is for driver use only, and should not be passed to FW */
922 opcode_modifier = vhcr->op_modifier & ~0x8; /* clear netw view bit */
923 network_view = !!(vhcr->op_modifier & 0x8);
924
925 if (smp->base_version == 1 &&
926 smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
927 smp->class_version == 1) {
928 /* host view is paravirtualized */
929 if (!network_view && smp->method == IB_MGMT_METHOD_GET) {
930 if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) {
931 index = be32_to_cpu(smp->attr_mod);
932 if (port < 1 || port > dev->caps.num_ports)
933 return -EINVAL;
934 table = kcalloc((dev->caps.pkey_table_len[port] / 32) + 1,
935 sizeof(*table) * 32, GFP_KERNEL);
936
937 if (!table)
938 return -ENOMEM;
939 /* need to get the full pkey table because the paravirtualized
940 * pkeys may be scattered among several pkey blocks.
941 */
942 err = get_full_pkey_table(dev, port, table, inbox, outbox);
943 if (!err) {
944 for (vidx = index * 32; vidx < (index + 1) * 32; ++vidx) {
945 pidx = priv->virt2phys_pkey[slave][port - 1][vidx];
946 outtab[vidx % 32] = cpu_to_be16(table[pidx]);
947 }
948 }
949 kfree(table);
950 return err;
951 }
952 if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) {
953 /*get the slave specific caps:*/
954 /*do the command */
955 smp->attr_mod = cpu_to_be32(port);
956 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
957 port, opcode_modifier,
958 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
959 /* modify the response for slaves */
960 if (!err && slave != mlx4_master_func_num(dev)) {
961 u8 *state = outsmp->data + PORT_STATE_OFFSET;
962
963 *state = (*state & 0xf0) | vf_port_state(dev, port, slave);
964 slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
965 memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4);
966 }
967 return err;
968 }
969 if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) {
970 __be64 guid = mlx4_get_admin_guid(dev, slave,
971 port);
972
973 /* set the PF admin guid to the FW/HW burned
974 * GUID, if it wasn't yet set
975 */
976 if (slave == 0 && guid == 0) {
977 smp->attr_mod = 0;
978 err = mlx4_cmd_box(dev,
979 inbox->dma,
980 outbox->dma,
981 vhcr->in_modifier,
982 opcode_modifier,
983 vhcr->op,
984 MLX4_CMD_TIME_CLASS_C,
985 MLX4_CMD_NATIVE);
986 if (err)
987 return err;
988 mlx4_set_admin_guid(dev,
989 *(__be64 *)outsmp->
990 data, slave, port);
991 } else {
992 memcpy(outsmp->data, &guid, 8);
993 }
994
995 /* clean all other gids */
996 memset(outsmp->data + 8, 0, 56);
997 return 0;
998 }
999 if (smp->attr_id == IB_SMP_ATTR_NODE_INFO) {
1000 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
1001 port, opcode_modifier,
1002 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
1003 if (!err) {
1004 slave_node_guid = mlx4_get_slave_node_guid(dev, slave);
1005 memcpy(outsmp->data + 12, &slave_node_guid, 8);
1006 }
1007 return err;
1008 }
1009 }
1010 }
1011
1012 /* Non-privileged VFs are only allowed "host" view LID-routed 'Get' MADs.
1013 * These are the MADs used by ib verbs (such as ib_query_gids).
1014 */
1015 if (slave != mlx4_master_func_num(dev) &&
1016 !mlx4_vf_smi_enabled(dev, slave, port)) {
1017 if (!(smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
1018 smp->method == IB_MGMT_METHOD_GET) || network_view) {
1019 mlx4_err(dev, "Unprivileged slave %d is trying to execute a Subnet MGMT MAD, class 0x%x, method 0x%x, view=%s for attr 0x%x. Rejecting\n",
1020 slave, smp->mgmt_class, smp->method,
1021 network_view ? "Network" : "Host",
1022 be16_to_cpu(smp->attr_id));
1023 return -EPERM;
1024 }
1025 }
1026
1027 return mlx4_cmd_box(dev, inbox->dma, outbox->dma,
1028 vhcr->in_modifier, opcode_modifier,
1029 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
1030 }
1031
mlx4_CMD_EPERM_wrapper(struct mlx4_dev * dev,int slave,struct mlx4_vhcr * vhcr,struct mlx4_cmd_mailbox * inbox,struct mlx4_cmd_mailbox * outbox,struct mlx4_cmd_info * cmd)1032 static int mlx4_CMD_EPERM_wrapper(struct mlx4_dev *dev, int slave,
1033 struct mlx4_vhcr *vhcr,
1034 struct mlx4_cmd_mailbox *inbox,
1035 struct mlx4_cmd_mailbox *outbox,
1036 struct mlx4_cmd_info *cmd)
1037 {
1038 return -EPERM;
1039 }
1040
mlx4_DMA_wrapper(struct mlx4_dev * dev,int slave,struct mlx4_vhcr * vhcr,struct mlx4_cmd_mailbox * inbox,struct mlx4_cmd_mailbox * outbox,struct mlx4_cmd_info * cmd)1041 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
1042 struct mlx4_vhcr *vhcr,
1043 struct mlx4_cmd_mailbox *inbox,
1044 struct mlx4_cmd_mailbox *outbox,
1045 struct mlx4_cmd_info *cmd)
1046 {
1047 u64 in_param;
1048 u64 out_param;
1049 int err;
1050
1051 in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
1052 out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
1053 if (cmd->encode_slave_id) {
1054 in_param &= 0xffffffffffffff00ll;
1055 in_param |= slave;
1056 }
1057
1058 err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
1059 vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
1060 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1061
1062 if (cmd->out_is_imm)
1063 vhcr->out_param = out_param;
1064
1065 return err;
1066 }
1067
1068 static struct mlx4_cmd_info cmd_info[] = {
1069 {
1070 .opcode = MLX4_CMD_QUERY_FW,
1071 .has_inbox = false,
1072 .has_outbox = true,
1073 .out_is_imm = false,
1074 .encode_slave_id = false,
1075 .verify = NULL,
1076 .wrapper = mlx4_QUERY_FW_wrapper
1077 },
1078 {
1079 .opcode = MLX4_CMD_QUERY_HCA,
1080 .has_inbox = false,
1081 .has_outbox = true,
1082 .out_is_imm = false,
1083 .encode_slave_id = false,
1084 .verify = NULL,
1085 .wrapper = NULL
1086 },
1087 {
1088 .opcode = MLX4_CMD_QUERY_DEV_CAP,
1089 .has_inbox = false,
1090 .has_outbox = true,
1091 .out_is_imm = false,
1092 .encode_slave_id = false,
1093 .verify = NULL,
1094 .wrapper = mlx4_QUERY_DEV_CAP_wrapper
1095 },
1096 {
1097 .opcode = MLX4_CMD_QUERY_FUNC_CAP,
1098 .has_inbox = false,
1099 .has_outbox = true,
1100 .out_is_imm = false,
1101 .encode_slave_id = false,
1102 .verify = NULL,
1103 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper
1104 },
1105 {
1106 .opcode = MLX4_CMD_QUERY_ADAPTER,
1107 .has_inbox = false,
1108 .has_outbox = true,
1109 .out_is_imm = false,
1110 .encode_slave_id = false,
1111 .verify = NULL,
1112 .wrapper = NULL
1113 },
1114 {
1115 .opcode = MLX4_CMD_INIT_PORT,
1116 .has_inbox = false,
1117 .has_outbox = false,
1118 .out_is_imm = false,
1119 .encode_slave_id = false,
1120 .verify = NULL,
1121 .wrapper = mlx4_INIT_PORT_wrapper
1122 },
1123 {
1124 .opcode = MLX4_CMD_CLOSE_PORT,
1125 .has_inbox = false,
1126 .has_outbox = false,
1127 .out_is_imm = false,
1128 .encode_slave_id = false,
1129 .verify = NULL,
1130 .wrapper = mlx4_CLOSE_PORT_wrapper
1131 },
1132 {
1133 .opcode = MLX4_CMD_QUERY_PORT,
1134 .has_inbox = false,
1135 .has_outbox = true,
1136 .out_is_imm = false,
1137 .encode_slave_id = false,
1138 .verify = NULL,
1139 .wrapper = mlx4_QUERY_PORT_wrapper
1140 },
1141 {
1142 .opcode = MLX4_CMD_SET_PORT,
1143 .has_inbox = true,
1144 .has_outbox = false,
1145 .out_is_imm = false,
1146 .encode_slave_id = false,
1147 .verify = NULL,
1148 .wrapper = mlx4_SET_PORT_wrapper
1149 },
1150 {
1151 .opcode = MLX4_CMD_MAP_EQ,
1152 .has_inbox = false,
1153 .has_outbox = false,
1154 .out_is_imm = false,
1155 .encode_slave_id = false,
1156 .verify = NULL,
1157 .wrapper = mlx4_MAP_EQ_wrapper
1158 },
1159 {
1160 .opcode = MLX4_CMD_SW2HW_EQ,
1161 .has_inbox = true,
1162 .has_outbox = false,
1163 .out_is_imm = false,
1164 .encode_slave_id = true,
1165 .verify = NULL,
1166 .wrapper = mlx4_SW2HW_EQ_wrapper
1167 },
1168 {
1169 .opcode = MLX4_CMD_HW_HEALTH_CHECK,
1170 .has_inbox = false,
1171 .has_outbox = false,
1172 .out_is_imm = false,
1173 .encode_slave_id = false,
1174 .verify = NULL,
1175 .wrapper = NULL
1176 },
1177 {
1178 .opcode = MLX4_CMD_NOP,
1179 .has_inbox = false,
1180 .has_outbox = false,
1181 .out_is_imm = false,
1182 .encode_slave_id = false,
1183 .verify = NULL,
1184 .wrapper = NULL
1185 },
1186 {
1187 .opcode = MLX4_CMD_CONFIG_DEV,
1188 .has_inbox = false,
1189 .has_outbox = true,
1190 .out_is_imm = false,
1191 .encode_slave_id = false,
1192 .verify = NULL,
1193 .wrapper = mlx4_CONFIG_DEV_wrapper
1194 },
1195 {
1196 .opcode = MLX4_CMD_ALLOC_RES,
1197 .has_inbox = false,
1198 .has_outbox = false,
1199 .out_is_imm = true,
1200 .encode_slave_id = false,
1201 .verify = NULL,
1202 .wrapper = mlx4_ALLOC_RES_wrapper
1203 },
1204 {
1205 .opcode = MLX4_CMD_FREE_RES,
1206 .has_inbox = false,
1207 .has_outbox = false,
1208 .out_is_imm = false,
1209 .encode_slave_id = false,
1210 .verify = NULL,
1211 .wrapper = mlx4_FREE_RES_wrapper
1212 },
1213 {
1214 .opcode = MLX4_CMD_SW2HW_MPT,
1215 .has_inbox = true,
1216 .has_outbox = false,
1217 .out_is_imm = false,
1218 .encode_slave_id = true,
1219 .verify = NULL,
1220 .wrapper = mlx4_SW2HW_MPT_wrapper
1221 },
1222 {
1223 .opcode = MLX4_CMD_QUERY_MPT,
1224 .has_inbox = false,
1225 .has_outbox = true,
1226 .out_is_imm = false,
1227 .encode_slave_id = false,
1228 .verify = NULL,
1229 .wrapper = mlx4_QUERY_MPT_wrapper
1230 },
1231 {
1232 .opcode = MLX4_CMD_HW2SW_MPT,
1233 .has_inbox = false,
1234 .has_outbox = false,
1235 .out_is_imm = false,
1236 .encode_slave_id = false,
1237 .verify = NULL,
1238 .wrapper = mlx4_HW2SW_MPT_wrapper
1239 },
1240 {
1241 .opcode = MLX4_CMD_READ_MTT,
1242 .has_inbox = false,
1243 .has_outbox = true,
1244 .out_is_imm = false,
1245 .encode_slave_id = false,
1246 .verify = NULL,
1247 .wrapper = NULL
1248 },
1249 {
1250 .opcode = MLX4_CMD_WRITE_MTT,
1251 .has_inbox = true,
1252 .has_outbox = false,
1253 .out_is_imm = false,
1254 .encode_slave_id = false,
1255 .verify = NULL,
1256 .wrapper = mlx4_WRITE_MTT_wrapper
1257 },
1258 {
1259 .opcode = MLX4_CMD_SYNC_TPT,
1260 .has_inbox = true,
1261 .has_outbox = false,
1262 .out_is_imm = false,
1263 .encode_slave_id = false,
1264 .verify = NULL,
1265 .wrapper = NULL
1266 },
1267 {
1268 .opcode = MLX4_CMD_HW2SW_EQ,
1269 .has_inbox = false,
1270 .has_outbox = false,
1271 .out_is_imm = false,
1272 .encode_slave_id = true,
1273 .verify = NULL,
1274 .wrapper = mlx4_HW2SW_EQ_wrapper
1275 },
1276 {
1277 .opcode = MLX4_CMD_QUERY_EQ,
1278 .has_inbox = false,
1279 .has_outbox = true,
1280 .out_is_imm = false,
1281 .encode_slave_id = true,
1282 .verify = NULL,
1283 .wrapper = mlx4_QUERY_EQ_wrapper
1284 },
1285 {
1286 .opcode = MLX4_CMD_SW2HW_CQ,
1287 .has_inbox = true,
1288 .has_outbox = false,
1289 .out_is_imm = false,
1290 .encode_slave_id = true,
1291 .verify = NULL,
1292 .wrapper = mlx4_SW2HW_CQ_wrapper
1293 },
1294 {
1295 .opcode = MLX4_CMD_HW2SW_CQ,
1296 .has_inbox = false,
1297 .has_outbox = false,
1298 .out_is_imm = false,
1299 .encode_slave_id = false,
1300 .verify = NULL,
1301 .wrapper = mlx4_HW2SW_CQ_wrapper
1302 },
1303 {
1304 .opcode = MLX4_CMD_QUERY_CQ,
1305 .has_inbox = false,
1306 .has_outbox = true,
1307 .out_is_imm = false,
1308 .encode_slave_id = false,
1309 .verify = NULL,
1310 .wrapper = mlx4_QUERY_CQ_wrapper
1311 },
1312 {
1313 .opcode = MLX4_CMD_MODIFY_CQ,
1314 .has_inbox = true,
1315 .has_outbox = false,
1316 .out_is_imm = true,
1317 .encode_slave_id = false,
1318 .verify = NULL,
1319 .wrapper = mlx4_MODIFY_CQ_wrapper
1320 },
1321 {
1322 .opcode = MLX4_CMD_SW2HW_SRQ,
1323 .has_inbox = true,
1324 .has_outbox = false,
1325 .out_is_imm = false,
1326 .encode_slave_id = true,
1327 .verify = NULL,
1328 .wrapper = mlx4_SW2HW_SRQ_wrapper
1329 },
1330 {
1331 .opcode = MLX4_CMD_HW2SW_SRQ,
1332 .has_inbox = false,
1333 .has_outbox = false,
1334 .out_is_imm = false,
1335 .encode_slave_id = false,
1336 .verify = NULL,
1337 .wrapper = mlx4_HW2SW_SRQ_wrapper
1338 },
1339 {
1340 .opcode = MLX4_CMD_QUERY_SRQ,
1341 .has_inbox = false,
1342 .has_outbox = true,
1343 .out_is_imm = false,
1344 .encode_slave_id = false,
1345 .verify = NULL,
1346 .wrapper = mlx4_QUERY_SRQ_wrapper
1347 },
1348 {
1349 .opcode = MLX4_CMD_ARM_SRQ,
1350 .has_inbox = false,
1351 .has_outbox = false,
1352 .out_is_imm = false,
1353 .encode_slave_id = false,
1354 .verify = NULL,
1355 .wrapper = mlx4_ARM_SRQ_wrapper
1356 },
1357 {
1358 .opcode = MLX4_CMD_RST2INIT_QP,
1359 .has_inbox = true,
1360 .has_outbox = false,
1361 .out_is_imm = false,
1362 .encode_slave_id = true,
1363 .verify = NULL,
1364 .wrapper = mlx4_RST2INIT_QP_wrapper
1365 },
1366 {
1367 .opcode = MLX4_CMD_INIT2INIT_QP,
1368 .has_inbox = true,
1369 .has_outbox = false,
1370 .out_is_imm = false,
1371 .encode_slave_id = false,
1372 .verify = NULL,
1373 .wrapper = mlx4_INIT2INIT_QP_wrapper
1374 },
1375 {
1376 .opcode = MLX4_CMD_INIT2RTR_QP,
1377 .has_inbox = true,
1378 .has_outbox = false,
1379 .out_is_imm = false,
1380 .encode_slave_id = false,
1381 .verify = NULL,
1382 .wrapper = mlx4_INIT2RTR_QP_wrapper
1383 },
1384 {
1385 .opcode = MLX4_CMD_RTR2RTS_QP,
1386 .has_inbox = true,
1387 .has_outbox = false,
1388 .out_is_imm = false,
1389 .encode_slave_id = false,
1390 .verify = NULL,
1391 .wrapper = mlx4_RTR2RTS_QP_wrapper
1392 },
1393 {
1394 .opcode = MLX4_CMD_RTS2RTS_QP,
1395 .has_inbox = true,
1396 .has_outbox = false,
1397 .out_is_imm = false,
1398 .encode_slave_id = false,
1399 .verify = NULL,
1400 .wrapper = mlx4_RTS2RTS_QP_wrapper
1401 },
1402 {
1403 .opcode = MLX4_CMD_SQERR2RTS_QP,
1404 .has_inbox = true,
1405 .has_outbox = false,
1406 .out_is_imm = false,
1407 .encode_slave_id = false,
1408 .verify = NULL,
1409 .wrapper = mlx4_SQERR2RTS_QP_wrapper
1410 },
1411 {
1412 .opcode = MLX4_CMD_2ERR_QP,
1413 .has_inbox = false,
1414 .has_outbox = false,
1415 .out_is_imm = false,
1416 .encode_slave_id = false,
1417 .verify = NULL,
1418 .wrapper = mlx4_GEN_QP_wrapper
1419 },
1420 {
1421 .opcode = MLX4_CMD_RTS2SQD_QP,
1422 .has_inbox = false,
1423 .has_outbox = false,
1424 .out_is_imm = false,
1425 .encode_slave_id = false,
1426 .verify = NULL,
1427 .wrapper = mlx4_GEN_QP_wrapper
1428 },
1429 {
1430 .opcode = MLX4_CMD_SQD2SQD_QP,
1431 .has_inbox = true,
1432 .has_outbox = false,
1433 .out_is_imm = false,
1434 .encode_slave_id = false,
1435 .verify = NULL,
1436 .wrapper = mlx4_SQD2SQD_QP_wrapper
1437 },
1438 {
1439 .opcode = MLX4_CMD_SQD2RTS_QP,
1440 .has_inbox = true,
1441 .has_outbox = false,
1442 .out_is_imm = false,
1443 .encode_slave_id = false,
1444 .verify = NULL,
1445 .wrapper = mlx4_SQD2RTS_QP_wrapper
1446 },
1447 {
1448 .opcode = MLX4_CMD_2RST_QP,
1449 .has_inbox = false,
1450 .has_outbox = false,
1451 .out_is_imm = false,
1452 .encode_slave_id = false,
1453 .verify = NULL,
1454 .wrapper = mlx4_2RST_QP_wrapper
1455 },
1456 {
1457 .opcode = MLX4_CMD_QUERY_QP,
1458 .has_inbox = false,
1459 .has_outbox = true,
1460 .out_is_imm = false,
1461 .encode_slave_id = false,
1462 .verify = NULL,
1463 .wrapper = mlx4_GEN_QP_wrapper
1464 },
1465 {
1466 .opcode = MLX4_CMD_SUSPEND_QP,
1467 .has_inbox = false,
1468 .has_outbox = false,
1469 .out_is_imm = false,
1470 .encode_slave_id = false,
1471 .verify = NULL,
1472 .wrapper = mlx4_GEN_QP_wrapper
1473 },
1474 {
1475 .opcode = MLX4_CMD_UNSUSPEND_QP,
1476 .has_inbox = false,
1477 .has_outbox = false,
1478 .out_is_imm = false,
1479 .encode_slave_id = false,
1480 .verify = NULL,
1481 .wrapper = mlx4_GEN_QP_wrapper
1482 },
1483 {
1484 .opcode = MLX4_CMD_UPDATE_QP,
1485 .has_inbox = true,
1486 .has_outbox = false,
1487 .out_is_imm = false,
1488 .encode_slave_id = false,
1489 .verify = NULL,
1490 .wrapper = mlx4_UPDATE_QP_wrapper
1491 },
1492 {
1493 .opcode = MLX4_CMD_GET_OP_REQ,
1494 .has_inbox = false,
1495 .has_outbox = false,
1496 .out_is_imm = false,
1497 .encode_slave_id = false,
1498 .verify = NULL,
1499 .wrapper = mlx4_CMD_EPERM_wrapper,
1500 },
1501 {
1502 .opcode = MLX4_CMD_ALLOCATE_VPP,
1503 .has_inbox = false,
1504 .has_outbox = true,
1505 .out_is_imm = false,
1506 .encode_slave_id = false,
1507 .verify = NULL,
1508 .wrapper = mlx4_CMD_EPERM_wrapper,
1509 },
1510 {
1511 .opcode = MLX4_CMD_SET_VPORT_QOS,
1512 .has_inbox = false,
1513 .has_outbox = true,
1514 .out_is_imm = false,
1515 .encode_slave_id = false,
1516 .verify = NULL,
1517 .wrapper = mlx4_CMD_EPERM_wrapper,
1518 },
1519 {
1520 .opcode = MLX4_CMD_CONF_SPECIAL_QP,
1521 .has_inbox = false,
1522 .has_outbox = false,
1523 .out_is_imm = false,
1524 .encode_slave_id = false,
1525 .verify = NULL, /* XXX verify: only demux can do this */
1526 .wrapper = NULL
1527 },
1528 {
1529 .opcode = MLX4_CMD_MAD_IFC,
1530 .has_inbox = true,
1531 .has_outbox = true,
1532 .out_is_imm = false,
1533 .encode_slave_id = false,
1534 .verify = NULL,
1535 .wrapper = mlx4_MAD_IFC_wrapper
1536 },
1537 {
1538 .opcode = MLX4_CMD_MAD_DEMUX,
1539 .has_inbox = false,
1540 .has_outbox = false,
1541 .out_is_imm = false,
1542 .encode_slave_id = false,
1543 .verify = NULL,
1544 .wrapper = mlx4_CMD_EPERM_wrapper
1545 },
1546 {
1547 .opcode = MLX4_CMD_QUERY_IF_STAT,
1548 .has_inbox = false,
1549 .has_outbox = true,
1550 .out_is_imm = false,
1551 .encode_slave_id = false,
1552 .verify = NULL,
1553 .wrapper = mlx4_QUERY_IF_STAT_wrapper
1554 },
1555 {
1556 .opcode = MLX4_CMD_ACCESS_REG,
1557 .has_inbox = true,
1558 .has_outbox = true,
1559 .out_is_imm = false,
1560 .encode_slave_id = false,
1561 .verify = NULL,
1562 .wrapper = mlx4_ACCESS_REG_wrapper,
1563 },
1564 {
1565 .opcode = MLX4_CMD_CONGESTION_CTRL_OPCODE,
1566 .has_inbox = false,
1567 .has_outbox = false,
1568 .out_is_imm = false,
1569 .encode_slave_id = false,
1570 .verify = NULL,
1571 .wrapper = mlx4_CMD_EPERM_wrapper,
1572 },
1573 /* Native multicast commands are not available for guests */
1574 {
1575 .opcode = MLX4_CMD_QP_ATTACH,
1576 .has_inbox = true,
1577 .has_outbox = false,
1578 .out_is_imm = false,
1579 .encode_slave_id = false,
1580 .verify = NULL,
1581 .wrapper = mlx4_QP_ATTACH_wrapper
1582 },
1583 {
1584 .opcode = MLX4_CMD_PROMISC,
1585 .has_inbox = false,
1586 .has_outbox = false,
1587 .out_is_imm = false,
1588 .encode_slave_id = false,
1589 .verify = NULL,
1590 .wrapper = mlx4_PROMISC_wrapper
1591 },
1592 /* Ethernet specific commands */
1593 {
1594 .opcode = MLX4_CMD_SET_VLAN_FLTR,
1595 .has_inbox = true,
1596 .has_outbox = false,
1597 .out_is_imm = false,
1598 .encode_slave_id = false,
1599 .verify = NULL,
1600 .wrapper = mlx4_SET_VLAN_FLTR_wrapper
1601 },
1602 {
1603 .opcode = MLX4_CMD_SET_MCAST_FLTR,
1604 .has_inbox = false,
1605 .has_outbox = false,
1606 .out_is_imm = false,
1607 .encode_slave_id = false,
1608 .verify = NULL,
1609 .wrapper = mlx4_SET_MCAST_FLTR_wrapper
1610 },
1611 {
1612 .opcode = MLX4_CMD_DUMP_ETH_STATS,
1613 .has_inbox = false,
1614 .has_outbox = true,
1615 .out_is_imm = false,
1616 .encode_slave_id = false,
1617 .verify = NULL,
1618 .wrapper = mlx4_DUMP_ETH_STATS_wrapper
1619 },
1620 {
1621 .opcode = MLX4_CMD_INFORM_FLR_DONE,
1622 .has_inbox = false,
1623 .has_outbox = false,
1624 .out_is_imm = false,
1625 .encode_slave_id = false,
1626 .verify = NULL,
1627 .wrapper = NULL
1628 },
1629 /* flow steering commands */
1630 {
1631 .opcode = MLX4_QP_FLOW_STEERING_ATTACH,
1632 .has_inbox = true,
1633 .has_outbox = false,
1634 .out_is_imm = true,
1635 .encode_slave_id = false,
1636 .verify = NULL,
1637 .wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1638 },
1639 {
1640 .opcode = MLX4_QP_FLOW_STEERING_DETACH,
1641 .has_inbox = false,
1642 .has_outbox = false,
1643 .out_is_imm = false,
1644 .encode_slave_id = false,
1645 .verify = NULL,
1646 .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
1647 },
1648 {
1649 .opcode = MLX4_FLOW_STEERING_IB_UC_QP_RANGE,
1650 .has_inbox = false,
1651 .has_outbox = false,
1652 .out_is_imm = false,
1653 .encode_slave_id = false,
1654 .verify = NULL,
1655 .wrapper = mlx4_CMD_EPERM_wrapper
1656 },
1657 {
1658 .opcode = MLX4_CMD_VIRT_PORT_MAP,
1659 .has_inbox = false,
1660 .has_outbox = false,
1661 .out_is_imm = false,
1662 .encode_slave_id = false,
1663 .verify = NULL,
1664 .wrapper = mlx4_CMD_EPERM_wrapper
1665 },
1666 };
1667
mlx4_master_process_vhcr(struct mlx4_dev * dev,int slave,struct mlx4_vhcr_cmd * in_vhcr)1668 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
1669 struct mlx4_vhcr_cmd *in_vhcr)
1670 {
1671 struct mlx4_priv *priv = mlx4_priv(dev);
1672 struct mlx4_cmd_info *cmd = NULL;
1673 struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1674 struct mlx4_vhcr *vhcr;
1675 struct mlx4_cmd_mailbox *inbox = NULL;
1676 struct mlx4_cmd_mailbox *outbox = NULL;
1677 u64 in_param;
1678 u64 out_param;
1679 int ret = 0;
1680 int i;
1681 int err = 0;
1682
1683 /* Create sw representation of Virtual HCR */
1684 vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
1685 if (!vhcr)
1686 return -ENOMEM;
1687
1688 /* DMA in the vHCR */
1689 if (!in_vhcr) {
1690 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1691 priv->mfunc.master.slave_state[slave].vhcr_dma,
1692 ALIGN(sizeof(struct mlx4_vhcr_cmd),
1693 MLX4_ACCESS_MEM_ALIGN), 1);
1694 if (ret) {
1695 if (!(dev->persist->state &
1696 MLX4_DEVICE_STATE_INTERNAL_ERROR))
1697 mlx4_err(dev, "%s: Failed reading vhcr ret: 0x%x\n",
1698 __func__, ret);
1699 kfree(vhcr);
1700 return ret;
1701 }
1702 }
1703
1704 /* Fill SW VHCR fields */
1705 vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
1706 vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
1707 vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
1708 vhcr->token = be16_to_cpu(vhcr_cmd->token);
1709 vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
1710 vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
1711 vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
1712
1713 /* Lookup command */
1714 for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
1715 if (vhcr->op == cmd_info[i].opcode) {
1716 cmd = &cmd_info[i];
1717 break;
1718 }
1719 }
1720 if (!cmd) {
1721 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
1722 vhcr->op, slave);
1723 vhcr_cmd->status = CMD_STAT_BAD_PARAM;
1724 goto out_status;
1725 }
1726
1727 /* Read inbox */
1728 if (cmd->has_inbox) {
1729 vhcr->in_param &= INBOX_MASK;
1730 inbox = mlx4_alloc_cmd_mailbox(dev);
1731 if (IS_ERR(inbox)) {
1732 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1733 inbox = NULL;
1734 goto out_status;
1735 }
1736
1737 ret = mlx4_ACCESS_MEM(dev, inbox->dma, slave,
1738 vhcr->in_param,
1739 MLX4_MAILBOX_SIZE, 1);
1740 if (ret) {
1741 if (!(dev->persist->state &
1742 MLX4_DEVICE_STATE_INTERNAL_ERROR))
1743 mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
1744 __func__, cmd->opcode);
1745 vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
1746 goto out_status;
1747 }
1748 }
1749
1750 /* Apply permission and bound checks if applicable */
1751 if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
1752 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection checks for resource_id:%d\n",
1753 vhcr->op, slave, vhcr->in_modifier);
1754 vhcr_cmd->status = CMD_STAT_BAD_OP;
1755 goto out_status;
1756 }
1757
1758 /* Allocate outbox */
1759 if (cmd->has_outbox) {
1760 outbox = mlx4_alloc_cmd_mailbox(dev);
1761 if (IS_ERR(outbox)) {
1762 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1763 outbox = NULL;
1764 goto out_status;
1765 }
1766 }
1767
1768 /* Execute the command! */
1769 if (cmd->wrapper) {
1770 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
1771 cmd);
1772 if (cmd->out_is_imm)
1773 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1774 } else {
1775 in_param = cmd->has_inbox ? (u64) inbox->dma :
1776 vhcr->in_param;
1777 out_param = cmd->has_outbox ? (u64) outbox->dma :
1778 vhcr->out_param;
1779 err = __mlx4_cmd(dev, in_param, &out_param,
1780 cmd->out_is_imm, vhcr->in_modifier,
1781 vhcr->op_modifier, vhcr->op,
1782 MLX4_CMD_TIME_CLASS_A,
1783 MLX4_CMD_NATIVE);
1784
1785 if (cmd->out_is_imm) {
1786 vhcr->out_param = out_param;
1787 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1788 }
1789 }
1790
1791 if (err) {
1792 if (!(dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)) {
1793 if (vhcr->op == MLX4_CMD_ALLOC_RES &&
1794 (vhcr->in_modifier & 0xff) == RES_COUNTER &&
1795 err == -EDQUOT)
1796 mlx4_dbg(dev,
1797 "Unable to allocate counter for slave %d (%d)\n",
1798 slave, err);
1799 else
1800 mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with error:%d, status %d\n",
1801 vhcr->op, slave, vhcr->errno, err);
1802 }
1803 vhcr_cmd->status = mlx4_errno_to_status(err);
1804 goto out_status;
1805 }
1806
1807
1808 /* Write outbox if command completed successfully */
1809 if (cmd->has_outbox && !vhcr_cmd->status) {
1810 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
1811 vhcr->out_param,
1812 MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
1813 if (ret) {
1814 /* If we failed to write back the outbox after the
1815 *command was successfully executed, we must fail this
1816 * slave, as it is now in undefined state */
1817 if (!(dev->persist->state &
1818 MLX4_DEVICE_STATE_INTERNAL_ERROR))
1819 mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
1820 goto out;
1821 }
1822 }
1823
1824 out_status:
1825 /* DMA back vhcr result */
1826 if (!in_vhcr) {
1827 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1828 priv->mfunc.master.slave_state[slave].vhcr_dma,
1829 ALIGN(sizeof(struct mlx4_vhcr),
1830 MLX4_ACCESS_MEM_ALIGN),
1831 MLX4_CMD_WRAPPED);
1832 if (ret)
1833 mlx4_err(dev, "%s:Failed writing vhcr result\n",
1834 __func__);
1835 else if (vhcr->e_bit &&
1836 mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1837 mlx4_warn(dev, "Failed to generate command completion eqe for slave %d\n",
1838 slave);
1839 }
1840
1841 out:
1842 kfree(vhcr);
1843 mlx4_free_cmd_mailbox(dev, inbox);
1844 mlx4_free_cmd_mailbox(dev, outbox);
1845 return ret;
1846 }
1847
mlx4_master_immediate_activate_vlan_qos(struct mlx4_priv * priv,int slave,int port)1848 static int mlx4_master_immediate_activate_vlan_qos(struct mlx4_priv *priv,
1849 int slave, int port)
1850 {
1851 struct mlx4_vport_oper_state *vp_oper;
1852 struct mlx4_vport_state *vp_admin;
1853 struct mlx4_vf_immed_vlan_work *work;
1854 struct mlx4_dev *dev = &(priv->dev);
1855 int err;
1856 int admin_vlan_ix = NO_INDX;
1857
1858 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1859 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1860
1861 if (vp_oper->state.default_vlan == vp_admin->default_vlan &&
1862 vp_oper->state.default_qos == vp_admin->default_qos &&
1863 vp_oper->state.vlan_proto == vp_admin->vlan_proto &&
1864 vp_oper->state.link_state == vp_admin->link_state &&
1865 vp_oper->state.qos_vport == vp_admin->qos_vport)
1866 return 0;
1867
1868 if (!(priv->mfunc.master.slave_state[slave].active &&
1869 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP)) {
1870 /* even if the UPDATE_QP command isn't supported, we still want
1871 * to set this VF link according to the admin directive
1872 */
1873 vp_oper->state.link_state = vp_admin->link_state;
1874 return -1;
1875 }
1876
1877 mlx4_dbg(dev, "updating immediately admin params slave %d port %d\n",
1878 slave, port);
1879 mlx4_dbg(dev, "vlan %d QoS %d link down %d\n",
1880 vp_admin->default_vlan, vp_admin->default_qos,
1881 vp_admin->link_state);
1882
1883 work = kzalloc(sizeof(*work), GFP_KERNEL);
1884 if (!work)
1885 return -ENOMEM;
1886
1887 if (vp_oper->state.default_vlan != vp_admin->default_vlan) {
1888 if (MLX4_VGT != vp_admin->default_vlan) {
1889 err = __mlx4_register_vlan(&priv->dev, port,
1890 vp_admin->default_vlan,
1891 &admin_vlan_ix);
1892 if (err) {
1893 kfree(work);
1894 mlx4_warn(&priv->dev,
1895 "No vlan resources slave %d, port %d\n",
1896 slave, port);
1897 return err;
1898 }
1899 } else {
1900 admin_vlan_ix = NO_INDX;
1901 }
1902 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_VLAN;
1903 mlx4_dbg(&priv->dev,
1904 "alloc vlan %d idx %d slave %d port %d\n",
1905 (int)(vp_admin->default_vlan),
1906 admin_vlan_ix, slave, port);
1907 }
1908
1909 /* save original vlan ix and vlan id */
1910 work->orig_vlan_id = vp_oper->state.default_vlan;
1911 work->orig_vlan_ix = vp_oper->vlan_idx;
1912
1913 /* handle new qos */
1914 if (vp_oper->state.default_qos != vp_admin->default_qos)
1915 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_QOS;
1916
1917 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN)
1918 vp_oper->vlan_idx = admin_vlan_ix;
1919
1920 vp_oper->state.default_vlan = vp_admin->default_vlan;
1921 vp_oper->state.default_qos = vp_admin->default_qos;
1922 vp_oper->state.vlan_proto = vp_admin->vlan_proto;
1923 vp_oper->state.link_state = vp_admin->link_state;
1924 vp_oper->state.qos_vport = vp_admin->qos_vport;
1925
1926 if (vp_admin->link_state == IFLA_VF_LINK_STATE_DISABLE)
1927 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE;
1928
1929 /* iterate over QPs owned by this slave, using UPDATE_QP */
1930 work->port = port;
1931 work->slave = slave;
1932 work->qos = vp_oper->state.default_qos;
1933 work->qos_vport = vp_oper->state.qos_vport;
1934 work->vlan_id = vp_oper->state.default_vlan;
1935 work->vlan_ix = vp_oper->vlan_idx;
1936 work->vlan_proto = vp_oper->state.vlan_proto;
1937 work->priv = priv;
1938 INIT_WORK(&work->work, mlx4_vf_immed_vlan_work_handler);
1939 queue_work(priv->mfunc.master.comm_wq, &work->work);
1940
1941 return 0;
1942 }
1943
mlx4_set_default_port_qos(struct mlx4_dev * dev,int port)1944 static void mlx4_set_default_port_qos(struct mlx4_dev *dev, int port)
1945 {
1946 struct mlx4_qos_manager *port_qos_ctl;
1947 struct mlx4_priv *priv = mlx4_priv(dev);
1948
1949 port_qos_ctl = &priv->mfunc.master.qos_ctl[port];
1950 bitmap_zero(port_qos_ctl->priority_bm, MLX4_NUM_UP);
1951
1952 /* Enable only default prio at PF init routine */
1953 set_bit(MLX4_DEFAULT_QOS_PRIO, port_qos_ctl->priority_bm);
1954 }
1955
mlx4_allocate_port_vpps(struct mlx4_dev * dev,int port)1956 static void mlx4_allocate_port_vpps(struct mlx4_dev *dev, int port)
1957 {
1958 int i;
1959 int err;
1960 int num_vfs;
1961 u16 available_vpp;
1962 u8 vpp_param[MLX4_NUM_UP];
1963 struct mlx4_qos_manager *port_qos;
1964 struct mlx4_priv *priv = mlx4_priv(dev);
1965
1966 err = mlx4_ALLOCATE_VPP_get(dev, port, &available_vpp, vpp_param);
1967 if (err) {
1968 mlx4_info(dev, "Failed query available VPPs\n");
1969 return;
1970 }
1971
1972 port_qos = &priv->mfunc.master.qos_ctl[port];
1973 num_vfs = (available_vpp /
1974 bitmap_weight(port_qos->priority_bm, MLX4_NUM_UP));
1975
1976 for (i = 0; i < MLX4_NUM_UP; i++) {
1977 if (test_bit(i, port_qos->priority_bm))
1978 vpp_param[i] = num_vfs;
1979 }
1980
1981 err = mlx4_ALLOCATE_VPP_set(dev, port, vpp_param);
1982 if (err) {
1983 mlx4_info(dev, "Failed allocating VPPs\n");
1984 return;
1985 }
1986
1987 /* Query actual allocated VPP, just to make sure */
1988 err = mlx4_ALLOCATE_VPP_get(dev, port, &available_vpp, vpp_param);
1989 if (err) {
1990 mlx4_info(dev, "Failed query available VPPs\n");
1991 return;
1992 }
1993
1994 port_qos->num_of_qos_vfs = num_vfs;
1995 mlx4_dbg(dev, "Port %d Available VPPs %d\n", port, available_vpp);
1996
1997 for (i = 0; i < MLX4_NUM_UP; i++)
1998 mlx4_dbg(dev, "Port %d UP %d Allocated %d VPPs\n", port, i,
1999 vpp_param[i]);
2000 }
2001
mlx4_master_activate_admin_state(struct mlx4_priv * priv,int slave)2002 static int mlx4_master_activate_admin_state(struct mlx4_priv *priv, int slave)
2003 {
2004 int port, err;
2005 struct mlx4_vport_state *vp_admin;
2006 struct mlx4_vport_oper_state *vp_oper;
2007 struct mlx4_slave_state *slave_state =
2008 &priv->mfunc.master.slave_state[slave];
2009 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
2010 &priv->dev, slave);
2011 int min_port = find_first_bit(actv_ports.ports,
2012 priv->dev.caps.num_ports) + 1;
2013 int max_port = min_port - 1 +
2014 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
2015
2016 for (port = min_port; port <= max_port; port++) {
2017 if (!test_bit(port - 1, actv_ports.ports))
2018 continue;
2019 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
2020 priv->mfunc.master.vf_admin[slave].enable_smi[port];
2021 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2022 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
2023 if (vp_admin->vlan_proto != htons(ETH_P_8021AD) ||
2024 slave_state->vst_qinq_supported) {
2025 vp_oper->state.vlan_proto = vp_admin->vlan_proto;
2026 vp_oper->state.default_vlan = vp_admin->default_vlan;
2027 vp_oper->state.default_qos = vp_admin->default_qos;
2028 }
2029 vp_oper->state.link_state = vp_admin->link_state;
2030 vp_oper->state.mac = vp_admin->mac;
2031 vp_oper->state.spoofchk = vp_admin->spoofchk;
2032 vp_oper->state.tx_rate = vp_admin->tx_rate;
2033 vp_oper->state.qos_vport = vp_admin->qos_vport;
2034 vp_oper->state.guid = vp_admin->guid;
2035
2036 if (MLX4_VGT != vp_admin->default_vlan) {
2037 err = __mlx4_register_vlan(&priv->dev, port,
2038 vp_admin->default_vlan, &(vp_oper->vlan_idx));
2039 if (err) {
2040 vp_oper->vlan_idx = NO_INDX;
2041 vp_oper->state.default_vlan = MLX4_VGT;
2042 vp_oper->state.vlan_proto = htons(ETH_P_8021Q);
2043 mlx4_warn(&priv->dev,
2044 "No vlan resources slave %d, port %d\n",
2045 slave, port);
2046 return err;
2047 }
2048 mlx4_dbg(&priv->dev, "alloc vlan %d idx %d slave %d port %d\n",
2049 (int)(vp_oper->state.default_vlan),
2050 vp_oper->vlan_idx, slave, port);
2051 }
2052 if (vp_admin->spoofchk) {
2053 vp_oper->mac_idx = __mlx4_register_mac(&priv->dev,
2054 port,
2055 vp_admin->mac);
2056 if (0 > vp_oper->mac_idx) {
2057 err = vp_oper->mac_idx;
2058 vp_oper->mac_idx = NO_INDX;
2059 mlx4_warn(&priv->dev,
2060 "No mac resources slave %d, port %d\n",
2061 slave, port);
2062 return err;
2063 }
2064 mlx4_dbg(&priv->dev, "alloc mac %llx idx %d slave %d port %d\n",
2065 vp_oper->state.mac, vp_oper->mac_idx, slave, port);
2066 }
2067 }
2068 return 0;
2069 }
2070
mlx4_master_deactivate_admin_state(struct mlx4_priv * priv,int slave)2071 static void mlx4_master_deactivate_admin_state(struct mlx4_priv *priv, int slave)
2072 {
2073 int port;
2074 struct mlx4_vport_oper_state *vp_oper;
2075 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
2076 &priv->dev, slave);
2077 int min_port = find_first_bit(actv_ports.ports,
2078 priv->dev.caps.num_ports) + 1;
2079 int max_port = min_port - 1 +
2080 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
2081
2082
2083 for (port = min_port; port <= max_port; port++) {
2084 if (!test_bit(port - 1, actv_ports.ports))
2085 continue;
2086 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
2087 MLX4_VF_SMI_DISABLED;
2088 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2089 if (NO_INDX != vp_oper->vlan_idx) {
2090 __mlx4_unregister_vlan(&priv->dev,
2091 port, vp_oper->state.default_vlan);
2092 vp_oper->vlan_idx = NO_INDX;
2093 }
2094 if (NO_INDX != vp_oper->mac_idx) {
2095 __mlx4_unregister_mac(&priv->dev, port, vp_oper->state.mac);
2096 vp_oper->mac_idx = NO_INDX;
2097 }
2098 }
2099 return;
2100 }
2101
mlx4_master_do_cmd(struct mlx4_dev * dev,int slave,u8 cmd,u16 param,u8 toggle)2102 static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd,
2103 u16 param, u8 toggle)
2104 {
2105 struct mlx4_priv *priv = mlx4_priv(dev);
2106 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
2107 u32 reply;
2108 u8 is_going_down = 0;
2109 int i;
2110 unsigned long flags;
2111
2112 slave_state[slave].comm_toggle ^= 1;
2113 reply = (u32) slave_state[slave].comm_toggle << 31;
2114 if (toggle != slave_state[slave].comm_toggle) {
2115 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER STATE COMPROMISED ***\n",
2116 toggle, slave);
2117 goto reset_slave;
2118 }
2119 if (cmd == MLX4_COMM_CMD_RESET) {
2120 mlx4_warn(dev, "Received reset from slave:%d\n", slave);
2121 slave_state[slave].active = false;
2122 slave_state[slave].old_vlan_api = false;
2123 slave_state[slave].vst_qinq_supported = false;
2124 mlx4_master_deactivate_admin_state(priv, slave);
2125 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) {
2126 slave_state[slave].event_eq[i].eqn = -1;
2127 slave_state[slave].event_eq[i].token = 0;
2128 }
2129 /*check if we are in the middle of FLR process,
2130 if so return "retry" status to the slave*/
2131 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd)
2132 goto inform_slave_state;
2133
2134 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, slave);
2135
2136 /* write the version in the event field */
2137 reply |= mlx4_comm_get_version();
2138
2139 goto reset_slave;
2140 }
2141 /*command from slave in the middle of FLR*/
2142 if (cmd != MLX4_COMM_CMD_RESET &&
2143 MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
2144 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) in the middle of FLR\n",
2145 slave, cmd);
2146 return;
2147 }
2148
2149 switch (cmd) {
2150 case MLX4_COMM_CMD_VHCR0:
2151 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET)
2152 goto reset_slave;
2153 slave_state[slave].vhcr_dma = ((u64) param) << 48;
2154 priv->mfunc.master.slave_state[slave].cookie = 0;
2155 break;
2156 case MLX4_COMM_CMD_VHCR1:
2157 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0)
2158 goto reset_slave;
2159 slave_state[slave].vhcr_dma |= ((u64) param) << 32;
2160 break;
2161 case MLX4_COMM_CMD_VHCR2:
2162 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1)
2163 goto reset_slave;
2164 slave_state[slave].vhcr_dma |= ((u64) param) << 16;
2165 break;
2166 case MLX4_COMM_CMD_VHCR_EN:
2167 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2)
2168 goto reset_slave;
2169 slave_state[slave].vhcr_dma |= param;
2170 if (mlx4_master_activate_admin_state(priv, slave))
2171 goto reset_slave;
2172 slave_state[slave].active = true;
2173 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_INIT, slave);
2174 break;
2175 case MLX4_COMM_CMD_VHCR_POST:
2176 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) &&
2177 (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST)) {
2178 mlx4_warn(dev, "slave:%d is out of sync, cmd=0x%x, last command=0x%x, reset is needed\n",
2179 slave, cmd, slave_state[slave].last_cmd);
2180 goto reset_slave;
2181 }
2182
2183 mutex_lock(&priv->cmd.slave_cmd_mutex);
2184 if (mlx4_master_process_vhcr(dev, slave, NULL)) {
2185 mlx4_err(dev, "Failed processing vhcr for slave:%d, resetting slave\n",
2186 slave);
2187 mutex_unlock(&priv->cmd.slave_cmd_mutex);
2188 goto reset_slave;
2189 }
2190 mutex_unlock(&priv->cmd.slave_cmd_mutex);
2191 break;
2192 default:
2193 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave);
2194 goto reset_slave;
2195 }
2196 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
2197 if (!slave_state[slave].is_slave_going_down)
2198 slave_state[slave].last_cmd = cmd;
2199 else
2200 is_going_down = 1;
2201 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
2202 if (is_going_down) {
2203 mlx4_warn(dev, "Slave is going down aborting command(%d) executing from slave:%d\n",
2204 cmd, slave);
2205 return;
2206 }
2207 __raw_writel((__force u32) cpu_to_be32(reply),
2208 &priv->mfunc.comm[slave].slave_read);
2209 mmiowb();
2210
2211 return;
2212
2213 reset_slave:
2214 /* cleanup any slave resources */
2215 if (dev->persist->interface_state & MLX4_INTERFACE_STATE_UP)
2216 mlx4_delete_all_resources_for_slave(dev, slave);
2217
2218 if (cmd != MLX4_COMM_CMD_RESET) {
2219 mlx4_warn(dev, "Turn on internal error to force reset, slave=%d, cmd=0x%x\n",
2220 slave, cmd);
2221 /* Turn on internal error letting slave reset itself immeditaly,
2222 * otherwise it might take till timeout on command is passed
2223 */
2224 reply |= ((u32)COMM_CHAN_EVENT_INTERNAL_ERR);
2225 }
2226
2227 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
2228 if (!slave_state[slave].is_slave_going_down)
2229 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET;
2230 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
2231 /*with slave in the middle of flr, no need to clean resources again.*/
2232 inform_slave_state:
2233 memset(&slave_state[slave].event_eq, 0,
2234 sizeof(struct mlx4_slave_event_eq_info));
2235 __raw_writel((__force u32) cpu_to_be32(reply),
2236 &priv->mfunc.comm[slave].slave_read);
2237 wmb();
2238 }
2239
2240 /* master command processing */
mlx4_master_comm_channel(struct work_struct * work)2241 void mlx4_master_comm_channel(struct work_struct *work)
2242 {
2243 struct mlx4_mfunc_master_ctx *master =
2244 container_of(work,
2245 struct mlx4_mfunc_master_ctx,
2246 comm_work);
2247 struct mlx4_mfunc *mfunc =
2248 container_of(master, struct mlx4_mfunc, master);
2249 struct mlx4_priv *priv =
2250 container_of(mfunc, struct mlx4_priv, mfunc);
2251 struct mlx4_dev *dev = &priv->dev;
2252 __be32 *bit_vec;
2253 u32 comm_cmd;
2254 u32 vec;
2255 int i, j, slave;
2256 int toggle;
2257 int served = 0;
2258 int reported = 0;
2259 u32 slt;
2260
2261 bit_vec = master->comm_arm_bit_vector;
2262 for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) {
2263 vec = be32_to_cpu(bit_vec[i]);
2264 for (j = 0; j < 32; j++) {
2265 if (!(vec & (1 << j)))
2266 continue;
2267 ++reported;
2268 slave = (i * 32) + j;
2269 comm_cmd = swab32(readl(
2270 &mfunc->comm[slave].slave_write));
2271 slt = swab32(readl(&mfunc->comm[slave].slave_read))
2272 >> 31;
2273 toggle = comm_cmd >> 31;
2274 if (toggle != slt) {
2275 if (master->slave_state[slave].comm_toggle
2276 != slt) {
2277 pr_info("slave %d out of sync. read toggle %d, state toggle %d. Resynching.\n",
2278 slave, slt,
2279 master->slave_state[slave].comm_toggle);
2280 master->slave_state[slave].comm_toggle =
2281 slt;
2282 }
2283 mlx4_master_do_cmd(dev, slave,
2284 comm_cmd >> 16 & 0xff,
2285 comm_cmd & 0xffff, toggle);
2286 ++served;
2287 }
2288 }
2289 }
2290
2291 if (reported && reported != served)
2292 mlx4_warn(dev, "Got command event with bitmask from %d slaves but %d were served\n",
2293 reported, served);
2294
2295 if (mlx4_ARM_COMM_CHANNEL(dev))
2296 mlx4_warn(dev, "Failed to arm comm channel events\n");
2297 }
2298
sync_toggles(struct mlx4_dev * dev)2299 static int sync_toggles(struct mlx4_dev *dev)
2300 {
2301 struct mlx4_priv *priv = mlx4_priv(dev);
2302 u32 wr_toggle;
2303 u32 rd_toggle;
2304 unsigned long end;
2305
2306 wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write));
2307 if (wr_toggle == 0xffffffff)
2308 end = jiffies + msecs_to_jiffies(30000);
2309 else
2310 end = jiffies + msecs_to_jiffies(5000);
2311
2312 while (time_before(jiffies, end)) {
2313 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read));
2314 if (wr_toggle == 0xffffffff || rd_toggle == 0xffffffff) {
2315 /* PCI might be offline */
2316
2317 /* If device removal has been requested,
2318 * do not continue retrying.
2319 */
2320 if (dev->persist->interface_state &
2321 MLX4_INTERFACE_STATE_NOWAIT) {
2322 mlx4_warn(dev,
2323 "communication channel is offline\n");
2324 return -EIO;
2325 }
2326
2327 msleep(100);
2328 wr_toggle = swab32(readl(&priv->mfunc.comm->
2329 slave_write));
2330 continue;
2331 }
2332
2333 if (rd_toggle >> 31 == wr_toggle >> 31) {
2334 priv->cmd.comm_toggle = rd_toggle >> 31;
2335 return 0;
2336 }
2337
2338 cond_resched();
2339 }
2340
2341 /*
2342 * we could reach here if for example the previous VM using this
2343 * function misbehaved and left the channel with unsynced state. We
2344 * should fix this here and give this VM a chance to use a properly
2345 * synced channel
2346 */
2347 mlx4_warn(dev, "recovering from previously mis-behaved VM\n");
2348 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
2349 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
2350 priv->cmd.comm_toggle = 0;
2351
2352 return 0;
2353 }
2354
mlx4_multi_func_init(struct mlx4_dev * dev)2355 int mlx4_multi_func_init(struct mlx4_dev *dev)
2356 {
2357 struct mlx4_priv *priv = mlx4_priv(dev);
2358 struct mlx4_slave_state *s_state;
2359 int i, j, err, port;
2360
2361 if (mlx4_is_master(dev))
2362 priv->mfunc.comm =
2363 ioremap(pci_resource_start(dev->persist->pdev,
2364 priv->fw.comm_bar) +
2365 priv->fw.comm_base, MLX4_COMM_PAGESIZE);
2366 else
2367 priv->mfunc.comm =
2368 ioremap(pci_resource_start(dev->persist->pdev, 2) +
2369 MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE);
2370 if (!priv->mfunc.comm) {
2371 mlx4_err(dev, "Couldn't map communication vector\n");
2372 goto err_vhcr;
2373 }
2374
2375 if (mlx4_is_master(dev)) {
2376 struct mlx4_vf_oper_state *vf_oper;
2377 struct mlx4_vf_admin_state *vf_admin;
2378
2379 priv->mfunc.master.slave_state =
2380 kcalloc(dev->num_slaves,
2381 sizeof(struct mlx4_slave_state),
2382 GFP_KERNEL);
2383 if (!priv->mfunc.master.slave_state)
2384 goto err_comm;
2385
2386 priv->mfunc.master.vf_admin =
2387 kcalloc(dev->num_slaves,
2388 sizeof(struct mlx4_vf_admin_state),
2389 GFP_KERNEL);
2390 if (!priv->mfunc.master.vf_admin)
2391 goto err_comm_admin;
2392
2393 priv->mfunc.master.vf_oper =
2394 kcalloc(dev->num_slaves,
2395 sizeof(struct mlx4_vf_oper_state),
2396 GFP_KERNEL);
2397 if (!priv->mfunc.master.vf_oper)
2398 goto err_comm_oper;
2399
2400 for (i = 0; i < dev->num_slaves; ++i) {
2401 vf_admin = &priv->mfunc.master.vf_admin[i];
2402 vf_oper = &priv->mfunc.master.vf_oper[i];
2403 s_state = &priv->mfunc.master.slave_state[i];
2404 s_state->last_cmd = MLX4_COMM_CMD_RESET;
2405 s_state->vst_qinq_supported = false;
2406 mutex_init(&priv->mfunc.master.gen_eqe_mutex[i]);
2407 for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j)
2408 s_state->event_eq[j].eqn = -1;
2409 __raw_writel((__force u32) 0,
2410 &priv->mfunc.comm[i].slave_write);
2411 __raw_writel((__force u32) 0,
2412 &priv->mfunc.comm[i].slave_read);
2413 mmiowb();
2414 for (port = 1; port <= MLX4_MAX_PORTS; port++) {
2415 struct mlx4_vport_state *admin_vport;
2416 struct mlx4_vport_state *oper_vport;
2417
2418 s_state->vlan_filter[port] =
2419 kzalloc(sizeof(struct mlx4_vlan_fltr),
2420 GFP_KERNEL);
2421 if (!s_state->vlan_filter[port]) {
2422 if (--port)
2423 kfree(s_state->vlan_filter[port]);
2424 goto err_slaves;
2425 }
2426
2427 admin_vport = &vf_admin->vport[port];
2428 oper_vport = &vf_oper->vport[port].state;
2429 INIT_LIST_HEAD(&s_state->mcast_filters[port]);
2430 admin_vport->default_vlan = MLX4_VGT;
2431 oper_vport->default_vlan = MLX4_VGT;
2432 admin_vport->qos_vport =
2433 MLX4_VPP_DEFAULT_VPORT;
2434 oper_vport->qos_vport = MLX4_VPP_DEFAULT_VPORT;
2435 admin_vport->vlan_proto = htons(ETH_P_8021Q);
2436 oper_vport->vlan_proto = htons(ETH_P_8021Q);
2437 vf_oper->vport[port].vlan_idx = NO_INDX;
2438 vf_oper->vport[port].mac_idx = NO_INDX;
2439 mlx4_set_random_admin_guid(dev, i, port);
2440 }
2441 spin_lock_init(&s_state->lock);
2442 }
2443
2444 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP) {
2445 for (port = 1; port <= dev->caps.num_ports; port++) {
2446 if (mlx4_is_eth(dev, port)) {
2447 mlx4_set_default_port_qos(dev, port);
2448 mlx4_allocate_port_vpps(dev, port);
2449 }
2450 }
2451 }
2452
2453 memset(&priv->mfunc.master.cmd_eqe, 0, sizeof(struct mlx4_eqe));
2454 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
2455 INIT_WORK(&priv->mfunc.master.comm_work,
2456 mlx4_master_comm_channel);
2457 INIT_WORK(&priv->mfunc.master.slave_event_work,
2458 mlx4_gen_slave_eqe);
2459 INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
2460 mlx4_master_handle_slave_flr);
2461 spin_lock_init(&priv->mfunc.master.slave_state_lock);
2462 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock);
2463 priv->mfunc.master.comm_wq =
2464 create_singlethread_workqueue("mlx4_comm");
2465 if (!priv->mfunc.master.comm_wq)
2466 goto err_slaves;
2467
2468 if (mlx4_init_resource_tracker(dev))
2469 goto err_thread;
2470
2471 } else {
2472 err = sync_toggles(dev);
2473 if (err) {
2474 mlx4_err(dev, "Couldn't sync toggles\n");
2475 goto err_comm;
2476 }
2477 }
2478 return 0;
2479
2480 err_thread:
2481 flush_workqueue(priv->mfunc.master.comm_wq);
2482 destroy_workqueue(priv->mfunc.master.comm_wq);
2483 err_slaves:
2484 while (i--) {
2485 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2486 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2487 }
2488 kfree(priv->mfunc.master.vf_oper);
2489 err_comm_oper:
2490 kfree(priv->mfunc.master.vf_admin);
2491 err_comm_admin:
2492 kfree(priv->mfunc.master.slave_state);
2493 err_comm:
2494 iounmap(priv->mfunc.comm);
2495 priv->mfunc.comm = NULL;
2496 err_vhcr:
2497 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
2498 priv->mfunc.vhcr,
2499 priv->mfunc.vhcr_dma);
2500 priv->mfunc.vhcr = NULL;
2501 return -ENOMEM;
2502 }
2503
mlx4_cmd_init(struct mlx4_dev * dev)2504 int mlx4_cmd_init(struct mlx4_dev *dev)
2505 {
2506 struct mlx4_priv *priv = mlx4_priv(dev);
2507 int flags = 0;
2508
2509 if (!priv->cmd.initialized) {
2510 init_rwsem(&priv->cmd.switch_sem);
2511 mutex_init(&priv->cmd.slave_cmd_mutex);
2512 sema_init(&priv->cmd.poll_sem, 1);
2513 priv->cmd.use_events = 0;
2514 priv->cmd.toggle = 1;
2515 priv->cmd.initialized = 1;
2516 flags |= MLX4_CMD_CLEANUP_STRUCT;
2517 }
2518
2519 if (!mlx4_is_slave(dev) && !priv->cmd.hcr) {
2520 priv->cmd.hcr = ioremap(pci_resource_start(dev->persist->pdev,
2521 0) + MLX4_HCR_BASE, MLX4_HCR_SIZE);
2522 if (!priv->cmd.hcr) {
2523 mlx4_err(dev, "Couldn't map command register\n");
2524 goto err;
2525 }
2526 flags |= MLX4_CMD_CLEANUP_HCR;
2527 }
2528
2529 if (mlx4_is_mfunc(dev) && !priv->mfunc.vhcr) {
2530 priv->mfunc.vhcr = dma_alloc_coherent(&dev->persist->pdev->dev,
2531 PAGE_SIZE,
2532 &priv->mfunc.vhcr_dma,
2533 GFP_KERNEL);
2534 if (!priv->mfunc.vhcr)
2535 goto err;
2536
2537 flags |= MLX4_CMD_CLEANUP_VHCR;
2538 }
2539
2540 if (!priv->cmd.pool) {
2541 priv->cmd.pool = dma_pool_create("mlx4_cmd",
2542 &dev->persist->pdev->dev,
2543 MLX4_MAILBOX_SIZE,
2544 MLX4_MAILBOX_SIZE, 0);
2545 if (!priv->cmd.pool)
2546 goto err;
2547
2548 flags |= MLX4_CMD_CLEANUP_POOL;
2549 }
2550
2551 return 0;
2552
2553 err:
2554 mlx4_cmd_cleanup(dev, flags);
2555 return -ENOMEM;
2556 }
2557
mlx4_report_internal_err_comm_event(struct mlx4_dev * dev)2558 void mlx4_report_internal_err_comm_event(struct mlx4_dev *dev)
2559 {
2560 struct mlx4_priv *priv = mlx4_priv(dev);
2561 int slave;
2562 u32 slave_read;
2563
2564 /* If the comm channel has not yet been initialized,
2565 * skip reporting the internal error event to all
2566 * the communication channels.
2567 */
2568 if (!priv->mfunc.comm)
2569 return;
2570
2571 /* Report an internal error event to all
2572 * communication channels.
2573 */
2574 for (slave = 0; slave < dev->num_slaves; slave++) {
2575 slave_read = swab32(readl(&priv->mfunc.comm[slave].slave_read));
2576 slave_read |= (u32)COMM_CHAN_EVENT_INTERNAL_ERR;
2577 __raw_writel((__force u32)cpu_to_be32(slave_read),
2578 &priv->mfunc.comm[slave].slave_read);
2579 /* Make sure that our comm channel write doesn't
2580 * get mixed in with writes from another CPU.
2581 */
2582 mmiowb();
2583 }
2584 }
2585
mlx4_multi_func_cleanup(struct mlx4_dev * dev)2586 void mlx4_multi_func_cleanup(struct mlx4_dev *dev)
2587 {
2588 struct mlx4_priv *priv = mlx4_priv(dev);
2589 int i, port;
2590
2591 if (mlx4_is_master(dev)) {
2592 flush_workqueue(priv->mfunc.master.comm_wq);
2593 destroy_workqueue(priv->mfunc.master.comm_wq);
2594 for (i = 0; i < dev->num_slaves; i++) {
2595 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2596 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2597 }
2598 kfree(priv->mfunc.master.slave_state);
2599 kfree(priv->mfunc.master.vf_admin);
2600 kfree(priv->mfunc.master.vf_oper);
2601 dev->num_slaves = 0;
2602 }
2603
2604 iounmap(priv->mfunc.comm);
2605 priv->mfunc.comm = NULL;
2606 }
2607
mlx4_cmd_cleanup(struct mlx4_dev * dev,int cleanup_mask)2608 void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask)
2609 {
2610 struct mlx4_priv *priv = mlx4_priv(dev);
2611
2612 if (priv->cmd.pool && (cleanup_mask & MLX4_CMD_CLEANUP_POOL)) {
2613 dma_pool_destroy(priv->cmd.pool);
2614 priv->cmd.pool = NULL;
2615 }
2616
2617 if (!mlx4_is_slave(dev) && priv->cmd.hcr &&
2618 (cleanup_mask & MLX4_CMD_CLEANUP_HCR)) {
2619 iounmap(priv->cmd.hcr);
2620 priv->cmd.hcr = NULL;
2621 }
2622 if (mlx4_is_mfunc(dev) && priv->mfunc.vhcr &&
2623 (cleanup_mask & MLX4_CMD_CLEANUP_VHCR)) {
2624 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
2625 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
2626 priv->mfunc.vhcr = NULL;
2627 }
2628 if (priv->cmd.initialized && (cleanup_mask & MLX4_CMD_CLEANUP_STRUCT))
2629 priv->cmd.initialized = 0;
2630 }
2631
2632 /*
2633 * Switch to using events to issue FW commands (can only be called
2634 * after event queue for command events has been initialized).
2635 */
mlx4_cmd_use_events(struct mlx4_dev * dev)2636 int mlx4_cmd_use_events(struct mlx4_dev *dev)
2637 {
2638 struct mlx4_priv *priv = mlx4_priv(dev);
2639 int i;
2640 int err = 0;
2641
2642 priv->cmd.context = kmalloc_array(priv->cmd.max_cmds,
2643 sizeof(struct mlx4_cmd_context),
2644 GFP_KERNEL);
2645 if (!priv->cmd.context)
2646 return -ENOMEM;
2647
2648 down_write(&priv->cmd.switch_sem);
2649 for (i = 0; i < priv->cmd.max_cmds; ++i) {
2650 priv->cmd.context[i].token = i;
2651 priv->cmd.context[i].next = i + 1;
2652 /* To support fatal error flow, initialize all
2653 * cmd contexts to allow simulating completions
2654 * with complete() at any time.
2655 */
2656 init_completion(&priv->cmd.context[i].done);
2657 }
2658
2659 priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
2660 priv->cmd.free_head = 0;
2661
2662 sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
2663
2664 for (priv->cmd.token_mask = 1;
2665 priv->cmd.token_mask < priv->cmd.max_cmds;
2666 priv->cmd.token_mask <<= 1)
2667 ; /* nothing */
2668 --priv->cmd.token_mask;
2669
2670 down(&priv->cmd.poll_sem);
2671 priv->cmd.use_events = 1;
2672 up_write(&priv->cmd.switch_sem);
2673
2674 return err;
2675 }
2676
2677 /*
2678 * Switch back to polling (used when shutting down the device)
2679 */
mlx4_cmd_use_polling(struct mlx4_dev * dev)2680 void mlx4_cmd_use_polling(struct mlx4_dev *dev)
2681 {
2682 struct mlx4_priv *priv = mlx4_priv(dev);
2683 int i;
2684
2685 down_write(&priv->cmd.switch_sem);
2686 priv->cmd.use_events = 0;
2687
2688 for (i = 0; i < priv->cmd.max_cmds; ++i)
2689 down(&priv->cmd.event_sem);
2690
2691 kfree(priv->cmd.context);
2692
2693 up(&priv->cmd.poll_sem);
2694 up_write(&priv->cmd.switch_sem);
2695 }
2696
mlx4_alloc_cmd_mailbox(struct mlx4_dev * dev)2697 struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
2698 {
2699 struct mlx4_cmd_mailbox *mailbox;
2700
2701 mailbox = kmalloc(sizeof(*mailbox), GFP_KERNEL);
2702 if (!mailbox)
2703 return ERR_PTR(-ENOMEM);
2704
2705 mailbox->buf = dma_pool_zalloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
2706 &mailbox->dma);
2707 if (!mailbox->buf) {
2708 kfree(mailbox);
2709 return ERR_PTR(-ENOMEM);
2710 }
2711
2712 return mailbox;
2713 }
2714 EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
2715
mlx4_free_cmd_mailbox(struct mlx4_dev * dev,struct mlx4_cmd_mailbox * mailbox)2716 void mlx4_free_cmd_mailbox(struct mlx4_dev *dev,
2717 struct mlx4_cmd_mailbox *mailbox)
2718 {
2719 if (!mailbox)
2720 return;
2721
2722 dma_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
2723 kfree(mailbox);
2724 }
2725 EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
2726
mlx4_comm_get_version(void)2727 u32 mlx4_comm_get_version(void)
2728 {
2729 return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER;
2730 }
2731
mlx4_get_slave_indx(struct mlx4_dev * dev,int vf)2732 static int mlx4_get_slave_indx(struct mlx4_dev *dev, int vf)
2733 {
2734 if ((vf < 0) || (vf >= dev->persist->num_vfs)) {
2735 mlx4_err(dev, "Bad vf number:%d (number of activated vf: %d)\n",
2736 vf, dev->persist->num_vfs);
2737 return -EINVAL;
2738 }
2739
2740 return vf+1;
2741 }
2742
mlx4_get_vf_indx(struct mlx4_dev * dev,int slave)2743 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave)
2744 {
2745 if (slave < 1 || slave > dev->persist->num_vfs) {
2746 mlx4_err(dev,
2747 "Bad slave number:%d (number of activated slaves: %lu)\n",
2748 slave, dev->num_slaves);
2749 return -EINVAL;
2750 }
2751 return slave - 1;
2752 }
2753
mlx4_cmd_wake_completions(struct mlx4_dev * dev)2754 void mlx4_cmd_wake_completions(struct mlx4_dev *dev)
2755 {
2756 struct mlx4_priv *priv = mlx4_priv(dev);
2757 struct mlx4_cmd_context *context;
2758 int i;
2759
2760 spin_lock(&priv->cmd.context_lock);
2761 if (priv->cmd.context) {
2762 for (i = 0; i < priv->cmd.max_cmds; ++i) {
2763 context = &priv->cmd.context[i];
2764 context->fw_status = CMD_STAT_INTERNAL_ERR;
2765 context->result =
2766 mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
2767 complete(&context->done);
2768 }
2769 }
2770 spin_unlock(&priv->cmd.context_lock);
2771 }
2772
mlx4_get_active_ports(struct mlx4_dev * dev,int slave)2773 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave)
2774 {
2775 struct mlx4_active_ports actv_ports;
2776 int vf;
2777
2778 bitmap_zero(actv_ports.ports, MLX4_MAX_PORTS);
2779
2780 if (slave == 0) {
2781 bitmap_fill(actv_ports.ports, dev->caps.num_ports);
2782 return actv_ports;
2783 }
2784
2785 vf = mlx4_get_vf_indx(dev, slave);
2786 if (vf < 0)
2787 return actv_ports;
2788
2789 bitmap_set(actv_ports.ports, dev->dev_vfs[vf].min_port - 1,
2790 min((int)dev->dev_vfs[mlx4_get_vf_indx(dev, slave)].n_ports,
2791 dev->caps.num_ports));
2792
2793 return actv_ports;
2794 }
2795 EXPORT_SYMBOL_GPL(mlx4_get_active_ports);
2796
mlx4_slave_convert_port(struct mlx4_dev * dev,int slave,int port)2797 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port)
2798 {
2799 unsigned n;
2800 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2801 unsigned m = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2802
2803 if (port <= 0 || port > m)
2804 return -EINVAL;
2805
2806 n = find_first_bit(actv_ports.ports, dev->caps.num_ports);
2807 if (port <= n)
2808 port = n + 1;
2809
2810 return port;
2811 }
2812 EXPORT_SYMBOL_GPL(mlx4_slave_convert_port);
2813
mlx4_phys_to_slave_port(struct mlx4_dev * dev,int slave,int port)2814 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port)
2815 {
2816 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2817 if (test_bit(port - 1, actv_ports.ports))
2818 return port -
2819 find_first_bit(actv_ports.ports, dev->caps.num_ports);
2820
2821 return -1;
2822 }
2823 EXPORT_SYMBOL_GPL(mlx4_phys_to_slave_port);
2824
mlx4_phys_to_slaves_pport(struct mlx4_dev * dev,int port)2825 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
2826 int port)
2827 {
2828 unsigned i;
2829 struct mlx4_slaves_pport slaves_pport;
2830
2831 bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2832
2833 if (port <= 0 || port > dev->caps.num_ports)
2834 return slaves_pport;
2835
2836 for (i = 0; i < dev->persist->num_vfs + 1; i++) {
2837 struct mlx4_active_ports actv_ports =
2838 mlx4_get_active_ports(dev, i);
2839 if (test_bit(port - 1, actv_ports.ports))
2840 set_bit(i, slaves_pport.slaves);
2841 }
2842
2843 return slaves_pport;
2844 }
2845 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport);
2846
mlx4_phys_to_slaves_pport_actv(struct mlx4_dev * dev,const struct mlx4_active_ports * crit_ports)2847 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
2848 struct mlx4_dev *dev,
2849 const struct mlx4_active_ports *crit_ports)
2850 {
2851 unsigned i;
2852 struct mlx4_slaves_pport slaves_pport;
2853
2854 bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2855
2856 for (i = 0; i < dev->persist->num_vfs + 1; i++) {
2857 struct mlx4_active_ports actv_ports =
2858 mlx4_get_active_ports(dev, i);
2859 if (bitmap_equal(crit_ports->ports, actv_ports.ports,
2860 dev->caps.num_ports))
2861 set_bit(i, slaves_pport.slaves);
2862 }
2863
2864 return slaves_pport;
2865 }
2866 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport_actv);
2867
mlx4_slaves_closest_port(struct mlx4_dev * dev,int slave,int port)2868 static int mlx4_slaves_closest_port(struct mlx4_dev *dev, int slave, int port)
2869 {
2870 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2871 int min_port = find_first_bit(actv_ports.ports, dev->caps.num_ports)
2872 + 1;
2873 int max_port = min_port +
2874 bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2875
2876 if (port < min_port)
2877 port = min_port;
2878 else if (port >= max_port)
2879 port = max_port - 1;
2880
2881 return port;
2882 }
2883
mlx4_set_vport_qos(struct mlx4_priv * priv,int slave,int port,int max_tx_rate)2884 static int mlx4_set_vport_qos(struct mlx4_priv *priv, int slave, int port,
2885 int max_tx_rate)
2886 {
2887 int i;
2888 int err;
2889 struct mlx4_qos_manager *port_qos;
2890 struct mlx4_dev *dev = &priv->dev;
2891 struct mlx4_vport_qos_param vpp_qos[MLX4_NUM_UP];
2892
2893 port_qos = &priv->mfunc.master.qos_ctl[port];
2894 memset(vpp_qos, 0, sizeof(struct mlx4_vport_qos_param) * MLX4_NUM_UP);
2895
2896 if (slave > port_qos->num_of_qos_vfs) {
2897 mlx4_info(dev, "No available VPP resources for this VF\n");
2898 return -EINVAL;
2899 }
2900
2901 /* Query for default QoS values from Vport 0 is needed */
2902 err = mlx4_SET_VPORT_QOS_get(dev, port, 0, vpp_qos);
2903 if (err) {
2904 mlx4_info(dev, "Failed to query Vport 0 QoS values\n");
2905 return err;
2906 }
2907
2908 for (i = 0; i < MLX4_NUM_UP; i++) {
2909 if (test_bit(i, port_qos->priority_bm) && max_tx_rate) {
2910 vpp_qos[i].max_avg_bw = max_tx_rate;
2911 vpp_qos[i].enable = 1;
2912 } else {
2913 /* if user supplied tx_rate == 0, meaning no rate limit
2914 * configuration is required. so we are leaving the
2915 * value of max_avg_bw as queried from Vport 0.
2916 */
2917 vpp_qos[i].enable = 0;
2918 }
2919 }
2920
2921 err = mlx4_SET_VPORT_QOS_set(dev, port, slave, vpp_qos);
2922 if (err) {
2923 mlx4_info(dev, "Failed to set Vport %d QoS values\n", slave);
2924 return err;
2925 }
2926
2927 return 0;
2928 }
2929
mlx4_is_vf_vst_and_prio_qos(struct mlx4_dev * dev,int port,struct mlx4_vport_state * vf_admin)2930 static bool mlx4_is_vf_vst_and_prio_qos(struct mlx4_dev *dev, int port,
2931 struct mlx4_vport_state *vf_admin)
2932 {
2933 struct mlx4_qos_manager *info;
2934 struct mlx4_priv *priv = mlx4_priv(dev);
2935
2936 if (!mlx4_is_master(dev) ||
2937 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP))
2938 return false;
2939
2940 info = &priv->mfunc.master.qos_ctl[port];
2941
2942 if (vf_admin->default_vlan != MLX4_VGT &&
2943 test_bit(vf_admin->default_qos, info->priority_bm))
2944 return true;
2945
2946 return false;
2947 }
2948
mlx4_valid_vf_state_change(struct mlx4_dev * dev,int port,struct mlx4_vport_state * vf_admin,int vlan,int qos)2949 static bool mlx4_valid_vf_state_change(struct mlx4_dev *dev, int port,
2950 struct mlx4_vport_state *vf_admin,
2951 int vlan, int qos)
2952 {
2953 struct mlx4_vport_state dummy_admin = {0};
2954
2955 if (!mlx4_is_vf_vst_and_prio_qos(dev, port, vf_admin) ||
2956 !vf_admin->tx_rate)
2957 return true;
2958
2959 dummy_admin.default_qos = qos;
2960 dummy_admin.default_vlan = vlan;
2961
2962 /* VF wants to move to other VST state which is valid with current
2963 * rate limit. Either differnt default vlan in VST or other
2964 * supported QoS priority. Otherwise we don't allow this change when
2965 * the TX rate is still configured.
2966 */
2967 if (mlx4_is_vf_vst_and_prio_qos(dev, port, &dummy_admin))
2968 return true;
2969
2970 mlx4_info(dev, "Cannot change VF state to %s while rate is set\n",
2971 (vlan == MLX4_VGT) ? "VGT" : "VST");
2972
2973 if (vlan != MLX4_VGT)
2974 mlx4_info(dev, "VST priority %d not supported for QoS\n", qos);
2975
2976 mlx4_info(dev, "Please set rate to 0 prior to this VF state change\n");
2977
2978 return false;
2979 }
2980
mlx4_set_vf_mac(struct mlx4_dev * dev,int port,int vf,u8 * mac)2981 int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u8 *mac)
2982 {
2983 struct mlx4_priv *priv = mlx4_priv(dev);
2984 struct mlx4_vport_state *s_info;
2985 int slave;
2986
2987 if (!mlx4_is_master(dev))
2988 return -EPROTONOSUPPORT;
2989
2990 if (is_multicast_ether_addr(mac))
2991 return -EINVAL;
2992
2993 slave = mlx4_get_slave_indx(dev, vf);
2994 if (slave < 0)
2995 return -EINVAL;
2996
2997 port = mlx4_slaves_closest_port(dev, slave, port);
2998 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2999
3000 if (s_info->spoofchk && is_zero_ether_addr(mac)) {
3001 mlx4_info(dev, "MAC invalidation is not allowed when spoofchk is on\n");
3002 return -EPERM;
3003 }
3004
3005 s_info->mac = mlx4_mac_to_u64(mac);
3006 mlx4_info(dev, "default mac on vf %d port %d to %llX will take effect only after vf restart\n",
3007 vf, port, s_info->mac);
3008 return 0;
3009 }
3010 EXPORT_SYMBOL_GPL(mlx4_set_vf_mac);
3011
3012
mlx4_set_vf_vlan(struct mlx4_dev * dev,int port,int vf,u16 vlan,u8 qos,__be16 proto)3013 int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos,
3014 __be16 proto)
3015 {
3016 struct mlx4_priv *priv = mlx4_priv(dev);
3017 struct mlx4_vport_state *vf_admin;
3018 struct mlx4_slave_state *slave_state;
3019 struct mlx4_vport_oper_state *vf_oper;
3020 int slave;
3021
3022 if ((!mlx4_is_master(dev)) ||
3023 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VLAN_CONTROL))
3024 return -EPROTONOSUPPORT;
3025
3026 if ((vlan > 4095) || (qos > 7))
3027 return -EINVAL;
3028
3029 if (proto == htons(ETH_P_8021AD) &&
3030 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SVLAN_BY_QP))
3031 return -EPROTONOSUPPORT;
3032
3033 if (proto != htons(ETH_P_8021Q) &&
3034 proto != htons(ETH_P_8021AD))
3035 return -EINVAL;
3036
3037 if ((proto == htons(ETH_P_8021AD)) &&
3038 ((vlan == 0) || (vlan == MLX4_VGT)))
3039 return -EINVAL;
3040
3041 slave = mlx4_get_slave_indx(dev, vf);
3042 if (slave < 0)
3043 return -EINVAL;
3044
3045 slave_state = &priv->mfunc.master.slave_state[slave];
3046 if ((proto == htons(ETH_P_8021AD)) && (slave_state->active) &&
3047 (!slave_state->vst_qinq_supported)) {
3048 mlx4_err(dev, "vf %d does not support VST QinQ mode\n", vf);
3049 return -EPROTONOSUPPORT;
3050 }
3051 port = mlx4_slaves_closest_port(dev, slave, port);
3052 vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
3053 vf_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
3054
3055 if (!mlx4_valid_vf_state_change(dev, port, vf_admin, vlan, qos))
3056 return -EPERM;
3057
3058 if ((0 == vlan) && (0 == qos))
3059 vf_admin->default_vlan = MLX4_VGT;
3060 else
3061 vf_admin->default_vlan = vlan;
3062 vf_admin->default_qos = qos;
3063 vf_admin->vlan_proto = proto;
3064
3065 /* If rate was configured prior to VST, we saved the configured rate
3066 * in vf_admin->rate and now, if priority supported we enforce the QoS
3067 */
3068 if (mlx4_is_vf_vst_and_prio_qos(dev, port, vf_admin) &&
3069 vf_admin->tx_rate)
3070 vf_admin->qos_vport = slave;
3071
3072 /* Try to activate new vf state without restart,
3073 * this option is not supported while moving to VST QinQ mode.
3074 */
3075 if ((proto == htons(ETH_P_8021AD) &&
3076 vf_oper->state.vlan_proto != proto) ||
3077 mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
3078 mlx4_info(dev,
3079 "updating vf %d port %d config will take effect on next VF restart\n",
3080 vf, port);
3081 return 0;
3082 }
3083 EXPORT_SYMBOL_GPL(mlx4_set_vf_vlan);
3084
mlx4_set_vf_rate(struct mlx4_dev * dev,int port,int vf,int min_tx_rate,int max_tx_rate)3085 int mlx4_set_vf_rate(struct mlx4_dev *dev, int port, int vf, int min_tx_rate,
3086 int max_tx_rate)
3087 {
3088 int err;
3089 int slave;
3090 struct mlx4_vport_state *vf_admin;
3091 struct mlx4_priv *priv = mlx4_priv(dev);
3092
3093 if (!mlx4_is_master(dev) ||
3094 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QOS_VPP))
3095 return -EPROTONOSUPPORT;
3096
3097 if (min_tx_rate) {
3098 mlx4_info(dev, "Minimum BW share not supported\n");
3099 return -EPROTONOSUPPORT;
3100 }
3101
3102 slave = mlx4_get_slave_indx(dev, vf);
3103 if (slave < 0)
3104 return -EINVAL;
3105
3106 port = mlx4_slaves_closest_port(dev, slave, port);
3107 vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
3108
3109 err = mlx4_set_vport_qos(priv, slave, port, max_tx_rate);
3110 if (err) {
3111 mlx4_info(dev, "vf %d failed to set rate %d\n", vf,
3112 max_tx_rate);
3113 return err;
3114 }
3115
3116 vf_admin->tx_rate = max_tx_rate;
3117 /* if VF is not in supported mode (VST with supported prio),
3118 * we do not change vport configuration for its QPs, but save
3119 * the rate, so it will be enforced when it moves to supported
3120 * mode next time.
3121 */
3122 if (!mlx4_is_vf_vst_and_prio_qos(dev, port, vf_admin)) {
3123 mlx4_info(dev,
3124 "rate set for VF %d when not in valid state\n", vf);
3125
3126 if (vf_admin->default_vlan != MLX4_VGT)
3127 mlx4_info(dev, "VST priority not supported by QoS\n");
3128 else
3129 mlx4_info(dev, "VF in VGT mode (needed VST)\n");
3130
3131 mlx4_info(dev,
3132 "rate %d take affect when VF moves to valid state\n",
3133 max_tx_rate);
3134 return 0;
3135 }
3136
3137 /* If user sets rate 0 assigning default vport for its QPs */
3138 vf_admin->qos_vport = max_tx_rate ? slave : MLX4_VPP_DEFAULT_VPORT;
3139
3140 if (priv->mfunc.master.slave_state[slave].active &&
3141 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP)
3142 mlx4_master_immediate_activate_vlan_qos(priv, slave, port);
3143
3144 return 0;
3145 }
3146 EXPORT_SYMBOL_GPL(mlx4_set_vf_rate);
3147
3148 /* mlx4_get_slave_default_vlan -
3149 * return true if VST ( default vlan)
3150 * if VST, will return vlan & qos (if not NULL)
3151 */
mlx4_get_slave_default_vlan(struct mlx4_dev * dev,int port,int slave,u16 * vlan,u8 * qos)3152 bool mlx4_get_slave_default_vlan(struct mlx4_dev *dev, int port, int slave,
3153 u16 *vlan, u8 *qos)
3154 {
3155 struct mlx4_vport_oper_state *vp_oper;
3156 struct mlx4_priv *priv;
3157
3158 priv = mlx4_priv(dev);
3159 port = mlx4_slaves_closest_port(dev, slave, port);
3160 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
3161
3162 if (MLX4_VGT != vp_oper->state.default_vlan) {
3163 if (vlan)
3164 *vlan = vp_oper->state.default_vlan;
3165 if (qos)
3166 *qos = vp_oper->state.default_qos;
3167 return true;
3168 }
3169 return false;
3170 }
3171 EXPORT_SYMBOL_GPL(mlx4_get_slave_default_vlan);
3172
mlx4_set_vf_spoofchk(struct mlx4_dev * dev,int port,int vf,bool setting)3173 int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting)
3174 {
3175 struct mlx4_priv *priv = mlx4_priv(dev);
3176 struct mlx4_vport_state *s_info;
3177 int slave;
3178 u8 mac[ETH_ALEN];
3179
3180 if ((!mlx4_is_master(dev)) ||
3181 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FSM))
3182 return -EPROTONOSUPPORT;
3183
3184 slave = mlx4_get_slave_indx(dev, vf);
3185 if (slave < 0)
3186 return -EINVAL;
3187
3188 port = mlx4_slaves_closest_port(dev, slave, port);
3189 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
3190
3191 mlx4_u64_to_mac(mac, s_info->mac);
3192 if (setting && !is_valid_ether_addr(mac)) {
3193 mlx4_info(dev, "Illegal MAC with spoofchk\n");
3194 return -EPERM;
3195 }
3196
3197 s_info->spoofchk = setting;
3198
3199 return 0;
3200 }
3201 EXPORT_SYMBOL_GPL(mlx4_set_vf_spoofchk);
3202
mlx4_get_vf_config(struct mlx4_dev * dev,int port,int vf,struct ifla_vf_info * ivf)3203 int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf)
3204 {
3205 struct mlx4_priv *priv = mlx4_priv(dev);
3206 struct mlx4_vport_state *s_info;
3207 int slave;
3208
3209 if (!mlx4_is_master(dev))
3210 return -EPROTONOSUPPORT;
3211
3212 slave = mlx4_get_slave_indx(dev, vf);
3213 if (slave < 0)
3214 return -EINVAL;
3215
3216 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
3217 ivf->vf = vf;
3218
3219 /* need to convert it to a func */
3220 ivf->mac[0] = ((s_info->mac >> (5*8)) & 0xff);
3221 ivf->mac[1] = ((s_info->mac >> (4*8)) & 0xff);
3222 ivf->mac[2] = ((s_info->mac >> (3*8)) & 0xff);
3223 ivf->mac[3] = ((s_info->mac >> (2*8)) & 0xff);
3224 ivf->mac[4] = ((s_info->mac >> (1*8)) & 0xff);
3225 ivf->mac[5] = ((s_info->mac) & 0xff);
3226
3227 ivf->vlan = s_info->default_vlan;
3228 ivf->qos = s_info->default_qos;
3229 ivf->vlan_proto = s_info->vlan_proto;
3230
3231 if (mlx4_is_vf_vst_and_prio_qos(dev, port, s_info))
3232 ivf->max_tx_rate = s_info->tx_rate;
3233 else
3234 ivf->max_tx_rate = 0;
3235
3236 ivf->min_tx_rate = 0;
3237 ivf->spoofchk = s_info->spoofchk;
3238 ivf->linkstate = s_info->link_state;
3239
3240 return 0;
3241 }
3242 EXPORT_SYMBOL_GPL(mlx4_get_vf_config);
3243
mlx4_set_vf_link_state(struct mlx4_dev * dev,int port,int vf,int link_state)3244 int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state)
3245 {
3246 struct mlx4_priv *priv = mlx4_priv(dev);
3247 struct mlx4_vport_state *s_info;
3248 int slave;
3249 u8 link_stat_event;
3250
3251 slave = mlx4_get_slave_indx(dev, vf);
3252 if (slave < 0)
3253 return -EINVAL;
3254
3255 port = mlx4_slaves_closest_port(dev, slave, port);
3256 switch (link_state) {
3257 case IFLA_VF_LINK_STATE_AUTO:
3258 /* get current link state */
3259 if (!priv->sense.do_sense_port[port])
3260 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
3261 else
3262 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
3263 break;
3264
3265 case IFLA_VF_LINK_STATE_ENABLE:
3266 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
3267 break;
3268
3269 case IFLA_VF_LINK_STATE_DISABLE:
3270 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
3271 break;
3272
3273 default:
3274 mlx4_warn(dev, "unknown value for link_state %02x on slave %d port %d\n",
3275 link_state, slave, port);
3276 return -EINVAL;
3277 };
3278 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
3279 s_info->link_state = link_state;
3280
3281 /* send event */
3282 mlx4_gen_port_state_change_eqe(dev, slave, port, link_stat_event);
3283
3284 if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
3285 mlx4_dbg(dev,
3286 "updating vf %d port %d no link state HW enforcement\n",
3287 vf, port);
3288 return 0;
3289 }
3290 EXPORT_SYMBOL_GPL(mlx4_set_vf_link_state);
3291
mlx4_get_counter_stats(struct mlx4_dev * dev,int counter_index,struct mlx4_counter * counter_stats,int reset)3292 int mlx4_get_counter_stats(struct mlx4_dev *dev, int counter_index,
3293 struct mlx4_counter *counter_stats, int reset)
3294 {
3295 struct mlx4_cmd_mailbox *mailbox = NULL;
3296 struct mlx4_counter *tmp_counter;
3297 int err;
3298 u32 if_stat_in_mod;
3299
3300 if (!counter_stats)
3301 return -EINVAL;
3302
3303 if (counter_index == MLX4_SINK_COUNTER_INDEX(dev))
3304 return 0;
3305
3306 mailbox = mlx4_alloc_cmd_mailbox(dev);
3307 if (IS_ERR(mailbox))
3308 return PTR_ERR(mailbox);
3309
3310 memset(mailbox->buf, 0, sizeof(struct mlx4_counter));
3311 if_stat_in_mod = counter_index;
3312 if (reset)
3313 if_stat_in_mod |= MLX4_QUERY_IF_STAT_RESET;
3314 err = mlx4_cmd_box(dev, 0, mailbox->dma,
3315 if_stat_in_mod, 0,
3316 MLX4_CMD_QUERY_IF_STAT,
3317 MLX4_CMD_TIME_CLASS_C,
3318 MLX4_CMD_NATIVE);
3319 if (err) {
3320 mlx4_dbg(dev, "%s: failed to read statistics for counter index %d\n",
3321 __func__, counter_index);
3322 goto if_stat_out;
3323 }
3324 tmp_counter = (struct mlx4_counter *)mailbox->buf;
3325 counter_stats->counter_mode = tmp_counter->counter_mode;
3326 if (counter_stats->counter_mode == 0) {
3327 counter_stats->rx_frames =
3328 cpu_to_be64(be64_to_cpu(counter_stats->rx_frames) +
3329 be64_to_cpu(tmp_counter->rx_frames));
3330 counter_stats->tx_frames =
3331 cpu_to_be64(be64_to_cpu(counter_stats->tx_frames) +
3332 be64_to_cpu(tmp_counter->tx_frames));
3333 counter_stats->rx_bytes =
3334 cpu_to_be64(be64_to_cpu(counter_stats->rx_bytes) +
3335 be64_to_cpu(tmp_counter->rx_bytes));
3336 counter_stats->tx_bytes =
3337 cpu_to_be64(be64_to_cpu(counter_stats->tx_bytes) +
3338 be64_to_cpu(tmp_counter->tx_bytes));
3339 }
3340
3341 if_stat_out:
3342 mlx4_free_cmd_mailbox(dev, mailbox);
3343
3344 return err;
3345 }
3346 EXPORT_SYMBOL_GPL(mlx4_get_counter_stats);
3347
mlx4_get_vf_stats(struct mlx4_dev * dev,int port,int vf_idx,struct ifla_vf_stats * vf_stats)3348 int mlx4_get_vf_stats(struct mlx4_dev *dev, int port, int vf_idx,
3349 struct ifla_vf_stats *vf_stats)
3350 {
3351 struct mlx4_counter tmp_vf_stats;
3352 int slave;
3353 int err = 0;
3354
3355 if (!vf_stats)
3356 return -EINVAL;
3357
3358 if (!mlx4_is_master(dev))
3359 return -EPROTONOSUPPORT;
3360
3361 slave = mlx4_get_slave_indx(dev, vf_idx);
3362 if (slave < 0)
3363 return -EINVAL;
3364
3365 port = mlx4_slaves_closest_port(dev, slave, port);
3366 err = mlx4_calc_vf_counters(dev, slave, port, &tmp_vf_stats);
3367 if (!err && tmp_vf_stats.counter_mode == 0) {
3368 vf_stats->rx_packets = be64_to_cpu(tmp_vf_stats.rx_frames);
3369 vf_stats->tx_packets = be64_to_cpu(tmp_vf_stats.tx_frames);
3370 vf_stats->rx_bytes = be64_to_cpu(tmp_vf_stats.rx_bytes);
3371 vf_stats->tx_bytes = be64_to_cpu(tmp_vf_stats.tx_bytes);
3372 }
3373
3374 return err;
3375 }
3376 EXPORT_SYMBOL_GPL(mlx4_get_vf_stats);
3377
mlx4_vf_smi_enabled(struct mlx4_dev * dev,int slave,int port)3378 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port)
3379 {
3380 struct mlx4_priv *priv = mlx4_priv(dev);
3381
3382 if (slave < 1 || slave >= dev->num_slaves ||
3383 port < 1 || port > MLX4_MAX_PORTS)
3384 return 0;
3385
3386 return priv->mfunc.master.vf_oper[slave].smi_enabled[port] ==
3387 MLX4_VF_SMI_ENABLED;
3388 }
3389 EXPORT_SYMBOL_GPL(mlx4_vf_smi_enabled);
3390
mlx4_vf_get_enable_smi_admin(struct mlx4_dev * dev,int slave,int port)3391 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port)
3392 {
3393 struct mlx4_priv *priv = mlx4_priv(dev);
3394
3395 if (slave == mlx4_master_func_num(dev))
3396 return 1;
3397
3398 if (slave < 1 || slave >= dev->num_slaves ||
3399 port < 1 || port > MLX4_MAX_PORTS)
3400 return 0;
3401
3402 return priv->mfunc.master.vf_admin[slave].enable_smi[port] ==
3403 MLX4_VF_SMI_ENABLED;
3404 }
3405 EXPORT_SYMBOL_GPL(mlx4_vf_get_enable_smi_admin);
3406
mlx4_vf_set_enable_smi_admin(struct mlx4_dev * dev,int slave,int port,int enabled)3407 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
3408 int enabled)
3409 {
3410 struct mlx4_priv *priv = mlx4_priv(dev);
3411 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
3412 &priv->dev, slave);
3413 int min_port = find_first_bit(actv_ports.ports,
3414 priv->dev.caps.num_ports) + 1;
3415 int max_port = min_port - 1 +
3416 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
3417
3418 if (slave == mlx4_master_func_num(dev))
3419 return 0;
3420
3421 if (slave < 1 || slave >= dev->num_slaves ||
3422 port < 1 || port > MLX4_MAX_PORTS ||
3423 enabled < 0 || enabled > 1)
3424 return -EINVAL;
3425
3426 if (min_port == max_port && dev->caps.num_ports > 1) {
3427 mlx4_info(dev, "SMI access disallowed for single ported VFs\n");
3428 return -EPROTONOSUPPORT;
3429 }
3430
3431 priv->mfunc.master.vf_admin[slave].enable_smi[port] = enabled;
3432 return 0;
3433 }
3434 EXPORT_SYMBOL_GPL(mlx4_vf_set_enable_smi_admin);
3435
