1 /* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG (wei_wang@realsil.com.cn)
20 * Micky Ching (micky_ching@realsil.com.cn)
21 */
22
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
26
27 #include "rtsx.h"
28 #include "spi.h"
29
spi_set_err_code(struct rtsx_chip * chip,u8 err_code)30 static inline void spi_set_err_code(struct rtsx_chip *chip, u8 err_code)
31 {
32 struct spi_info *spi = &chip->spi;
33
34 spi->err_code = err_code;
35 }
36
spi_init(struct rtsx_chip * chip)37 static int spi_init(struct rtsx_chip *chip)
38 {
39 int retval;
40
41 retval = rtsx_write_register(chip, SPI_CONTROL, 0xFF,
42 CS_POLARITY_LOW | DTO_MSB_FIRST
43 | SPI_MASTER | SPI_MODE0 | SPI_AUTO);
44 if (retval) {
45 return retval;
46 }
47 retval = rtsx_write_register(chip, SPI_TCTL, EDO_TIMING_MASK,
48 SAMPLE_DELAY_HALF);
49 if (retval) {
50 return retval;
51 }
52
53 return STATUS_SUCCESS;
54 }
55
spi_set_init_para(struct rtsx_chip * chip)56 static int spi_set_init_para(struct rtsx_chip *chip)
57 {
58 struct spi_info *spi = &chip->spi;
59 int retval;
60
61 retval = rtsx_write_register(chip, SPI_CLK_DIVIDER1, 0xFF,
62 (u8)(spi->clk_div >> 8));
63 if (retval) {
64 return retval;
65 }
66 retval = rtsx_write_register(chip, SPI_CLK_DIVIDER0, 0xFF,
67 (u8)(spi->clk_div));
68 if (retval) {
69 return retval;
70 }
71
72 retval = switch_clock(chip, spi->spi_clock);
73 if (retval != STATUS_SUCCESS) {
74 return STATUS_FAIL;
75 }
76
77 retval = select_card(chip, SPI_CARD);
78 if (retval != STATUS_SUCCESS) {
79 return STATUS_FAIL;
80 }
81
82 retval = rtsx_write_register(chip, CARD_CLK_EN, SPI_CLK_EN,
83 SPI_CLK_EN);
84 if (retval) {
85 return retval;
86 }
87 retval = rtsx_write_register(chip, CARD_OE, SPI_OUTPUT_EN,
88 SPI_OUTPUT_EN);
89 if (retval) {
90 return retval;
91 }
92
93 wait_timeout(10);
94
95 retval = spi_init(chip);
96 if (retval != STATUS_SUCCESS) {
97 return STATUS_FAIL;
98 }
99
100 return STATUS_SUCCESS;
101 }
102
sf_polling_status(struct rtsx_chip * chip,int msec)103 static int sf_polling_status(struct rtsx_chip *chip, int msec)
104 {
105 int retval;
106
107 rtsx_init_cmd(chip);
108
109 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, SPI_RDSR);
110 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
111 SPI_TRANSFER0_START | SPI_POLLING_MODE0);
112 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
113 SPI_TRANSFER0_END);
114
115 retval = rtsx_send_cmd(chip, 0, msec);
116 if (retval < 0) {
117 rtsx_clear_spi_error(chip);
118 spi_set_err_code(chip, SPI_BUSY_ERR);
119 return STATUS_FAIL;
120 }
121
122 return STATUS_SUCCESS;
123 }
124
sf_enable_write(struct rtsx_chip * chip,u8 ins)125 static int sf_enable_write(struct rtsx_chip *chip, u8 ins)
126 {
127 struct spi_info *spi = &chip->spi;
128 int retval;
129
130 if (!spi->write_en)
131 return STATUS_SUCCESS;
132
133 rtsx_init_cmd(chip);
134
135 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
136 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
137 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
138 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
139 SPI_TRANSFER0_START | SPI_C_MODE0);
140 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
141 SPI_TRANSFER0_END);
142
143 retval = rtsx_send_cmd(chip, 0, 100);
144 if (retval < 0) {
145 rtsx_clear_spi_error(chip);
146 spi_set_err_code(chip, SPI_HW_ERR);
147 return STATUS_FAIL;
148 }
149
150 return STATUS_SUCCESS;
151 }
152
sf_disable_write(struct rtsx_chip * chip,u8 ins)153 static int sf_disable_write(struct rtsx_chip *chip, u8 ins)
154 {
155 struct spi_info *spi = &chip->spi;
156 int retval;
157
158 if (!spi->write_en)
159 return STATUS_SUCCESS;
160
161 rtsx_init_cmd(chip);
162
163 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
164 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
165 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
166 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
167 SPI_TRANSFER0_START | SPI_C_MODE0);
168 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
169 SPI_TRANSFER0_END);
170
171 retval = rtsx_send_cmd(chip, 0, 100);
172 if (retval < 0) {
173 rtsx_clear_spi_error(chip);
174 spi_set_err_code(chip, SPI_HW_ERR);
175 return STATUS_FAIL;
176 }
177
178 return STATUS_SUCCESS;
179 }
180
sf_program(struct rtsx_chip * chip,u8 ins,u8 addr_mode,u32 addr,u16 len)181 static void sf_program(struct rtsx_chip *chip, u8 ins, u8 addr_mode, u32 addr,
182 u16 len)
183 {
184 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
185 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
186 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
187 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, (u8)len);
188 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, (u8)(len >> 8));
189 if (addr_mode) {
190 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
191 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
192 (u8)(addr >> 8));
193 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
194 (u8)(addr >> 16));
195 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
196 SPI_TRANSFER0_START | SPI_CADO_MODE0);
197 } else {
198 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
199 SPI_TRANSFER0_START | SPI_CDO_MODE0);
200 }
201 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
202 SPI_TRANSFER0_END);
203 }
204
sf_erase(struct rtsx_chip * chip,u8 ins,u8 addr_mode,u32 addr)205 static int sf_erase(struct rtsx_chip *chip, u8 ins, u8 addr_mode, u32 addr)
206 {
207 int retval;
208
209 rtsx_init_cmd(chip);
210
211 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
212 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
213 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
214 if (addr_mode) {
215 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
216 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
217 (u8)(addr >> 8));
218 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
219 (u8)(addr >> 16));
220 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
221 SPI_TRANSFER0_START | SPI_CA_MODE0);
222 } else {
223 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
224 SPI_TRANSFER0_START | SPI_C_MODE0);
225 }
226 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
227 SPI_TRANSFER0_END);
228
229 retval = rtsx_send_cmd(chip, 0, 100);
230 if (retval < 0) {
231 rtsx_clear_spi_error(chip);
232 spi_set_err_code(chip, SPI_HW_ERR);
233 return STATUS_FAIL;
234 }
235
236 return STATUS_SUCCESS;
237 }
238
spi_init_eeprom(struct rtsx_chip * chip)239 static int spi_init_eeprom(struct rtsx_chip *chip)
240 {
241 int retval;
242 int clk;
243
244 if (chip->asic_code)
245 clk = 30;
246 else
247 clk = CLK_30;
248
249 retval = rtsx_write_register(chip, SPI_CLK_DIVIDER1, 0xFF, 0x00);
250 if (retval) {
251 return retval;
252 }
253 retval = rtsx_write_register(chip, SPI_CLK_DIVIDER0, 0xFF, 0x27);
254 if (retval) {
255 return retval;
256 }
257
258 retval = switch_clock(chip, clk);
259 if (retval != STATUS_SUCCESS) {
260 return STATUS_FAIL;
261 }
262
263 retval = select_card(chip, SPI_CARD);
264 if (retval != STATUS_SUCCESS) {
265 return STATUS_FAIL;
266 }
267
268 retval = rtsx_write_register(chip, CARD_CLK_EN, SPI_CLK_EN,
269 SPI_CLK_EN);
270 if (retval) {
271 return retval;
272 }
273 retval = rtsx_write_register(chip, CARD_OE, SPI_OUTPUT_EN,
274 SPI_OUTPUT_EN);
275 if (retval) {
276 return retval;
277 }
278
279 wait_timeout(10);
280
281 retval = rtsx_write_register(chip, SPI_CONTROL, 0xFF,
282 CS_POLARITY_HIGH | SPI_EEPROM_AUTO);
283 if (retval) {
284 return retval;
285 }
286 retval = rtsx_write_register(chip, SPI_TCTL, EDO_TIMING_MASK,
287 SAMPLE_DELAY_HALF);
288 if (retval) {
289 return retval;
290 }
291
292 return STATUS_SUCCESS;
293 }
294
spi_eeprom_program_enable(struct rtsx_chip * chip)295 static int spi_eeprom_program_enable(struct rtsx_chip *chip)
296 {
297 int retval;
298
299 rtsx_init_cmd(chip);
300
301 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x86);
302 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x13);
303 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
304 SPI_TRANSFER0_START | SPI_CA_MODE0);
305 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
306 SPI_TRANSFER0_END);
307
308 retval = rtsx_send_cmd(chip, 0, 100);
309 if (retval < 0) {
310 return STATUS_FAIL;
311 }
312
313 return STATUS_SUCCESS;
314 }
315
spi_erase_eeprom_chip(struct rtsx_chip * chip)316 int spi_erase_eeprom_chip(struct rtsx_chip *chip)
317 {
318 int retval;
319
320 retval = spi_init_eeprom(chip);
321 if (retval != STATUS_SUCCESS) {
322 return STATUS_FAIL;
323 }
324
325 retval = spi_eeprom_program_enable(chip);
326 if (retval != STATUS_SUCCESS) {
327 return STATUS_FAIL;
328 }
329
330 rtsx_init_cmd(chip);
331
332 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
333 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
334 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x12);
335 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x84);
336 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
337 SPI_TRANSFER0_START | SPI_CA_MODE0);
338 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
339 SPI_TRANSFER0_END);
340
341 retval = rtsx_send_cmd(chip, 0, 100);
342 if (retval < 0) {
343 return STATUS_FAIL;
344 }
345
346 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01);
347 if (retval) {
348 return retval;
349 }
350
351 return STATUS_SUCCESS;
352 }
353
spi_erase_eeprom_byte(struct rtsx_chip * chip,u16 addr)354 int spi_erase_eeprom_byte(struct rtsx_chip *chip, u16 addr)
355 {
356 int retval;
357
358 retval = spi_init_eeprom(chip);
359 if (retval != STATUS_SUCCESS) {
360 return STATUS_FAIL;
361 }
362
363 retval = spi_eeprom_program_enable(chip);
364 if (retval != STATUS_SUCCESS) {
365 return STATUS_FAIL;
366 }
367
368 rtsx_init_cmd(chip);
369
370 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
371 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
372 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x07);
373 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
374 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)(addr >> 8));
375 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x46);
376 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
377 SPI_TRANSFER0_START | SPI_CA_MODE0);
378 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
379 SPI_TRANSFER0_END);
380
381 retval = rtsx_send_cmd(chip, 0, 100);
382 if (retval < 0) {
383 return STATUS_FAIL;
384 }
385
386 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01);
387 if (retval) {
388 return retval;
389 }
390
391 return STATUS_SUCCESS;
392 }
393
spi_read_eeprom(struct rtsx_chip * chip,u16 addr,u8 * val)394 int spi_read_eeprom(struct rtsx_chip *chip, u16 addr, u8 *val)
395 {
396 int retval;
397 u8 data;
398
399 retval = spi_init_eeprom(chip);
400 if (retval != STATUS_SUCCESS) {
401 return STATUS_FAIL;
402 }
403
404 rtsx_init_cmd(chip);
405
406 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
407 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
408 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x06);
409 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
410 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)(addr >> 8));
411 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x46);
412 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 1);
413 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
414 SPI_TRANSFER0_START | SPI_CADI_MODE0);
415 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
416 SPI_TRANSFER0_END);
417
418 retval = rtsx_send_cmd(chip, 0, 100);
419 if (retval < 0) {
420 return STATUS_FAIL;
421 }
422
423 wait_timeout(5);
424 retval = rtsx_read_register(chip, SPI_DATA, &data);
425 if (retval) {
426 return retval;
427 }
428
429 if (val)
430 *val = data;
431
432 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01);
433 if (retval) {
434 return retval;
435 }
436
437 return STATUS_SUCCESS;
438 }
439
spi_write_eeprom(struct rtsx_chip * chip,u16 addr,u8 val)440 int spi_write_eeprom(struct rtsx_chip *chip, u16 addr, u8 val)
441 {
442 int retval;
443
444 retval = spi_init_eeprom(chip);
445 if (retval != STATUS_SUCCESS) {
446 return STATUS_FAIL;
447 }
448
449 retval = spi_eeprom_program_enable(chip);
450 if (retval != STATUS_SUCCESS) {
451 return STATUS_FAIL;
452 }
453
454 rtsx_init_cmd(chip);
455
456 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
457 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
458 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x05);
459 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, val);
460 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)addr);
461 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, (u8)(addr >> 8));
462 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x4E);
463 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
464 SPI_TRANSFER0_START | SPI_CA_MODE0);
465 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
466 SPI_TRANSFER0_END);
467
468 retval = rtsx_send_cmd(chip, 0, 100);
469 if (retval < 0) {
470 return STATUS_FAIL;
471 }
472
473 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01);
474 if (retval) {
475 return retval;
476 }
477
478 return STATUS_SUCCESS;
479 }
480
spi_get_status(struct scsi_cmnd * srb,struct rtsx_chip * chip)481 int spi_get_status(struct scsi_cmnd *srb, struct rtsx_chip *chip)
482 {
483 struct spi_info *spi = &chip->spi;
484
485 dev_dbg(rtsx_dev(chip), "%s: err_code = 0x%x\n", __func__,
486 spi->err_code);
487 rtsx_stor_set_xfer_buf(&spi->err_code,
488 min_t(int, scsi_bufflen(srb), 1), srb);
489 scsi_set_resid(srb, scsi_bufflen(srb) - 1);
490
491 return STATUS_SUCCESS;
492 }
493
spi_set_parameter(struct scsi_cmnd * srb,struct rtsx_chip * chip)494 int spi_set_parameter(struct scsi_cmnd *srb, struct rtsx_chip *chip)
495 {
496 struct spi_info *spi = &chip->spi;
497
498 spi_set_err_code(chip, SPI_NO_ERR);
499
500 if (chip->asic_code)
501 spi->spi_clock = ((u16)(srb->cmnd[8]) << 8) | srb->cmnd[9];
502 else
503 spi->spi_clock = srb->cmnd[3];
504
505 spi->clk_div = ((u16)(srb->cmnd[4]) << 8) | srb->cmnd[5];
506 spi->write_en = srb->cmnd[6];
507
508 dev_dbg(rtsx_dev(chip), "%s: ", __func__);
509 dev_dbg(rtsx_dev(chip), "spi_clock = %d, ", spi->spi_clock);
510 dev_dbg(rtsx_dev(chip), "clk_div = %d, ", spi->clk_div);
511 dev_dbg(rtsx_dev(chip), "write_en = %d\n", spi->write_en);
512
513 return STATUS_SUCCESS;
514 }
515
spi_read_flash_id(struct scsi_cmnd * srb,struct rtsx_chip * chip)516 int spi_read_flash_id(struct scsi_cmnd *srb, struct rtsx_chip *chip)
517 {
518 int retval;
519 u16 len;
520 u8 *buf;
521
522 spi_set_err_code(chip, SPI_NO_ERR);
523
524 len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8];
525 if (len > 512) {
526 spi_set_err_code(chip, SPI_INVALID_COMMAND);
527 return STATUS_FAIL;
528 }
529
530 retval = spi_set_init_para(chip);
531 if (retval != STATUS_SUCCESS) {
532 spi_set_err_code(chip, SPI_HW_ERR);
533 return STATUS_FAIL;
534 }
535
536 rtsx_init_cmd(chip);
537
538 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
539 PINGPONG_BUFFER);
540
541 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, srb->cmnd[3]);
542 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, srb->cmnd[4]);
543 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, srb->cmnd[5]);
544 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, srb->cmnd[6]);
545 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
546 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
547 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, srb->cmnd[7]);
548 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, srb->cmnd[8]);
549
550 if (len == 0) {
551 if (srb->cmnd[9]) {
552 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0,
553 0xFF, SPI_TRANSFER0_START | SPI_CA_MODE0);
554 } else {
555 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0,
556 0xFF, SPI_TRANSFER0_START | SPI_C_MODE0);
557 }
558 } else {
559 if (srb->cmnd[9]) {
560 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
561 SPI_TRANSFER0_START | SPI_CADI_MODE0);
562 } else {
563 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
564 SPI_TRANSFER0_START | SPI_CDI_MODE0);
565 }
566 }
567
568 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
569 SPI_TRANSFER0_END);
570
571 retval = rtsx_send_cmd(chip, 0, 100);
572 if (retval < 0) {
573 rtsx_clear_spi_error(chip);
574 spi_set_err_code(chip, SPI_HW_ERR);
575 return STATUS_FAIL;
576 }
577
578 if (len) {
579 buf = kmalloc(len, GFP_KERNEL);
580 if (!buf) {
581 return STATUS_ERROR;
582 }
583
584 retval = rtsx_read_ppbuf(chip, buf, len);
585 if (retval != STATUS_SUCCESS) {
586 spi_set_err_code(chip, SPI_READ_ERR);
587 kfree(buf);
588 return STATUS_FAIL;
589 }
590
591 rtsx_stor_set_xfer_buf(buf, scsi_bufflen(srb), srb);
592 scsi_set_resid(srb, 0);
593
594 kfree(buf);
595 }
596
597 return STATUS_SUCCESS;
598 }
599
spi_read_flash(struct scsi_cmnd * srb,struct rtsx_chip * chip)600 int spi_read_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip)
601 {
602 int retval;
603 unsigned int index = 0, offset = 0;
604 u8 ins, slow_read;
605 u32 addr;
606 u16 len;
607 u8 *buf;
608
609 spi_set_err_code(chip, SPI_NO_ERR);
610
611 ins = srb->cmnd[3];
612 addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5])
613 << 8) | srb->cmnd[6];
614 len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8];
615 slow_read = srb->cmnd[9];
616
617 retval = spi_set_init_para(chip);
618 if (retval != STATUS_SUCCESS) {
619 spi_set_err_code(chip, SPI_HW_ERR);
620 return STATUS_FAIL;
621 }
622
623 buf = kmalloc(SF_PAGE_LEN, GFP_KERNEL);
624 if (!buf) {
625 return STATUS_ERROR;
626 }
627
628 while (len) {
629 u16 pagelen = SF_PAGE_LEN - (u8)addr;
630
631 if (pagelen > len)
632 pagelen = len;
633
634 rtsx_init_cmd(chip);
635
636 trans_dma_enable(DMA_FROM_DEVICE, chip, 256, DMA_256);
637
638 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
639
640 if (slow_read) {
641 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF,
642 (u8)addr);
643 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
644 (u8)(addr >> 8));
645 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
646 (u8)(addr >> 16));
647 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
648 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
649 } else {
650 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
651 (u8)addr);
652 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
653 (u8)(addr >> 8));
654 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR3, 0xFF,
655 (u8)(addr >> 16));
656 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
657 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_32);
658 }
659
660 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF,
661 (u8)(pagelen >> 8));
662 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF,
663 (u8)pagelen);
664
665 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
666 SPI_TRANSFER0_START | SPI_CADI_MODE0);
667 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0,
668 SPI_TRANSFER0_END, SPI_TRANSFER0_END);
669
670 rtsx_send_cmd_no_wait(chip);
671
672 retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0,
673 DMA_FROM_DEVICE, 10000);
674 if (retval < 0) {
675 kfree(buf);
676 rtsx_clear_spi_error(chip);
677 spi_set_err_code(chip, SPI_HW_ERR);
678 return STATUS_FAIL;
679 }
680
681 rtsx_stor_access_xfer_buf(buf, pagelen, srb, &index, &offset,
682 TO_XFER_BUF);
683
684 addr += pagelen;
685 len -= pagelen;
686 }
687
688 scsi_set_resid(srb, 0);
689 kfree(buf);
690
691 return STATUS_SUCCESS;
692 }
693
spi_write_flash(struct scsi_cmnd * srb,struct rtsx_chip * chip)694 int spi_write_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip)
695 {
696 int retval;
697 u8 ins, program_mode;
698 u32 addr;
699 u16 len;
700 u8 *buf;
701 unsigned int index = 0, offset = 0;
702
703 spi_set_err_code(chip, SPI_NO_ERR);
704
705 ins = srb->cmnd[3];
706 addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5])
707 << 8) | srb->cmnd[6];
708 len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8];
709 program_mode = srb->cmnd[9];
710
711 retval = spi_set_init_para(chip);
712 if (retval != STATUS_SUCCESS) {
713 spi_set_err_code(chip, SPI_HW_ERR);
714 return STATUS_FAIL;
715 }
716
717 if (program_mode == BYTE_PROGRAM) {
718 buf = kmalloc(4, GFP_KERNEL);
719 if (!buf) {
720 return STATUS_ERROR;
721 }
722
723 while (len) {
724 retval = sf_enable_write(chip, SPI_WREN);
725 if (retval != STATUS_SUCCESS) {
726 kfree(buf);
727 return STATUS_FAIL;
728 }
729
730 rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset,
731 FROM_XFER_BUF);
732
733 rtsx_init_cmd(chip);
734
735 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
736 0x01, PINGPONG_BUFFER);
737 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF,
738 buf[0]);
739 sf_program(chip, ins, 1, addr, 1);
740
741 retval = rtsx_send_cmd(chip, 0, 100);
742 if (retval < 0) {
743 kfree(buf);
744 rtsx_clear_spi_error(chip);
745 spi_set_err_code(chip, SPI_HW_ERR);
746 return STATUS_FAIL;
747 }
748
749 retval = sf_polling_status(chip, 100);
750 if (retval != STATUS_SUCCESS) {
751 kfree(buf);
752 return STATUS_FAIL;
753 }
754
755 addr++;
756 len--;
757 }
758
759 kfree(buf);
760
761 } else if (program_mode == AAI_PROGRAM) {
762 int first_byte = 1;
763
764 retval = sf_enable_write(chip, SPI_WREN);
765 if (retval != STATUS_SUCCESS) {
766 return STATUS_FAIL;
767 }
768
769 buf = kmalloc(4, GFP_KERNEL);
770 if (!buf) {
771 return STATUS_ERROR;
772 }
773
774 while (len) {
775 rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset,
776 FROM_XFER_BUF);
777
778 rtsx_init_cmd(chip);
779
780 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
781 0x01, PINGPONG_BUFFER);
782 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF,
783 buf[0]);
784 if (first_byte) {
785 sf_program(chip, ins, 1, addr, 1);
786 first_byte = 0;
787 } else {
788 sf_program(chip, ins, 0, 0, 1);
789 }
790
791 retval = rtsx_send_cmd(chip, 0, 100);
792 if (retval < 0) {
793 kfree(buf);
794 rtsx_clear_spi_error(chip);
795 spi_set_err_code(chip, SPI_HW_ERR);
796 return STATUS_FAIL;
797 }
798
799 retval = sf_polling_status(chip, 100);
800 if (retval != STATUS_SUCCESS) {
801 kfree(buf);
802 return STATUS_FAIL;
803 }
804
805 len--;
806 }
807
808 kfree(buf);
809
810 retval = sf_disable_write(chip, SPI_WRDI);
811 if (retval != STATUS_SUCCESS) {
812 return STATUS_FAIL;
813 }
814
815 retval = sf_polling_status(chip, 100);
816 if (retval != STATUS_SUCCESS) {
817 return STATUS_FAIL;
818 }
819 } else if (program_mode == PAGE_PROGRAM) {
820 buf = kmalloc(SF_PAGE_LEN, GFP_KERNEL);
821 if (!buf) {
822 return STATUS_NOMEM;
823 }
824
825 while (len) {
826 u16 pagelen = SF_PAGE_LEN - (u8)addr;
827
828 if (pagelen > len)
829 pagelen = len;
830
831 retval = sf_enable_write(chip, SPI_WREN);
832 if (retval != STATUS_SUCCESS) {
833 kfree(buf);
834 return STATUS_FAIL;
835 }
836
837 rtsx_init_cmd(chip);
838
839 trans_dma_enable(DMA_TO_DEVICE, chip, 256, DMA_256);
840 sf_program(chip, ins, 1, addr, pagelen);
841
842 rtsx_send_cmd_no_wait(chip);
843
844 rtsx_stor_access_xfer_buf(buf, pagelen, srb, &index,
845 &offset, FROM_XFER_BUF);
846
847 retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0,
848 DMA_TO_DEVICE, 100);
849 if (retval < 0) {
850 kfree(buf);
851 rtsx_clear_spi_error(chip);
852 spi_set_err_code(chip, SPI_HW_ERR);
853 return STATUS_FAIL;
854 }
855
856 retval = sf_polling_status(chip, 100);
857 if (retval != STATUS_SUCCESS) {
858 kfree(buf);
859 return STATUS_FAIL;
860 }
861
862 addr += pagelen;
863 len -= pagelen;
864 }
865
866 kfree(buf);
867 } else {
868 spi_set_err_code(chip, SPI_INVALID_COMMAND);
869 return STATUS_FAIL;
870 }
871
872 return STATUS_SUCCESS;
873 }
874
spi_erase_flash(struct scsi_cmnd * srb,struct rtsx_chip * chip)875 int spi_erase_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip)
876 {
877 int retval;
878 u8 ins, erase_mode;
879 u32 addr;
880
881 spi_set_err_code(chip, SPI_NO_ERR);
882
883 ins = srb->cmnd[3];
884 addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5])
885 << 8) | srb->cmnd[6];
886 erase_mode = srb->cmnd[9];
887
888 retval = spi_set_init_para(chip);
889 if (retval != STATUS_SUCCESS) {
890 spi_set_err_code(chip, SPI_HW_ERR);
891 return STATUS_FAIL;
892 }
893
894 if (erase_mode == PAGE_ERASE) {
895 retval = sf_enable_write(chip, SPI_WREN);
896 if (retval != STATUS_SUCCESS) {
897 return STATUS_FAIL;
898 }
899
900 retval = sf_erase(chip, ins, 1, addr);
901 if (retval != STATUS_SUCCESS) {
902 return STATUS_FAIL;
903 }
904 } else if (erase_mode == CHIP_ERASE) {
905 retval = sf_enable_write(chip, SPI_WREN);
906 if (retval != STATUS_SUCCESS) {
907 return STATUS_FAIL;
908 }
909
910 retval = sf_erase(chip, ins, 0, 0);
911 if (retval != STATUS_SUCCESS) {
912 return STATUS_FAIL;
913 }
914 } else {
915 spi_set_err_code(chip, SPI_INVALID_COMMAND);
916 return STATUS_FAIL;
917 }
918
919 return STATUS_SUCCESS;
920 }
921
spi_write_flash_status(struct scsi_cmnd * srb,struct rtsx_chip * chip)922 int spi_write_flash_status(struct scsi_cmnd *srb, struct rtsx_chip *chip)
923 {
924 int retval;
925 u8 ins, status, ewsr;
926
927 ins = srb->cmnd[3];
928 status = srb->cmnd[4];
929 ewsr = srb->cmnd[5];
930
931 retval = spi_set_init_para(chip);
932 if (retval != STATUS_SUCCESS) {
933 spi_set_err_code(chip, SPI_HW_ERR);
934 return STATUS_FAIL;
935 }
936
937 retval = sf_enable_write(chip, ewsr);
938 if (retval != STATUS_SUCCESS) {
939 return STATUS_FAIL;
940 }
941
942 rtsx_init_cmd(chip);
943
944 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
945 PINGPONG_BUFFER);
946
947 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
948 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
949 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
950 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, 0);
951 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 1);
952 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF, status);
953 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
954 SPI_TRANSFER0_START | SPI_CDO_MODE0);
955 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
956 SPI_TRANSFER0_END);
957
958 retval = rtsx_send_cmd(chip, 0, 100);
959 if (retval != STATUS_SUCCESS) {
960 rtsx_clear_spi_error(chip);
961 spi_set_err_code(chip, SPI_HW_ERR);
962 return STATUS_FAIL;
963 }
964
965 return STATUS_SUCCESS;
966 }
967
