1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include <linux/pci.h>
28 #include <linux/i2c.h>
29 #include "amdgpu.h"
30 #include "amdgpu_smu.h"
31 #include "atomfirmware.h"
32 #include "amdgpu_atomfirmware.h"
33 #include "amdgpu_atombios.h"
34 #include "smu_v11_0.h"
35 #include "smu11_driver_if_sienna_cichlid.h"
36 #include "soc15_common.h"
37 #include "atom.h"
38 #include "sienna_cichlid_ppt.h"
39 #include "smu_v11_0_7_pptable.h"
40 #include "smu_v11_0_7_ppsmc.h"
41 #include "nbio/nbio_2_3_offset.h"
42 #include "nbio/nbio_2_3_sh_mask.h"
43 #include "thm/thm_11_0_2_offset.h"
44 #include "thm/thm_11_0_2_sh_mask.h"
45 #include "mp/mp_11_0_offset.h"
46 #include "mp/mp_11_0_sh_mask.h"
47
48 #include "asic_reg/mp/mp_11_0_sh_mask.h"
49 #include "smu_cmn.h"
50
51 /*
52 * DO NOT use these for err/warn/info/debug messages.
53 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
54 * They are more MGPU friendly.
55 */
56 #undef pr_err
57 #undef pr_warn
58 #undef pr_info
59 #undef pr_debug
60
61 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
62
63 #define FEATURE_MASK(feature) (1ULL << feature)
64 #define SMC_DPM_FEATURE ( \
65 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
66 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
67 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
68 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
69 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
70 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
71 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | \
72 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
73
74 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
75
76 #define GET_PPTABLE_MEMBER(field, member) do {\
77 if (smu->adev->asic_type == CHIP_BEIGE_GOBY)\
78 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\
79 else\
80 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\
81 } while(0)
82
get_table_size(struct smu_context * smu)83 static int get_table_size(struct smu_context *smu)
84 {
85 if (smu->adev->asic_type == CHIP_BEIGE_GOBY)
86 return sizeof(PPTable_beige_goby_t);
87 else
88 return sizeof(PPTable_t);
89 }
90
91 static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
92 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
93 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
94 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
95 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
96 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
97 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
98 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
99 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 1),
100 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 1),
101 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 1),
102 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 1),
103 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetRunningSmuFeaturesLow, 1),
104 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetRunningSmuFeaturesHigh, 1),
105 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 1),
106 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
107 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
108 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
109 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
110 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
111 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
112 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
113 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
114 MSG_MAP(RunDcBtc, PPSMC_MSG_RunDcBtc, 0),
115 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
116 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
117 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
118 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 1),
119 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
120 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
121 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
122 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
123 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0),
124 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0),
125 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0),
126 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
127 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
128 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
129 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0),
130 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0),
131 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
132 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
133 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
134 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
135 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
136 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
137 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
138 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
139 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
140 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
141 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0),
142 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
143 MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
144 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
145 MSG_MAP(SetGpoFeaturePMask, PPSMC_MSG_SetGpoFeaturePMask, 0),
146 MSG_MAP(DisallowGpo, PPSMC_MSG_DisallowGpo, 0),
147 MSG_MAP(Enable2ndUSB20Port, PPSMC_MSG_Enable2ndUSB20Port, 0),
148 };
149
150 static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
151 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
152 CLK_MAP(SCLK, PPCLK_GFXCLK),
153 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
154 CLK_MAP(FCLK, PPCLK_FCLK),
155 CLK_MAP(UCLK, PPCLK_UCLK),
156 CLK_MAP(MCLK, PPCLK_UCLK),
157 CLK_MAP(DCLK, PPCLK_DCLK_0),
158 CLK_MAP(DCLK1, PPCLK_DCLK_1),
159 CLK_MAP(VCLK, PPCLK_VCLK_0),
160 CLK_MAP(VCLK1, PPCLK_VCLK_1),
161 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
162 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
163 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
164 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
165 };
166
167 static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
168 FEA_MAP(DPM_PREFETCHER),
169 FEA_MAP(DPM_GFXCLK),
170 FEA_MAP(DPM_GFX_GPO),
171 FEA_MAP(DPM_UCLK),
172 FEA_MAP(DPM_FCLK),
173 FEA_MAP(DPM_SOCCLK),
174 FEA_MAP(DPM_MP0CLK),
175 FEA_MAP(DPM_LINK),
176 FEA_MAP(DPM_DCEFCLK),
177 FEA_MAP(DPM_XGMI),
178 FEA_MAP(MEM_VDDCI_SCALING),
179 FEA_MAP(MEM_MVDD_SCALING),
180 FEA_MAP(DS_GFXCLK),
181 FEA_MAP(DS_SOCCLK),
182 FEA_MAP(DS_FCLK),
183 FEA_MAP(DS_LCLK),
184 FEA_MAP(DS_DCEFCLK),
185 FEA_MAP(DS_UCLK),
186 FEA_MAP(GFX_ULV),
187 FEA_MAP(FW_DSTATE),
188 FEA_MAP(GFXOFF),
189 FEA_MAP(BACO),
190 FEA_MAP(MM_DPM_PG),
191 FEA_MAP(RSMU_SMN_CG),
192 FEA_MAP(PPT),
193 FEA_MAP(TDC),
194 FEA_MAP(APCC_PLUS),
195 FEA_MAP(GTHR),
196 FEA_MAP(ACDC),
197 FEA_MAP(VR0HOT),
198 FEA_MAP(VR1HOT),
199 FEA_MAP(FW_CTF),
200 FEA_MAP(FAN_CONTROL),
201 FEA_MAP(THERMAL),
202 FEA_MAP(GFX_DCS),
203 FEA_MAP(RM),
204 FEA_MAP(LED_DISPLAY),
205 FEA_MAP(GFX_SS),
206 FEA_MAP(OUT_OF_BAND_MONITOR),
207 FEA_MAP(TEMP_DEPENDENT_VMIN),
208 FEA_MAP(MMHUB_PG),
209 FEA_MAP(ATHUB_PG),
210 FEA_MAP(APCC_DFLL),
211 };
212
213 static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
214 TAB_MAP(PPTABLE),
215 TAB_MAP(WATERMARKS),
216 TAB_MAP(AVFS_PSM_DEBUG),
217 TAB_MAP(AVFS_FUSE_OVERRIDE),
218 TAB_MAP(PMSTATUSLOG),
219 TAB_MAP(SMU_METRICS),
220 TAB_MAP(DRIVER_SMU_CONFIG),
221 TAB_MAP(ACTIVITY_MONITOR_COEFF),
222 TAB_MAP(OVERDRIVE),
223 TAB_MAP(I2C_COMMANDS),
224 TAB_MAP(PACE),
225 };
226
227 static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
228 PWR_MAP(AC),
229 PWR_MAP(DC),
230 };
231
232 static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
233 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
234 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
235 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
236 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
237 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
238 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
239 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
240 };
241
242 static const uint8_t sienna_cichlid_throttler_map[] = {
243 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
244 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
245 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
246 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
247 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
248 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
249 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
250 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
251 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
252 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
253 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
254 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
255 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
256 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
257 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
258 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
259 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
260 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT),
261 };
262
263 static int
sienna_cichlid_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)264 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
265 uint32_t *feature_mask, uint32_t num)
266 {
267 struct amdgpu_device *adev = smu->adev;
268
269 if (num > 2)
270 return -EINVAL;
271
272 memset(feature_mask, 0, sizeof(uint32_t) * num);
273
274 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
275 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
276 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
277 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
278 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
279 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
280 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
281 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
282 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
283 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
284 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
285 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
286 | FEATURE_MASK(FEATURE_PPT_BIT)
287 | FEATURE_MASK(FEATURE_TDC_BIT)
288 | FEATURE_MASK(FEATURE_BACO_BIT)
289 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
290 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
291 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
292 | FEATURE_MASK(FEATURE_THERMAL_BIT)
293 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
294
295 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
296 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
297 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
298 }
299
300 if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
301 (adev->asic_type > CHIP_SIENNA_CICHLID) &&
302 !(adev->flags & AMD_IS_APU))
303 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
304
305 if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
306 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
307 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
308 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
309
310 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
312
313 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
315
316 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
318
319 if (adev->pm.pp_feature & PP_ULV_MASK)
320 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
321
322 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
323 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
324
325 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
326 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
327
328 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
329 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
330
331 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
332 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
333
334 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
335 smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
336 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
337
338 if (smu->dc_controlled_by_gpio)
339 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
340
341 if (amdgpu_aspm)
342 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
343
344 return 0;
345 }
346
sienna_cichlid_check_bxco_support(struct smu_context * smu)347 static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
348 {
349 struct smu_table_context *table_context = &smu->smu_table;
350 struct smu_11_0_7_powerplay_table *powerplay_table =
351 table_context->power_play_table;
352 struct smu_baco_context *smu_baco = &smu->smu_baco;
353 struct amdgpu_device *adev = smu->adev;
354 uint32_t val;
355
356 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO) {
357 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
358 smu_baco->platform_support =
359 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
360 false;
361 }
362 }
363
sienna_cichlid_check_powerplay_table(struct smu_context * smu)364 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
365 {
366 struct smu_table_context *table_context = &smu->smu_table;
367 struct smu_11_0_7_powerplay_table *powerplay_table =
368 table_context->power_play_table;
369
370 if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
371 smu->dc_controlled_by_gpio = true;
372
373 sienna_cichlid_check_bxco_support(smu);
374
375 table_context->thermal_controller_type =
376 powerplay_table->thermal_controller_type;
377
378 /*
379 * Instead of having its own buffer space and get overdrive_table copied,
380 * smu->od_settings just points to the actual overdrive_table
381 */
382 smu->od_settings = &powerplay_table->overdrive_table;
383
384 return 0;
385 }
386
sienna_cichlid_append_powerplay_table(struct smu_context * smu)387 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
388 {
389 struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
390 int index, ret;
391 I2cControllerConfig_t *table_member;
392
393 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
394 smc_dpm_info);
395
396 ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
397 (uint8_t **)&smc_dpm_table);
398 if (ret)
399 return ret;
400 GET_PPTABLE_MEMBER(I2cControllers, &table_member);
401 memcpy(table_member, smc_dpm_table->I2cControllers,
402 sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
403
404 return 0;
405 }
406
sienna_cichlid_store_powerplay_table(struct smu_context * smu)407 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
408 {
409 struct smu_table_context *table_context = &smu->smu_table;
410 struct smu_11_0_7_powerplay_table *powerplay_table =
411 table_context->power_play_table;
412 int table_size;
413
414 table_size = get_table_size(smu);
415 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
416 table_size);
417
418 return 0;
419 }
420
sienna_cichlid_setup_pptable(struct smu_context * smu)421 static int sienna_cichlid_setup_pptable(struct smu_context *smu)
422 {
423 int ret = 0;
424
425 ret = smu_v11_0_setup_pptable(smu);
426 if (ret)
427 return ret;
428
429 ret = sienna_cichlid_store_powerplay_table(smu);
430 if (ret)
431 return ret;
432
433 ret = sienna_cichlid_append_powerplay_table(smu);
434 if (ret)
435 return ret;
436
437 ret = sienna_cichlid_check_powerplay_table(smu);
438 if (ret)
439 return ret;
440
441 return ret;
442 }
443
sienna_cichlid_tables_init(struct smu_context * smu)444 static int sienna_cichlid_tables_init(struct smu_context *smu)
445 {
446 struct smu_table_context *smu_table = &smu->smu_table;
447 struct smu_table *tables = smu_table->tables;
448 int table_size;
449
450 table_size = get_table_size(smu);
451 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size,
452 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
453 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
454 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
455 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
456 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
457 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
458 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
459 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
460 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
461 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
462 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
463 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
464 sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
465 AMDGPU_GEM_DOMAIN_VRAM);
466
467 smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
468 if (!smu_table->metrics_table)
469 goto err0_out;
470 smu_table->metrics_time = 0;
471
472 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
473 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
474 if (!smu_table->gpu_metrics_table)
475 goto err1_out;
476
477 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
478 if (!smu_table->watermarks_table)
479 goto err2_out;
480
481 return 0;
482
483 err2_out:
484 kfree(smu_table->gpu_metrics_table);
485 err1_out:
486 kfree(smu_table->metrics_table);
487 err0_out:
488 return -ENOMEM;
489 }
490
sienna_cichlid_get_throttler_status_locked(struct smu_context * smu)491 static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu)
492 {
493 struct smu_table_context *smu_table= &smu->smu_table;
494 SmuMetricsExternal_t *metrics_ext =
495 (SmuMetricsExternal_t *)(smu_table->metrics_table);
496 uint32_t throttler_status = 0;
497 int i;
498
499 if ((smu->adev->asic_type == CHIP_SIENNA_CICHLID) &&
500 (smu->smc_fw_version >= 0x3A4300)) {
501 for (i = 0; i < THROTTLER_COUNT; i++)
502 throttler_status |=
503 (metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0);
504 } else {
505 throttler_status = metrics_ext->SmuMetrics.ThrottlerStatus;
506 }
507
508 return throttler_status;
509 }
510
sienna_cichlid_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)511 static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
512 MetricsMember_t member,
513 uint32_t *value)
514 {
515 struct smu_table_context *smu_table= &smu->smu_table;
516 SmuMetrics_t *metrics =
517 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
518 SmuMetrics_V2_t *metrics_v2 =
519 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
520 bool use_metrics_v2 = ((smu->adev->asic_type == CHIP_SIENNA_CICHLID) &&
521 (smu->smc_fw_version >= 0x3A4300)) ? true : false;
522 uint16_t average_gfx_activity;
523 int ret = 0;
524
525 mutex_lock(&smu->metrics_lock);
526
527 ret = smu_cmn_get_metrics_table_locked(smu,
528 NULL,
529 false);
530 if (ret) {
531 mutex_unlock(&smu->metrics_lock);
532 return ret;
533 }
534
535 switch (member) {
536 case METRICS_CURR_GFXCLK:
537 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] :
538 metrics->CurrClock[PPCLK_GFXCLK];
539 break;
540 case METRICS_CURR_SOCCLK:
541 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] :
542 metrics->CurrClock[PPCLK_SOCCLK];
543 break;
544 case METRICS_CURR_UCLK:
545 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] :
546 metrics->CurrClock[PPCLK_UCLK];
547 break;
548 case METRICS_CURR_VCLK:
549 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] :
550 metrics->CurrClock[PPCLK_VCLK_0];
551 break;
552 case METRICS_CURR_VCLK1:
553 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] :
554 metrics->CurrClock[PPCLK_VCLK_1];
555 break;
556 case METRICS_CURR_DCLK:
557 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] :
558 metrics->CurrClock[PPCLK_DCLK_0];
559 break;
560 case METRICS_CURR_DCLK1:
561 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] :
562 metrics->CurrClock[PPCLK_DCLK_1];
563 break;
564 case METRICS_CURR_DCEFCLK:
565 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCEFCLK] :
566 metrics->CurrClock[PPCLK_DCEFCLK];
567 break;
568 case METRICS_CURR_FCLK:
569 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] :
570 metrics->CurrClock[PPCLK_FCLK];
571 break;
572 case METRICS_AVERAGE_GFXCLK:
573 average_gfx_activity = use_metrics_v2 ? metrics_v2->AverageGfxActivity :
574 metrics->AverageGfxActivity;
575 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
576 *value = use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
577 metrics->AverageGfxclkFrequencyPostDs;
578 else
579 *value = use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
580 metrics->AverageGfxclkFrequencyPreDs;
581 break;
582 case METRICS_AVERAGE_FCLK:
583 *value = use_metrics_v2 ? metrics_v2->AverageFclkFrequencyPostDs :
584 metrics->AverageFclkFrequencyPostDs;
585 break;
586 case METRICS_AVERAGE_UCLK:
587 *value = use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
588 metrics->AverageUclkFrequencyPostDs;
589 break;
590 case METRICS_AVERAGE_GFXACTIVITY:
591 *value = use_metrics_v2 ? metrics_v2->AverageGfxActivity :
592 metrics->AverageGfxActivity;
593 break;
594 case METRICS_AVERAGE_MEMACTIVITY:
595 *value = use_metrics_v2 ? metrics_v2->AverageUclkActivity :
596 metrics->AverageUclkActivity;
597 break;
598 case METRICS_AVERAGE_SOCKETPOWER:
599 *value = use_metrics_v2 ? metrics_v2->AverageSocketPower << 8 :
600 metrics->AverageSocketPower << 8;
601 break;
602 case METRICS_TEMPERATURE_EDGE:
603 *value = (use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge) *
604 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
605 break;
606 case METRICS_TEMPERATURE_HOTSPOT:
607 *value = (use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot) *
608 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
609 break;
610 case METRICS_TEMPERATURE_MEM:
611 *value = (use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem) *
612 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
613 break;
614 case METRICS_TEMPERATURE_VRGFX:
615 *value = (use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx) *
616 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
617 break;
618 case METRICS_TEMPERATURE_VRSOC:
619 *value = (use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc) *
620 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
621 break;
622 case METRICS_THROTTLER_STATUS:
623 *value = sienna_cichlid_get_throttler_status_locked(smu);
624 break;
625 case METRICS_CURR_FANSPEED:
626 *value = use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
627 break;
628 default:
629 *value = UINT_MAX;
630 break;
631 }
632
633 mutex_unlock(&smu->metrics_lock);
634
635 return ret;
636
637 }
638
sienna_cichlid_allocate_dpm_context(struct smu_context * smu)639 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
640 {
641 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
642
643 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
644 GFP_KERNEL);
645 if (!smu_dpm->dpm_context)
646 return -ENOMEM;
647
648 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
649
650 return 0;
651 }
652
sienna_cichlid_init_smc_tables(struct smu_context * smu)653 static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
654 {
655 int ret = 0;
656
657 ret = sienna_cichlid_tables_init(smu);
658 if (ret)
659 return ret;
660
661 ret = sienna_cichlid_allocate_dpm_context(smu);
662 if (ret)
663 return ret;
664
665 return smu_v11_0_init_smc_tables(smu);
666 }
667
sienna_cichlid_set_default_dpm_table(struct smu_context * smu)668 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
669 {
670 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
671 struct smu_11_0_dpm_table *dpm_table;
672 struct amdgpu_device *adev = smu->adev;
673 int ret = 0;
674 DpmDescriptor_t *table_member;
675
676 /* socclk dpm table setup */
677 dpm_table = &dpm_context->dpm_tables.soc_table;
678 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
679 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
680 ret = smu_v11_0_set_single_dpm_table(smu,
681 SMU_SOCCLK,
682 dpm_table);
683 if (ret)
684 return ret;
685 dpm_table->is_fine_grained =
686 !table_member[PPCLK_SOCCLK].SnapToDiscrete;
687 } else {
688 dpm_table->count = 1;
689 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
690 dpm_table->dpm_levels[0].enabled = true;
691 dpm_table->min = dpm_table->dpm_levels[0].value;
692 dpm_table->max = dpm_table->dpm_levels[0].value;
693 }
694
695 /* gfxclk dpm table setup */
696 dpm_table = &dpm_context->dpm_tables.gfx_table;
697 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
698 ret = smu_v11_0_set_single_dpm_table(smu,
699 SMU_GFXCLK,
700 dpm_table);
701 if (ret)
702 return ret;
703 dpm_table->is_fine_grained =
704 !table_member[PPCLK_GFXCLK].SnapToDiscrete;
705 } else {
706 dpm_table->count = 1;
707 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
708 dpm_table->dpm_levels[0].enabled = true;
709 dpm_table->min = dpm_table->dpm_levels[0].value;
710 dpm_table->max = dpm_table->dpm_levels[0].value;
711 }
712
713 /* uclk dpm table setup */
714 dpm_table = &dpm_context->dpm_tables.uclk_table;
715 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
716 ret = smu_v11_0_set_single_dpm_table(smu,
717 SMU_UCLK,
718 dpm_table);
719 if (ret)
720 return ret;
721 dpm_table->is_fine_grained =
722 !table_member[PPCLK_UCLK].SnapToDiscrete;
723 } else {
724 dpm_table->count = 1;
725 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
726 dpm_table->dpm_levels[0].enabled = true;
727 dpm_table->min = dpm_table->dpm_levels[0].value;
728 dpm_table->max = dpm_table->dpm_levels[0].value;
729 }
730
731 /* fclk dpm table setup */
732 dpm_table = &dpm_context->dpm_tables.fclk_table;
733 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
734 ret = smu_v11_0_set_single_dpm_table(smu,
735 SMU_FCLK,
736 dpm_table);
737 if (ret)
738 return ret;
739 dpm_table->is_fine_grained =
740 !table_member[PPCLK_FCLK].SnapToDiscrete;
741 } else {
742 dpm_table->count = 1;
743 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
744 dpm_table->dpm_levels[0].enabled = true;
745 dpm_table->min = dpm_table->dpm_levels[0].value;
746 dpm_table->max = dpm_table->dpm_levels[0].value;
747 }
748
749 /* vclk0 dpm table setup */
750 dpm_table = &dpm_context->dpm_tables.vclk_table;
751 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
752 ret = smu_v11_0_set_single_dpm_table(smu,
753 SMU_VCLK,
754 dpm_table);
755 if (ret)
756 return ret;
757 dpm_table->is_fine_grained =
758 !table_member[PPCLK_VCLK_0].SnapToDiscrete;
759 } else {
760 dpm_table->count = 1;
761 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
762 dpm_table->dpm_levels[0].enabled = true;
763 dpm_table->min = dpm_table->dpm_levels[0].value;
764 dpm_table->max = dpm_table->dpm_levels[0].value;
765 }
766
767 /* vclk1 dpm table setup */
768 if (adev->vcn.num_vcn_inst > 1) {
769 dpm_table = &dpm_context->dpm_tables.vclk1_table;
770 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
771 ret = smu_v11_0_set_single_dpm_table(smu,
772 SMU_VCLK1,
773 dpm_table);
774 if (ret)
775 return ret;
776 dpm_table->is_fine_grained =
777 !table_member[PPCLK_VCLK_1].SnapToDiscrete;
778 } else {
779 dpm_table->count = 1;
780 dpm_table->dpm_levels[0].value =
781 smu->smu_table.boot_values.vclk / 100;
782 dpm_table->dpm_levels[0].enabled = true;
783 dpm_table->min = dpm_table->dpm_levels[0].value;
784 dpm_table->max = dpm_table->dpm_levels[0].value;
785 }
786 }
787
788 /* dclk0 dpm table setup */
789 dpm_table = &dpm_context->dpm_tables.dclk_table;
790 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
791 ret = smu_v11_0_set_single_dpm_table(smu,
792 SMU_DCLK,
793 dpm_table);
794 if (ret)
795 return ret;
796 dpm_table->is_fine_grained =
797 !table_member[PPCLK_DCLK_0].SnapToDiscrete;
798 } else {
799 dpm_table->count = 1;
800 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
801 dpm_table->dpm_levels[0].enabled = true;
802 dpm_table->min = dpm_table->dpm_levels[0].value;
803 dpm_table->max = dpm_table->dpm_levels[0].value;
804 }
805
806 /* dclk1 dpm table setup */
807 if (adev->vcn.num_vcn_inst > 1) {
808 dpm_table = &dpm_context->dpm_tables.dclk1_table;
809 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
810 ret = smu_v11_0_set_single_dpm_table(smu,
811 SMU_DCLK1,
812 dpm_table);
813 if (ret)
814 return ret;
815 dpm_table->is_fine_grained =
816 !table_member[PPCLK_DCLK_1].SnapToDiscrete;
817 } else {
818 dpm_table->count = 1;
819 dpm_table->dpm_levels[0].value =
820 smu->smu_table.boot_values.dclk / 100;
821 dpm_table->dpm_levels[0].enabled = true;
822 dpm_table->min = dpm_table->dpm_levels[0].value;
823 dpm_table->max = dpm_table->dpm_levels[0].value;
824 }
825 }
826
827 /* dcefclk dpm table setup */
828 dpm_table = &dpm_context->dpm_tables.dcef_table;
829 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
830 ret = smu_v11_0_set_single_dpm_table(smu,
831 SMU_DCEFCLK,
832 dpm_table);
833 if (ret)
834 return ret;
835 dpm_table->is_fine_grained =
836 !table_member[PPCLK_DCEFCLK].SnapToDiscrete;
837 } else {
838 dpm_table->count = 1;
839 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
840 dpm_table->dpm_levels[0].enabled = true;
841 dpm_table->min = dpm_table->dpm_levels[0].value;
842 dpm_table->max = dpm_table->dpm_levels[0].value;
843 }
844
845 /* pixelclk dpm table setup */
846 dpm_table = &dpm_context->dpm_tables.pixel_table;
847 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
848 ret = smu_v11_0_set_single_dpm_table(smu,
849 SMU_PIXCLK,
850 dpm_table);
851 if (ret)
852 return ret;
853 dpm_table->is_fine_grained =
854 !table_member[PPCLK_PIXCLK].SnapToDiscrete;
855 } else {
856 dpm_table->count = 1;
857 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
858 dpm_table->dpm_levels[0].enabled = true;
859 dpm_table->min = dpm_table->dpm_levels[0].value;
860 dpm_table->max = dpm_table->dpm_levels[0].value;
861 }
862
863 /* displayclk dpm table setup */
864 dpm_table = &dpm_context->dpm_tables.display_table;
865 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
866 ret = smu_v11_0_set_single_dpm_table(smu,
867 SMU_DISPCLK,
868 dpm_table);
869 if (ret)
870 return ret;
871 dpm_table->is_fine_grained =
872 !table_member[PPCLK_DISPCLK].SnapToDiscrete;
873 } else {
874 dpm_table->count = 1;
875 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
876 dpm_table->dpm_levels[0].enabled = true;
877 dpm_table->min = dpm_table->dpm_levels[0].value;
878 dpm_table->max = dpm_table->dpm_levels[0].value;
879 }
880
881 /* phyclk dpm table setup */
882 dpm_table = &dpm_context->dpm_tables.phy_table;
883 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
884 ret = smu_v11_0_set_single_dpm_table(smu,
885 SMU_PHYCLK,
886 dpm_table);
887 if (ret)
888 return ret;
889 dpm_table->is_fine_grained =
890 !table_member[PPCLK_PHYCLK].SnapToDiscrete;
891 } else {
892 dpm_table->count = 1;
893 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
894 dpm_table->dpm_levels[0].enabled = true;
895 dpm_table->min = dpm_table->dpm_levels[0].value;
896 dpm_table->max = dpm_table->dpm_levels[0].value;
897 }
898
899 return 0;
900 }
901
sienna_cichlid_dpm_set_vcn_enable(struct smu_context * smu,bool enable)902 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
903 {
904 struct amdgpu_device *adev = smu->adev;
905 int ret = 0;
906
907 if (enable) {
908 /* vcn dpm on is a prerequisite for vcn power gate messages */
909 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
910 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
911 if (ret)
912 return ret;
913 if (adev->vcn.num_vcn_inst > 1) {
914 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
915 0x10000, NULL);
916 if (ret)
917 return ret;
918 }
919 }
920 } else {
921 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
922 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
923 if (ret)
924 return ret;
925 if (adev->vcn.num_vcn_inst > 1) {
926 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
927 0x10000, NULL);
928 if (ret)
929 return ret;
930 }
931 }
932 }
933
934 return ret;
935 }
936
sienna_cichlid_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)937 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
938 {
939 int ret = 0;
940
941 if (enable) {
942 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
943 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
944 if (ret)
945 return ret;
946 }
947 } else {
948 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
949 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
950 if (ret)
951 return ret;
952 }
953 }
954
955 return ret;
956 }
957
sienna_cichlid_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)958 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
959 enum smu_clk_type clk_type,
960 uint32_t *value)
961 {
962 MetricsMember_t member_type;
963 int clk_id = 0;
964
965 clk_id = smu_cmn_to_asic_specific_index(smu,
966 CMN2ASIC_MAPPING_CLK,
967 clk_type);
968 if (clk_id < 0)
969 return clk_id;
970
971 switch (clk_id) {
972 case PPCLK_GFXCLK:
973 member_type = METRICS_CURR_GFXCLK;
974 break;
975 case PPCLK_UCLK:
976 member_type = METRICS_CURR_UCLK;
977 break;
978 case PPCLK_SOCCLK:
979 member_type = METRICS_CURR_SOCCLK;
980 break;
981 case PPCLK_FCLK:
982 member_type = METRICS_CURR_FCLK;
983 break;
984 case PPCLK_VCLK_0:
985 member_type = METRICS_CURR_VCLK;
986 break;
987 case PPCLK_VCLK_1:
988 member_type = METRICS_CURR_VCLK1;
989 break;
990 case PPCLK_DCLK_0:
991 member_type = METRICS_CURR_DCLK;
992 break;
993 case PPCLK_DCLK_1:
994 member_type = METRICS_CURR_DCLK1;
995 break;
996 case PPCLK_DCEFCLK:
997 member_type = METRICS_CURR_DCEFCLK;
998 break;
999 default:
1000 return -EINVAL;
1001 }
1002
1003 return sienna_cichlid_get_smu_metrics_data(smu,
1004 member_type,
1005 value);
1006
1007 }
1008
sienna_cichlid_is_support_fine_grained_dpm(struct smu_context * smu,enum smu_clk_type clk_type)1009 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1010 {
1011 DpmDescriptor_t *dpm_desc = NULL;
1012 DpmDescriptor_t *table_member;
1013 uint32_t clk_index = 0;
1014
1015 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
1016 clk_index = smu_cmn_to_asic_specific_index(smu,
1017 CMN2ASIC_MAPPING_CLK,
1018 clk_type);
1019 dpm_desc = &table_member[clk_index];
1020
1021 /* 0 - Fine grained DPM, 1 - Discrete DPM */
1022 return dpm_desc->SnapToDiscrete == 0;
1023 }
1024
sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table * od_table,enum SMU_11_0_7_ODFEATURE_CAP cap)1025 static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,
1026 enum SMU_11_0_7_ODFEATURE_CAP cap)
1027 {
1028 return od_table->cap[cap];
1029 }
1030
sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table * od_table,enum SMU_11_0_7_ODSETTING_ID setting,uint32_t * min,uint32_t * max)1031 static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table,
1032 enum SMU_11_0_7_ODSETTING_ID setting,
1033 uint32_t *min, uint32_t *max)
1034 {
1035 if (min)
1036 *min = od_table->min[setting];
1037 if (max)
1038 *max = od_table->max[setting];
1039 }
1040
sienna_cichlid_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)1041 static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
1042 enum smu_clk_type clk_type, char *buf)
1043 {
1044 struct amdgpu_device *adev = smu->adev;
1045 struct smu_table_context *table_context = &smu->smu_table;
1046 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1047 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1048 uint16_t *table_member;
1049
1050 struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
1051 OverDriveTable_t *od_table =
1052 (OverDriveTable_t *)table_context->overdrive_table;
1053 int i, size = 0, ret = 0;
1054 uint32_t cur_value = 0, value = 0, count = 0;
1055 uint32_t freq_values[3] = {0};
1056 uint32_t mark_index = 0;
1057 uint32_t gen_speed, lane_width;
1058 uint32_t min_value, max_value;
1059 uint32_t smu_version;
1060
1061 smu_cmn_get_sysfs_buf(&buf, &size);
1062
1063 switch (clk_type) {
1064 case SMU_GFXCLK:
1065 case SMU_SCLK:
1066 case SMU_SOCCLK:
1067 case SMU_MCLK:
1068 case SMU_UCLK:
1069 case SMU_FCLK:
1070 case SMU_VCLK:
1071 case SMU_VCLK1:
1072 case SMU_DCLK:
1073 case SMU_DCLK1:
1074 case SMU_DCEFCLK:
1075 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1076 if (ret)
1077 goto print_clk_out;
1078
1079 /* no need to disable gfxoff when retrieving the current gfxclk */
1080 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1081 amdgpu_gfx_off_ctrl(adev, false);
1082
1083 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1084 if (ret)
1085 goto print_clk_out;
1086
1087 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1088 for (i = 0; i < count; i++) {
1089 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
1090 if (ret)
1091 goto print_clk_out;
1092
1093 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
1094 cur_value == value ? "*" : "");
1095 }
1096 } else {
1097 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
1098 if (ret)
1099 goto print_clk_out;
1100 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
1101 if (ret)
1102 goto print_clk_out;
1103
1104 freq_values[1] = cur_value;
1105 mark_index = cur_value == freq_values[0] ? 0 :
1106 cur_value == freq_values[2] ? 2 : 1;
1107
1108 count = 3;
1109 if (mark_index != 1) {
1110 count = 2;
1111 freq_values[1] = freq_values[2];
1112 }
1113
1114 for (i = 0; i < count; i++) {
1115 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
1116 cur_value == freq_values[i] ? "*" : "");
1117 }
1118
1119 }
1120 break;
1121 case SMU_PCIE:
1122 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1123 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1124 GET_PPTABLE_MEMBER(LclkFreq, &table_member);
1125 for (i = 0; i < NUM_LINK_LEVELS; i++)
1126 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1127 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1128 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1129 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1130 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1131 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1132 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1133 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1134 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1135 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1136 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1137 table_member[i],
1138 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1139 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1140 "*" : "");
1141 break;
1142 case SMU_OD_SCLK:
1143 if (!smu->od_enabled || !od_table || !od_settings)
1144 break;
1145
1146 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS))
1147 break;
1148
1149 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1150 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1151 break;
1152
1153 case SMU_OD_MCLK:
1154 if (!smu->od_enabled || !od_table || !od_settings)
1155 break;
1156
1157 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS))
1158 break;
1159
1160 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1161 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax);
1162 break;
1163
1164 case SMU_OD_VDDGFX_OFFSET:
1165 if (!smu->od_enabled || !od_table || !od_settings)
1166 break;
1167
1168 /*
1169 * OD GFX Voltage Offset functionality is supported only by 58.41.0
1170 * and onwards SMU firmwares.
1171 */
1172 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1173 if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
1174 (smu_version < 0x003a2900))
1175 break;
1176
1177 size += sysfs_emit_at(buf, size, "OD_VDDGFX_OFFSET:\n");
1178 size += sysfs_emit_at(buf, size, "%dmV\n", od_table->VddGfxOffset);
1179 break;
1180
1181 case SMU_OD_RANGE:
1182 if (!smu->od_enabled || !od_table || !od_settings)
1183 break;
1184
1185 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1186
1187 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1188 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN,
1189 &min_value, NULL);
1190 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX,
1191 NULL, &max_value);
1192 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1193 min_value, max_value);
1194 }
1195
1196 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
1197 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN,
1198 &min_value, NULL);
1199 sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX,
1200 NULL, &max_value);
1201 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1202 min_value, max_value);
1203 }
1204 break;
1205
1206 default:
1207 break;
1208 }
1209
1210 print_clk_out:
1211 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1212 amdgpu_gfx_off_ctrl(adev, true);
1213
1214 return size;
1215 }
1216
sienna_cichlid_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1217 static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1218 enum smu_clk_type clk_type, uint32_t mask)
1219 {
1220 struct amdgpu_device *adev = smu->adev;
1221 int ret = 0, size = 0;
1222 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1223
1224 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1225 soft_max_level = mask ? (fls(mask) - 1) : 0;
1226
1227 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1228 amdgpu_gfx_off_ctrl(adev, false);
1229
1230 switch (clk_type) {
1231 case SMU_GFXCLK:
1232 case SMU_SCLK:
1233 case SMU_SOCCLK:
1234 case SMU_MCLK:
1235 case SMU_UCLK:
1236 case SMU_FCLK:
1237 /* There is only 2 levels for fine grained DPM */
1238 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1239 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1240 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1241 }
1242
1243 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1244 if (ret)
1245 goto forec_level_out;
1246
1247 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1248 if (ret)
1249 goto forec_level_out;
1250
1251 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1252 if (ret)
1253 goto forec_level_out;
1254 break;
1255 case SMU_DCEFCLK:
1256 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1257 break;
1258 default:
1259 break;
1260 }
1261
1262 forec_level_out:
1263 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1264 amdgpu_gfx_off_ctrl(adev, true);
1265
1266 return size;
1267 }
1268
sienna_cichlid_populate_umd_state_clk(struct smu_context * smu)1269 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1270 {
1271 struct smu_11_0_dpm_context *dpm_context =
1272 smu->smu_dpm.dpm_context;
1273 struct smu_11_0_dpm_table *gfx_table =
1274 &dpm_context->dpm_tables.gfx_table;
1275 struct smu_11_0_dpm_table *mem_table =
1276 &dpm_context->dpm_tables.uclk_table;
1277 struct smu_11_0_dpm_table *soc_table =
1278 &dpm_context->dpm_tables.soc_table;
1279 struct smu_umd_pstate_table *pstate_table =
1280 &smu->pstate_table;
1281
1282 pstate_table->gfxclk_pstate.min = gfx_table->min;
1283 pstate_table->gfxclk_pstate.peak = gfx_table->max;
1284 if (gfx_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK)
1285 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
1286
1287 pstate_table->uclk_pstate.min = mem_table->min;
1288 pstate_table->uclk_pstate.peak = mem_table->max;
1289 if (mem_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK)
1290 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
1291
1292 pstate_table->socclk_pstate.min = soc_table->min;
1293 pstate_table->socclk_pstate.peak = soc_table->max;
1294 if (soc_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK)
1295 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
1296
1297 return 0;
1298 }
1299
sienna_cichlid_pre_display_config_changed(struct smu_context * smu)1300 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1301 {
1302 int ret = 0;
1303 uint32_t max_freq = 0;
1304
1305 /* Sienna_Cichlid do not support to change display num currently */
1306 return 0;
1307 #if 0
1308 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1309 if (ret)
1310 return ret;
1311 #endif
1312
1313 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1314 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1315 if (ret)
1316 return ret;
1317 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1318 if (ret)
1319 return ret;
1320 }
1321
1322 return ret;
1323 }
1324
sienna_cichlid_display_config_changed(struct smu_context * smu)1325 static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1326 {
1327 int ret = 0;
1328
1329 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1330 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1331 smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1332 #if 0
1333 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1334 smu->display_config->num_display,
1335 NULL);
1336 #endif
1337 if (ret)
1338 return ret;
1339 }
1340
1341 return ret;
1342 }
1343
sienna_cichlid_is_dpm_running(struct smu_context * smu)1344 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1345 {
1346 int ret = 0;
1347 uint32_t feature_mask[2];
1348 uint64_t feature_enabled;
1349
1350 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1351 if (ret)
1352 return false;
1353
1354 feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1355
1356 return !!(feature_enabled & SMC_DPM_FEATURE);
1357 }
1358
sienna_cichlid_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)1359 static int sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
1360 uint32_t *speed)
1361 {
1362 if (!speed)
1363 return -EINVAL;
1364
1365 /*
1366 * For Sienna_Cichlid and later, the fan speed(rpm) reported
1367 * by pmfw is always trustable(even when the fan control feature
1368 * disabled or 0 RPM kicked in).
1369 */
1370 return sienna_cichlid_get_smu_metrics_data(smu,
1371 METRICS_CURR_FANSPEED,
1372 speed);
1373 }
1374
sienna_cichlid_get_fan_parameters(struct smu_context * smu)1375 static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1376 {
1377 uint16_t *table_member;
1378
1379 GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member);
1380 smu->fan_max_rpm = *table_member;
1381
1382 return 0;
1383 }
1384
sienna_cichlid_get_power_profile_mode(struct smu_context * smu,char * buf)1385 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1386 {
1387 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1388 DpmActivityMonitorCoeffInt_t *activity_monitor =
1389 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1390 uint32_t i, size = 0;
1391 int16_t workload_type = 0;
1392 static const char *profile_name[] = {
1393 "BOOTUP_DEFAULT",
1394 "3D_FULL_SCREEN",
1395 "POWER_SAVING",
1396 "VIDEO",
1397 "VR",
1398 "COMPUTE",
1399 "CUSTOM"};
1400 static const char *title[] = {
1401 "PROFILE_INDEX(NAME)",
1402 "CLOCK_TYPE(NAME)",
1403 "FPS",
1404 "MinFreqType",
1405 "MinActiveFreqType",
1406 "MinActiveFreq",
1407 "BoosterFreqType",
1408 "BoosterFreq",
1409 "PD_Data_limit_c",
1410 "PD_Data_error_coeff",
1411 "PD_Data_error_rate_coeff"};
1412 int result = 0;
1413
1414 if (!buf)
1415 return -EINVAL;
1416
1417 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1418 title[0], title[1], title[2], title[3], title[4], title[5],
1419 title[6], title[7], title[8], title[9], title[10]);
1420
1421 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1422 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1423 workload_type = smu_cmn_to_asic_specific_index(smu,
1424 CMN2ASIC_MAPPING_WORKLOAD,
1425 i);
1426 if (workload_type < 0)
1427 return -EINVAL;
1428
1429 result = smu_cmn_update_table(smu,
1430 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1431 (void *)(&activity_monitor_external), false);
1432 if (result) {
1433 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1434 return result;
1435 }
1436
1437 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
1438 i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1439
1440 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1441 " ",
1442 0,
1443 "GFXCLK",
1444 activity_monitor->Gfx_FPS,
1445 activity_monitor->Gfx_MinFreqStep,
1446 activity_monitor->Gfx_MinActiveFreqType,
1447 activity_monitor->Gfx_MinActiveFreq,
1448 activity_monitor->Gfx_BoosterFreqType,
1449 activity_monitor->Gfx_BoosterFreq,
1450 activity_monitor->Gfx_PD_Data_limit_c,
1451 activity_monitor->Gfx_PD_Data_error_coeff,
1452 activity_monitor->Gfx_PD_Data_error_rate_coeff);
1453
1454 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1455 " ",
1456 1,
1457 "SOCCLK",
1458 activity_monitor->Fclk_FPS,
1459 activity_monitor->Fclk_MinFreqStep,
1460 activity_monitor->Fclk_MinActiveFreqType,
1461 activity_monitor->Fclk_MinActiveFreq,
1462 activity_monitor->Fclk_BoosterFreqType,
1463 activity_monitor->Fclk_BoosterFreq,
1464 activity_monitor->Fclk_PD_Data_limit_c,
1465 activity_monitor->Fclk_PD_Data_error_coeff,
1466 activity_monitor->Fclk_PD_Data_error_rate_coeff);
1467
1468 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1469 " ",
1470 2,
1471 "MEMLK",
1472 activity_monitor->Mem_FPS,
1473 activity_monitor->Mem_MinFreqStep,
1474 activity_monitor->Mem_MinActiveFreqType,
1475 activity_monitor->Mem_MinActiveFreq,
1476 activity_monitor->Mem_BoosterFreqType,
1477 activity_monitor->Mem_BoosterFreq,
1478 activity_monitor->Mem_PD_Data_limit_c,
1479 activity_monitor->Mem_PD_Data_error_coeff,
1480 activity_monitor->Mem_PD_Data_error_rate_coeff);
1481 }
1482
1483 return size;
1484 }
1485
sienna_cichlid_set_power_profile_mode(struct smu_context * smu,long * input,uint32_t size)1486 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1487 {
1488
1489 DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1490 DpmActivityMonitorCoeffInt_t *activity_monitor =
1491 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1492 int workload_type, ret = 0;
1493
1494 smu->power_profile_mode = input[size];
1495
1496 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1497 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1498 return -EINVAL;
1499 }
1500
1501 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1502
1503 ret = smu_cmn_update_table(smu,
1504 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1505 (void *)(&activity_monitor_external), false);
1506 if (ret) {
1507 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1508 return ret;
1509 }
1510
1511 switch (input[0]) {
1512 case 0: /* Gfxclk */
1513 activity_monitor->Gfx_FPS = input[1];
1514 activity_monitor->Gfx_MinFreqStep = input[2];
1515 activity_monitor->Gfx_MinActiveFreqType = input[3];
1516 activity_monitor->Gfx_MinActiveFreq = input[4];
1517 activity_monitor->Gfx_BoosterFreqType = input[5];
1518 activity_monitor->Gfx_BoosterFreq = input[6];
1519 activity_monitor->Gfx_PD_Data_limit_c = input[7];
1520 activity_monitor->Gfx_PD_Data_error_coeff = input[8];
1521 activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9];
1522 break;
1523 case 1: /* Socclk */
1524 activity_monitor->Fclk_FPS = input[1];
1525 activity_monitor->Fclk_MinFreqStep = input[2];
1526 activity_monitor->Fclk_MinActiveFreqType = input[3];
1527 activity_monitor->Fclk_MinActiveFreq = input[4];
1528 activity_monitor->Fclk_BoosterFreqType = input[5];
1529 activity_monitor->Fclk_BoosterFreq = input[6];
1530 activity_monitor->Fclk_PD_Data_limit_c = input[7];
1531 activity_monitor->Fclk_PD_Data_error_coeff = input[8];
1532 activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9];
1533 break;
1534 case 2: /* Memlk */
1535 activity_monitor->Mem_FPS = input[1];
1536 activity_monitor->Mem_MinFreqStep = input[2];
1537 activity_monitor->Mem_MinActiveFreqType = input[3];
1538 activity_monitor->Mem_MinActiveFreq = input[4];
1539 activity_monitor->Mem_BoosterFreqType = input[5];
1540 activity_monitor->Mem_BoosterFreq = input[6];
1541 activity_monitor->Mem_PD_Data_limit_c = input[7];
1542 activity_monitor->Mem_PD_Data_error_coeff = input[8];
1543 activity_monitor->Mem_PD_Data_error_rate_coeff = input[9];
1544 break;
1545 }
1546
1547 ret = smu_cmn_update_table(smu,
1548 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1549 (void *)(&activity_monitor_external), true);
1550 if (ret) {
1551 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1552 return ret;
1553 }
1554 }
1555
1556 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1557 workload_type = smu_cmn_to_asic_specific_index(smu,
1558 CMN2ASIC_MAPPING_WORKLOAD,
1559 smu->power_profile_mode);
1560 if (workload_type < 0)
1561 return -EINVAL;
1562 smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1563 1 << workload_type, NULL);
1564
1565 return ret;
1566 }
1567
sienna_cichlid_notify_smc_display_config(struct smu_context * smu)1568 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1569 {
1570 struct smu_clocks min_clocks = {0};
1571 struct pp_display_clock_request clock_req;
1572 int ret = 0;
1573
1574 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1575 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1576 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1577
1578 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1579 clock_req.clock_type = amd_pp_dcef_clock;
1580 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1581
1582 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1583 if (!ret) {
1584 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1585 ret = smu_cmn_send_smc_msg_with_param(smu,
1586 SMU_MSG_SetMinDeepSleepDcefclk,
1587 min_clocks.dcef_clock_in_sr/100,
1588 NULL);
1589 if (ret) {
1590 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1591 return ret;
1592 }
1593 }
1594 } else {
1595 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1596 }
1597 }
1598
1599 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1600 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1601 if (ret) {
1602 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1603 return ret;
1604 }
1605 }
1606
1607 return 0;
1608 }
1609
sienna_cichlid_set_watermarks_table(struct smu_context * smu,struct pp_smu_wm_range_sets * clock_ranges)1610 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1611 struct pp_smu_wm_range_sets *clock_ranges)
1612 {
1613 Watermarks_t *table = smu->smu_table.watermarks_table;
1614 int ret = 0;
1615 int i;
1616
1617 if (clock_ranges) {
1618 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1619 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1620 return -EINVAL;
1621
1622 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1623 table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1624 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1625 table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1626 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1627 table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1628 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1629 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1630 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1631
1632 table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1633 clock_ranges->reader_wm_sets[i].wm_inst;
1634 }
1635
1636 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1637 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1638 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1639 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1640 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1641 table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1642 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1643 table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1644 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1645
1646 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1647 clock_ranges->writer_wm_sets[i].wm_inst;
1648 }
1649
1650 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1651 }
1652
1653 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1654 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1655 ret = smu_cmn_write_watermarks_table(smu);
1656 if (ret) {
1657 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1658 return ret;
1659 }
1660 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1661 }
1662
1663 return 0;
1664 }
1665
sienna_cichlid_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1666 static int sienna_cichlid_read_sensor(struct smu_context *smu,
1667 enum amd_pp_sensors sensor,
1668 void *data, uint32_t *size)
1669 {
1670 int ret = 0;
1671 uint16_t *temp;
1672
1673 if(!data || !size)
1674 return -EINVAL;
1675
1676 mutex_lock(&smu->sensor_lock);
1677 switch (sensor) {
1678 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1679 GET_PPTABLE_MEMBER(FanMaximumRpm, &temp);
1680 *(uint16_t *)data = *temp;
1681 *size = 4;
1682 break;
1683 case AMDGPU_PP_SENSOR_MEM_LOAD:
1684 ret = sienna_cichlid_get_smu_metrics_data(smu,
1685 METRICS_AVERAGE_MEMACTIVITY,
1686 (uint32_t *)data);
1687 *size = 4;
1688 break;
1689 case AMDGPU_PP_SENSOR_GPU_LOAD:
1690 ret = sienna_cichlid_get_smu_metrics_data(smu,
1691 METRICS_AVERAGE_GFXACTIVITY,
1692 (uint32_t *)data);
1693 *size = 4;
1694 break;
1695 case AMDGPU_PP_SENSOR_GPU_POWER:
1696 ret = sienna_cichlid_get_smu_metrics_data(smu,
1697 METRICS_AVERAGE_SOCKETPOWER,
1698 (uint32_t *)data);
1699 *size = 4;
1700 break;
1701 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1702 ret = sienna_cichlid_get_smu_metrics_data(smu,
1703 METRICS_TEMPERATURE_HOTSPOT,
1704 (uint32_t *)data);
1705 *size = 4;
1706 break;
1707 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1708 ret = sienna_cichlid_get_smu_metrics_data(smu,
1709 METRICS_TEMPERATURE_EDGE,
1710 (uint32_t *)data);
1711 *size = 4;
1712 break;
1713 case AMDGPU_PP_SENSOR_MEM_TEMP:
1714 ret = sienna_cichlid_get_smu_metrics_data(smu,
1715 METRICS_TEMPERATURE_MEM,
1716 (uint32_t *)data);
1717 *size = 4;
1718 break;
1719 case AMDGPU_PP_SENSOR_GFX_MCLK:
1720 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1721 *(uint32_t *)data *= 100;
1722 *size = 4;
1723 break;
1724 case AMDGPU_PP_SENSOR_GFX_SCLK:
1725 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1726 *(uint32_t *)data *= 100;
1727 *size = 4;
1728 break;
1729 case AMDGPU_PP_SENSOR_VDDGFX:
1730 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1731 *size = 4;
1732 break;
1733 default:
1734 ret = -EOPNOTSUPP;
1735 break;
1736 }
1737 mutex_unlock(&smu->sensor_lock);
1738
1739 return ret;
1740 }
1741
sienna_cichlid_get_uclk_dpm_states(struct smu_context * smu,uint32_t * clocks_in_khz,uint32_t * num_states)1742 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1743 {
1744 uint32_t num_discrete_levels = 0;
1745 uint16_t *dpm_levels = NULL;
1746 uint16_t i = 0;
1747 struct smu_table_context *table_context = &smu->smu_table;
1748 DpmDescriptor_t *table_member1;
1749 uint16_t *table_member2;
1750
1751 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1752 return -EINVAL;
1753
1754 GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1);
1755 num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels;
1756 GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2);
1757 dpm_levels = table_member2;
1758
1759 if (num_discrete_levels == 0 || dpm_levels == NULL)
1760 return -EINVAL;
1761
1762 *num_states = num_discrete_levels;
1763 for (i = 0; i < num_discrete_levels; i++) {
1764 /* convert to khz */
1765 *clocks_in_khz = (*dpm_levels) * 1000;
1766 clocks_in_khz++;
1767 dpm_levels++;
1768 }
1769
1770 return 0;
1771 }
1772
sienna_cichlid_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)1773 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1774 struct smu_temperature_range *range)
1775 {
1776 struct smu_table_context *table_context = &smu->smu_table;
1777 struct smu_11_0_7_powerplay_table *powerplay_table =
1778 table_context->power_play_table;
1779 uint16_t *table_member;
1780 uint16_t temp_edge, temp_hotspot, temp_mem;
1781
1782 if (!range)
1783 return -EINVAL;
1784
1785 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1786
1787 GET_PPTABLE_MEMBER(TemperatureLimit, &table_member);
1788 temp_edge = table_member[TEMP_EDGE];
1789 temp_hotspot = table_member[TEMP_HOTSPOT];
1790 temp_mem = table_member[TEMP_MEM];
1791
1792 range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1793 range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) *
1794 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1795 range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1796 range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) *
1797 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1798 range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1799 range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)*
1800 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1801
1802 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1803
1804 return 0;
1805 }
1806
sienna_cichlid_display_disable_memory_clock_switch(struct smu_context * smu,bool disable_memory_clock_switch)1807 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1808 bool disable_memory_clock_switch)
1809 {
1810 int ret = 0;
1811 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1812 (struct smu_11_0_max_sustainable_clocks *)
1813 smu->smu_table.max_sustainable_clocks;
1814 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1815 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1816
1817 if(smu->disable_uclk_switch == disable_memory_clock_switch)
1818 return 0;
1819
1820 if(disable_memory_clock_switch)
1821 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
1822 else
1823 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
1824
1825 if(!ret)
1826 smu->disable_uclk_switch = disable_memory_clock_switch;
1827
1828 return ret;
1829 }
1830
sienna_cichlid_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit)1831 static int sienna_cichlid_get_power_limit(struct smu_context *smu,
1832 uint32_t *current_power_limit,
1833 uint32_t *default_power_limit,
1834 uint32_t *max_power_limit)
1835 {
1836 struct smu_11_0_7_powerplay_table *powerplay_table =
1837 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
1838 uint32_t power_limit, od_percent;
1839 uint16_t *table_member;
1840
1841 GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member);
1842
1843 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1844 power_limit =
1845 table_member[PPT_THROTTLER_PPT0];
1846 }
1847
1848 if (current_power_limit)
1849 *current_power_limit = power_limit;
1850 if (default_power_limit)
1851 *default_power_limit = power_limit;
1852
1853 if (max_power_limit) {
1854 if (smu->od_enabled) {
1855 od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
1856
1857 dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1858
1859 power_limit *= (100 + od_percent);
1860 power_limit /= 100;
1861 }
1862 *max_power_limit = power_limit;
1863 }
1864
1865 return 0;
1866 }
1867
sienna_cichlid_update_pcie_parameters(struct smu_context * smu,uint32_t pcie_gen_cap,uint32_t pcie_width_cap)1868 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
1869 uint32_t pcie_gen_cap,
1870 uint32_t pcie_width_cap)
1871 {
1872 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1873
1874 uint32_t smu_pcie_arg;
1875 uint8_t *table_member1, *table_member2;
1876 int ret, i;
1877
1878 GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
1879 GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
1880
1881 /* lclk dpm table setup */
1882 for (i = 0; i < MAX_PCIE_CONF; i++) {
1883 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = table_member1[i];
1884 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = table_member2[i];
1885 }
1886
1887 for (i = 0; i < NUM_LINK_LEVELS; i++) {
1888 smu_pcie_arg = (i << 16) |
1889 ((table_member1[i] <= pcie_gen_cap) ?
1890 (table_member1[i] << 8) :
1891 (pcie_gen_cap << 8)) |
1892 ((table_member2[i] <= pcie_width_cap) ?
1893 table_member2[i] :
1894 pcie_width_cap);
1895
1896 ret = smu_cmn_send_smc_msg_with_param(smu,
1897 SMU_MSG_OverridePcieParameters,
1898 smu_pcie_arg,
1899 NULL);
1900 if (ret)
1901 return ret;
1902
1903 if (table_member1[i] > pcie_gen_cap)
1904 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1905 if (table_member2[i] > pcie_width_cap)
1906 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1907 }
1908
1909 return 0;
1910 }
1911
sienna_cichlid_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)1912 static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
1913 enum smu_clk_type clk_type,
1914 uint32_t *min, uint32_t *max)
1915 {
1916 struct amdgpu_device *adev = smu->adev;
1917 int ret;
1918
1919 if (clk_type == SMU_GFXCLK)
1920 amdgpu_gfx_off_ctrl(adev, false);
1921 ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
1922 if (clk_type == SMU_GFXCLK)
1923 amdgpu_gfx_off_ctrl(adev, true);
1924
1925 return ret;
1926 }
1927
sienna_cichlid_dump_od_table(struct smu_context * smu,OverDriveTable_t * od_table)1928 static void sienna_cichlid_dump_od_table(struct smu_context *smu,
1929 OverDriveTable_t *od_table)
1930 {
1931 struct amdgpu_device *adev = smu->adev;
1932 uint32_t smu_version;
1933
1934 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin,
1935 od_table->GfxclkFmax);
1936 dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin,
1937 od_table->UclkFmax);
1938
1939 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1940 if (!((adev->asic_type == CHIP_SIENNA_CICHLID) &&
1941 (smu_version < 0x003a2900)))
1942 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
1943 }
1944
sienna_cichlid_set_default_od_settings(struct smu_context * smu)1945 static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
1946 {
1947 OverDriveTable_t *od_table =
1948 (OverDriveTable_t *)smu->smu_table.overdrive_table;
1949 OverDriveTable_t *boot_od_table =
1950 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
1951 OverDriveTable_t *user_od_table =
1952 (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
1953 int ret = 0;
1954
1955 /*
1956 * For S3/S4/Runpm resume, no need to setup those overdrive tables again as
1957 * - either they already have the default OD settings got during cold bootup
1958 * - or they have some user customized OD settings which cannot be overwritten
1959 */
1960 if (smu->adev->in_suspend)
1961 return 0;
1962
1963 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
1964 0, (void *)boot_od_table, false);
1965 if (ret) {
1966 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
1967 return ret;
1968 }
1969
1970 sienna_cichlid_dump_od_table(smu, boot_od_table);
1971
1972 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
1973 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
1974
1975 return 0;
1976 }
1977
sienna_cichlid_od_setting_check_range(struct smu_context * smu,struct smu_11_0_7_overdrive_table * od_table,enum SMU_11_0_7_ODSETTING_ID setting,uint32_t value)1978 static int sienna_cichlid_od_setting_check_range(struct smu_context *smu,
1979 struct smu_11_0_7_overdrive_table *od_table,
1980 enum SMU_11_0_7_ODSETTING_ID setting,
1981 uint32_t value)
1982 {
1983 if (value < od_table->min[setting]) {
1984 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n",
1985 setting, value, od_table->min[setting]);
1986 return -EINVAL;
1987 }
1988 if (value > od_table->max[setting]) {
1989 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n",
1990 setting, value, od_table->max[setting]);
1991 return -EINVAL;
1992 }
1993
1994 return 0;
1995 }
1996
sienna_cichlid_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)1997 static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
1998 enum PP_OD_DPM_TABLE_COMMAND type,
1999 long input[], uint32_t size)
2000 {
2001 struct smu_table_context *table_context = &smu->smu_table;
2002 OverDriveTable_t *od_table =
2003 (OverDriveTable_t *)table_context->overdrive_table;
2004 struct smu_11_0_7_overdrive_table *od_settings =
2005 (struct smu_11_0_7_overdrive_table *)smu->od_settings;
2006 struct amdgpu_device *adev = smu->adev;
2007 enum SMU_11_0_7_ODSETTING_ID freq_setting;
2008 uint16_t *freq_ptr;
2009 int i, ret = 0;
2010 uint32_t smu_version;
2011
2012 if (!smu->od_enabled) {
2013 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2014 return -EINVAL;
2015 }
2016
2017 if (!smu->od_settings) {
2018 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2019 return -ENOENT;
2020 }
2021
2022 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2023 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2024 return -EINVAL;
2025 }
2026
2027 switch (type) {
2028 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2029 if (!sienna_cichlid_is_od_feature_supported(od_settings,
2030 SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
2031 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2032 return -ENOTSUPP;
2033 }
2034
2035 for (i = 0; i < size; i += 2) {
2036 if (i + 2 > size) {
2037 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2038 return -EINVAL;
2039 }
2040
2041 switch (input[i]) {
2042 case 0:
2043 if (input[i + 1] > od_table->GfxclkFmax) {
2044 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2045 input[i + 1], od_table->GfxclkFmax);
2046 return -EINVAL;
2047 }
2048
2049 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN;
2050 freq_ptr = &od_table->GfxclkFmin;
2051 break;
2052
2053 case 1:
2054 if (input[i + 1] < od_table->GfxclkFmin) {
2055 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2056 input[i + 1], od_table->GfxclkFmin);
2057 return -EINVAL;
2058 }
2059
2060 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX;
2061 freq_ptr = &od_table->GfxclkFmax;
2062 break;
2063
2064 default:
2065 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2066 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2067 return -EINVAL;
2068 }
2069
2070 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2071 freq_setting, input[i + 1]);
2072 if (ret)
2073 return ret;
2074
2075 *freq_ptr = (uint16_t)input[i + 1];
2076 }
2077 break;
2078
2079 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2080 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
2081 dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n");
2082 return -ENOTSUPP;
2083 }
2084
2085 for (i = 0; i < size; i += 2) {
2086 if (i + 2 > size) {
2087 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2088 return -EINVAL;
2089 }
2090
2091 switch (input[i]) {
2092 case 0:
2093 if (input[i + 1] > od_table->UclkFmax) {
2094 dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n",
2095 input[i + 1], od_table->UclkFmax);
2096 return -EINVAL;
2097 }
2098
2099 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN;
2100 freq_ptr = &od_table->UclkFmin;
2101 break;
2102
2103 case 1:
2104 if (input[i + 1] < od_table->UclkFmin) {
2105 dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n",
2106 input[i + 1], od_table->UclkFmin);
2107 return -EINVAL;
2108 }
2109
2110 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX;
2111 freq_ptr = &od_table->UclkFmax;
2112 break;
2113
2114 default:
2115 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
2116 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2117 return -EINVAL;
2118 }
2119
2120 ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2121 freq_setting, input[i + 1]);
2122 if (ret)
2123 return ret;
2124
2125 *freq_ptr = (uint16_t)input[i + 1];
2126 }
2127 break;
2128
2129 case PP_OD_RESTORE_DEFAULT_TABLE:
2130 memcpy(table_context->overdrive_table,
2131 table_context->boot_overdrive_table,
2132 sizeof(OverDriveTable_t));
2133 fallthrough;
2134
2135 case PP_OD_COMMIT_DPM_TABLE:
2136 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) {
2137 sienna_cichlid_dump_od_table(smu, od_table);
2138 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2139 if (ret) {
2140 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2141 return ret;
2142 }
2143 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t));
2144 smu->user_dpm_profile.user_od = true;
2145
2146 if (!memcmp(table_context->user_overdrive_table,
2147 table_context->boot_overdrive_table,
2148 sizeof(OverDriveTable_t)))
2149 smu->user_dpm_profile.user_od = false;
2150 }
2151 break;
2152
2153 case PP_OD_EDIT_VDDGFX_OFFSET:
2154 if (size != 1) {
2155 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2156 return -EINVAL;
2157 }
2158
2159 /*
2160 * OD GFX Voltage Offset functionality is supported only by 58.41.0
2161 * and onwards SMU firmwares.
2162 */
2163 smu_cmn_get_smc_version(smu, NULL, &smu_version);
2164 if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
2165 (smu_version < 0x003a2900)) {
2166 dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
2167 "only by 58.41.0 and onwards SMU firmwares!\n");
2168 return -EOPNOTSUPP;
2169 }
2170
2171 od_table->VddGfxOffset = (int16_t)input[0];
2172
2173 sienna_cichlid_dump_od_table(smu, od_table);
2174 break;
2175
2176 default:
2177 return -ENOSYS;
2178 }
2179
2180 return ret;
2181 }
2182
sienna_cichlid_run_btc(struct smu_context * smu)2183 static int sienna_cichlid_run_btc(struct smu_context *smu)
2184 {
2185 return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2186 }
2187
sienna_cichlid_baco_enter(struct smu_context * smu)2188 static int sienna_cichlid_baco_enter(struct smu_context *smu)
2189 {
2190 struct amdgpu_device *adev = smu->adev;
2191
2192 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
2193 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2194 else
2195 return smu_v11_0_baco_enter(smu);
2196 }
2197
sienna_cichlid_baco_exit(struct smu_context * smu)2198 static int sienna_cichlid_baco_exit(struct smu_context *smu)
2199 {
2200 struct amdgpu_device *adev = smu->adev;
2201
2202 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2203 /* Wait for PMFW handling for the Dstate change */
2204 msleep(10);
2205 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2206 } else {
2207 return smu_v11_0_baco_exit(smu);
2208 }
2209 }
2210
sienna_cichlid_is_mode1_reset_supported(struct smu_context * smu)2211 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
2212 {
2213 struct amdgpu_device *adev = smu->adev;
2214 uint32_t val;
2215 u32 smu_version;
2216
2217 /**
2218 * SRIOV env will not support SMU mode1 reset
2219 * PM FW support mode1 reset from 58.26
2220 */
2221 smu_cmn_get_smc_version(smu, NULL, &smu_version);
2222 if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
2223 return false;
2224
2225 /**
2226 * mode1 reset relies on PSP, so we should check if
2227 * PSP is alive.
2228 */
2229 val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
2230 return val != 0x0;
2231 }
2232
beige_goby_dump_pptable(struct smu_context * smu)2233 static void beige_goby_dump_pptable(struct smu_context *smu)
2234 {
2235 struct smu_table_context *table_context = &smu->smu_table;
2236 PPTable_beige_goby_t *pptable = table_context->driver_pptable;
2237 int i;
2238
2239 dev_info(smu->adev->dev, "Dumped PPTable:\n");
2240
2241 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2242 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2243 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2244
2245 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
2246 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2247 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2248 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2249 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2250 }
2251
2252 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
2253 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2254 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2255 }
2256
2257 for (i = 0; i < TEMP_COUNT; i++) {
2258 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2259 }
2260
2261 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2262 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2263 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2264 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2265 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2266
2267 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2268 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
2269 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2270 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2271 }
2272 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2273
2274 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2275
2276 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2277 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2278 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2279 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2280
2281 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2282
2283 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2284
2285 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2286 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2287 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2288 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2289
2290 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2291 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2292
2293 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2294 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2295 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2296 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2297 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2298 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2299 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2300 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2301
2302 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2303 " .VoltageMode = 0x%02x\n"
2304 " .SnapToDiscrete = 0x%02x\n"
2305 " .NumDiscreteLevels = 0x%02x\n"
2306 " .padding = 0x%02x\n"
2307 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2308 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2309 " .SsFmin = 0x%04x\n"
2310 " .Padding_16 = 0x%04x\n",
2311 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2312 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2313 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2314 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2315 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2316 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2317 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2318 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2319 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2320 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2321 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2322
2323 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2324 " .VoltageMode = 0x%02x\n"
2325 " .SnapToDiscrete = 0x%02x\n"
2326 " .NumDiscreteLevels = 0x%02x\n"
2327 " .padding = 0x%02x\n"
2328 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2329 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2330 " .SsFmin = 0x%04x\n"
2331 " .Padding_16 = 0x%04x\n",
2332 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2333 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2334 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2335 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2336 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2337 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2338 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2339 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2340 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2341 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2342 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2343
2344 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2345 " .VoltageMode = 0x%02x\n"
2346 " .SnapToDiscrete = 0x%02x\n"
2347 " .NumDiscreteLevels = 0x%02x\n"
2348 " .padding = 0x%02x\n"
2349 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2350 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2351 " .SsFmin = 0x%04x\n"
2352 " .Padding_16 = 0x%04x\n",
2353 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2354 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2355 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2356 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2357 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2358 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2359 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2360 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2361 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2362 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2363 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2364
2365 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
2366 " .VoltageMode = 0x%02x\n"
2367 " .SnapToDiscrete = 0x%02x\n"
2368 " .NumDiscreteLevels = 0x%02x\n"
2369 " .padding = 0x%02x\n"
2370 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2371 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2372 " .SsFmin = 0x%04x\n"
2373 " .Padding_16 = 0x%04x\n",
2374 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2375 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2376 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2377 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2378 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2379 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2380 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2381 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2382 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2383 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2384 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2385
2386 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
2387 " .VoltageMode = 0x%02x\n"
2388 " .SnapToDiscrete = 0x%02x\n"
2389 " .NumDiscreteLevels = 0x%02x\n"
2390 " .padding = 0x%02x\n"
2391 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2392 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2393 " .SsFmin = 0x%04x\n"
2394 " .Padding_16 = 0x%04x\n",
2395 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2396 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2397 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2398 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2399 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2400 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2401 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2402 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2403 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2404 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2405 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2406
2407 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
2408 " .VoltageMode = 0x%02x\n"
2409 " .SnapToDiscrete = 0x%02x\n"
2410 " .NumDiscreteLevels = 0x%02x\n"
2411 " .padding = 0x%02x\n"
2412 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2413 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2414 " .SsFmin = 0x%04x\n"
2415 " .Padding_16 = 0x%04x\n",
2416 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
2417 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
2418 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
2419 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
2420 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
2421 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
2422 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
2423 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
2424 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
2425 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
2426 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
2427
2428 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
2429 " .VoltageMode = 0x%02x\n"
2430 " .SnapToDiscrete = 0x%02x\n"
2431 " .NumDiscreteLevels = 0x%02x\n"
2432 " .padding = 0x%02x\n"
2433 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2434 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2435 " .SsFmin = 0x%04x\n"
2436 " .Padding_16 = 0x%04x\n",
2437 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
2438 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
2439 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
2440 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
2441 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
2442 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
2443 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
2444 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
2445 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
2446 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
2447 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
2448
2449 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
2450 " .VoltageMode = 0x%02x\n"
2451 " .SnapToDiscrete = 0x%02x\n"
2452 " .NumDiscreteLevels = 0x%02x\n"
2453 " .padding = 0x%02x\n"
2454 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2455 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2456 " .SsFmin = 0x%04x\n"
2457 " .Padding_16 = 0x%04x\n",
2458 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2459 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2460 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2461 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2462 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2463 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2464 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2465 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2466 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2467 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2468 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2469
2470 dev_info(smu->adev->dev, "FreqTableGfx\n");
2471 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2472 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2473
2474 dev_info(smu->adev->dev, "FreqTableVclk\n");
2475 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2476 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2477
2478 dev_info(smu->adev->dev, "FreqTableDclk\n");
2479 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2480 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2481
2482 dev_info(smu->adev->dev, "FreqTableSocclk\n");
2483 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2484 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2485
2486 dev_info(smu->adev->dev, "FreqTableUclk\n");
2487 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2488 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2489
2490 dev_info(smu->adev->dev, "FreqTableFclk\n");
2491 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2492 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2493
2494 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2495 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2496 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2497 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2498 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2499 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2500 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2501 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2502 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2503
2504 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2505 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2506 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2507
2508 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2509 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2510
2511 dev_info(smu->adev->dev, "Mp0clkFreq\n");
2512 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2513 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2514
2515 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2516 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2517 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2518
2519 dev_info(smu->adev->dev, "MemVddciVoltage\n");
2520 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2521 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2522
2523 dev_info(smu->adev->dev, "MemMvddVoltage\n");
2524 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2525 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2526
2527 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2528 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2529 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2530 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2531 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2532
2533 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2534
2535 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2536 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2537 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2538 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2539 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2540 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2541 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2542 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2543 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2544 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2545 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2546
2547 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2548 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2549 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2550 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2551 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2552 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2553
2554 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2555 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2556 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2557 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2558 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2559
2560 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2561 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2562 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2563
2564 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2565 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2566 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2567 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2568
2569 dev_info(smu->adev->dev, "UclkDpmPstates\n");
2570 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2571 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2572
2573 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2574 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2575 pptable->UclkDpmSrcFreqRange.Fmin);
2576 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2577 pptable->UclkDpmSrcFreqRange.Fmax);
2578 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2579 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
2580 pptable->UclkDpmTargFreqRange.Fmin);
2581 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
2582 pptable->UclkDpmTargFreqRange.Fmax);
2583 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2584 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2585
2586 dev_info(smu->adev->dev, "PcieGenSpeed\n");
2587 for (i = 0; i < NUM_LINK_LEVELS; i++)
2588 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2589
2590 dev_info(smu->adev->dev, "PcieLaneCount\n");
2591 for (i = 0; i < NUM_LINK_LEVELS; i++)
2592 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2593
2594 dev_info(smu->adev->dev, "LclkFreq\n");
2595 for (i = 0; i < NUM_LINK_LEVELS; i++)
2596 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2597
2598 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2599 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2600
2601 dev_info(smu->adev->dev, "FanGain\n");
2602 for (i = 0; i < TEMP_COUNT; i++)
2603 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2604
2605 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2606 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2607 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2608 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2609 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2610 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2611 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2612 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2613 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2614 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2615 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2616 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2617
2618 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2619 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2620 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2621 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2622
2623 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2624 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2625 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2626 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2627
2628 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2629 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2630 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2631 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2632 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2633 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2634 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2635 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2636 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2637 pptable->dBtcGbGfxPll.a,
2638 pptable->dBtcGbGfxPll.b,
2639 pptable->dBtcGbGfxPll.c);
2640 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2641 pptable->dBtcGbGfxDfll.a,
2642 pptable->dBtcGbGfxDfll.b,
2643 pptable->dBtcGbGfxDfll.c);
2644 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2645 pptable->dBtcGbSoc.a,
2646 pptable->dBtcGbSoc.b,
2647 pptable->dBtcGbSoc.c);
2648 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2649 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2650 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2651 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2652 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2653 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2654
2655 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2656 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2657 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
2658 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2659 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
2660 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2661 }
2662
2663 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2664 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2665 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2666 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2667 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2668 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2669 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2670 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2671
2672 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2673 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2674
2675 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2676 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2677 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2678 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2679
2680 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2681 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2682 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2683 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2684
2685 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2686 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2687
2688 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2689 for (i = 0; i < NUM_XGMI_LEVELS; i++)
2690 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2691 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2692 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2693
2694 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2695 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2696 pptable->ReservedEquation0.a,
2697 pptable->ReservedEquation0.b,
2698 pptable->ReservedEquation0.c);
2699 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2700 pptable->ReservedEquation1.a,
2701 pptable->ReservedEquation1.b,
2702 pptable->ReservedEquation1.c);
2703 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2704 pptable->ReservedEquation2.a,
2705 pptable->ReservedEquation2.b,
2706 pptable->ReservedEquation2.c);
2707 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2708 pptable->ReservedEquation3.a,
2709 pptable->ReservedEquation3.b,
2710 pptable->ReservedEquation3.c);
2711
2712 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2713 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2714 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2715 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2716 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2717 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2718 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2719 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2720
2721 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2722 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2723 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2724 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2725 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2726 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2727
2728 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2729 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2730 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
2731 pptable->I2cControllers[i].Enabled);
2732 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
2733 pptable->I2cControllers[i].Speed);
2734 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
2735 pptable->I2cControllers[i].SlaveAddress);
2736 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
2737 pptable->I2cControllers[i].ControllerPort);
2738 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
2739 pptable->I2cControllers[i].ControllerName);
2740 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
2741 pptable->I2cControllers[i].ThermalThrotter);
2742 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
2743 pptable->I2cControllers[i].I2cProtocol);
2744 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
2745 pptable->I2cControllers[i].PaddingConfig);
2746 }
2747
2748 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2749 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2750 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2751 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2752
2753 dev_info(smu->adev->dev, "Board Parameters:\n");
2754 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2755 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2756 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2757 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2758 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2759 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2760 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2761 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2762
2763 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2764 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
2765 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2766
2767 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2768 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
2769 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2770
2771 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2772 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2773 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2774
2775 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2776 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2777 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2778
2779 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
2780
2781 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2782 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2783 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2784 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2785 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2786 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2787 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
2788 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2789 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
2790 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
2791 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
2792 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2793 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
2794 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
2795 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2796 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2797
2798 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2799 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2800 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
2801
2802 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2803 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2804 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
2805
2806 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
2807 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2808
2809 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2810 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2811 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2812
2813 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2814 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2815 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2816 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2817 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2818
2819 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2820 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2821
2822 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
2823 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2824 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2825 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
2826 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2827 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2828 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
2829 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2830 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2831 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
2832 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2833 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2834
2835 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2836 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2837 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2838 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2839
2840 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2841 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2842 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2843 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2844 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2845 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2846 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2847 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2848 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2849 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2850 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
2851
2852 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2853 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2854 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2855 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2856 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2857 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2858 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2859 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
2860 }
2861
sienna_cichlid_dump_pptable(struct smu_context * smu)2862 static void sienna_cichlid_dump_pptable(struct smu_context *smu)
2863 {
2864 struct smu_table_context *table_context = &smu->smu_table;
2865 PPTable_t *pptable = table_context->driver_pptable;
2866 int i;
2867
2868 if (smu->adev->asic_type == CHIP_BEIGE_GOBY) {
2869 beige_goby_dump_pptable(smu);
2870 return;
2871 }
2872
2873 dev_info(smu->adev->dev, "Dumped PPTable:\n");
2874
2875 dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2876 dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2877 dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2878
2879 for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
2880 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2881 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2882 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2883 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2884 }
2885
2886 for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
2887 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2888 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2889 }
2890
2891 for (i = 0; i < TEMP_COUNT; i++) {
2892 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2893 }
2894
2895 dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2896 dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2897 dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2898 dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2899 dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2900
2901 dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2902 for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
2903 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2904 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2905 }
2906 dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2907
2908 dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2909
2910 dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2911 dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2912 dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2913 dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2914
2915 dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2916 dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
2917
2918 dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2919 dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
2920 dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
2921 dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
2922
2923 dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2924 dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2925 dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2926 dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2927
2928 dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2929 dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2930
2931 dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2932 dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2933 dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2934 dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2935 dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2936 dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2937 dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2938 dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2939
2940 dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2941 " .VoltageMode = 0x%02x\n"
2942 " .SnapToDiscrete = 0x%02x\n"
2943 " .NumDiscreteLevels = 0x%02x\n"
2944 " .padding = 0x%02x\n"
2945 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2946 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2947 " .SsFmin = 0x%04x\n"
2948 " .Padding_16 = 0x%04x\n",
2949 pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2950 pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2951 pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2952 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2953 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2954 pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2955 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2956 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2957 pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2958 pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2959 pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2960
2961 dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2962 " .VoltageMode = 0x%02x\n"
2963 " .SnapToDiscrete = 0x%02x\n"
2964 " .NumDiscreteLevels = 0x%02x\n"
2965 " .padding = 0x%02x\n"
2966 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2967 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2968 " .SsFmin = 0x%04x\n"
2969 " .Padding_16 = 0x%04x\n",
2970 pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2971 pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2972 pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2973 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2974 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2975 pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2976 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2977 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2978 pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2979 pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2980 pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2981
2982 dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2983 " .VoltageMode = 0x%02x\n"
2984 " .SnapToDiscrete = 0x%02x\n"
2985 " .NumDiscreteLevels = 0x%02x\n"
2986 " .padding = 0x%02x\n"
2987 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2988 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2989 " .SsFmin = 0x%04x\n"
2990 " .Padding_16 = 0x%04x\n",
2991 pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2992 pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2993 pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2994 pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2995 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2996 pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2997 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2998 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2999 pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
3000 pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
3001 pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
3002
3003 dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
3004 " .VoltageMode = 0x%02x\n"
3005 " .SnapToDiscrete = 0x%02x\n"
3006 " .NumDiscreteLevels = 0x%02x\n"
3007 " .padding = 0x%02x\n"
3008 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3009 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3010 " .SsFmin = 0x%04x\n"
3011 " .Padding_16 = 0x%04x\n",
3012 pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
3013 pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
3014 pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
3015 pptable->DpmDescriptor[PPCLK_FCLK].Padding,
3016 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
3017 pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
3018 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
3019 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
3020 pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
3021 pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
3022 pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
3023
3024 dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
3025 " .VoltageMode = 0x%02x\n"
3026 " .SnapToDiscrete = 0x%02x\n"
3027 " .NumDiscreteLevels = 0x%02x\n"
3028 " .padding = 0x%02x\n"
3029 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3030 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3031 " .SsFmin = 0x%04x\n"
3032 " .Padding_16 = 0x%04x\n",
3033 pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
3034 pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
3035 pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
3036 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
3037 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
3038 pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
3039 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
3040 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
3041 pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
3042 pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
3043 pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
3044
3045 dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
3046 " .VoltageMode = 0x%02x\n"
3047 " .SnapToDiscrete = 0x%02x\n"
3048 " .NumDiscreteLevels = 0x%02x\n"
3049 " .padding = 0x%02x\n"
3050 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3051 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3052 " .SsFmin = 0x%04x\n"
3053 " .Padding_16 = 0x%04x\n",
3054 pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
3055 pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
3056 pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
3057 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
3058 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
3059 pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
3060 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
3061 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
3062 pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
3063 pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
3064 pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
3065
3066 dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
3067 " .VoltageMode = 0x%02x\n"
3068 " .SnapToDiscrete = 0x%02x\n"
3069 " .NumDiscreteLevels = 0x%02x\n"
3070 " .padding = 0x%02x\n"
3071 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3072 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3073 " .SsFmin = 0x%04x\n"
3074 " .Padding_16 = 0x%04x\n",
3075 pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
3076 pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
3077 pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
3078 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
3079 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
3080 pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
3081 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
3082 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
3083 pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
3084 pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
3085 pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
3086
3087 dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
3088 " .VoltageMode = 0x%02x\n"
3089 " .SnapToDiscrete = 0x%02x\n"
3090 " .NumDiscreteLevels = 0x%02x\n"
3091 " .padding = 0x%02x\n"
3092 " .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3093 " .SsCurve {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3094 " .SsFmin = 0x%04x\n"
3095 " .Padding_16 = 0x%04x\n",
3096 pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
3097 pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
3098 pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
3099 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
3100 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
3101 pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
3102 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
3103 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
3104 pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
3105 pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
3106 pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
3107
3108 dev_info(smu->adev->dev, "FreqTableGfx\n");
3109 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
3110 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
3111
3112 dev_info(smu->adev->dev, "FreqTableVclk\n");
3113 for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
3114 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
3115
3116 dev_info(smu->adev->dev, "FreqTableDclk\n");
3117 for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
3118 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
3119
3120 dev_info(smu->adev->dev, "FreqTableSocclk\n");
3121 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
3122 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
3123
3124 dev_info(smu->adev->dev, "FreqTableUclk\n");
3125 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3126 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
3127
3128 dev_info(smu->adev->dev, "FreqTableFclk\n");
3129 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
3130 dev_info(smu->adev->dev, " .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
3131
3132 dev_info(smu->adev->dev, "DcModeMaxFreq\n");
3133 dev_info(smu->adev->dev, " .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
3134 dev_info(smu->adev->dev, " .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
3135 dev_info(smu->adev->dev, " .PPCLK_UCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
3136 dev_info(smu->adev->dev, " .PPCLK_FCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
3137 dev_info(smu->adev->dev, " .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
3138 dev_info(smu->adev->dev, " .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
3139 dev_info(smu->adev->dev, " .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
3140 dev_info(smu->adev->dev, " .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
3141
3142 dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
3143 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3144 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
3145
3146 dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
3147 dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
3148
3149 dev_info(smu->adev->dev, "Mp0clkFreq\n");
3150 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
3151 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
3152
3153 dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
3154 for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
3155 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
3156
3157 dev_info(smu->adev->dev, "MemVddciVoltage\n");
3158 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3159 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
3160
3161 dev_info(smu->adev->dev, "MemMvddVoltage\n");
3162 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3163 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
3164
3165 dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
3166 dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
3167 dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
3168 dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
3169 dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
3170
3171 dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
3172
3173 dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
3174 dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
3175 dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
3176 dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
3177 dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
3178 dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
3179 dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
3180 dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
3181 dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
3182 dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
3183 dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
3184
3185 dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
3186 dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
3187 dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
3188 dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
3189 dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
3190 dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
3191
3192 dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
3193 dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
3194 dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
3195 dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
3196 dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
3197
3198 dev_info(smu->adev->dev, "FlopsPerByteTable\n");
3199 for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
3200 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
3201
3202 dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
3203 dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
3204 dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
3205 dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
3206
3207 dev_info(smu->adev->dev, "UclkDpmPstates\n");
3208 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3209 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
3210
3211 dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
3212 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
3213 pptable->UclkDpmSrcFreqRange.Fmin);
3214 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
3215 pptable->UclkDpmSrcFreqRange.Fmax);
3216 dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
3217 dev_info(smu->adev->dev, " .Fmin = 0x%x\n",
3218 pptable->UclkDpmTargFreqRange.Fmin);
3219 dev_info(smu->adev->dev, " .Fmax = 0x%x\n",
3220 pptable->UclkDpmTargFreqRange.Fmax);
3221 dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
3222 dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
3223
3224 dev_info(smu->adev->dev, "PcieGenSpeed\n");
3225 for (i = 0; i < NUM_LINK_LEVELS; i++)
3226 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
3227
3228 dev_info(smu->adev->dev, "PcieLaneCount\n");
3229 for (i = 0; i < NUM_LINK_LEVELS; i++)
3230 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
3231
3232 dev_info(smu->adev->dev, "LclkFreq\n");
3233 for (i = 0; i < NUM_LINK_LEVELS; i++)
3234 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
3235
3236 dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
3237 dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
3238
3239 dev_info(smu->adev->dev, "FanGain\n");
3240 for (i = 0; i < TEMP_COUNT; i++)
3241 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->FanGain[i]);
3242
3243 dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
3244 dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
3245 dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
3246 dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
3247 dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
3248 dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
3249 dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
3250 dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
3251 dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
3252 dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
3253 dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
3254 dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
3255
3256 dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
3257 dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
3258 dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
3259 dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
3260
3261 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
3262 dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
3263 dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
3264 dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
3265
3266 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3267 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
3268 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
3269 pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
3270 dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3271 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
3272 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
3273 pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
3274 dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
3275 pptable->dBtcGbGfxPll.a,
3276 pptable->dBtcGbGfxPll.b,
3277 pptable->dBtcGbGfxPll.c);
3278 dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
3279 pptable->dBtcGbGfxDfll.a,
3280 pptable->dBtcGbGfxDfll.b,
3281 pptable->dBtcGbGfxDfll.c);
3282 dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
3283 pptable->dBtcGbSoc.a,
3284 pptable->dBtcGbSoc.b,
3285 pptable->dBtcGbSoc.c);
3286 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
3287 pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
3288 pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
3289 dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
3290 pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
3291 pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
3292
3293 dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
3294 for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
3295 dev_info(smu->adev->dev, " Fset[%d] = 0x%x\n",
3296 i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
3297 dev_info(smu->adev->dev, " Vdroop[%d] = 0x%x\n",
3298 i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
3299 }
3300
3301 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3302 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
3303 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
3304 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
3305 dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3306 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
3307 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
3308 pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
3309
3310 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
3311 dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
3312
3313 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
3314 dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
3315 dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
3316 dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
3317
3318 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
3319 dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
3320 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
3321 dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
3322
3323 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
3324 dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
3325
3326 dev_info(smu->adev->dev, "XgmiDpmPstates\n");
3327 for (i = 0; i < NUM_XGMI_LEVELS; i++)
3328 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
3329 dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
3330 dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
3331
3332 dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
3333 dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
3334 pptable->ReservedEquation0.a,
3335 pptable->ReservedEquation0.b,
3336 pptable->ReservedEquation0.c);
3337 dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
3338 pptable->ReservedEquation1.a,
3339 pptable->ReservedEquation1.b,
3340 pptable->ReservedEquation1.c);
3341 dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
3342 pptable->ReservedEquation2.a,
3343 pptable->ReservedEquation2.b,
3344 pptable->ReservedEquation2.c);
3345 dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
3346 pptable->ReservedEquation3.a,
3347 pptable->ReservedEquation3.b,
3348 pptable->ReservedEquation3.c);
3349
3350 dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
3351 dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
3352 dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
3353 dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
3354 dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
3355 dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
3356 dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
3357 dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
3358
3359 dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
3360 dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
3361 dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
3362 dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
3363 dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
3364 dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
3365
3366 for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
3367 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
3368 dev_info(smu->adev->dev, " .Enabled = 0x%x\n",
3369 pptable->I2cControllers[i].Enabled);
3370 dev_info(smu->adev->dev, " .Speed = 0x%x\n",
3371 pptable->I2cControllers[i].Speed);
3372 dev_info(smu->adev->dev, " .SlaveAddress = 0x%x\n",
3373 pptable->I2cControllers[i].SlaveAddress);
3374 dev_info(smu->adev->dev, " .ControllerPort = 0x%x\n",
3375 pptable->I2cControllers[i].ControllerPort);
3376 dev_info(smu->adev->dev, " .ControllerName = 0x%x\n",
3377 pptable->I2cControllers[i].ControllerName);
3378 dev_info(smu->adev->dev, " .ThermalThrottler = 0x%x\n",
3379 pptable->I2cControllers[i].ThermalThrotter);
3380 dev_info(smu->adev->dev, " .I2cProtocol = 0x%x\n",
3381 pptable->I2cControllers[i].I2cProtocol);
3382 dev_info(smu->adev->dev, " .PaddingConfig = 0x%x\n",
3383 pptable->I2cControllers[i].PaddingConfig);
3384 }
3385
3386 dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3387 dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3388 dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3389 dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3390
3391 dev_info(smu->adev->dev, "Board Parameters:\n");
3392 dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3393 dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3394 dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3395 dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3396 dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3397 dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3398 dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3399 dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3400
3401 dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3402 dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3403 dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3404
3405 dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3406 dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3407 dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3408
3409 dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3410 dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3411 dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3412
3413 dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3414 dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3415 dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3416
3417 dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3418
3419 dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3420 dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3421 dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3422 dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3423 dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3424 dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3425 dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3426 dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3427 dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3428 dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3429 dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3430 dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3431 dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3432 dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3433 dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3434 dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3435
3436 dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3437 dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3438 dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n", pptable->PllGfxclkSpreadFreq);
3439
3440 dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3441 dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3442 dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
3443
3444 dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
3445 dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3446
3447 dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3448 dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3449 dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3450
3451 dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3452 dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3453 dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3454 dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3455 dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3456
3457 dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3458 dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3459
3460 dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3461 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3462 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3463 dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3464 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3465 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3466 dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3467 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3468 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3469 dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3470 for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3471 dev_info(smu->adev->dev, " .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3472
3473 dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3474 dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3475 dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3476 dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3477
3478 dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3479 dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3480 dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3481 dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3482 dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3483 dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3484 dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3485 dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3486 dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3487 dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3488 dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3489
3490 dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3491 dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3492 dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3493 dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3494 dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3495 dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3496 dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3497 dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3498 }
3499
sienna_cichlid_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msg,int num_msgs)3500 static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
3501 struct i2c_msg *msg, int num_msgs)
3502 {
3503 struct amdgpu_device *adev = to_amdgpu_device(i2c_adap);
3504 struct smu_table_context *smu_table = &adev->smu.smu_table;
3505 struct smu_table *table = &smu_table->driver_table;
3506 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
3507 int i, j, r, c;
3508 u16 dir;
3509
3510 req = kzalloc(sizeof(*req), GFP_KERNEL);
3511 if (!req)
3512 return -ENOMEM;
3513
3514 req->I2CcontrollerPort = 1;
3515 req->I2CSpeed = I2C_SPEED_FAST_400K;
3516 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
3517 dir = msg[0].flags & I2C_M_RD;
3518
3519 for (c = i = 0; i < num_msgs; i++) {
3520 for (j = 0; j < msg[i].len; j++, c++) {
3521 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
3522
3523 if (!(msg[i].flags & I2C_M_RD)) {
3524 /* write */
3525 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
3526 cmd->ReadWriteData = msg[i].buf[j];
3527 }
3528
3529 if ((dir ^ msg[i].flags) & I2C_M_RD) {
3530 /* The direction changes.
3531 */
3532 dir = msg[i].flags & I2C_M_RD;
3533 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
3534 }
3535
3536 req->NumCmds++;
3537
3538 /*
3539 * Insert STOP if we are at the last byte of either last
3540 * message for the transaction or the client explicitly
3541 * requires a STOP at this particular message.
3542 */
3543 if ((j == msg[i].len - 1) &&
3544 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
3545 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
3546 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
3547 }
3548 }
3549 }
3550 mutex_lock(&adev->smu.mutex);
3551 r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
3552 mutex_unlock(&adev->smu.mutex);
3553 if (r)
3554 goto fail;
3555
3556 for (c = i = 0; i < num_msgs; i++) {
3557 if (!(msg[i].flags & I2C_M_RD)) {
3558 c += msg[i].len;
3559 continue;
3560 }
3561 for (j = 0; j < msg[i].len; j++, c++) {
3562 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
3563
3564 msg[i].buf[j] = cmd->ReadWriteData;
3565 }
3566 }
3567 r = num_msgs;
3568 fail:
3569 kfree(req);
3570 return r;
3571 }
3572
sienna_cichlid_i2c_func(struct i2c_adapter * adap)3573 static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
3574 {
3575 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3576 }
3577
3578
3579 static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
3580 .master_xfer = sienna_cichlid_i2c_xfer,
3581 .functionality = sienna_cichlid_i2c_func,
3582 };
3583
3584 static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = {
3585 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
3586 .max_read_len = MAX_SW_I2C_COMMANDS,
3587 .max_write_len = MAX_SW_I2C_COMMANDS,
3588 .max_comb_1st_msg_len = 2,
3589 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
3590 };
3591
sienna_cichlid_i2c_control_init(struct smu_context * smu,struct i2c_adapter * control)3592 static int sienna_cichlid_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
3593 {
3594 struct amdgpu_device *adev = to_amdgpu_device(control);
3595 int res;
3596
3597 control->owner = THIS_MODULE;
3598 control->class = I2C_CLASS_HWMON;
3599 control->dev.parent = &adev->pdev->dev;
3600 control->algo = &sienna_cichlid_i2c_algo;
3601 snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
3602 control->quirks = &sienna_cichlid_i2c_control_quirks;
3603
3604 res = i2c_add_adapter(control);
3605 if (res)
3606 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
3607
3608 return res;
3609 }
3610
sienna_cichlid_i2c_control_fini(struct smu_context * smu,struct i2c_adapter * control)3611 static void sienna_cichlid_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
3612 {
3613 i2c_del_adapter(control);
3614 }
3615
sienna_cichlid_get_gpu_metrics(struct smu_context * smu,void ** table)3616 static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
3617 void **table)
3618 {
3619 struct smu_table_context *smu_table = &smu->smu_table;
3620 struct gpu_metrics_v1_3 *gpu_metrics =
3621 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
3622 SmuMetricsExternal_t metrics_external;
3623 SmuMetrics_t *metrics =
3624 &(metrics_external.SmuMetrics);
3625 SmuMetrics_V2_t *metrics_v2 =
3626 &(metrics_external.SmuMetrics_V2);
3627 struct amdgpu_device *adev = smu->adev;
3628 bool use_metrics_v2 = ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
3629 (smu->smc_fw_version >= 0x3A4300)) ? true : false;
3630 uint16_t average_gfx_activity;
3631 int ret = 0;
3632
3633 mutex_lock(&smu->metrics_lock);
3634 ret = smu_cmn_get_metrics_table_locked(smu,
3635 &metrics_external,
3636 true);
3637 if (ret) {
3638 mutex_unlock(&smu->metrics_lock);
3639 return ret;
3640 }
3641
3642 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3643
3644 gpu_metrics->temperature_edge =
3645 use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge;
3646 gpu_metrics->temperature_hotspot =
3647 use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot;
3648 gpu_metrics->temperature_mem =
3649 use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem;
3650 gpu_metrics->temperature_vrgfx =
3651 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx;
3652 gpu_metrics->temperature_vrsoc =
3653 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc;
3654 gpu_metrics->temperature_vrmem =
3655 use_metrics_v2 ? metrics_v2->TemperatureVrMem0 : metrics->TemperatureVrMem0;
3656
3657 gpu_metrics->average_gfx_activity =
3658 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3659 gpu_metrics->average_umc_activity =
3660 use_metrics_v2 ? metrics_v2->AverageUclkActivity : metrics->AverageUclkActivity;
3661 gpu_metrics->average_mm_activity =
3662 use_metrics_v2 ? metrics_v2->VcnActivityPercentage : metrics->VcnActivityPercentage;
3663
3664 gpu_metrics->average_socket_power =
3665 use_metrics_v2 ? metrics_v2->AverageSocketPower : metrics->AverageSocketPower;
3666 gpu_metrics->energy_accumulator =
3667 use_metrics_v2 ? metrics_v2->EnergyAccumulator : metrics->EnergyAccumulator;
3668
3669 average_gfx_activity = use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3670 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
3671 gpu_metrics->average_gfxclk_frequency =
3672 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs : metrics->AverageGfxclkFrequencyPostDs;
3673 else
3674 gpu_metrics->average_gfxclk_frequency =
3675 use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs : metrics->AverageGfxclkFrequencyPreDs;
3676 gpu_metrics->average_uclk_frequency =
3677 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs : metrics->AverageUclkFrequencyPostDs;
3678 gpu_metrics->average_vclk0_frequency =
3679 use_metrics_v2 ? metrics_v2->AverageVclk0Frequency : metrics->AverageVclk0Frequency;
3680 gpu_metrics->average_dclk0_frequency =
3681 use_metrics_v2 ? metrics_v2->AverageDclk0Frequency : metrics->AverageDclk0Frequency;
3682 gpu_metrics->average_vclk1_frequency =
3683 use_metrics_v2 ? metrics_v2->AverageVclk1Frequency : metrics->AverageVclk1Frequency;
3684 gpu_metrics->average_dclk1_frequency =
3685 use_metrics_v2 ? metrics_v2->AverageDclk1Frequency : metrics->AverageDclk1Frequency;
3686
3687 gpu_metrics->current_gfxclk =
3688 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : metrics->CurrClock[PPCLK_GFXCLK];
3689 gpu_metrics->current_socclk =
3690 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : metrics->CurrClock[PPCLK_SOCCLK];
3691 gpu_metrics->current_uclk =
3692 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK];
3693 gpu_metrics->current_vclk0 =
3694 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0];
3695 gpu_metrics->current_dclk0 =
3696 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : metrics->CurrClock[PPCLK_DCLK_0];
3697 gpu_metrics->current_vclk1 =
3698 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : metrics->CurrClock[PPCLK_VCLK_1];
3699 gpu_metrics->current_dclk1 =
3700 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1];
3701
3702 gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu);
3703 gpu_metrics->indep_throttle_status =
3704 smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
3705 sienna_cichlid_throttler_map);
3706
3707 gpu_metrics->current_fan_speed = use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
3708
3709 if (((adev->asic_type == CHIP_SIENNA_CICHLID) && smu->smc_fw_version > 0x003A1E00) ||
3710 ((adev->asic_type == CHIP_NAVY_FLOUNDER) && smu->smc_fw_version > 0x00410400)) {
3711 gpu_metrics->pcie_link_width = use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth;
3712 gpu_metrics->pcie_link_speed = link_speed[use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate];
3713 } else {
3714 gpu_metrics->pcie_link_width =
3715 smu_v11_0_get_current_pcie_link_width(smu);
3716 gpu_metrics->pcie_link_speed =
3717 smu_v11_0_get_current_pcie_link_speed(smu);
3718 }
3719
3720 mutex_unlock(&smu->metrics_lock);
3721
3722 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3723
3724 *table = (void *)gpu_metrics;
3725
3726 return sizeof(struct gpu_metrics_v1_3);
3727 }
3728
sienna_cichlid_enable_mgpu_fan_boost(struct smu_context * smu)3729 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
3730 {
3731 struct smu_table_context *table_context = &smu->smu_table;
3732 PPTable_t *smc_pptable = table_context->driver_pptable;
3733
3734 /*
3735 * Skip the MGpuFanBoost setting for those ASICs
3736 * which do not support it
3737 */
3738 if (!smc_pptable->MGpuFanBoostLimitRpm)
3739 return 0;
3740
3741 return smu_cmn_send_smc_msg_with_param(smu,
3742 SMU_MSG_SetMGpuFanBoostLimitRpm,
3743 0,
3744 NULL);
3745 }
3746
sienna_cichlid_gpo_control(struct smu_context * smu,bool enablement)3747 static int sienna_cichlid_gpo_control(struct smu_context *smu,
3748 bool enablement)
3749 {
3750 uint32_t smu_version;
3751 int ret = 0;
3752
3753
3754 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
3755 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
3756 if (ret)
3757 return ret;
3758
3759 if (enablement) {
3760 if (smu_version < 0x003a2500) {
3761 ret = smu_cmn_send_smc_msg_with_param(smu,
3762 SMU_MSG_SetGpoFeaturePMask,
3763 GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
3764 NULL);
3765 } else {
3766 ret = smu_cmn_send_smc_msg_with_param(smu,
3767 SMU_MSG_DisallowGpo,
3768 0,
3769 NULL);
3770 }
3771 } else {
3772 if (smu_version < 0x003a2500) {
3773 ret = smu_cmn_send_smc_msg_with_param(smu,
3774 SMU_MSG_SetGpoFeaturePMask,
3775 0,
3776 NULL);
3777 } else {
3778 ret = smu_cmn_send_smc_msg_with_param(smu,
3779 SMU_MSG_DisallowGpo,
3780 1,
3781 NULL);
3782 }
3783 }
3784 }
3785
3786 return ret;
3787 }
3788
sienna_cichlid_notify_2nd_usb20_port(struct smu_context * smu)3789 static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)
3790 {
3791 uint32_t smu_version;
3792 int ret = 0;
3793
3794 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
3795 if (ret)
3796 return ret;
3797
3798 /*
3799 * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
3800 * onwards PMFWs.
3801 */
3802 if (smu_version < 0x003A2D00)
3803 return 0;
3804
3805 return smu_cmn_send_smc_msg_with_param(smu,
3806 SMU_MSG_Enable2ndUSB20Port,
3807 smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
3808 1 : 0,
3809 NULL);
3810 }
3811
sienna_cichlid_system_features_control(struct smu_context * smu,bool en)3812 static int sienna_cichlid_system_features_control(struct smu_context *smu,
3813 bool en)
3814 {
3815 int ret = 0;
3816
3817 if (en) {
3818 ret = sienna_cichlid_notify_2nd_usb20_port(smu);
3819 if (ret)
3820 return ret;
3821 }
3822
3823 return smu_v11_0_system_features_control(smu, en);
3824 }
3825
sienna_cichlid_set_mp1_state(struct smu_context * smu,enum pp_mp1_state mp1_state)3826 static int sienna_cichlid_set_mp1_state(struct smu_context *smu,
3827 enum pp_mp1_state mp1_state)
3828 {
3829 int ret;
3830
3831 switch (mp1_state) {
3832 case PP_MP1_STATE_UNLOAD:
3833 ret = smu_cmn_set_mp1_state(smu, mp1_state);
3834 break;
3835 default:
3836 /* Ignore others */
3837 ret = 0;
3838 }
3839
3840 return ret;
3841 }
3842
3843 static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
3844 .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
3845 .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
3846 .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
3847 .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
3848 .i2c_init = sienna_cichlid_i2c_control_init,
3849 .i2c_fini = sienna_cichlid_i2c_control_fini,
3850 .print_clk_levels = sienna_cichlid_print_clk_levels,
3851 .force_clk_levels = sienna_cichlid_force_clk_levels,
3852 .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
3853 .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
3854 .display_config_changed = sienna_cichlid_display_config_changed,
3855 .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
3856 .is_dpm_running = sienna_cichlid_is_dpm_running,
3857 .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm,
3858 .get_fan_speed_rpm = sienna_cichlid_get_fan_speed_rpm,
3859 .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
3860 .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
3861 .set_watermarks_table = sienna_cichlid_set_watermarks_table,
3862 .read_sensor = sienna_cichlid_read_sensor,
3863 .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
3864 .set_performance_level = smu_v11_0_set_performance_level,
3865 .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
3866 .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
3867 .get_power_limit = sienna_cichlid_get_power_limit,
3868 .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
3869 .dump_pptable = sienna_cichlid_dump_pptable,
3870 .init_microcode = smu_v11_0_init_microcode,
3871 .load_microcode = smu_v11_0_load_microcode,
3872 .init_smc_tables = sienna_cichlid_init_smc_tables,
3873 .fini_smc_tables = smu_v11_0_fini_smc_tables,
3874 .init_power = smu_v11_0_init_power,
3875 .fini_power = smu_v11_0_fini_power,
3876 .check_fw_status = smu_v11_0_check_fw_status,
3877 .setup_pptable = sienna_cichlid_setup_pptable,
3878 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
3879 .check_fw_version = smu_v11_0_check_fw_version,
3880 .write_pptable = smu_cmn_write_pptable,
3881 .set_driver_table_location = smu_v11_0_set_driver_table_location,
3882 .set_tool_table_location = smu_v11_0_set_tool_table_location,
3883 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
3884 .system_features_control = sienna_cichlid_system_features_control,
3885 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
3886 .send_smc_msg = smu_cmn_send_smc_msg,
3887 .init_display_count = NULL,
3888 .set_allowed_mask = smu_v11_0_set_allowed_mask,
3889 .get_enabled_mask = smu_cmn_get_enabled_mask,
3890 .feature_is_enabled = smu_cmn_feature_is_enabled,
3891 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
3892 .notify_display_change = NULL,
3893 .set_power_limit = smu_v11_0_set_power_limit,
3894 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
3895 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
3896 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
3897 .set_min_dcef_deep_sleep = NULL,
3898 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
3899 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
3900 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
3901 .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm,
3902 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
3903 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
3904 .gfx_off_control = smu_v11_0_gfx_off_control,
3905 .register_irq_handler = smu_v11_0_register_irq_handler,
3906 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
3907 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
3908 .baco_is_support = smu_v11_0_baco_is_support,
3909 .baco_get_state = smu_v11_0_baco_get_state,
3910 .baco_set_state = smu_v11_0_baco_set_state,
3911 .baco_enter = sienna_cichlid_baco_enter,
3912 .baco_exit = sienna_cichlid_baco_exit,
3913 .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
3914 .mode1_reset = smu_v11_0_mode1_reset,
3915 .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
3916 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
3917 .set_default_od_settings = sienna_cichlid_set_default_od_settings,
3918 .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table,
3919 .restore_user_od_settings = smu_v11_0_restore_user_od_settings,
3920 .run_btc = sienna_cichlid_run_btc,
3921 .set_power_source = smu_v11_0_set_power_source,
3922 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3923 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
3924 .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
3925 .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
3926 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
3927 .deep_sleep_control = smu_v11_0_deep_sleep_control,
3928 .get_fan_parameters = sienna_cichlid_get_fan_parameters,
3929 .interrupt_work = smu_v11_0_interrupt_work,
3930 .gpo_control = sienna_cichlid_gpo_control,
3931 .set_mp1_state = sienna_cichlid_set_mp1_state,
3932 };
3933
sienna_cichlid_set_ppt_funcs(struct smu_context * smu)3934 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
3935 {
3936 smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
3937 smu->message_map = sienna_cichlid_message_map;
3938 smu->clock_map = sienna_cichlid_clk_map;
3939 smu->feature_map = sienna_cichlid_feature_mask_map;
3940 smu->table_map = sienna_cichlid_table_map;
3941 smu->pwr_src_map = sienna_cichlid_pwr_src_map;
3942 smu->workload_map = sienna_cichlid_workload_map;
3943 }
3944
