1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26 #ifndef __AMDGPU_GMC_H__
27 #define __AMDGPU_GMC_H__
28
29 #include <linux/types.h>
30
31 #include "amdgpu_irq.h"
32
33 /* VA hole for 48bit addresses on Vega10 */
34 #define AMDGPU_GMC_HOLE_START 0x0000800000000000ULL
35 #define AMDGPU_GMC_HOLE_END 0xffff800000000000ULL
36
37 /*
38 * Hardware is programmed as if the hole doesn't exists with start and end
39 * address values.
40 *
41 * This mask is used to remove the upper 16bits of the VA and so come up with
42 * the linear addr value.
43 */
44 #define AMDGPU_GMC_HOLE_MASK 0x0000ffffffffffffULL
45
46 /*
47 * Ring size as power of two for the log of recent faults.
48 */
49 #define AMDGPU_GMC_FAULT_RING_ORDER 8
50 #define AMDGPU_GMC_FAULT_RING_SIZE (1 << AMDGPU_GMC_FAULT_RING_ORDER)
51
52 /*
53 * Hash size as power of two for the log of recent faults
54 */
55 #define AMDGPU_GMC_FAULT_HASH_ORDER 8
56 #define AMDGPU_GMC_FAULT_HASH_SIZE (1 << AMDGPU_GMC_FAULT_HASH_ORDER)
57
58 /*
59 * Number of IH timestamp ticks until a fault is considered handled
60 */
61 #define AMDGPU_GMC_FAULT_TIMEOUT 5000ULL
62
63 struct firmware;
64
65 /*
66 * GMC page fault information
67 */
68 struct amdgpu_gmc_fault {
69 uint64_t timestamp;
70 uint64_t next:AMDGPU_GMC_FAULT_RING_ORDER;
71 uint64_t key:52;
72 };
73
74 /*
75 * VMHUB structures, functions & helpers
76 */
77 struct amdgpu_vmhub {
78 uint32_t ctx0_ptb_addr_lo32;
79 uint32_t ctx0_ptb_addr_hi32;
80 uint32_t vm_inv_eng0_req;
81 uint32_t vm_inv_eng0_ack;
82 uint32_t vm_context0_cntl;
83 uint32_t vm_l2_pro_fault_status;
84 uint32_t vm_l2_pro_fault_cntl;
85 };
86
87 /*
88 * GPU MC structures, functions & helpers
89 */
90 struct amdgpu_gmc_funcs {
91 /* flush the vm tlb via mmio */
92 void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid,
93 uint32_t vmhub, uint32_t flush_type);
94 /* flush the vm tlb via ring */
95 uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
96 uint64_t pd_addr);
97 /* Change the VMID -> PASID mapping */
98 void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid,
99 unsigned pasid);
100 /* enable/disable PRT support */
101 void (*set_prt)(struct amdgpu_device *adev, bool enable);
102 /* set pte flags based per asic */
103 uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
104 uint32_t flags);
105 /* get the pde for a given mc addr */
106 void (*get_vm_pde)(struct amdgpu_device *adev, int level,
107 u64 *dst, u64 *flags);
108 };
109
110 struct amdgpu_xgmi {
111 /* from psp */
112 u64 node_id;
113 u64 hive_id;
114 /* fixed per family */
115 u64 node_segment_size;
116 /* physical node (0-3) */
117 unsigned physical_node_id;
118 /* number of nodes (0-4) */
119 unsigned num_physical_nodes;
120 /* gpu list in the same hive */
121 struct list_head head;
122 bool supported;
123 };
124
125 struct amdgpu_gmc {
126 resource_size_t aper_size;
127 resource_size_t aper_base;
128 /* for some chips with <= 32MB we need to lie
129 * about vram size near mc fb location */
130 u64 mc_vram_size;
131 u64 visible_vram_size;
132 u64 agp_size;
133 u64 agp_start;
134 u64 agp_end;
135 u64 gart_size;
136 u64 gart_start;
137 u64 gart_end;
138 u64 vram_start;
139 u64 vram_end;
140 /* FB region , it's same as local vram region in single GPU, in XGMI
141 * configuration, this region covers all GPUs in the same hive ,
142 * each GPU in the hive has the same view of this FB region .
143 * GPU0's vram starts at offset (0 * segment size) ,
144 * GPU1 starts at offset (1 * segment size), etc.
145 */
146 u64 fb_start;
147 u64 fb_end;
148 unsigned vram_width;
149 u64 real_vram_size;
150 int vram_mtrr;
151 u64 mc_mask;
152 const struct firmware *fw; /* MC firmware */
153 uint32_t fw_version;
154 struct amdgpu_irq_src vm_fault;
155 uint32_t vram_type;
156 uint32_t srbm_soft_reset;
157 bool prt_warning;
158 uint64_t stolen_size;
159 /* apertures */
160 u64 shared_aperture_start;
161 u64 shared_aperture_end;
162 u64 private_aperture_start;
163 u64 private_aperture_end;
164 /* protects concurrent invalidation */
165 spinlock_t invalidate_lock;
166 bool translate_further;
167 struct kfd_vm_fault_info *vm_fault_info;
168 atomic_t vm_fault_info_updated;
169
170 struct amdgpu_gmc_fault fault_ring[AMDGPU_GMC_FAULT_RING_SIZE];
171 struct {
172 uint64_t idx:AMDGPU_GMC_FAULT_RING_ORDER;
173 } fault_hash[AMDGPU_GMC_FAULT_HASH_SIZE];
174 uint64_t last_fault:AMDGPU_GMC_FAULT_RING_ORDER;
175
176 const struct amdgpu_gmc_funcs *gmc_funcs;
177
178 struct amdgpu_xgmi xgmi;
179 struct amdgpu_irq_src ecc_irq;
180 struct ras_common_if *umc_ras_if;
181 struct ras_common_if *mmhub_ras_if;
182 };
183
184 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))
185 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
186 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
187 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))
188 #define amdgpu_gmc_get_pte_flags(adev, flags) (adev)->gmc.gmc_funcs->get_vm_pte_flags((adev),(flags))
189
190 /**
191 * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR
192 *
193 * @adev: amdgpu_device pointer
194 *
195 * Returns:
196 * True if full VRAM is visible through the BAR
197 */
amdgpu_gmc_vram_full_visible(struct amdgpu_gmc * gmc)198 static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc)
199 {
200 WARN_ON(gmc->real_vram_size < gmc->visible_vram_size);
201
202 return (gmc->real_vram_size == gmc->visible_vram_size);
203 }
204
205 /**
206 * amdgpu_gmc_sign_extend - sign extend the given gmc address
207 *
208 * @addr: address to extend
209 */
amdgpu_gmc_sign_extend(uint64_t addr)210 static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr)
211 {
212 if (addr >= AMDGPU_GMC_HOLE_START)
213 addr |= AMDGPU_GMC_HOLE_END;
214
215 return addr;
216 }
217
218 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
219 uint64_t *addr, uint64_t *flags);
220 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
221 uint32_t gpu_page_idx, uint64_t addr,
222 uint64_t flags);
223 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
224 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo);
225 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
226 u64 base);
227 void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
228 struct amdgpu_gmc *mc);
229 void amdgpu_gmc_agp_location(struct amdgpu_device *adev,
230 struct amdgpu_gmc *mc);
231 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, uint64_t addr,
232 uint16_t pasid, uint64_t timestamp);
233
234 #endif
235
