1 /*
2 * Pin Control and GPIO driver for SuperH Pin Function Controller.
3 *
4 * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
5 *
6 * Copyright (C) 2008 Magnus Damm
7 * Copyright (C) 2009 - 2012 Paul Mundt
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13
14 #define DRV_NAME "sh-pfc"
15
16 #include <linux/bitops.h>
17 #include <linux/err.h>
18 #include <linux/errno.h>
19 #include <linux/io.h>
20 #include <linux/ioport.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/pinctrl/machine.h>
26 #include <linux/platform_device.h>
27 #include <linux/psci.h>
28 #include <linux/slab.h>
29
30 #include "core.h"
31
sh_pfc_map_resources(struct sh_pfc * pfc,struct platform_device * pdev)32 static int sh_pfc_map_resources(struct sh_pfc *pfc,
33 struct platform_device *pdev)
34 {
35 unsigned int num_windows, num_irqs;
36 struct sh_pfc_window *windows;
37 unsigned int *irqs = NULL;
38 struct resource *res;
39 unsigned int i;
40 int irq;
41
42 /* Count the MEM and IRQ resources. */
43 for (num_windows = 0;; num_windows++) {
44 res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows);
45 if (!res)
46 break;
47 }
48 for (num_irqs = 0;; num_irqs++) {
49 irq = platform_get_irq(pdev, num_irqs);
50 if (irq == -EPROBE_DEFER)
51 return irq;
52 if (irq < 0)
53 break;
54 }
55
56 if (num_windows == 0)
57 return -EINVAL;
58
59 /* Allocate memory windows and IRQs arrays. */
60 windows = devm_kcalloc(pfc->dev, num_windows, sizeof(*windows),
61 GFP_KERNEL);
62 if (windows == NULL)
63 return -ENOMEM;
64
65 pfc->num_windows = num_windows;
66 pfc->windows = windows;
67
68 if (num_irqs) {
69 irqs = devm_kcalloc(pfc->dev, num_irqs, sizeof(*irqs),
70 GFP_KERNEL);
71 if (irqs == NULL)
72 return -ENOMEM;
73
74 pfc->num_irqs = num_irqs;
75 pfc->irqs = irqs;
76 }
77
78 /* Fill them. */
79 for (i = 0; i < num_windows; i++) {
80 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
81 windows->phys = res->start;
82 windows->size = resource_size(res);
83 windows->virt = devm_ioremap_resource(pfc->dev, res);
84 if (IS_ERR(windows->virt))
85 return -ENOMEM;
86 windows++;
87 }
88 for (i = 0; i < num_irqs; i++)
89 *irqs++ = platform_get_irq(pdev, i);
90
91 return 0;
92 }
93
sh_pfc_phys_to_virt(struct sh_pfc * pfc,u32 reg)94 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg)
95 {
96 struct sh_pfc_window *window;
97 phys_addr_t address = reg;
98 unsigned int i;
99
100 /* scan through physical windows and convert address */
101 for (i = 0; i < pfc->num_windows; i++) {
102 window = pfc->windows + i;
103
104 if (address < window->phys)
105 continue;
106
107 if (address >= (window->phys + window->size))
108 continue;
109
110 return window->virt + (address - window->phys);
111 }
112
113 BUG();
114 return NULL;
115 }
116
sh_pfc_get_pin_index(struct sh_pfc * pfc,unsigned int pin)117 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
118 {
119 unsigned int offset;
120 unsigned int i;
121
122 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
123 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
124
125 if (pin <= range->end)
126 return pin >= range->start
127 ? offset + pin - range->start : -1;
128
129 offset += range->end - range->start + 1;
130 }
131
132 return -EINVAL;
133 }
134
sh_pfc_enum_in_range(u16 enum_id,const struct pinmux_range * r)135 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
136 {
137 if (enum_id < r->begin)
138 return 0;
139
140 if (enum_id > r->end)
141 return 0;
142
143 return 1;
144 }
145
sh_pfc_read_raw_reg(void __iomem * mapped_reg,unsigned int reg_width)146 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
147 {
148 switch (reg_width) {
149 case 8:
150 return ioread8(mapped_reg);
151 case 16:
152 return ioread16(mapped_reg);
153 case 32:
154 return ioread32(mapped_reg);
155 }
156
157 BUG();
158 return 0;
159 }
160
sh_pfc_write_raw_reg(void __iomem * mapped_reg,unsigned int reg_width,u32 data)161 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
162 u32 data)
163 {
164 switch (reg_width) {
165 case 8:
166 iowrite8(data, mapped_reg);
167 return;
168 case 16:
169 iowrite16(data, mapped_reg);
170 return;
171 case 32:
172 iowrite32(data, mapped_reg);
173 return;
174 }
175
176 BUG();
177 }
178
sh_pfc_read(struct sh_pfc * pfc,u32 reg)179 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
180 {
181 return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32);
182 }
183
sh_pfc_write(struct sh_pfc * pfc,u32 reg,u32 data)184 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
185 {
186 if (pfc->info->unlock_reg)
187 sh_pfc_write_raw_reg(
188 sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
189 ~data);
190
191 sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data);
192 }
193
sh_pfc_config_reg_helper(struct sh_pfc * pfc,const struct pinmux_cfg_reg * crp,unsigned int in_pos,void __iomem ** mapped_regp,u32 * maskp,unsigned int * posp)194 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
195 const struct pinmux_cfg_reg *crp,
196 unsigned int in_pos,
197 void __iomem **mapped_regp, u32 *maskp,
198 unsigned int *posp)
199 {
200 unsigned int k;
201
202 *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
203
204 if (crp->field_width) {
205 *maskp = (1 << crp->field_width) - 1;
206 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
207 } else {
208 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
209 *posp = crp->reg_width;
210 for (k = 0; k <= in_pos; k++)
211 *posp -= crp->var_field_width[k];
212 }
213 }
214
sh_pfc_write_config_reg(struct sh_pfc * pfc,const struct pinmux_cfg_reg * crp,unsigned int field,u32 value)215 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
216 const struct pinmux_cfg_reg *crp,
217 unsigned int field, u32 value)
218 {
219 void __iomem *mapped_reg;
220 unsigned int pos;
221 u32 mask, data;
222
223 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
224
225 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
226 "r_width = %u, f_width = %u\n",
227 crp->reg, value, field, crp->reg_width, crp->field_width);
228
229 mask = ~(mask << pos);
230 value = value << pos;
231
232 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
233 data &= mask;
234 data |= value;
235
236 if (pfc->info->unlock_reg)
237 sh_pfc_write_raw_reg(
238 sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
239 ~data);
240
241 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
242 }
243
sh_pfc_get_config_reg(struct sh_pfc * pfc,u16 enum_id,const struct pinmux_cfg_reg ** crp,unsigned int * fieldp,u32 * valuep)244 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
245 const struct pinmux_cfg_reg **crp,
246 unsigned int *fieldp, u32 *valuep)
247 {
248 unsigned int k = 0;
249
250 while (1) {
251 const struct pinmux_cfg_reg *config_reg =
252 pfc->info->cfg_regs + k;
253 unsigned int r_width = config_reg->reg_width;
254 unsigned int f_width = config_reg->field_width;
255 unsigned int curr_width;
256 unsigned int bit_pos;
257 unsigned int pos = 0;
258 unsigned int m = 0;
259
260 if (!r_width)
261 break;
262
263 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
264 u32 ncomb;
265 u32 n;
266
267 if (f_width)
268 curr_width = f_width;
269 else
270 curr_width = config_reg->var_field_width[m];
271
272 ncomb = 1 << curr_width;
273 for (n = 0; n < ncomb; n++) {
274 if (config_reg->enum_ids[pos + n] == enum_id) {
275 *crp = config_reg;
276 *fieldp = m;
277 *valuep = n;
278 return 0;
279 }
280 }
281 pos += ncomb;
282 m++;
283 }
284 k++;
285 }
286
287 return -EINVAL;
288 }
289
sh_pfc_mark_to_enum(struct sh_pfc * pfc,u16 mark,int pos,u16 * enum_idp)290 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
291 u16 *enum_idp)
292 {
293 const u16 *data = pfc->info->pinmux_data;
294 unsigned int k;
295
296 if (pos) {
297 *enum_idp = data[pos + 1];
298 return pos + 1;
299 }
300
301 for (k = 0; k < pfc->info->pinmux_data_size; k++) {
302 if (data[k] == mark) {
303 *enum_idp = data[k + 1];
304 return k + 1;
305 }
306 }
307
308 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
309 mark);
310 return -EINVAL;
311 }
312
sh_pfc_config_mux(struct sh_pfc * pfc,unsigned mark,int pinmux_type)313 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
314 {
315 const struct pinmux_range *range;
316 int pos = 0;
317
318 switch (pinmux_type) {
319 case PINMUX_TYPE_GPIO:
320 case PINMUX_TYPE_FUNCTION:
321 range = NULL;
322 break;
323
324 case PINMUX_TYPE_OUTPUT:
325 range = &pfc->info->output;
326 break;
327
328 case PINMUX_TYPE_INPUT:
329 range = &pfc->info->input;
330 break;
331
332 default:
333 return -EINVAL;
334 }
335
336 /* Iterate over all the configuration fields we need to update. */
337 while (1) {
338 const struct pinmux_cfg_reg *cr;
339 unsigned int field;
340 u16 enum_id;
341 u32 value;
342 int in_range;
343 int ret;
344
345 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
346 if (pos < 0)
347 return pos;
348
349 if (!enum_id)
350 break;
351
352 /* Check if the configuration field selects a function. If it
353 * doesn't, skip the field if it's not applicable to the
354 * requested pinmux type.
355 */
356 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
357 if (!in_range) {
358 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
359 /* Functions are allowed to modify all
360 * fields.
361 */
362 in_range = 1;
363 } else if (pinmux_type != PINMUX_TYPE_GPIO) {
364 /* Input/output types can only modify fields
365 * that correspond to their respective ranges.
366 */
367 in_range = sh_pfc_enum_in_range(enum_id, range);
368
369 /*
370 * special case pass through for fixed
371 * input-only or output-only pins without
372 * function enum register association.
373 */
374 if (in_range && enum_id == range->force)
375 continue;
376 }
377 /* GPIOs are only allowed to modify function fields. */
378 }
379
380 if (!in_range)
381 continue;
382
383 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
384 if (ret < 0)
385 return ret;
386
387 sh_pfc_write_config_reg(pfc, cr, field, value);
388 }
389
390 return 0;
391 }
392
393 const struct pinmux_bias_reg *
sh_pfc_pin_to_bias_reg(const struct sh_pfc * pfc,unsigned int pin,unsigned int * bit)394 sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
395 unsigned int *bit)
396 {
397 unsigned int i, j;
398
399 for (i = 0; pfc->info->bias_regs[i].puen; i++) {
400 for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
401 if (pfc->info->bias_regs[i].pins[j] == pin) {
402 *bit = j;
403 return &pfc->info->bias_regs[i];
404 }
405 }
406 }
407
408 WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
409
410 return NULL;
411 }
412
sh_pfc_init_ranges(struct sh_pfc * pfc)413 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
414 {
415 struct sh_pfc_pin_range *range;
416 unsigned int nr_ranges;
417 unsigned int i;
418
419 if (pfc->info->pins[0].pin == (u16)-1) {
420 /* Pin number -1 denotes that the SoC doesn't report pin numbers
421 * in its pin arrays yet. Consider the pin numbers range as
422 * continuous and allocate a single range.
423 */
424 pfc->nr_ranges = 1;
425 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
426 GFP_KERNEL);
427 if (pfc->ranges == NULL)
428 return -ENOMEM;
429
430 pfc->ranges->start = 0;
431 pfc->ranges->end = pfc->info->nr_pins - 1;
432 pfc->nr_gpio_pins = pfc->info->nr_pins;
433
434 return 0;
435 }
436
437 /* Count, allocate and fill the ranges. The PFC SoC data pins array must
438 * be sorted by pin numbers, and pins without a GPIO port must come
439 * last.
440 */
441 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
442 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
443 nr_ranges++;
444 }
445
446 pfc->nr_ranges = nr_ranges;
447 pfc->ranges = devm_kcalloc(pfc->dev, nr_ranges, sizeof(*pfc->ranges),
448 GFP_KERNEL);
449 if (pfc->ranges == NULL)
450 return -ENOMEM;
451
452 range = pfc->ranges;
453 range->start = pfc->info->pins[0].pin;
454
455 for (i = 1; i < pfc->info->nr_pins; ++i) {
456 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
457 continue;
458
459 range->end = pfc->info->pins[i-1].pin;
460 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
461 pfc->nr_gpio_pins = range->end + 1;
462
463 range++;
464 range->start = pfc->info->pins[i].pin;
465 }
466
467 range->end = pfc->info->pins[i-1].pin;
468 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
469 pfc->nr_gpio_pins = range->end + 1;
470
471 return 0;
472 }
473
474 #ifdef CONFIG_OF
475 static const struct of_device_id sh_pfc_of_table[] = {
476 #ifdef CONFIG_PINCTRL_PFC_EMEV2
477 {
478 .compatible = "renesas,pfc-emev2",
479 .data = &emev2_pinmux_info,
480 },
481 #endif
482 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
483 {
484 .compatible = "renesas,pfc-r8a73a4",
485 .data = &r8a73a4_pinmux_info,
486 },
487 #endif
488 #ifdef CONFIG_PINCTRL_PFC_R8A7740
489 {
490 .compatible = "renesas,pfc-r8a7740",
491 .data = &r8a7740_pinmux_info,
492 },
493 #endif
494 #ifdef CONFIG_PINCTRL_PFC_R8A7743
495 {
496 .compatible = "renesas,pfc-r8a7743",
497 .data = &r8a7743_pinmux_info,
498 },
499 #endif
500 #ifdef CONFIG_PINCTRL_PFC_R8A7745
501 {
502 .compatible = "renesas,pfc-r8a7745",
503 .data = &r8a7745_pinmux_info,
504 },
505 #endif
506 #ifdef CONFIG_PINCTRL_PFC_R8A77470
507 {
508 .compatible = "renesas,pfc-r8a77470",
509 .data = &r8a77470_pinmux_info,
510 },
511 #endif
512 #ifdef CONFIG_PINCTRL_PFC_R8A7778
513 {
514 .compatible = "renesas,pfc-r8a7778",
515 .data = &r8a7778_pinmux_info,
516 },
517 #endif
518 #ifdef CONFIG_PINCTRL_PFC_R8A7779
519 {
520 .compatible = "renesas,pfc-r8a7779",
521 .data = &r8a7779_pinmux_info,
522 },
523 #endif
524 #ifdef CONFIG_PINCTRL_PFC_R8A7790
525 {
526 .compatible = "renesas,pfc-r8a7790",
527 .data = &r8a7790_pinmux_info,
528 },
529 #endif
530 #ifdef CONFIG_PINCTRL_PFC_R8A7791
531 {
532 .compatible = "renesas,pfc-r8a7791",
533 .data = &r8a7791_pinmux_info,
534 },
535 #endif
536 #ifdef CONFIG_PINCTRL_PFC_R8A7792
537 {
538 .compatible = "renesas,pfc-r8a7792",
539 .data = &r8a7792_pinmux_info,
540 },
541 #endif
542 #ifdef CONFIG_PINCTRL_PFC_R8A7793
543 {
544 .compatible = "renesas,pfc-r8a7793",
545 .data = &r8a7793_pinmux_info,
546 },
547 #endif
548 #ifdef CONFIG_PINCTRL_PFC_R8A7794
549 {
550 .compatible = "renesas,pfc-r8a7794",
551 .data = &r8a7794_pinmux_info,
552 },
553 #endif
554 #ifdef CONFIG_PINCTRL_PFC_R8A7795
555 {
556 .compatible = "renesas,pfc-r8a7795",
557 .data = &r8a7795_pinmux_info,
558 },
559 #endif
560 #ifdef CONFIG_PINCTRL_PFC_R8A7796
561 {
562 .compatible = "renesas,pfc-r8a7796",
563 .data = &r8a7796_pinmux_info,
564 },
565 #endif
566 #ifdef CONFIG_PINCTRL_PFC_R8A77965
567 {
568 .compatible = "renesas,pfc-r8a77965",
569 .data = &r8a77965_pinmux_info,
570 },
571 #endif
572 #ifdef CONFIG_PINCTRL_PFC_R8A77970
573 {
574 .compatible = "renesas,pfc-r8a77970",
575 .data = &r8a77970_pinmux_info,
576 },
577 #endif
578 #ifdef CONFIG_PINCTRL_PFC_R8A77980
579 {
580 .compatible = "renesas,pfc-r8a77980",
581 .data = &r8a77980_pinmux_info,
582 },
583 #endif
584 #ifdef CONFIG_PINCTRL_PFC_R8A77990
585 {
586 .compatible = "renesas,pfc-r8a77990",
587 .data = &r8a77990_pinmux_info,
588 },
589 #endif
590 #ifdef CONFIG_PINCTRL_PFC_R8A77995
591 {
592 .compatible = "renesas,pfc-r8a77995",
593 .data = &r8a77995_pinmux_info,
594 },
595 #endif
596 #ifdef CONFIG_PINCTRL_PFC_SH73A0
597 {
598 .compatible = "renesas,pfc-sh73a0",
599 .data = &sh73a0_pinmux_info,
600 },
601 #endif
602 { },
603 };
604 #endif
605
606 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
sh_pfc_nop_reg(struct sh_pfc * pfc,u32 reg,unsigned int idx)607 static void sh_pfc_nop_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
608 {
609 }
610
sh_pfc_save_reg(struct sh_pfc * pfc,u32 reg,unsigned int idx)611 static void sh_pfc_save_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
612 {
613 pfc->saved_regs[idx] = sh_pfc_read(pfc, reg);
614 }
615
sh_pfc_restore_reg(struct sh_pfc * pfc,u32 reg,unsigned int idx)616 static void sh_pfc_restore_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
617 {
618 sh_pfc_write(pfc, reg, pfc->saved_regs[idx]);
619 }
620
sh_pfc_walk_regs(struct sh_pfc * pfc,void (* do_reg)(struct sh_pfc * pfc,u32 reg,unsigned int idx))621 static unsigned int sh_pfc_walk_regs(struct sh_pfc *pfc,
622 void (*do_reg)(struct sh_pfc *pfc, u32 reg, unsigned int idx))
623 {
624 unsigned int i, n = 0;
625
626 if (pfc->info->cfg_regs)
627 for (i = 0; pfc->info->cfg_regs[i].reg; i++)
628 do_reg(pfc, pfc->info->cfg_regs[i].reg, n++);
629
630 if (pfc->info->drive_regs)
631 for (i = 0; pfc->info->drive_regs[i].reg; i++)
632 do_reg(pfc, pfc->info->drive_regs[i].reg, n++);
633
634 if (pfc->info->bias_regs)
635 for (i = 0; pfc->info->bias_regs[i].puen; i++) {
636 do_reg(pfc, pfc->info->bias_regs[i].puen, n++);
637 if (pfc->info->bias_regs[i].pud)
638 do_reg(pfc, pfc->info->bias_regs[i].pud, n++);
639 }
640
641 if (pfc->info->ioctrl_regs)
642 for (i = 0; pfc->info->ioctrl_regs[i].reg; i++)
643 do_reg(pfc, pfc->info->ioctrl_regs[i].reg, n++);
644
645 return n;
646 }
647
sh_pfc_suspend_init(struct sh_pfc * pfc)648 static int sh_pfc_suspend_init(struct sh_pfc *pfc)
649 {
650 unsigned int n;
651
652 /* This is the best we can do to check for the presence of PSCI */
653 if (!psci_ops.cpu_suspend)
654 return 0;
655
656 n = sh_pfc_walk_regs(pfc, sh_pfc_nop_reg);
657 if (!n)
658 return 0;
659
660 pfc->saved_regs = devm_kmalloc_array(pfc->dev, n,
661 sizeof(*pfc->saved_regs),
662 GFP_KERNEL);
663 if (!pfc->saved_regs)
664 return -ENOMEM;
665
666 dev_dbg(pfc->dev, "Allocated space to save %u regs\n", n);
667 return 0;
668 }
669
sh_pfc_suspend_noirq(struct device * dev)670 static int sh_pfc_suspend_noirq(struct device *dev)
671 {
672 struct sh_pfc *pfc = dev_get_drvdata(dev);
673
674 if (pfc->saved_regs)
675 sh_pfc_walk_regs(pfc, sh_pfc_save_reg);
676 return 0;
677 }
678
sh_pfc_resume_noirq(struct device * dev)679 static int sh_pfc_resume_noirq(struct device *dev)
680 {
681 struct sh_pfc *pfc = dev_get_drvdata(dev);
682
683 if (pfc->saved_regs)
684 sh_pfc_walk_regs(pfc, sh_pfc_restore_reg);
685 return 0;
686 }
687
688 static const struct dev_pm_ops sh_pfc_pm = {
689 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sh_pfc_suspend_noirq, sh_pfc_resume_noirq)
690 };
691 #define DEV_PM_OPS &sh_pfc_pm
692 #else
sh_pfc_suspend_init(struct sh_pfc * pfc)693 static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; }
694 #define DEV_PM_OPS NULL
695 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
696
sh_pfc_probe(struct platform_device * pdev)697 static int sh_pfc_probe(struct platform_device *pdev)
698 {
699 #ifdef CONFIG_OF
700 struct device_node *np = pdev->dev.of_node;
701 #endif
702 const struct sh_pfc_soc_info *info;
703 struct sh_pfc *pfc;
704 int ret;
705
706 #ifdef CONFIG_OF
707 if (np)
708 info = of_device_get_match_data(&pdev->dev);
709 else
710 #endif
711 info = (const void *)platform_get_device_id(pdev)->driver_data;
712
713 pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
714 if (pfc == NULL)
715 return -ENOMEM;
716
717 pfc->info = info;
718 pfc->dev = &pdev->dev;
719
720 ret = sh_pfc_map_resources(pfc, pdev);
721 if (unlikely(ret < 0))
722 return ret;
723
724 spin_lock_init(&pfc->lock);
725
726 if (info->ops && info->ops->init) {
727 ret = info->ops->init(pfc);
728 if (ret < 0)
729 return ret;
730
731 /* .init() may have overridden pfc->info */
732 info = pfc->info;
733 }
734
735 ret = sh_pfc_suspend_init(pfc);
736 if (ret)
737 return ret;
738
739 /* Enable dummy states for those platforms without pinctrl support */
740 if (!of_have_populated_dt())
741 pinctrl_provide_dummies();
742
743 ret = sh_pfc_init_ranges(pfc);
744 if (ret < 0)
745 return ret;
746
747 /*
748 * Initialize pinctrl bindings first
749 */
750 ret = sh_pfc_register_pinctrl(pfc);
751 if (unlikely(ret != 0))
752 return ret;
753
754 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
755 /*
756 * Then the GPIO chip
757 */
758 ret = sh_pfc_register_gpiochip(pfc);
759 if (unlikely(ret != 0)) {
760 /*
761 * If the GPIO chip fails to come up we still leave the
762 * PFC state as it is, given that there are already
763 * extant users of it that have succeeded by this point.
764 */
765 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
766 }
767 #endif
768
769 platform_set_drvdata(pdev, pfc);
770
771 dev_info(pfc->dev, "%s support registered\n", info->name);
772
773 return 0;
774 }
775
776 static const struct platform_device_id sh_pfc_id_table[] = {
777 #ifdef CONFIG_PINCTRL_PFC_SH7203
778 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
779 #endif
780 #ifdef CONFIG_PINCTRL_PFC_SH7264
781 { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
782 #endif
783 #ifdef CONFIG_PINCTRL_PFC_SH7269
784 { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
785 #endif
786 #ifdef CONFIG_PINCTRL_PFC_SH7720
787 { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
788 #endif
789 #ifdef CONFIG_PINCTRL_PFC_SH7722
790 { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
791 #endif
792 #ifdef CONFIG_PINCTRL_PFC_SH7723
793 { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
794 #endif
795 #ifdef CONFIG_PINCTRL_PFC_SH7724
796 { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
797 #endif
798 #ifdef CONFIG_PINCTRL_PFC_SH7734
799 { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
800 #endif
801 #ifdef CONFIG_PINCTRL_PFC_SH7757
802 { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
803 #endif
804 #ifdef CONFIG_PINCTRL_PFC_SH7785
805 { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
806 #endif
807 #ifdef CONFIG_PINCTRL_PFC_SH7786
808 { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
809 #endif
810 #ifdef CONFIG_PINCTRL_PFC_SHX3
811 { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
812 #endif
813 { },
814 };
815
816 static struct platform_driver sh_pfc_driver = {
817 .probe = sh_pfc_probe,
818 .id_table = sh_pfc_id_table,
819 .driver = {
820 .name = DRV_NAME,
821 .of_match_table = of_match_ptr(sh_pfc_of_table),
822 .pm = DEV_PM_OPS,
823 },
824 };
825
sh_pfc_init(void)826 static int __init sh_pfc_init(void)
827 {
828 return platform_driver_register(&sh_pfc_driver);
829 }
830 postcore_initcall(sh_pfc_init);
831
