1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Pin Control and GPIO driver for SuperH Pin Function Controller.
4 *
5 * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
6 *
7 * Copyright (C) 2008 Magnus Damm
8 * Copyright (C) 2009 - 2012 Paul Mundt
9 */
10
11 #define DRV_NAME "sh-pfc"
12
13 #include <linux/bitops.h>
14 #include <linux/err.h>
15 #include <linux/errno.h>
16 #include <linux/io.h>
17 #include <linux/ioport.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/of.h>
21 #include <linux/of_device.h>
22 #include <linux/pinctrl/machine.h>
23 #include <linux/platform_device.h>
24 #include <linux/psci.h>
25 #include <linux/slab.h>
26
27 #include "core.h"
28
sh_pfc_map_resources(struct sh_pfc * pfc,struct platform_device * pdev)29 static int sh_pfc_map_resources(struct sh_pfc *pfc,
30 struct platform_device *pdev)
31 {
32 unsigned int num_windows, num_irqs;
33 struct sh_pfc_window *windows;
34 unsigned int *irqs = NULL;
35 struct resource *res;
36 unsigned int i;
37 int irq;
38
39 /* Count the MEM and IRQ resources. */
40 for (num_windows = 0;; num_windows++) {
41 res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows);
42 if (!res)
43 break;
44 }
45 for (num_irqs = 0;; num_irqs++) {
46 irq = platform_get_irq(pdev, num_irqs);
47 if (irq == -EPROBE_DEFER)
48 return irq;
49 if (irq < 0)
50 break;
51 }
52
53 if (num_windows == 0)
54 return -EINVAL;
55
56 /* Allocate memory windows and IRQs arrays. */
57 windows = devm_kcalloc(pfc->dev, num_windows, sizeof(*windows),
58 GFP_KERNEL);
59 if (windows == NULL)
60 return -ENOMEM;
61
62 pfc->num_windows = num_windows;
63 pfc->windows = windows;
64
65 if (num_irqs) {
66 irqs = devm_kcalloc(pfc->dev, num_irqs, sizeof(*irqs),
67 GFP_KERNEL);
68 if (irqs == NULL)
69 return -ENOMEM;
70
71 pfc->num_irqs = num_irqs;
72 pfc->irqs = irqs;
73 }
74
75 /* Fill them. */
76 for (i = 0; i < num_windows; i++) {
77 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
78 windows->phys = res->start;
79 windows->size = resource_size(res);
80 windows->virt = devm_ioremap_resource(pfc->dev, res);
81 if (IS_ERR(windows->virt))
82 return -ENOMEM;
83 windows++;
84 }
85 for (i = 0; i < num_irqs; i++)
86 *irqs++ = platform_get_irq(pdev, i);
87
88 return 0;
89 }
90
sh_pfc_phys_to_virt(struct sh_pfc * pfc,u32 reg)91 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg)
92 {
93 struct sh_pfc_window *window;
94 phys_addr_t address = reg;
95 unsigned int i;
96
97 /* scan through physical windows and convert address */
98 for (i = 0; i < pfc->num_windows; i++) {
99 window = pfc->windows + i;
100
101 if (address < window->phys)
102 continue;
103
104 if (address >= (window->phys + window->size))
105 continue;
106
107 return window->virt + (address - window->phys);
108 }
109
110 BUG();
111 return NULL;
112 }
113
sh_pfc_get_pin_index(struct sh_pfc * pfc,unsigned int pin)114 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
115 {
116 unsigned int offset;
117 unsigned int i;
118
119 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
120 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
121
122 if (pin <= range->end)
123 return pin >= range->start
124 ? offset + pin - range->start : -1;
125
126 offset += range->end - range->start + 1;
127 }
128
129 return -EINVAL;
130 }
131
sh_pfc_enum_in_range(u16 enum_id,const struct pinmux_range * r)132 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
133 {
134 if (enum_id < r->begin)
135 return 0;
136
137 if (enum_id > r->end)
138 return 0;
139
140 return 1;
141 }
142
sh_pfc_read_raw_reg(void __iomem * mapped_reg,unsigned int reg_width)143 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
144 {
145 switch (reg_width) {
146 case 8:
147 return ioread8(mapped_reg);
148 case 16:
149 return ioread16(mapped_reg);
150 case 32:
151 return ioread32(mapped_reg);
152 }
153
154 BUG();
155 return 0;
156 }
157
sh_pfc_write_raw_reg(void __iomem * mapped_reg,unsigned int reg_width,u32 data)158 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
159 u32 data)
160 {
161 switch (reg_width) {
162 case 8:
163 iowrite8(data, mapped_reg);
164 return;
165 case 16:
166 iowrite16(data, mapped_reg);
167 return;
168 case 32:
169 iowrite32(data, mapped_reg);
170 return;
171 }
172
173 BUG();
174 }
175
sh_pfc_read(struct sh_pfc * pfc,u32 reg)176 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
177 {
178 return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32);
179 }
180
sh_pfc_write(struct sh_pfc * pfc,u32 reg,u32 data)181 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
182 {
183 if (pfc->info->unlock_reg)
184 sh_pfc_write_raw_reg(
185 sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
186 ~data);
187
188 sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data);
189 }
190
sh_pfc_config_reg_helper(struct sh_pfc * pfc,const struct pinmux_cfg_reg * crp,unsigned int in_pos,void __iomem ** mapped_regp,u32 * maskp,unsigned int * posp)191 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
192 const struct pinmux_cfg_reg *crp,
193 unsigned int in_pos,
194 void __iomem **mapped_regp, u32 *maskp,
195 unsigned int *posp)
196 {
197 unsigned int k;
198
199 *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
200
201 if (crp->field_width) {
202 *maskp = (1 << crp->field_width) - 1;
203 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
204 } else {
205 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
206 *posp = crp->reg_width;
207 for (k = 0; k <= in_pos; k++)
208 *posp -= crp->var_field_width[k];
209 }
210 }
211
sh_pfc_write_config_reg(struct sh_pfc * pfc,const struct pinmux_cfg_reg * crp,unsigned int field,u32 value)212 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
213 const struct pinmux_cfg_reg *crp,
214 unsigned int field, u32 value)
215 {
216 void __iomem *mapped_reg;
217 unsigned int pos;
218 u32 mask, data;
219
220 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
221
222 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
223 "r_width = %u, f_width = %u\n",
224 crp->reg, value, field, crp->reg_width, hweight32(mask));
225
226 mask = ~(mask << pos);
227 value = value << pos;
228
229 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
230 data &= mask;
231 data |= value;
232
233 if (pfc->info->unlock_reg)
234 sh_pfc_write_raw_reg(
235 sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
236 ~data);
237
238 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
239 }
240
sh_pfc_get_config_reg(struct sh_pfc * pfc,u16 enum_id,const struct pinmux_cfg_reg ** crp,unsigned int * fieldp,u32 * valuep)241 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
242 const struct pinmux_cfg_reg **crp,
243 unsigned int *fieldp, u32 *valuep)
244 {
245 unsigned int k = 0;
246
247 while (1) {
248 const struct pinmux_cfg_reg *config_reg =
249 pfc->info->cfg_regs + k;
250 unsigned int r_width = config_reg->reg_width;
251 unsigned int f_width = config_reg->field_width;
252 unsigned int curr_width;
253 unsigned int bit_pos;
254 unsigned int pos = 0;
255 unsigned int m = 0;
256
257 if (!r_width)
258 break;
259
260 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
261 u32 ncomb;
262 u32 n;
263
264 if (f_width)
265 curr_width = f_width;
266 else
267 curr_width = config_reg->var_field_width[m];
268
269 ncomb = 1 << curr_width;
270 for (n = 0; n < ncomb; n++) {
271 if (config_reg->enum_ids[pos + n] == enum_id) {
272 *crp = config_reg;
273 *fieldp = m;
274 *valuep = n;
275 return 0;
276 }
277 }
278 pos += ncomb;
279 m++;
280 }
281 k++;
282 }
283
284 return -EINVAL;
285 }
286
sh_pfc_mark_to_enum(struct sh_pfc * pfc,u16 mark,int pos,u16 * enum_idp)287 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
288 u16 *enum_idp)
289 {
290 const u16 *data = pfc->info->pinmux_data;
291 unsigned int k;
292
293 if (pos) {
294 *enum_idp = data[pos + 1];
295 return pos + 1;
296 }
297
298 for (k = 0; k < pfc->info->pinmux_data_size; k++) {
299 if (data[k] == mark) {
300 *enum_idp = data[k + 1];
301 return k + 1;
302 }
303 }
304
305 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
306 mark);
307 return -EINVAL;
308 }
309
sh_pfc_config_mux(struct sh_pfc * pfc,unsigned mark,int pinmux_type)310 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
311 {
312 const struct pinmux_range *range;
313 int pos = 0;
314
315 switch (pinmux_type) {
316 case PINMUX_TYPE_GPIO:
317 case PINMUX_TYPE_FUNCTION:
318 range = NULL;
319 break;
320
321 case PINMUX_TYPE_OUTPUT:
322 range = &pfc->info->output;
323 break;
324
325 case PINMUX_TYPE_INPUT:
326 range = &pfc->info->input;
327 break;
328
329 default:
330 return -EINVAL;
331 }
332
333 /* Iterate over all the configuration fields we need to update. */
334 while (1) {
335 const struct pinmux_cfg_reg *cr;
336 unsigned int field;
337 u16 enum_id;
338 u32 value;
339 int in_range;
340 int ret;
341
342 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
343 if (pos < 0)
344 return pos;
345
346 if (!enum_id)
347 break;
348
349 /* Check if the configuration field selects a function. If it
350 * doesn't, skip the field if it's not applicable to the
351 * requested pinmux type.
352 */
353 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
354 if (!in_range) {
355 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
356 /* Functions are allowed to modify all
357 * fields.
358 */
359 in_range = 1;
360 } else if (pinmux_type != PINMUX_TYPE_GPIO) {
361 /* Input/output types can only modify fields
362 * that correspond to their respective ranges.
363 */
364 in_range = sh_pfc_enum_in_range(enum_id, range);
365
366 /*
367 * special case pass through for fixed
368 * input-only or output-only pins without
369 * function enum register association.
370 */
371 if (in_range && enum_id == range->force)
372 continue;
373 }
374 /* GPIOs are only allowed to modify function fields. */
375 }
376
377 if (!in_range)
378 continue;
379
380 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
381 if (ret < 0)
382 return ret;
383
384 sh_pfc_write_config_reg(pfc, cr, field, value);
385 }
386
387 return 0;
388 }
389
390 const struct pinmux_bias_reg *
sh_pfc_pin_to_bias_reg(const struct sh_pfc * pfc,unsigned int pin,unsigned int * bit)391 sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
392 unsigned int *bit)
393 {
394 unsigned int i, j;
395
396 for (i = 0; pfc->info->bias_regs[i].puen; i++) {
397 for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
398 if (pfc->info->bias_regs[i].pins[j] == pin) {
399 *bit = j;
400 return &pfc->info->bias_regs[i];
401 }
402 }
403 }
404
405 WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
406
407 return NULL;
408 }
409
sh_pfc_init_ranges(struct sh_pfc * pfc)410 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
411 {
412 struct sh_pfc_pin_range *range;
413 unsigned int nr_ranges;
414 unsigned int i;
415
416 if (pfc->info->pins[0].pin == (u16)-1) {
417 /* Pin number -1 denotes that the SoC doesn't report pin numbers
418 * in its pin arrays yet. Consider the pin numbers range as
419 * continuous and allocate a single range.
420 */
421 pfc->nr_ranges = 1;
422 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
423 GFP_KERNEL);
424 if (pfc->ranges == NULL)
425 return -ENOMEM;
426
427 pfc->ranges->start = 0;
428 pfc->ranges->end = pfc->info->nr_pins - 1;
429 pfc->nr_gpio_pins = pfc->info->nr_pins;
430
431 return 0;
432 }
433
434 /* Count, allocate and fill the ranges. The PFC SoC data pins array must
435 * be sorted by pin numbers, and pins without a GPIO port must come
436 * last.
437 */
438 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
439 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
440 nr_ranges++;
441 }
442
443 pfc->nr_ranges = nr_ranges;
444 pfc->ranges = devm_kcalloc(pfc->dev, nr_ranges, sizeof(*pfc->ranges),
445 GFP_KERNEL);
446 if (pfc->ranges == NULL)
447 return -ENOMEM;
448
449 range = pfc->ranges;
450 range->start = pfc->info->pins[0].pin;
451
452 for (i = 1; i < pfc->info->nr_pins; ++i) {
453 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
454 continue;
455
456 range->end = pfc->info->pins[i-1].pin;
457 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
458 pfc->nr_gpio_pins = range->end + 1;
459
460 range++;
461 range->start = pfc->info->pins[i].pin;
462 }
463
464 range->end = pfc->info->pins[i-1].pin;
465 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
466 pfc->nr_gpio_pins = range->end + 1;
467
468 return 0;
469 }
470
471 #ifdef CONFIG_OF
472 static const struct of_device_id sh_pfc_of_table[] = {
473 #ifdef CONFIG_PINCTRL_PFC_EMEV2
474 {
475 .compatible = "renesas,pfc-emev2",
476 .data = &emev2_pinmux_info,
477 },
478 #endif
479 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
480 {
481 .compatible = "renesas,pfc-r8a73a4",
482 .data = &r8a73a4_pinmux_info,
483 },
484 #endif
485 #ifdef CONFIG_PINCTRL_PFC_R8A7740
486 {
487 .compatible = "renesas,pfc-r8a7740",
488 .data = &r8a7740_pinmux_info,
489 },
490 #endif
491 #ifdef CONFIG_PINCTRL_PFC_R8A7743
492 {
493 .compatible = "renesas,pfc-r8a7743",
494 .data = &r8a7743_pinmux_info,
495 },
496 #endif
497 #ifdef CONFIG_PINCTRL_PFC_R8A7744
498 {
499 .compatible = "renesas,pfc-r8a7744",
500 .data = &r8a7744_pinmux_info,
501 },
502 #endif
503 #ifdef CONFIG_PINCTRL_PFC_R8A7745
504 {
505 .compatible = "renesas,pfc-r8a7745",
506 .data = &r8a7745_pinmux_info,
507 },
508 #endif
509 #ifdef CONFIG_PINCTRL_PFC_R8A77470
510 {
511 .compatible = "renesas,pfc-r8a77470",
512 .data = &r8a77470_pinmux_info,
513 },
514 #endif
515 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
516 {
517 .compatible = "renesas,pfc-r8a774a1",
518 .data = &r8a774a1_pinmux_info,
519 },
520 #endif
521 #ifdef CONFIG_PINCTRL_PFC_R8A774C0
522 {
523 .compatible = "renesas,pfc-r8a774c0",
524 .data = &r8a774c0_pinmux_info,
525 },
526 #endif
527 #ifdef CONFIG_PINCTRL_PFC_R8A7778
528 {
529 .compatible = "renesas,pfc-r8a7778",
530 .data = &r8a7778_pinmux_info,
531 },
532 #endif
533 #ifdef CONFIG_PINCTRL_PFC_R8A7779
534 {
535 .compatible = "renesas,pfc-r8a7779",
536 .data = &r8a7779_pinmux_info,
537 },
538 #endif
539 #ifdef CONFIG_PINCTRL_PFC_R8A7790
540 {
541 .compatible = "renesas,pfc-r8a7790",
542 .data = &r8a7790_pinmux_info,
543 },
544 #endif
545 #ifdef CONFIG_PINCTRL_PFC_R8A7791
546 {
547 .compatible = "renesas,pfc-r8a7791",
548 .data = &r8a7791_pinmux_info,
549 },
550 #endif
551 #ifdef CONFIG_PINCTRL_PFC_R8A7792
552 {
553 .compatible = "renesas,pfc-r8a7792",
554 .data = &r8a7792_pinmux_info,
555 },
556 #endif
557 #ifdef CONFIG_PINCTRL_PFC_R8A7793
558 {
559 .compatible = "renesas,pfc-r8a7793",
560 .data = &r8a7793_pinmux_info,
561 },
562 #endif
563 #ifdef CONFIG_PINCTRL_PFC_R8A7794
564 {
565 .compatible = "renesas,pfc-r8a7794",
566 .data = &r8a7794_pinmux_info,
567 },
568 #endif
569 #ifdef CONFIG_PINCTRL_PFC_R8A7795
570 {
571 .compatible = "renesas,pfc-r8a7795",
572 .data = &r8a7795_pinmux_info,
573 },
574 #ifdef DEBUG
575 {
576 /* For sanity checks only (nothing matches against this) */
577 .compatible = "renesas,pfc-r8a77950", /* R-Car H3 ES1.0 */
578 .data = &r8a7795es1_pinmux_info,
579 },
580 #endif /* DEBUG */
581 #endif
582 #ifdef CONFIG_PINCTRL_PFC_R8A7796
583 {
584 .compatible = "renesas,pfc-r8a7796",
585 .data = &r8a7796_pinmux_info,
586 },
587 #endif
588 #ifdef CONFIG_PINCTRL_PFC_R8A77965
589 {
590 .compatible = "renesas,pfc-r8a77965",
591 .data = &r8a77965_pinmux_info,
592 },
593 #endif
594 #ifdef CONFIG_PINCTRL_PFC_R8A77970
595 {
596 .compatible = "renesas,pfc-r8a77970",
597 .data = &r8a77970_pinmux_info,
598 },
599 #endif
600 #ifdef CONFIG_PINCTRL_PFC_R8A77980
601 {
602 .compatible = "renesas,pfc-r8a77980",
603 .data = &r8a77980_pinmux_info,
604 },
605 #endif
606 #ifdef CONFIG_PINCTRL_PFC_R8A77990
607 {
608 .compatible = "renesas,pfc-r8a77990",
609 .data = &r8a77990_pinmux_info,
610 },
611 #endif
612 #ifdef CONFIG_PINCTRL_PFC_R8A77995
613 {
614 .compatible = "renesas,pfc-r8a77995",
615 .data = &r8a77995_pinmux_info,
616 },
617 #endif
618 #ifdef CONFIG_PINCTRL_PFC_SH73A0
619 {
620 .compatible = "renesas,pfc-sh73a0",
621 .data = &sh73a0_pinmux_info,
622 },
623 #endif
624 { },
625 };
626 #endif
627
628 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
sh_pfc_nop_reg(struct sh_pfc * pfc,u32 reg,unsigned int idx)629 static void sh_pfc_nop_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
630 {
631 }
632
sh_pfc_save_reg(struct sh_pfc * pfc,u32 reg,unsigned int idx)633 static void sh_pfc_save_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
634 {
635 pfc->saved_regs[idx] = sh_pfc_read(pfc, reg);
636 }
637
sh_pfc_restore_reg(struct sh_pfc * pfc,u32 reg,unsigned int idx)638 static void sh_pfc_restore_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
639 {
640 sh_pfc_write(pfc, reg, pfc->saved_regs[idx]);
641 }
642
sh_pfc_walk_regs(struct sh_pfc * pfc,void (* do_reg)(struct sh_pfc * pfc,u32 reg,unsigned int idx))643 static unsigned int sh_pfc_walk_regs(struct sh_pfc *pfc,
644 void (*do_reg)(struct sh_pfc *pfc, u32 reg, unsigned int idx))
645 {
646 unsigned int i, n = 0;
647
648 if (pfc->info->cfg_regs)
649 for (i = 0; pfc->info->cfg_regs[i].reg; i++)
650 do_reg(pfc, pfc->info->cfg_regs[i].reg, n++);
651
652 if (pfc->info->drive_regs)
653 for (i = 0; pfc->info->drive_regs[i].reg; i++)
654 do_reg(pfc, pfc->info->drive_regs[i].reg, n++);
655
656 if (pfc->info->bias_regs)
657 for (i = 0; pfc->info->bias_regs[i].puen; i++) {
658 do_reg(pfc, pfc->info->bias_regs[i].puen, n++);
659 if (pfc->info->bias_regs[i].pud)
660 do_reg(pfc, pfc->info->bias_regs[i].pud, n++);
661 }
662
663 if (pfc->info->ioctrl_regs)
664 for (i = 0; pfc->info->ioctrl_regs[i].reg; i++)
665 do_reg(pfc, pfc->info->ioctrl_regs[i].reg, n++);
666
667 return n;
668 }
669
sh_pfc_suspend_init(struct sh_pfc * pfc)670 static int sh_pfc_suspend_init(struct sh_pfc *pfc)
671 {
672 unsigned int n;
673
674 /* This is the best we can do to check for the presence of PSCI */
675 if (!psci_ops.cpu_suspend)
676 return 0;
677
678 n = sh_pfc_walk_regs(pfc, sh_pfc_nop_reg);
679 if (!n)
680 return 0;
681
682 pfc->saved_regs = devm_kmalloc_array(pfc->dev, n,
683 sizeof(*pfc->saved_regs),
684 GFP_KERNEL);
685 if (!pfc->saved_regs)
686 return -ENOMEM;
687
688 dev_dbg(pfc->dev, "Allocated space to save %u regs\n", n);
689 return 0;
690 }
691
sh_pfc_suspend_noirq(struct device * dev)692 static int sh_pfc_suspend_noirq(struct device *dev)
693 {
694 struct sh_pfc *pfc = dev_get_drvdata(dev);
695
696 if (pfc->saved_regs)
697 sh_pfc_walk_regs(pfc, sh_pfc_save_reg);
698 return 0;
699 }
700
sh_pfc_resume_noirq(struct device * dev)701 static int sh_pfc_resume_noirq(struct device *dev)
702 {
703 struct sh_pfc *pfc = dev_get_drvdata(dev);
704
705 if (pfc->saved_regs)
706 sh_pfc_walk_regs(pfc, sh_pfc_restore_reg);
707 return 0;
708 }
709
710 static const struct dev_pm_ops sh_pfc_pm = {
711 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sh_pfc_suspend_noirq, sh_pfc_resume_noirq)
712 };
713 #define DEV_PM_OPS &sh_pfc_pm
714 #else
sh_pfc_suspend_init(struct sh_pfc * pfc)715 static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; }
716 #define DEV_PM_OPS NULL
717 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
718
719 #ifdef DEBUG
is0s(const u16 * enum_ids,unsigned int n)720 static bool __init is0s(const u16 *enum_ids, unsigned int n)
721 {
722 unsigned int i;
723
724 for (i = 0; i < n; i++)
725 if (enum_ids[i])
726 return false;
727
728 return true;
729 }
730
731 static unsigned int sh_pfc_errors __initdata = 0;
732 static unsigned int sh_pfc_warnings __initdata = 0;
733
sh_pfc_check_cfg_reg(const char * drvname,const struct pinmux_cfg_reg * cfg_reg)734 static void __init sh_pfc_check_cfg_reg(const char *drvname,
735 const struct pinmux_cfg_reg *cfg_reg)
736 {
737 unsigned int i, n, rw, fw;
738
739 if (cfg_reg->field_width) {
740 /* Checked at build time */
741 return;
742 }
743
744 for (i = 0, n = 0, rw = 0; (fw = cfg_reg->var_field_width[i]); i++) {
745 if (fw > 3 && is0s(&cfg_reg->enum_ids[n], 1 << fw)) {
746 pr_warn("%s: reg 0x%x: reserved field [%u:%u] can be split to reduce table size\n",
747 drvname, cfg_reg->reg, rw, rw + fw - 1);
748 sh_pfc_warnings++;
749 }
750 n += 1 << fw;
751 rw += fw;
752 }
753
754 if (rw != cfg_reg->reg_width) {
755 pr_err("%s: reg 0x%x: var_field_width declares %u instead of %u bits\n",
756 drvname, cfg_reg->reg, rw, cfg_reg->reg_width);
757 sh_pfc_errors++;
758 }
759
760 if (n != cfg_reg->nr_enum_ids) {
761 pr_err("%s: reg 0x%x: enum_ids[] has %u instead of %u values\n",
762 drvname, cfg_reg->reg, cfg_reg->nr_enum_ids, n);
763 sh_pfc_errors++;
764 }
765 }
766
sh_pfc_check_info(const struct sh_pfc_soc_info * info)767 static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
768 {
769 const struct sh_pfc_function *func;
770 const char *drvname = info->name;
771 unsigned int *refcnts;
772 unsigned int i, j, k;
773
774 pr_info("Checking %s\n", drvname);
775
776 /* Check pins */
777 for (i = 0; i < info->nr_pins; i++) {
778 for (j = 0; j < i; j++) {
779 if (!strcmp(info->pins[i].name, info->pins[j].name)) {
780 pr_err("%s: pin %s/%s: name conflict\n",
781 drvname, info->pins[i].name,
782 info->pins[j].name);
783 sh_pfc_errors++;
784 }
785
786 if (info->pins[i].pin != (u16)-1 &&
787 info->pins[i].pin == info->pins[j].pin) {
788 pr_err("%s: pin %s/%s: pin %u conflict\n",
789 drvname, info->pins[i].name,
790 info->pins[j].name, info->pins[i].pin);
791 sh_pfc_errors++;
792 }
793
794 if (info->pins[i].enum_id &&
795 info->pins[i].enum_id == info->pins[j].enum_id) {
796 pr_err("%s: pin %s/%s: enum_id %u conflict\n",
797 drvname, info->pins[i].name,
798 info->pins[j].name,
799 info->pins[i].enum_id);
800 sh_pfc_errors++;
801 }
802 }
803 }
804
805 /* Check groups and functions */
806 refcnts = kcalloc(info->nr_groups, sizeof(*refcnts), GFP_KERNEL);
807 if (!refcnts)
808 return;
809
810 for (i = 0; i < info->nr_functions; i++) {
811 func = &info->functions[i];
812 if (!func->name) {
813 pr_err("%s: empty function %u\n", drvname, i);
814 sh_pfc_errors++;
815 continue;
816 }
817 for (j = 0; j < func->nr_groups; j++) {
818 for (k = 0; k < info->nr_groups; k++) {
819 if (info->groups[k].name &&
820 !strcmp(func->groups[j],
821 info->groups[k].name)) {
822 refcnts[k]++;
823 break;
824 }
825 }
826
827 if (k == info->nr_groups) {
828 pr_err("%s: function %s: group %s not found\n",
829 drvname, func->name, func->groups[j]);
830 sh_pfc_errors++;
831 }
832 }
833 }
834
835 for (i = 0; i < info->nr_groups; i++) {
836 if (!info->groups[i].name) {
837 pr_err("%s: empty group %u\n", drvname, i);
838 sh_pfc_errors++;
839 continue;
840 }
841 if (!refcnts[i]) {
842 pr_err("%s: orphan group %s\n", drvname,
843 info->groups[i].name);
844 sh_pfc_errors++;
845 } else if (refcnts[i] > 1) {
846 pr_warn("%s: group %s referenced by %u functions\n",
847 drvname, info->groups[i].name, refcnts[i]);
848 sh_pfc_warnings++;
849 }
850 }
851
852 kfree(refcnts);
853
854 /* Check config register descriptions */
855 for (i = 0; info->cfg_regs && info->cfg_regs[i].reg; i++)
856 sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]);
857 }
858
sh_pfc_check_driver(const struct platform_driver * pdrv)859 static void __init sh_pfc_check_driver(const struct platform_driver *pdrv)
860 {
861 unsigned int i;
862
863 pr_warn("Checking builtin pinmux tables\n");
864
865 for (i = 0; pdrv->id_table[i].name[0]; i++)
866 sh_pfc_check_info((void *)pdrv->id_table[i].driver_data);
867
868 #ifdef CONFIG_OF
869 for (i = 0; pdrv->driver.of_match_table[i].compatible[0]; i++)
870 sh_pfc_check_info(pdrv->driver.of_match_table[i].data);
871 #endif
872
873 pr_warn("Detected %u errors and %u warnings\n", sh_pfc_errors,
874 sh_pfc_warnings);
875 }
876
877 #else /* !DEBUG */
sh_pfc_check_driver(struct platform_driver * pdrv)878 static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {}
879 #endif /* !DEBUG */
880
sh_pfc_probe(struct platform_device * pdev)881 static int sh_pfc_probe(struct platform_device *pdev)
882 {
883 #ifdef CONFIG_OF
884 struct device_node *np = pdev->dev.of_node;
885 #endif
886 const struct sh_pfc_soc_info *info;
887 struct sh_pfc *pfc;
888 int ret;
889
890 #ifdef CONFIG_OF
891 if (np)
892 info = of_device_get_match_data(&pdev->dev);
893 else
894 #endif
895 info = (const void *)platform_get_device_id(pdev)->driver_data;
896
897 pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
898 if (pfc == NULL)
899 return -ENOMEM;
900
901 pfc->info = info;
902 pfc->dev = &pdev->dev;
903
904 ret = sh_pfc_map_resources(pfc, pdev);
905 if (unlikely(ret < 0))
906 return ret;
907
908 spin_lock_init(&pfc->lock);
909
910 if (info->ops && info->ops->init) {
911 ret = info->ops->init(pfc);
912 if (ret < 0)
913 return ret;
914
915 /* .init() may have overridden pfc->info */
916 info = pfc->info;
917 }
918
919 ret = sh_pfc_suspend_init(pfc);
920 if (ret)
921 return ret;
922
923 /* Enable dummy states for those platforms without pinctrl support */
924 if (!of_have_populated_dt())
925 pinctrl_provide_dummies();
926
927 ret = sh_pfc_init_ranges(pfc);
928 if (ret < 0)
929 return ret;
930
931 /*
932 * Initialize pinctrl bindings first
933 */
934 ret = sh_pfc_register_pinctrl(pfc);
935 if (unlikely(ret != 0))
936 return ret;
937
938 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
939 /*
940 * Then the GPIO chip
941 */
942 ret = sh_pfc_register_gpiochip(pfc);
943 if (unlikely(ret != 0)) {
944 /*
945 * If the GPIO chip fails to come up we still leave the
946 * PFC state as it is, given that there are already
947 * extant users of it that have succeeded by this point.
948 */
949 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
950 }
951 #endif
952
953 platform_set_drvdata(pdev, pfc);
954
955 dev_info(pfc->dev, "%s support registered\n", info->name);
956
957 return 0;
958 }
959
960 static const struct platform_device_id sh_pfc_id_table[] = {
961 #ifdef CONFIG_PINCTRL_PFC_SH7203
962 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
963 #endif
964 #ifdef CONFIG_PINCTRL_PFC_SH7264
965 { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
966 #endif
967 #ifdef CONFIG_PINCTRL_PFC_SH7269
968 { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
969 #endif
970 #ifdef CONFIG_PINCTRL_PFC_SH7720
971 { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
972 #endif
973 #ifdef CONFIG_PINCTRL_PFC_SH7722
974 { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
975 #endif
976 #ifdef CONFIG_PINCTRL_PFC_SH7723
977 { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
978 #endif
979 #ifdef CONFIG_PINCTRL_PFC_SH7724
980 { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
981 #endif
982 #ifdef CONFIG_PINCTRL_PFC_SH7734
983 { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
984 #endif
985 #ifdef CONFIG_PINCTRL_PFC_SH7757
986 { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
987 #endif
988 #ifdef CONFIG_PINCTRL_PFC_SH7785
989 { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
990 #endif
991 #ifdef CONFIG_PINCTRL_PFC_SH7786
992 { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
993 #endif
994 #ifdef CONFIG_PINCTRL_PFC_SHX3
995 { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
996 #endif
997 { },
998 };
999
1000 static struct platform_driver sh_pfc_driver = {
1001 .probe = sh_pfc_probe,
1002 .id_table = sh_pfc_id_table,
1003 .driver = {
1004 .name = DRV_NAME,
1005 .of_match_table = of_match_ptr(sh_pfc_of_table),
1006 .pm = DEV_PM_OPS,
1007 },
1008 };
1009
sh_pfc_init(void)1010 static int __init sh_pfc_init(void)
1011 {
1012 sh_pfc_check_driver(&sh_pfc_driver);
1013 return platform_driver_register(&sh_pfc_driver);
1014 }
1015 postcore_initcall(sh_pfc_init);
1016
