1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SH7786 Pinmux 4 * 5 * Copyright (C) 2008, 2009 Renesas Solutions Corp. 6 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 7 * 8 * Based on SH7785 pinmux 9 * 10 * Copyright (C) 2008 Magnus Damm 11 */ 12 13 #include <linux/init.h> 14 #include <linux/kernel.h> 15 #include <cpu/sh7786.h> 16 17 #include "sh_pfc.h" 18 19 enum { 20 PINMUX_RESERVED = 0, 21 22 PINMUX_DATA_BEGIN, 23 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, 24 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA, 25 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, 26 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA, 27 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, 28 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA, 29 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, 30 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA, 31 PE7_DATA, PE6_DATA, 32 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, 33 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA, 34 PG7_DATA, PG6_DATA, PG5_DATA, 35 PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA, 36 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA, 37 PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA, 38 PJ3_DATA, PJ2_DATA, PJ1_DATA, 39 PINMUX_DATA_END, 40 41 PINMUX_INPUT_BEGIN, 42 PA7_IN, PA6_IN, PA5_IN, PA4_IN, 43 PA3_IN, PA2_IN, PA1_IN, PA0_IN, 44 PB7_IN, PB6_IN, PB5_IN, PB4_IN, 45 PB3_IN, PB2_IN, PB1_IN, PB0_IN, 46 PC7_IN, PC6_IN, PC5_IN, PC4_IN, 47 PC3_IN, PC2_IN, PC1_IN, PC0_IN, 48 PD7_IN, PD6_IN, PD5_IN, PD4_IN, 49 PD3_IN, PD2_IN, PD1_IN, PD0_IN, 50 PE7_IN, PE6_IN, 51 PF7_IN, PF6_IN, PF5_IN, PF4_IN, 52 PF3_IN, PF2_IN, PF1_IN, PF0_IN, 53 PG7_IN, PG6_IN, PG5_IN, 54 PH7_IN, PH6_IN, PH5_IN, PH4_IN, 55 PH3_IN, PH2_IN, PH1_IN, PH0_IN, 56 PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN, 57 PJ3_IN, PJ2_IN, PJ1_IN, 58 PINMUX_INPUT_END, 59 60 PINMUX_OUTPUT_BEGIN, 61 PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT, 62 PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT, 63 PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT, 64 PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT, 65 PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT, 66 PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT, 67 PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT, 68 PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT, 69 PE7_OUT, PE6_OUT, 70 PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT, 71 PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT, 72 PG7_OUT, PG6_OUT, PG5_OUT, 73 PH7_OUT, PH6_OUT, PH5_OUT, PH4_OUT, 74 PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT, 75 PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT, 76 PJ3_OUT, PJ2_OUT, PJ1_OUT, 77 PINMUX_OUTPUT_END, 78 79 PINMUX_FUNCTION_BEGIN, 80 PA7_FN, PA6_FN, PA5_FN, PA4_FN, 81 PA3_FN, PA2_FN, PA1_FN, PA0_FN, 82 PB7_FN, PB6_FN, PB5_FN, PB4_FN, 83 PB3_FN, PB2_FN, PB1_FN, PB0_FN, 84 PC7_FN, PC6_FN, PC5_FN, PC4_FN, 85 PC3_FN, PC2_FN, PC1_FN, PC0_FN, 86 PD7_FN, PD6_FN, PD5_FN, PD4_FN, 87 PD3_FN, PD2_FN, PD1_FN, PD0_FN, 88 PE7_FN, PE6_FN, 89 PF7_FN, PF6_FN, PF5_FN, PF4_FN, 90 PF3_FN, PF2_FN, PF1_FN, PF0_FN, 91 PG7_FN, PG6_FN, PG5_FN, 92 PH7_FN, PH6_FN, PH5_FN, PH4_FN, 93 PH3_FN, PH2_FN, PH1_FN, PH0_FN, 94 PJ7_FN, PJ6_FN, PJ5_FN, PJ4_FN, 95 PJ3_FN, PJ2_FN, PJ1_FN, 96 P1MSEL14_0, P1MSEL14_1, 97 P1MSEL13_0, P1MSEL13_1, 98 P1MSEL12_0, P1MSEL12_1, 99 P1MSEL11_0, P1MSEL11_1, 100 P1MSEL10_0, P1MSEL10_1, 101 P1MSEL9_0, P1MSEL9_1, 102 P1MSEL8_0, P1MSEL8_1, 103 P1MSEL7_0, P1MSEL7_1, 104 P1MSEL6_0, P1MSEL6_1, 105 P1MSEL5_0, P1MSEL5_1, 106 P1MSEL4_0, P1MSEL4_1, 107 P1MSEL3_0, P1MSEL3_1, 108 P1MSEL2_0, P1MSEL2_1, 109 P1MSEL1_0, P1MSEL1_1, 110 P1MSEL0_0, P1MSEL0_1, 111 112 P2MSEL15_0, P2MSEL15_1, 113 P2MSEL14_0, P2MSEL14_1, 114 P2MSEL13_0, P2MSEL13_1, 115 P2MSEL12_0, P2MSEL12_1, 116 P2MSEL11_0, P2MSEL11_1, 117 P2MSEL10_0, P2MSEL10_1, 118 P2MSEL9_0, P2MSEL9_1, 119 P2MSEL8_0, P2MSEL8_1, 120 P2MSEL7_0, P2MSEL7_1, 121 P2MSEL6_0, P2MSEL6_1, 122 P2MSEL5_0, P2MSEL5_1, 123 P2MSEL4_0, P2MSEL4_1, 124 P2MSEL3_0, P2MSEL3_1, 125 P2MSEL2_0, P2MSEL2_1, 126 P2MSEL1_0, P2MSEL1_1, 127 P2MSEL0_0, P2MSEL0_1, 128 PINMUX_FUNCTION_END, 129 130 PINMUX_MARK_BEGIN, 131 DCLKIN_MARK, DCLKOUT_MARK, ODDF_MARK, 132 VSYNC_MARK, HSYNC_MARK, CDE_MARK, DISP_MARK, 133 DR0_MARK, DR1_MARK, DR2_MARK, DR3_MARK, DR4_MARK, DR5_MARK, 134 DG0_MARK, DG1_MARK, DG2_MARK, DG3_MARK, DG4_MARK, DG5_MARK, 135 DB0_MARK, DB1_MARK, DB2_MARK, DB3_MARK, DB4_MARK, DB5_MARK, 136 ETH_MAGIC_MARK, ETH_LINK_MARK, ETH_TX_ER_MARK, ETH_TX_EN_MARK, 137 ETH_MDIO_MARK, ETH_RX_CLK_MARK, ETH_MDC_MARK, ETH_COL_MARK, 138 ETH_TX_CLK_MARK, ETH_CRS_MARK, ETH_RX_DV_MARK, ETH_RX_ER_MARK, 139 ETH_TXD3_MARK, ETH_TXD2_MARK, ETH_TXD1_MARK, ETH_TXD0_MARK, 140 ETH_RXD3_MARK, ETH_RXD2_MARK, ETH_RXD1_MARK, ETH_RXD0_MARK, 141 HSPI_CLK_MARK, HSPI_CS_MARK, HSPI_RX_MARK, HSPI_TX_MARK, 142 SCIF0_CTS_MARK, SCIF0_RTS_MARK, 143 SCIF0_SCK_MARK, SCIF0_RXD_MARK, SCIF0_TXD_MARK, 144 SCIF1_SCK_MARK, SCIF1_RXD_MARK, SCIF1_TXD_MARK, 145 SCIF3_SCK_MARK, SCIF3_RXD_MARK, SCIF3_TXD_MARK, 146 SCIF4_SCK_MARK, SCIF4_RXD_MARK, SCIF4_TXD_MARK, 147 SCIF5_SCK_MARK, SCIF5_RXD_MARK, SCIF5_TXD_MARK, 148 BREQ_MARK, IOIS16_MARK, CE2B_MARK, CE2A_MARK, BACK_MARK, 149 FALE_MARK, FRB_MARK, FSTATUS_MARK, 150 FSE_MARK, FCLE_MARK, 151 DACK0_MARK, DACK1_MARK, DACK2_MARK, DACK3_MARK, 152 DREQ0_MARK, DREQ1_MARK, DREQ2_MARK, DREQ3_MARK, 153 DRAK0_MARK, DRAK1_MARK, DRAK2_MARK, DRAK3_MARK, 154 USB_OVC1_MARK, USB_OVC0_MARK, 155 USB_PENC1_MARK, USB_PENC0_MARK, 156 HAC_RES_MARK, 157 HAC1_SDOUT_MARK, HAC1_SDIN_MARK, HAC1_SYNC_MARK, HAC1_BITCLK_MARK, 158 HAC0_SDOUT_MARK, HAC0_SDIN_MARK, HAC0_SYNC_MARK, HAC0_BITCLK_MARK, 159 SSI0_SDATA_MARK, SSI0_SCK_MARK, SSI0_WS_MARK, SSI0_CLK_MARK, 160 SSI1_SDATA_MARK, SSI1_SCK_MARK, SSI1_WS_MARK, SSI1_CLK_MARK, 161 SSI2_SDATA_MARK, SSI2_SCK_MARK, SSI2_WS_MARK, 162 SSI3_SDATA_MARK, SSI3_SCK_MARK, SSI3_WS_MARK, 163 SDIF1CMD_MARK, SDIF1CD_MARK, SDIF1WP_MARK, SDIF1CLK_MARK, 164 SDIF1D3_MARK, SDIF1D2_MARK, SDIF1D1_MARK, SDIF1D0_MARK, 165 SDIF0CMD_MARK, SDIF0CD_MARK, SDIF0WP_MARK, SDIF0CLK_MARK, 166 SDIF0D3_MARK, SDIF0D2_MARK, SDIF0D1_MARK, SDIF0D0_MARK, 167 TCLK_MARK, 168 IRL7_MARK, IRL6_MARK, IRL5_MARK, IRL4_MARK, 169 PINMUX_MARK_END, 170 }; 171 172 static const u16 pinmux_data[] = { 173 /* PA GPIO */ 174 PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT), 175 PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT), 176 PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT), 177 PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT), 178 PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT), 179 PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT), 180 PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT), 181 PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT), 182 183 /* PB GPIO */ 184 PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT), 185 PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT), 186 PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT), 187 PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT), 188 PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT), 189 PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT), 190 PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT), 191 PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT), 192 193 /* PC GPIO */ 194 PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT), 195 PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT), 196 PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT), 197 PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT), 198 PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT), 199 PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT), 200 PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT), 201 PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT), 202 203 /* PD GPIO */ 204 PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT), 205 PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT), 206 PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT), 207 PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT), 208 PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT), 209 PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT), 210 PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT), 211 PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT), 212 213 /* PE GPIO */ 214 PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT), 215 PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT), 216 217 /* PF GPIO */ 218 PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT), 219 PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT), 220 PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT), 221 PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT), 222 PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT), 223 PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT), 224 PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT), 225 PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT), 226 227 /* PG GPIO */ 228 PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT), 229 PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT), 230 PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT), 231 232 /* PH GPIO */ 233 PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT), 234 PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT), 235 PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT), 236 PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT), 237 PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT), 238 PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT), 239 PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT), 240 PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT), 241 242 /* PJ GPIO */ 243 PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT), 244 PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT), 245 PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT), 246 PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT), 247 PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT), 248 PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT), 249 PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT), 250 251 /* PA FN */ 252 PINMUX_DATA(CDE_MARK, P1MSEL2_0, PA7_FN), 253 PINMUX_DATA(DISP_MARK, P1MSEL2_0, PA6_FN), 254 PINMUX_DATA(DR5_MARK, P1MSEL2_0, PA5_FN), 255 PINMUX_DATA(DR4_MARK, P1MSEL2_0, PA4_FN), 256 PINMUX_DATA(DR3_MARK, P1MSEL2_0, PA3_FN), 257 PINMUX_DATA(DR2_MARK, P1MSEL2_0, PA2_FN), 258 PINMUX_DATA(DR1_MARK, P1MSEL2_0, PA1_FN), 259 PINMUX_DATA(DR0_MARK, P1MSEL2_0, PA0_FN), 260 PINMUX_DATA(ETH_MAGIC_MARK, P1MSEL2_1, PA7_FN), 261 PINMUX_DATA(ETH_LINK_MARK, P1MSEL2_1, PA6_FN), 262 PINMUX_DATA(ETH_TX_ER_MARK, P1MSEL2_1, PA5_FN), 263 PINMUX_DATA(ETH_TX_EN_MARK, P1MSEL2_1, PA4_FN), 264 PINMUX_DATA(ETH_TXD3_MARK, P1MSEL2_1, PA3_FN), 265 PINMUX_DATA(ETH_TXD2_MARK, P1MSEL2_1, PA2_FN), 266 PINMUX_DATA(ETH_TXD1_MARK, P1MSEL2_1, PA1_FN), 267 PINMUX_DATA(ETH_TXD0_MARK, P1MSEL2_1, PA0_FN), 268 269 /* PB FN */ 270 PINMUX_DATA(VSYNC_MARK, P1MSEL3_0, PB7_FN), 271 PINMUX_DATA(ODDF_MARK, P1MSEL3_0, PB6_FN), 272 PINMUX_DATA(DG5_MARK, P1MSEL2_0, PB5_FN), 273 PINMUX_DATA(DG4_MARK, P1MSEL2_0, PB4_FN), 274 PINMUX_DATA(DG3_MARK, P1MSEL2_0, PB3_FN), 275 PINMUX_DATA(DG2_MARK, P1MSEL2_0, PB2_FN), 276 PINMUX_DATA(DG1_MARK, P1MSEL2_0, PB1_FN), 277 PINMUX_DATA(DG0_MARK, P1MSEL2_0, PB0_FN), 278 PINMUX_DATA(HSPI_CLK_MARK, P1MSEL3_1, PB7_FN), 279 PINMUX_DATA(HSPI_CS_MARK, P1MSEL3_1, PB6_FN), 280 PINMUX_DATA(ETH_MDIO_MARK, P1MSEL2_1, PB5_FN), 281 PINMUX_DATA(ETH_RX_CLK_MARK, P1MSEL2_1, PB4_FN), 282 PINMUX_DATA(ETH_MDC_MARK, P1MSEL2_1, PB3_FN), 283 PINMUX_DATA(ETH_COL_MARK, P1MSEL2_1, PB2_FN), 284 PINMUX_DATA(ETH_TX_CLK_MARK, P1MSEL2_1, PB1_FN), 285 PINMUX_DATA(ETH_CRS_MARK, P1MSEL2_1, PB0_FN), 286 287 /* PC FN */ 288 PINMUX_DATA(DCLKIN_MARK, P1MSEL3_0, PC7_FN), 289 PINMUX_DATA(HSYNC_MARK, P1MSEL3_0, PC6_FN), 290 PINMUX_DATA(DB5_MARK, P1MSEL2_0, PC5_FN), 291 PINMUX_DATA(DB4_MARK, P1MSEL2_0, PC4_FN), 292 PINMUX_DATA(DB3_MARK, P1MSEL2_0, PC3_FN), 293 PINMUX_DATA(DB2_MARK, P1MSEL2_0, PC2_FN), 294 PINMUX_DATA(DB1_MARK, P1MSEL2_0, PC1_FN), 295 PINMUX_DATA(DB0_MARK, P1MSEL2_0, PC0_FN), 296 297 PINMUX_DATA(HSPI_RX_MARK, P1MSEL3_1, PC7_FN), 298 PINMUX_DATA(HSPI_TX_MARK, P1MSEL3_1, PC6_FN), 299 PINMUX_DATA(ETH_RXD3_MARK, P1MSEL2_1, PC5_FN), 300 PINMUX_DATA(ETH_RXD2_MARK, P1MSEL2_1, PC4_FN), 301 PINMUX_DATA(ETH_RXD1_MARK, P1MSEL2_1, PC3_FN), 302 PINMUX_DATA(ETH_RXD0_MARK, P1MSEL2_1, PC2_FN), 303 PINMUX_DATA(ETH_RX_DV_MARK, P1MSEL2_1, PC1_FN), 304 PINMUX_DATA(ETH_RX_ER_MARK, P1MSEL2_1, PC0_FN), 305 306 /* PD FN */ 307 PINMUX_DATA(DCLKOUT_MARK, PD7_FN), 308 PINMUX_DATA(SCIF1_SCK_MARK, PD6_FN), 309 PINMUX_DATA(SCIF1_RXD_MARK, PD5_FN), 310 PINMUX_DATA(SCIF1_TXD_MARK, PD4_FN), 311 PINMUX_DATA(DACK1_MARK, P1MSEL13_1, P1MSEL12_0, PD3_FN), 312 PINMUX_DATA(BACK_MARK, P1MSEL13_0, P1MSEL12_1, PD3_FN), 313 PINMUX_DATA(FALE_MARK, P1MSEL13_0, P1MSEL12_0, PD3_FN), 314 PINMUX_DATA(DACK0_MARK, P1MSEL14_1, PD2_FN), 315 PINMUX_DATA(FCLE_MARK, P1MSEL14_0, PD2_FN), 316 PINMUX_DATA(DREQ1_MARK, P1MSEL10_0, P1MSEL9_1, PD1_FN), 317 PINMUX_DATA(BREQ_MARK, P1MSEL10_1, P1MSEL9_0, PD1_FN), 318 PINMUX_DATA(USB_OVC1_MARK, P1MSEL10_0, P1MSEL9_0, PD1_FN), 319 PINMUX_DATA(DREQ0_MARK, P1MSEL11_1, PD0_FN), 320 PINMUX_DATA(USB_OVC0_MARK, P1MSEL11_0, PD0_FN), 321 322 /* PE FN */ 323 PINMUX_DATA(USB_PENC1_MARK, PE7_FN), 324 PINMUX_DATA(USB_PENC0_MARK, PE6_FN), 325 326 /* PF FN */ 327 PINMUX_DATA(HAC1_SDOUT_MARK, P2MSEL15_0, P2MSEL14_0, PF7_FN), 328 PINMUX_DATA(HAC1_SDIN_MARK, P2MSEL15_0, P2MSEL14_0, PF6_FN), 329 PINMUX_DATA(HAC1_SYNC_MARK, P2MSEL15_0, P2MSEL14_0, PF5_FN), 330 PINMUX_DATA(HAC1_BITCLK_MARK, P2MSEL15_0, P2MSEL14_0, PF4_FN), 331 PINMUX_DATA(HAC0_SDOUT_MARK, P2MSEL13_0, P2MSEL12_0, PF3_FN), 332 PINMUX_DATA(HAC0_SDIN_MARK, P2MSEL13_0, P2MSEL12_0, PF2_FN), 333 PINMUX_DATA(HAC0_SYNC_MARK, P2MSEL13_0, P2MSEL12_0, PF1_FN), 334 PINMUX_DATA(HAC0_BITCLK_MARK, P2MSEL13_0, P2MSEL12_0, PF0_FN), 335 PINMUX_DATA(SSI1_SDATA_MARK, P2MSEL15_0, P2MSEL14_1, PF7_FN), 336 PINMUX_DATA(SSI1_SCK_MARK, P2MSEL15_0, P2MSEL14_1, PF6_FN), 337 PINMUX_DATA(SSI1_WS_MARK, P2MSEL15_0, P2MSEL14_1, PF5_FN), 338 PINMUX_DATA(SSI1_CLK_MARK, P2MSEL15_0, P2MSEL14_1, PF4_FN), 339 PINMUX_DATA(SSI0_SDATA_MARK, P2MSEL13_0, P2MSEL12_1, PF3_FN), 340 PINMUX_DATA(SSI0_SCK_MARK, P2MSEL13_0, P2MSEL12_1, PF2_FN), 341 PINMUX_DATA(SSI0_WS_MARK, P2MSEL13_0, P2MSEL12_1, PF1_FN), 342 PINMUX_DATA(SSI0_CLK_MARK, P2MSEL13_0, P2MSEL12_1, PF0_FN), 343 PINMUX_DATA(SDIF1CMD_MARK, P2MSEL15_1, P2MSEL14_0, PF7_FN), 344 PINMUX_DATA(SDIF1CD_MARK, P2MSEL15_1, P2MSEL14_0, PF6_FN), 345 PINMUX_DATA(SDIF1WP_MARK, P2MSEL15_1, P2MSEL14_0, PF5_FN), 346 PINMUX_DATA(SDIF1CLK_MARK, P2MSEL15_1, P2MSEL14_0, PF4_FN), 347 PINMUX_DATA(SDIF1D3_MARK, P2MSEL13_1, P2MSEL12_0, PF3_FN), 348 PINMUX_DATA(SDIF1D2_MARK, P2MSEL13_1, P2MSEL12_0, PF2_FN), 349 PINMUX_DATA(SDIF1D1_MARK, P2MSEL13_1, P2MSEL12_0, PF1_FN), 350 PINMUX_DATA(SDIF1D0_MARK, P2MSEL13_1, P2MSEL12_0, PF0_FN), 351 352 /* PG FN */ 353 PINMUX_DATA(SCIF3_SCK_MARK, P1MSEL8_0, PG7_FN), 354 PINMUX_DATA(SSI2_SDATA_MARK, P1MSEL8_1, PG7_FN), 355 PINMUX_DATA(SCIF3_RXD_MARK, P1MSEL7_0, P1MSEL6_0, PG6_FN), 356 PINMUX_DATA(SSI2_SCK_MARK, P1MSEL7_1, P1MSEL6_0, PG6_FN), 357 PINMUX_DATA(TCLK_MARK, P1MSEL7_0, P1MSEL6_1, PG6_FN), 358 PINMUX_DATA(SCIF3_TXD_MARK, P1MSEL5_0, P1MSEL4_0, PG5_FN), 359 PINMUX_DATA(SSI2_WS_MARK, P1MSEL5_1, P1MSEL4_0, PG5_FN), 360 PINMUX_DATA(HAC_RES_MARK, P1MSEL5_0, P1MSEL4_1, PG5_FN), 361 362 /* PH FN */ 363 PINMUX_DATA(DACK3_MARK, P2MSEL4_0, PH7_FN), 364 PINMUX_DATA(SDIF0CMD_MARK, P2MSEL4_1, PH7_FN), 365 PINMUX_DATA(DACK2_MARK, P2MSEL4_0, PH6_FN), 366 PINMUX_DATA(SDIF0CD_MARK, P2MSEL4_1, PH6_FN), 367 PINMUX_DATA(DREQ3_MARK, P2MSEL4_0, PH5_FN), 368 PINMUX_DATA(SDIF0WP_MARK, P2MSEL4_1, PH5_FN), 369 PINMUX_DATA(DREQ2_MARK, P2MSEL3_0, P2MSEL2_1, PH4_FN), 370 PINMUX_DATA(SDIF0CLK_MARK, P2MSEL3_1, P2MSEL2_0, PH4_FN), 371 PINMUX_DATA(SCIF0_CTS_MARK, P2MSEL3_0, P2MSEL2_0, PH4_FN), 372 PINMUX_DATA(SDIF0D3_MARK, P2MSEL1_1, P2MSEL0_0, PH3_FN), 373 PINMUX_DATA(SCIF0_RTS_MARK, P2MSEL1_0, P2MSEL0_0, PH3_FN), 374 PINMUX_DATA(IRL7_MARK, P2MSEL1_0, P2MSEL0_1, PH3_FN), 375 PINMUX_DATA(SDIF0D2_MARK, P2MSEL1_1, P2MSEL0_0, PH2_FN), 376 PINMUX_DATA(SCIF0_SCK_MARK, P2MSEL1_0, P2MSEL0_0, PH2_FN), 377 PINMUX_DATA(IRL6_MARK, P2MSEL1_0, P2MSEL0_1, PH2_FN), 378 PINMUX_DATA(SDIF0D1_MARK, P2MSEL1_1, P2MSEL0_0, PH1_FN), 379 PINMUX_DATA(SCIF0_RXD_MARK, P2MSEL1_0, P2MSEL0_0, PH1_FN), 380 PINMUX_DATA(IRL5_MARK, P2MSEL1_0, P2MSEL0_1, PH1_FN), 381 PINMUX_DATA(SDIF0D0_MARK, P2MSEL1_1, P2MSEL0_0, PH0_FN), 382 PINMUX_DATA(SCIF0_TXD_MARK, P2MSEL1_0, P2MSEL0_0, PH0_FN), 383 PINMUX_DATA(IRL4_MARK, P2MSEL1_0, P2MSEL0_1, PH0_FN), 384 385 /* PJ FN */ 386 PINMUX_DATA(SCIF5_SCK_MARK, P2MSEL11_1, PJ7_FN), 387 PINMUX_DATA(FRB_MARK, P2MSEL11_0, PJ7_FN), 388 PINMUX_DATA(SCIF5_RXD_MARK, P2MSEL10_0, PJ6_FN), 389 PINMUX_DATA(IOIS16_MARK, P2MSEL10_1, PJ6_FN), 390 PINMUX_DATA(SCIF5_TXD_MARK, P2MSEL10_0, PJ5_FN), 391 PINMUX_DATA(CE2B_MARK, P2MSEL10_1, PJ5_FN), 392 PINMUX_DATA(DRAK3_MARK, P2MSEL7_0, PJ4_FN), 393 PINMUX_DATA(CE2A_MARK, P2MSEL7_1, PJ4_FN), 394 PINMUX_DATA(SCIF4_SCK_MARK, P2MSEL9_0, P2MSEL8_0, PJ3_FN), 395 PINMUX_DATA(DRAK2_MARK, P2MSEL9_0, P2MSEL8_1, PJ3_FN), 396 PINMUX_DATA(SSI3_WS_MARK, P2MSEL9_1, P2MSEL8_0, PJ3_FN), 397 PINMUX_DATA(SCIF4_RXD_MARK, P2MSEL6_1, P2MSEL5_0, PJ2_FN), 398 PINMUX_DATA(DRAK1_MARK, P2MSEL6_0, P2MSEL5_1, PJ2_FN), 399 PINMUX_DATA(FSTATUS_MARK, P2MSEL6_0, P2MSEL5_0, PJ2_FN), 400 PINMUX_DATA(SSI3_SDATA_MARK, P2MSEL6_1, P2MSEL5_1, PJ2_FN), 401 PINMUX_DATA(SCIF4_TXD_MARK, P2MSEL6_1, P2MSEL5_0, PJ1_FN), 402 PINMUX_DATA(DRAK0_MARK, P2MSEL6_0, P2MSEL5_1, PJ1_FN), 403 PINMUX_DATA(FSE_MARK, P2MSEL6_0, P2MSEL5_0, PJ1_FN), 404 PINMUX_DATA(SSI3_SCK_MARK, P2MSEL6_1, P2MSEL5_1, PJ1_FN), 405 }; 406 407 static const struct sh_pfc_pin pinmux_pins[] = { 408 /* PA */ 409 PINMUX_GPIO(PA7), 410 PINMUX_GPIO(PA6), 411 PINMUX_GPIO(PA5), 412 PINMUX_GPIO(PA4), 413 PINMUX_GPIO(PA3), 414 PINMUX_GPIO(PA2), 415 PINMUX_GPIO(PA1), 416 PINMUX_GPIO(PA0), 417 418 /* PB */ 419 PINMUX_GPIO(PB7), 420 PINMUX_GPIO(PB6), 421 PINMUX_GPIO(PB5), 422 PINMUX_GPIO(PB4), 423 PINMUX_GPIO(PB3), 424 PINMUX_GPIO(PB2), 425 PINMUX_GPIO(PB1), 426 PINMUX_GPIO(PB0), 427 428 /* PC */ 429 PINMUX_GPIO(PC7), 430 PINMUX_GPIO(PC6), 431 PINMUX_GPIO(PC5), 432 PINMUX_GPIO(PC4), 433 PINMUX_GPIO(PC3), 434 PINMUX_GPIO(PC2), 435 PINMUX_GPIO(PC1), 436 PINMUX_GPIO(PC0), 437 438 /* PD */ 439 PINMUX_GPIO(PD7), 440 PINMUX_GPIO(PD6), 441 PINMUX_GPIO(PD5), 442 PINMUX_GPIO(PD4), 443 PINMUX_GPIO(PD3), 444 PINMUX_GPIO(PD2), 445 PINMUX_GPIO(PD1), 446 PINMUX_GPIO(PD0), 447 448 /* PE */ 449 PINMUX_GPIO(PE7), 450 PINMUX_GPIO(PE6), 451 452 /* PF */ 453 PINMUX_GPIO(PF7), 454 PINMUX_GPIO(PF6), 455 PINMUX_GPIO(PF5), 456 PINMUX_GPIO(PF4), 457 PINMUX_GPIO(PF3), 458 PINMUX_GPIO(PF2), 459 PINMUX_GPIO(PF1), 460 PINMUX_GPIO(PF0), 461 462 /* PG */ 463 PINMUX_GPIO(PG7), 464 PINMUX_GPIO(PG6), 465 PINMUX_GPIO(PG5), 466 467 /* PH */ 468 PINMUX_GPIO(PH7), 469 PINMUX_GPIO(PH6), 470 PINMUX_GPIO(PH5), 471 PINMUX_GPIO(PH4), 472 PINMUX_GPIO(PH3), 473 PINMUX_GPIO(PH2), 474 PINMUX_GPIO(PH1), 475 PINMUX_GPIO(PH0), 476 477 /* PJ */ 478 PINMUX_GPIO(PJ7), 479 PINMUX_GPIO(PJ6), 480 PINMUX_GPIO(PJ5), 481 PINMUX_GPIO(PJ4), 482 PINMUX_GPIO(PJ3), 483 PINMUX_GPIO(PJ2), 484 PINMUX_GPIO(PJ1), 485 }; 486 487 #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) 488 489 static const struct pinmux_func pinmux_func_gpios[] = { 490 /* FN */ 491 GPIO_FN(CDE), 492 GPIO_FN(ETH_MAGIC), 493 GPIO_FN(DISP), 494 GPIO_FN(ETH_LINK), 495 GPIO_FN(DR5), 496 GPIO_FN(ETH_TX_ER), 497 GPIO_FN(DR4), 498 GPIO_FN(ETH_TX_EN), 499 GPIO_FN(DR3), 500 GPIO_FN(ETH_TXD3), 501 GPIO_FN(DR2), 502 GPIO_FN(ETH_TXD2), 503 GPIO_FN(DR1), 504 GPIO_FN(ETH_TXD1), 505 GPIO_FN(DR0), 506 GPIO_FN(ETH_TXD0), 507 GPIO_FN(VSYNC), 508 GPIO_FN(HSPI_CLK), 509 GPIO_FN(ODDF), 510 GPIO_FN(HSPI_CS), 511 GPIO_FN(DG5), 512 GPIO_FN(ETH_MDIO), 513 GPIO_FN(DG4), 514 GPIO_FN(ETH_RX_CLK), 515 GPIO_FN(DG3), 516 GPIO_FN(ETH_MDC), 517 GPIO_FN(DG2), 518 GPIO_FN(ETH_COL), 519 GPIO_FN(DG1), 520 GPIO_FN(ETH_TX_CLK), 521 GPIO_FN(DG0), 522 GPIO_FN(ETH_CRS), 523 GPIO_FN(DCLKIN), 524 GPIO_FN(HSPI_RX), 525 GPIO_FN(HSYNC), 526 GPIO_FN(HSPI_TX), 527 GPIO_FN(DB5), 528 GPIO_FN(ETH_RXD3), 529 GPIO_FN(DB4), 530 GPIO_FN(ETH_RXD2), 531 GPIO_FN(DB3), 532 GPIO_FN(ETH_RXD1), 533 GPIO_FN(DB2), 534 GPIO_FN(ETH_RXD0), 535 GPIO_FN(DB1), 536 GPIO_FN(ETH_RX_DV), 537 GPIO_FN(DB0), 538 GPIO_FN(ETH_RX_ER), 539 GPIO_FN(DCLKOUT), 540 GPIO_FN(SCIF1_SCK), 541 GPIO_FN(SCIF1_RXD), 542 GPIO_FN(SCIF1_TXD), 543 GPIO_FN(DACK1), 544 GPIO_FN(BACK), 545 GPIO_FN(FALE), 546 GPIO_FN(DACK0), 547 GPIO_FN(FCLE), 548 GPIO_FN(DREQ1), 549 GPIO_FN(BREQ), 550 GPIO_FN(USB_OVC1), 551 GPIO_FN(DREQ0), 552 GPIO_FN(USB_OVC0), 553 GPIO_FN(USB_PENC1), 554 GPIO_FN(USB_PENC0), 555 GPIO_FN(HAC1_SDOUT), 556 GPIO_FN(SSI1_SDATA), 557 GPIO_FN(SDIF1CMD), 558 GPIO_FN(HAC1_SDIN), 559 GPIO_FN(SSI1_SCK), 560 GPIO_FN(SDIF1CD), 561 GPIO_FN(HAC1_SYNC), 562 GPIO_FN(SSI1_WS), 563 GPIO_FN(SDIF1WP), 564 GPIO_FN(HAC1_BITCLK), 565 GPIO_FN(SSI1_CLK), 566 GPIO_FN(SDIF1CLK), 567 GPIO_FN(HAC0_SDOUT), 568 GPIO_FN(SSI0_SDATA), 569 GPIO_FN(SDIF1D3), 570 GPIO_FN(HAC0_SDIN), 571 GPIO_FN(SSI0_SCK), 572 GPIO_FN(SDIF1D2), 573 GPIO_FN(HAC0_SYNC), 574 GPIO_FN(SSI0_WS), 575 GPIO_FN(SDIF1D1), 576 GPIO_FN(HAC0_BITCLK), 577 GPIO_FN(SSI0_CLK), 578 GPIO_FN(SDIF1D0), 579 GPIO_FN(SCIF3_SCK), 580 GPIO_FN(SSI2_SDATA), 581 GPIO_FN(SCIF3_RXD), 582 GPIO_FN(TCLK), 583 GPIO_FN(SSI2_SCK), 584 GPIO_FN(SCIF3_TXD), 585 GPIO_FN(HAC_RES), 586 GPIO_FN(SSI2_WS), 587 GPIO_FN(DACK3), 588 GPIO_FN(SDIF0CMD), 589 GPIO_FN(DACK2), 590 GPIO_FN(SDIF0CD), 591 GPIO_FN(DREQ3), 592 GPIO_FN(SDIF0WP), 593 GPIO_FN(SCIF0_CTS), 594 GPIO_FN(DREQ2), 595 GPIO_FN(SDIF0CLK), 596 GPIO_FN(SCIF0_RTS), 597 GPIO_FN(IRL7), 598 GPIO_FN(SDIF0D3), 599 GPIO_FN(SCIF0_SCK), 600 GPIO_FN(IRL6), 601 GPIO_FN(SDIF0D2), 602 GPIO_FN(SCIF0_RXD), 603 GPIO_FN(IRL5), 604 GPIO_FN(SDIF0D1), 605 GPIO_FN(SCIF0_TXD), 606 GPIO_FN(IRL4), 607 GPIO_FN(SDIF0D0), 608 GPIO_FN(SCIF5_SCK), 609 GPIO_FN(FRB), 610 GPIO_FN(SCIF5_RXD), 611 GPIO_FN(IOIS16), 612 GPIO_FN(SCIF5_TXD), 613 GPIO_FN(CE2B), 614 GPIO_FN(DRAK3), 615 GPIO_FN(CE2A), 616 GPIO_FN(SCIF4_SCK), 617 GPIO_FN(DRAK2), 618 GPIO_FN(SSI3_WS), 619 GPIO_FN(SCIF4_RXD), 620 GPIO_FN(DRAK1), 621 GPIO_FN(SSI3_SDATA), 622 GPIO_FN(FSTATUS), 623 GPIO_FN(SCIF4_TXD), 624 GPIO_FN(DRAK0), 625 GPIO_FN(SSI3_SCK), 626 GPIO_FN(FSE), 627 }; 628 629 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 630 { PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2, GROUP( 631 PA7_FN, PA7_OUT, PA7_IN, 0, 632 PA6_FN, PA6_OUT, PA6_IN, 0, 633 PA5_FN, PA5_OUT, PA5_IN, 0, 634 PA4_FN, PA4_OUT, PA4_IN, 0, 635 PA3_FN, PA3_OUT, PA3_IN, 0, 636 PA2_FN, PA2_OUT, PA2_IN, 0, 637 PA1_FN, PA1_OUT, PA1_IN, 0, 638 PA0_FN, PA0_OUT, PA0_IN, 0 )) 639 }, 640 { PINMUX_CFG_REG("PBCR", 0xffcc0002, 16, 2, GROUP( 641 PB7_FN, PB7_OUT, PB7_IN, 0, 642 PB6_FN, PB6_OUT, PB6_IN, 0, 643 PB5_FN, PB5_OUT, PB5_IN, 0, 644 PB4_FN, PB4_OUT, PB4_IN, 0, 645 PB3_FN, PB3_OUT, PB3_IN, 0, 646 PB2_FN, PB2_OUT, PB2_IN, 0, 647 PB1_FN, PB1_OUT, PB1_IN, 0, 648 PB0_FN, PB0_OUT, PB0_IN, 0 )) 649 }, 650 { PINMUX_CFG_REG("PCCR", 0xffcc0004, 16, 2, GROUP( 651 PC7_FN, PC7_OUT, PC7_IN, 0, 652 PC6_FN, PC6_OUT, PC6_IN, 0, 653 PC5_FN, PC5_OUT, PC5_IN, 0, 654 PC4_FN, PC4_OUT, PC4_IN, 0, 655 PC3_FN, PC3_OUT, PC3_IN, 0, 656 PC2_FN, PC2_OUT, PC2_IN, 0, 657 PC1_FN, PC1_OUT, PC1_IN, 0, 658 PC0_FN, PC0_OUT, PC0_IN, 0 )) 659 }, 660 { PINMUX_CFG_REG("PDCR", 0xffcc0006, 16, 2, GROUP( 661 PD7_FN, PD7_OUT, PD7_IN, 0, 662 PD6_FN, PD6_OUT, PD6_IN, 0, 663 PD5_FN, PD5_OUT, PD5_IN, 0, 664 PD4_FN, PD4_OUT, PD4_IN, 0, 665 PD3_FN, PD3_OUT, PD3_IN, 0, 666 PD2_FN, PD2_OUT, PD2_IN, 0, 667 PD1_FN, PD1_OUT, PD1_IN, 0, 668 PD0_FN, PD0_OUT, PD0_IN, 0 )) 669 }, 670 { PINMUX_CFG_REG("PECR", 0xffcc0008, 16, 2, GROUP( 671 PE7_FN, PE7_OUT, PE7_IN, 0, 672 PE6_FN, PE6_OUT, PE6_IN, 0, 673 0, 0, 0, 0, 674 0, 0, 0, 0, 675 0, 0, 0, 0, 676 0, 0, 0, 0, 677 0, 0, 0, 0, 678 0, 0, 0, 0, )) 679 }, 680 { PINMUX_CFG_REG("PFCR", 0xffcc000a, 16, 2, GROUP( 681 PF7_FN, PF7_OUT, PF7_IN, 0, 682 PF6_FN, PF6_OUT, PF6_IN, 0, 683 PF5_FN, PF5_OUT, PF5_IN, 0, 684 PF4_FN, PF4_OUT, PF4_IN, 0, 685 PF3_FN, PF3_OUT, PF3_IN, 0, 686 PF2_FN, PF2_OUT, PF2_IN, 0, 687 PF1_FN, PF1_OUT, PF1_IN, 0, 688 PF0_FN, PF0_OUT, PF0_IN, 0 )) 689 }, 690 { PINMUX_CFG_REG("PGCR", 0xffcc000c, 16, 2, GROUP( 691 PG7_FN, PG7_OUT, PG7_IN, 0, 692 PG6_FN, PG6_OUT, PG6_IN, 0, 693 PG5_FN, PG5_OUT, PG5_IN, 0, 694 0, 0, 0, 0, 695 0, 0, 0, 0, 696 0, 0, 0, 0, 697 0, 0, 0, 0, 698 0, 0, 0, 0, )) 699 }, 700 { PINMUX_CFG_REG("PHCR", 0xffcc000e, 16, 2, GROUP( 701 PH7_FN, PH7_OUT, PH7_IN, 0, 702 PH6_FN, PH6_OUT, PH6_IN, 0, 703 PH5_FN, PH5_OUT, PH5_IN, 0, 704 PH4_FN, PH4_OUT, PH4_IN, 0, 705 PH3_FN, PH3_OUT, PH3_IN, 0, 706 PH2_FN, PH2_OUT, PH2_IN, 0, 707 PH1_FN, PH1_OUT, PH1_IN, 0, 708 PH0_FN, PH0_OUT, PH0_IN, 0 )) 709 }, 710 { PINMUX_CFG_REG("PJCR", 0xffcc0010, 16, 2, GROUP( 711 PJ7_FN, PJ7_OUT, PJ7_IN, 0, 712 PJ6_FN, PJ6_OUT, PJ6_IN, 0, 713 PJ5_FN, PJ5_OUT, PJ5_IN, 0, 714 PJ4_FN, PJ4_OUT, PJ4_IN, 0, 715 PJ3_FN, PJ3_OUT, PJ3_IN, 0, 716 PJ2_FN, PJ2_OUT, PJ2_IN, 0, 717 PJ1_FN, PJ1_OUT, PJ1_IN, 0, 718 0, 0, 0, 0, )) 719 }, 720 { PINMUX_CFG_REG("P1MSELR", 0xffcc0080, 16, 1, GROUP( 721 0, 0, 722 P1MSEL14_0, P1MSEL14_1, 723 P1MSEL13_0, P1MSEL13_1, 724 P1MSEL12_0, P1MSEL12_1, 725 P1MSEL11_0, P1MSEL11_1, 726 P1MSEL10_0, P1MSEL10_1, 727 P1MSEL9_0, P1MSEL9_1, 728 P1MSEL8_0, P1MSEL8_1, 729 P1MSEL7_0, P1MSEL7_1, 730 P1MSEL6_0, P1MSEL6_1, 731 P1MSEL5_0, P1MSEL5_1, 732 P1MSEL4_0, P1MSEL4_1, 733 P1MSEL3_0, P1MSEL3_1, 734 P1MSEL2_0, P1MSEL2_1, 735 P1MSEL1_0, P1MSEL1_1, 736 P1MSEL0_0, P1MSEL0_1 )) 737 }, 738 { PINMUX_CFG_REG("P2MSELR", 0xffcc0082, 16, 1, GROUP( 739 P2MSEL15_0, P2MSEL15_1, 740 P2MSEL14_0, P2MSEL14_1, 741 P2MSEL13_0, P2MSEL13_1, 742 P2MSEL12_0, P2MSEL12_1, 743 P2MSEL11_0, P2MSEL11_1, 744 P2MSEL10_0, P2MSEL10_1, 745 P2MSEL9_0, P2MSEL9_1, 746 P2MSEL8_0, P2MSEL8_1, 747 P2MSEL7_0, P2MSEL7_1, 748 P2MSEL6_0, P2MSEL6_1, 749 P2MSEL5_0, P2MSEL5_1, 750 P2MSEL4_0, P2MSEL4_1, 751 P2MSEL3_0, P2MSEL3_1, 752 P2MSEL2_0, P2MSEL2_1, 753 P2MSEL1_0, P2MSEL1_1, 754 P2MSEL0_0, P2MSEL0_1 )) 755 }, 756 {} 757 }; 758 759 static const struct pinmux_data_reg pinmux_data_regs[] = { 760 { PINMUX_DATA_REG("PADR", 0xffcc0020, 8, GROUP( 761 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, 762 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA )) 763 }, 764 { PINMUX_DATA_REG("PBDR", 0xffcc0022, 8, GROUP( 765 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA, 766 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA )) 767 }, 768 { PINMUX_DATA_REG("PCDR", 0xffcc0024, 8, GROUP( 769 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA, 770 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA )) 771 }, 772 { PINMUX_DATA_REG("PDDR", 0xffcc0026, 8, GROUP( 773 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA, 774 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA )) 775 }, 776 { PINMUX_DATA_REG("PEDR", 0xffcc0028, 8, GROUP( 777 PE7_DATA, PE6_DATA, 778 0, 0, 0, 0, 0, 0 )) 779 }, 780 { PINMUX_DATA_REG("PFDR", 0xffcc002a, 8, GROUP( 781 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA, 782 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA )) 783 }, 784 { PINMUX_DATA_REG("PGDR", 0xffcc002c, 8, GROUP( 785 PG7_DATA, PG6_DATA, PG5_DATA, 0, 786 0, 0, 0, 0 )) 787 }, 788 { PINMUX_DATA_REG("PHDR", 0xffcc002e, 8, GROUP( 789 PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA, 790 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA )) 791 }, 792 { PINMUX_DATA_REG("PJDR", 0xffcc0030, 8, GROUP( 793 PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA, 794 PJ3_DATA, PJ2_DATA, PJ1_DATA, 0 )) 795 }, 796 { }, 797 }; 798 799 const struct sh_pfc_soc_info sh7786_pinmux_info = { 800 .name = "sh7786_pfc", 801 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 802 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 803 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 804 805 .pins = pinmux_pins, 806 .nr_pins = ARRAY_SIZE(pinmux_pins), 807 .func_gpios = pinmux_func_gpios, 808 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), 809 810 .cfg_regs = pinmux_config_regs, 811 .data_regs = pinmux_data_regs, 812 813 .pinmux_data = pinmux_data, 814 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 815 }; 816
