1 /*
2 * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 *
6 * Authors: Younghwan Joo <yhwan.joo@samsung.com>
7 * Sylwester Nawrocki <s.nawrocki@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13 #ifndef FIMC_IS_H_
14 #define FIMC_IS_H_
15
16 #include <asm/barrier.h>
17 #include <linux/clk.h>
18 #include <linux/device.h>
19 #include <linux/kernel.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/platform_device.h>
22 #include <linux/sizes.h>
23 #include <linux/spinlock.h>
24 #include <linux/types.h>
25 #include <media/videobuf2-v4l2.h>
26 #include <media/v4l2-ctrls.h>
27
28 #include "fimc-isp.h"
29 #include "fimc-is-command.h"
30 #include "fimc-is-sensor.h"
31 #include "fimc-is-param.h"
32 #include "fimc-is-regs.h"
33
34 #define FIMC_IS_DRV_NAME "exynos4-fimc-is"
35
36 #define FIMC_IS_FW_FILENAME "exynos4_fimc_is_fw.bin"
37 #define FIMC_IS_SETFILE_6A3 "exynos4_s5k6a3_setfile.bin"
38
39 #define FIMC_IS_FW_LOAD_TIMEOUT 1000 /* ms */
40 #define FIMC_IS_POWER_ON_TIMEOUT 1000 /* us */
41
42 #define FIMC_IS_SENSORS_NUM 2
43
44 /* Memory definitions */
45 #define FIMC_IS_CPU_MEM_SIZE (0xa00000)
46 #define FIMC_IS_CPU_BASE_MASK ((1 << 26) - 1)
47 #define FIMC_IS_REGION_SIZE 0x5000
48
49 #define FIMC_IS_DEBUG_REGION_OFFSET 0x0084b000
50 #define FIMC_IS_SHARED_REGION_OFFSET 0x008c0000
51 #define FIMC_IS_FW_INFO_LEN 31
52 #define FIMC_IS_FW_VER_LEN 7
53 #define FIMC_IS_FW_DESC_LEN (FIMC_IS_FW_INFO_LEN + \
54 FIMC_IS_FW_VER_LEN)
55 #define FIMC_IS_SETFILE_INFO_LEN 39
56
57 #define FIMC_IS_EXTRA_MEM_SIZE (FIMC_IS_EXTRA_FW_SIZE + \
58 FIMC_IS_EXTRA_SETFILE_SIZE + 0x1000)
59 #define FIMC_IS_EXTRA_FW_SIZE 0x180000
60 #define FIMC_IS_EXTRA_SETFILE_SIZE 0x4b000
61
62 /* TODO: revisit */
63 #define FIMC_IS_FW_ADDR_MASK ((1 << 26) - 1)
64 #define FIMC_IS_FW_SIZE_MAX (SZ_4M)
65 #define FIMC_IS_FW_SIZE_MIN (SZ_32K)
66
67 #define ATCLK_MCUISP_FREQUENCY 100000000UL
68 #define ACLK_AXI_FREQUENCY 100000000UL
69
70 enum {
71 ISS_CLK_PPMUISPX,
72 ISS_CLK_PPMUISPMX,
73 ISS_CLK_LITE0,
74 ISS_CLK_LITE1,
75 ISS_CLK_MPLL,
76 ISS_CLK_ISP,
77 ISS_CLK_DRC,
78 ISS_CLK_FD,
79 ISS_CLK_MCUISP,
80 ISS_CLK_GICISP,
81 ISS_CLK_PWM_ISP,
82 ISS_CLK_MCUCTL_ISP,
83 ISS_CLK_UART,
84 ISS_GATE_CLKS_MAX,
85 ISS_CLK_ISP_DIV0 = ISS_GATE_CLKS_MAX,
86 ISS_CLK_ISP_DIV1,
87 ISS_CLK_MCUISP_DIV0,
88 ISS_CLK_MCUISP_DIV1,
89 ISS_CLK_ACLK200,
90 ISS_CLK_ACLK200_DIV,
91 ISS_CLK_ACLK400MCUISP,
92 ISS_CLK_ACLK400MCUISP_DIV,
93 ISS_CLKS_MAX
94 };
95
96 /* The driver's internal state flags */
97 enum {
98 IS_ST_IDLE,
99 IS_ST_PWR_ON,
100 IS_ST_A5_PWR_ON,
101 IS_ST_FW_LOADED,
102 IS_ST_OPEN_SENSOR,
103 IS_ST_SETFILE_LOADED,
104 IS_ST_INIT_DONE,
105 IS_ST_STREAM_ON,
106 IS_ST_STREAM_OFF,
107 IS_ST_CHANGE_MODE,
108 IS_ST_BLOCK_CMD_CLEARED,
109 IS_ST_SET_ZOOM,
110 IS_ST_PWR_SUBIP_ON,
111 IS_ST_END,
112 };
113
114 enum af_state {
115 FIMC_IS_AF_IDLE = 0,
116 FIMC_IS_AF_SETCONFIG = 1,
117 FIMC_IS_AF_RUNNING = 2,
118 FIMC_IS_AF_LOCK = 3,
119 FIMC_IS_AF_ABORT = 4,
120 FIMC_IS_AF_FAILED = 5,
121 };
122
123 enum af_lock_state {
124 FIMC_IS_AF_UNLOCKED = 0,
125 FIMC_IS_AF_LOCKED = 2
126 };
127
128 enum ae_lock_state {
129 FIMC_IS_AE_UNLOCKED = 0,
130 FIMC_IS_AE_LOCKED = 1
131 };
132
133 enum awb_lock_state {
134 FIMC_IS_AWB_UNLOCKED = 0,
135 FIMC_IS_AWB_LOCKED = 1
136 };
137
138 enum {
139 IS_METERING_CONFIG_CMD,
140 IS_METERING_CONFIG_WIN_POS_X,
141 IS_METERING_CONFIG_WIN_POS_Y,
142 IS_METERING_CONFIG_WIN_WIDTH,
143 IS_METERING_CONFIG_WIN_HEIGHT,
144 IS_METERING_CONFIG_MAX
145 };
146
147 struct is_setfile {
148 const struct firmware *info;
149 int state;
150 u32 sub_index;
151 u32 base;
152 size_t size;
153 };
154
155 struct is_fd_result_header {
156 u32 offset;
157 u32 count;
158 u32 index;
159 u32 curr_index;
160 u32 width;
161 u32 height;
162 };
163
164 struct is_af_info {
165 u16 mode;
166 u32 af_state;
167 u32 af_lock_state;
168 u32 ae_lock_state;
169 u32 awb_lock_state;
170 u16 pos_x;
171 u16 pos_y;
172 u16 prev_pos_x;
173 u16 prev_pos_y;
174 u16 use_af;
175 };
176
177 struct fimc_is_firmware {
178 const struct firmware *f_w;
179
180 dma_addr_t paddr;
181 void *vaddr;
182 unsigned int size;
183
184 char info[FIMC_IS_FW_INFO_LEN + 1];
185 char version[FIMC_IS_FW_VER_LEN + 1];
186 char setfile_info[FIMC_IS_SETFILE_INFO_LEN + 1];
187 u8 state;
188 };
189
190 struct fimc_is_memory {
191 /* physical base address */
192 dma_addr_t paddr;
193 /* virtual base address */
194 void *vaddr;
195 /* total length */
196 unsigned int size;
197 };
198
199 #define FIMC_IS_I2H_MAX_ARGS 12
200
201 struct i2h_cmd {
202 u32 cmd;
203 u32 sensor_id;
204 u16 num_args;
205 u32 args[FIMC_IS_I2H_MAX_ARGS];
206 };
207
208 struct h2i_cmd {
209 u16 cmd_type;
210 u32 entry_id;
211 };
212
213 #define FIMC_IS_DEBUG_MSG 0x3f
214 #define FIMC_IS_DEBUG_LEVEL 3
215
216 struct fimc_is_setfile {
217 const struct firmware *info;
218 unsigned int state;
219 unsigned int size;
220 u32 sub_index;
221 u32 base;
222 };
223
224 struct chain_config {
225 struct global_param global;
226 struct sensor_param sensor;
227 struct isp_param isp;
228 struct drc_param drc;
229 struct fd_param fd;
230
231 unsigned long p_region_index[2];
232 };
233
234 /**
235 * struct fimc_is - fimc-is data structure
236 * @pdev: pointer to FIMC-IS platform device
237 * @pctrl: pointer to pinctrl structure for this device
238 * @v4l2_dev: pointer to top the level v4l2_device
239 * @lock: mutex serializing video device and the subdev operations
240 * @slock: spinlock protecting this data structure and the hw registers
241 * @clocks: FIMC-LITE gate clock
242 * @regs: MCUCTL mmapped registers region
243 * @pmu_regs: PMU ISP mmapped registers region
244 * @irq_queue: interrupt handling waitqueue
245 * @lpm: low power mode flag
246 * @state: internal driver's state flags
247 */
248 struct fimc_is {
249 struct platform_device *pdev;
250 struct pinctrl *pctrl;
251 struct v4l2_device *v4l2_dev;
252
253 struct fimc_is_firmware fw;
254 struct fimc_is_memory memory;
255 struct firmware *f_w;
256
257 struct fimc_isp isp;
258 struct fimc_is_sensor sensor[FIMC_IS_SENSORS_NUM];
259 struct fimc_is_setfile setfile;
260
261 struct v4l2_ctrl_handler ctrl_handler;
262
263 struct mutex lock;
264 spinlock_t slock;
265
266 struct clk *clocks[ISS_CLKS_MAX];
267 void __iomem *regs;
268 void __iomem *pmu_regs;
269 int irq;
270 wait_queue_head_t irq_queue;
271 u8 lpm;
272
273 unsigned long state;
274 unsigned int sensor_index;
275
276 struct i2h_cmd i2h_cmd;
277 struct h2i_cmd h2i_cmd;
278 struct is_fd_result_header fd_header;
279
280 struct chain_config config[IS_SC_MAX];
281 unsigned config_index;
282
283 struct is_region *is_p_region;
284 dma_addr_t is_dma_p_region;
285 struct is_share_region *is_shared_region;
286 struct is_af_info af;
287
288 struct dentry *debugfs_entry;
289 };
290
fimc_isp_to_is(struct fimc_isp * isp)291 static inline struct fimc_is *fimc_isp_to_is(struct fimc_isp *isp)
292 {
293 return container_of(isp, struct fimc_is, isp);
294 }
295
__get_curr_is_config(struct fimc_is * is)296 static inline struct chain_config *__get_curr_is_config(struct fimc_is *is)
297 {
298 return &is->config[is->config_index];
299 }
300
fimc_is_mem_barrier(void)301 static inline void fimc_is_mem_barrier(void)
302 {
303 mb();
304 }
305
fimc_is_set_param_bit(struct fimc_is * is,int num)306 static inline void fimc_is_set_param_bit(struct fimc_is *is, int num)
307 {
308 struct chain_config *cfg = &is->config[is->config_index];
309
310 set_bit(num, &cfg->p_region_index[0]);
311 }
312
fimc_is_set_param_ctrl_cmd(struct fimc_is * is,int cmd)313 static inline void fimc_is_set_param_ctrl_cmd(struct fimc_is *is, int cmd)
314 {
315 is->is_p_region->parameter.isp.control.cmd = cmd;
316 }
317
mcuctl_write(u32 v,struct fimc_is * is,unsigned int offset)318 static inline void mcuctl_write(u32 v, struct fimc_is *is, unsigned int offset)
319 {
320 writel(v, is->regs + offset);
321 }
322
mcuctl_read(struct fimc_is * is,unsigned int offset)323 static inline u32 mcuctl_read(struct fimc_is *is, unsigned int offset)
324 {
325 return readl(is->regs + offset);
326 }
327
pmuisp_write(u32 v,struct fimc_is * is,unsigned int offset)328 static inline void pmuisp_write(u32 v, struct fimc_is *is, unsigned int offset)
329 {
330 writel(v, is->pmu_regs + offset);
331 }
332
pmuisp_read(struct fimc_is * is,unsigned int offset)333 static inline u32 pmuisp_read(struct fimc_is *is, unsigned int offset)
334 {
335 return readl(is->pmu_regs + offset);
336 }
337
338 int fimc_is_wait_event(struct fimc_is *is, unsigned long bit,
339 unsigned int state, unsigned int timeout);
340 int fimc_is_cpu_set_power(struct fimc_is *is, int on);
341 int fimc_is_start_firmware(struct fimc_is *is);
342 int fimc_is_hw_initialize(struct fimc_is *is);
343 void fimc_is_log_dump(const char *level, const void *buf, size_t len);
344
345 #endif /* FIMC_IS_H_ */
346
