1 /*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright(c) 2012 Intel Corporation. All rights reserved.
8 * Copyright (C) 2015 EMC Corporation. All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * BSD LICENSE
15 *
16 * Copyright(c) 2012 Intel Corporation. All rights reserved.
17 * Copyright (C) 2015 EMC Corporation. All Rights Reserved.
18 *
19 * Redistribution and use in source and binary forms, with or without
20 * modification, are permitted provided that the following conditions
21 * are met:
22 *
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copy
26 * notice, this list of conditions and the following disclaimer in
27 * the documentation and/or other materials provided with the
28 * distribution.
29 * * Neither the name of Intel Corporation nor the names of its
30 * contributors may be used to endorse or promote products derived
31 * from this software without specific prior written permission.
32 *
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
34 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
35 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
36 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
37 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
38 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
39 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
40 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
41 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
42 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
43 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 *
45 * Intel PCIe NTB Linux driver
46 *
47 * Contact Information:
48 * Jon Mason <jon.mason@intel.com>
49 */
50
51 #ifndef NTB_HW_INTEL_H
52 #define NTB_HW_INTEL_H
53
54 #include <linux/ntb.h>
55 #include <linux/pci.h>
56 #include <linux/io-64-nonatomic-lo-hi.h>
57
58 /* PCI device IDs */
59 #define PCI_DEVICE_ID_INTEL_NTB_B2B_JSF 0x3725
60 #define PCI_DEVICE_ID_INTEL_NTB_PS_JSF 0x3726
61 #define PCI_DEVICE_ID_INTEL_NTB_SS_JSF 0x3727
62 #define PCI_DEVICE_ID_INTEL_NTB_B2B_SNB 0x3C0D
63 #define PCI_DEVICE_ID_INTEL_NTB_PS_SNB 0x3C0E
64 #define PCI_DEVICE_ID_INTEL_NTB_SS_SNB 0x3C0F
65 #define PCI_DEVICE_ID_INTEL_NTB_B2B_IVT 0x0E0D
66 #define PCI_DEVICE_ID_INTEL_NTB_PS_IVT 0x0E0E
67 #define PCI_DEVICE_ID_INTEL_NTB_SS_IVT 0x0E0F
68 #define PCI_DEVICE_ID_INTEL_NTB_B2B_HSX 0x2F0D
69 #define PCI_DEVICE_ID_INTEL_NTB_PS_HSX 0x2F0E
70 #define PCI_DEVICE_ID_INTEL_NTB_SS_HSX 0x2F0F
71 #define PCI_DEVICE_ID_INTEL_NTB_B2B_BDX 0x6F0D
72 #define PCI_DEVICE_ID_INTEL_NTB_PS_BDX 0x6F0E
73 #define PCI_DEVICE_ID_INTEL_NTB_SS_BDX 0x6F0F
74 #define PCI_DEVICE_ID_INTEL_NTB_B2B_SKX 0x201C
75 #define PCI_DEVICE_ID_INTEL_NTB_B2B_ICX 0x347e
76
77 /* Ntb control and link status */
78 #define NTB_CTL_CFG_LOCK BIT(0)
79 #define NTB_CTL_DISABLE BIT(1)
80 #define NTB_CTL_S2P_BAR2_SNOOP BIT(2)
81 #define NTB_CTL_P2S_BAR2_SNOOP BIT(4)
82 #define NTB_CTL_S2P_BAR4_SNOOP BIT(6)
83 #define NTB_CTL_P2S_BAR4_SNOOP BIT(8)
84 #define NTB_CTL_S2P_BAR5_SNOOP BIT(12)
85 #define NTB_CTL_P2S_BAR5_SNOOP BIT(14)
86
87 #define NTB_LNK_STA_ACTIVE_BIT 0x2000
88 #define NTB_LNK_STA_SPEED_MASK 0x000f
89 #define NTB_LNK_STA_WIDTH_MASK 0x03f0
90 #define NTB_LNK_STA_ACTIVE(x) (!!((x) & NTB_LNK_STA_ACTIVE_BIT))
91 #define NTB_LNK_STA_SPEED(x) ((x) & NTB_LNK_STA_SPEED_MASK)
92 #define NTB_LNK_STA_WIDTH(x) (((x) & NTB_LNK_STA_WIDTH_MASK) >> 4)
93
94 /* flags to indicate unsafe api */
95 #define NTB_UNSAFE_DB BIT_ULL(0)
96 #define NTB_UNSAFE_SPAD BIT_ULL(1)
97
98 #define NTB_BAR_MASK_64 ~(0xfull)
99 #define NTB_BAR_MASK_32 ~(0xfu)
100
101 struct intel_ntb_dev;
102
103 struct intel_ntb_reg {
104 int (*poll_link)(struct intel_ntb_dev *ndev);
105 int (*link_is_up)(struct intel_ntb_dev *ndev);
106 u64 (*db_ioread)(const void __iomem *mmio);
107 void (*db_iowrite)(u64 db_bits, void __iomem *mmio);
108 unsigned long ntb_ctl;
109 resource_size_t db_size;
110 int mw_bar[];
111 };
112
113 struct intel_ntb_alt_reg {
114 unsigned long db_bell;
115 unsigned long db_mask;
116 unsigned long db_clear;
117 unsigned long spad;
118 };
119
120 struct intel_ntb_xlat_reg {
121 unsigned long bar0_base;
122 unsigned long bar2_xlat;
123 unsigned long bar2_limit;
124 unsigned short bar2_idx;
125 };
126
127 struct intel_b2b_addr {
128 phys_addr_t bar0_addr;
129 phys_addr_t bar2_addr64;
130 phys_addr_t bar4_addr64;
131 phys_addr_t bar4_addr32;
132 phys_addr_t bar5_addr32;
133 };
134
135 struct intel_ntb_vec {
136 struct intel_ntb_dev *ndev;
137 int num;
138 };
139
140 struct intel_ntb_dev {
141 struct ntb_dev ntb;
142
143 /* offset of peer bar0 in b2b bar */
144 unsigned long b2b_off;
145 /* mw idx used to access peer bar0 */
146 unsigned int b2b_idx;
147
148 /* BAR45 is split into BAR4 and BAR5 */
149 bool bar4_split;
150
151 u32 ntb_ctl;
152 u32 lnk_sta;
153
154 unsigned char mw_count;
155 unsigned char spad_count;
156 unsigned char db_count;
157 unsigned char db_vec_count;
158 unsigned char db_vec_shift;
159
160 u64 db_valid_mask;
161 u64 db_link_mask;
162 u64 db_mask;
163
164 /* synchronize rmw access of db_mask and hw reg */
165 spinlock_t db_mask_lock;
166
167 struct msix_entry *msix;
168 struct intel_ntb_vec *vec;
169
170 const struct intel_ntb_reg *reg;
171 const struct intel_ntb_alt_reg *self_reg;
172 const struct intel_ntb_alt_reg *peer_reg;
173 const struct intel_ntb_xlat_reg *xlat_reg;
174 void __iomem *self_mmio;
175 void __iomem *peer_mmio;
176 phys_addr_t peer_addr;
177
178 unsigned long last_ts;
179 struct delayed_work hb_timer;
180
181 unsigned long hwerr_flags;
182 unsigned long unsafe_flags;
183 unsigned long unsafe_flags_ignore;
184
185 struct dentry *debugfs_dir;
186 struct dentry *debugfs_info;
187
188 /* gen4 entries */
189 int dev_up;
190 };
191
192 #define ntb_ndev(__ntb) container_of(__ntb, struct intel_ntb_dev, ntb)
193 #define hb_ndev(__work) container_of(__work, struct intel_ntb_dev, \
194 hb_timer.work)
195
pdev_is_gen1(struct pci_dev * pdev)196 static inline int pdev_is_gen1(struct pci_dev *pdev)
197 {
198 switch (pdev->device) {
199 case PCI_DEVICE_ID_INTEL_NTB_SS_JSF:
200 case PCI_DEVICE_ID_INTEL_NTB_SS_SNB:
201 case PCI_DEVICE_ID_INTEL_NTB_SS_IVT:
202 case PCI_DEVICE_ID_INTEL_NTB_SS_HSX:
203 case PCI_DEVICE_ID_INTEL_NTB_SS_BDX:
204 case PCI_DEVICE_ID_INTEL_NTB_PS_JSF:
205 case PCI_DEVICE_ID_INTEL_NTB_PS_SNB:
206 case PCI_DEVICE_ID_INTEL_NTB_PS_IVT:
207 case PCI_DEVICE_ID_INTEL_NTB_PS_HSX:
208 case PCI_DEVICE_ID_INTEL_NTB_PS_BDX:
209 case PCI_DEVICE_ID_INTEL_NTB_B2B_JSF:
210 case PCI_DEVICE_ID_INTEL_NTB_B2B_SNB:
211 case PCI_DEVICE_ID_INTEL_NTB_B2B_IVT:
212 case PCI_DEVICE_ID_INTEL_NTB_B2B_HSX:
213 case PCI_DEVICE_ID_INTEL_NTB_B2B_BDX:
214 return 1;
215 }
216 return 0;
217 }
218
pdev_is_gen3(struct pci_dev * pdev)219 static inline int pdev_is_gen3(struct pci_dev *pdev)
220 {
221 if (pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_SKX)
222 return 1;
223
224 return 0;
225 }
226
pdev_is_gen4(struct pci_dev * pdev)227 static inline int pdev_is_gen4(struct pci_dev *pdev)
228 {
229 if (pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_ICX)
230 return 1;
231
232 return 0;
233 }
234 #endif
235
