1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013 BayHub Technology Ltd.
4 *
5 * Authors: Peter Guo <peter.guo@bayhubtech.com>
6 * Adam Lee <adam.lee@canonical.com>
7 * Ernest Zhang <ernest.zhang@bayhubtech.com>
8 */
9
10 #include <linux/pci.h>
11 #include <linux/mmc/host.h>
12 #include <linux/mmc/mmc.h>
13 #include <linux/delay.h>
14 #include <linux/iopoll.h>
15 #include <linux/bitfield.h>
16
17 #include "sdhci.h"
18 #include "sdhci-pci.h"
19
20 /*
21 * O2Micro device registers
22 */
23
24 #define O2_SD_MISC_REG5 0x64
25 #define O2_SD_LD0_CTRL 0x68
26 #define O2_SD_DEV_CTRL 0x88
27 #define O2_SD_LOCK_WP 0xD3
28 #define O2_SD_TEST_REG 0xD4
29 #define O2_SD_FUNC_REG0 0xDC
30 #define O2_SD_MULTI_VCC3V 0xEE
31 #define O2_SD_CLKREQ 0xEC
32 #define O2_SD_CAPS 0xE0
33 #define O2_SD_ADMA1 0xE2
34 #define O2_SD_ADMA2 0xE7
35 #define O2_SD_MISC_CTRL2 0xF0
36 #define O2_SD_INF_MOD 0xF1
37 #define O2_SD_MISC_CTRL4 0xFC
38 #define O2_SD_MISC_CTRL 0x1C0
39 #define O2_SD_PWR_FORCE_L0 0x0002
40 #define O2_SD_TUNING_CTRL 0x300
41 #define O2_SD_PLL_SETTING 0x304
42 #define O2_SD_MISC_SETTING 0x308
43 #define O2_SD_CLK_SETTING 0x328
44 #define O2_SD_CAP_REG2 0x330
45 #define O2_SD_CAP_REG0 0x334
46 #define O2_SD_UHS1_CAP_SETTING 0x33C
47 #define O2_SD_DELAY_CTRL 0x350
48 #define O2_SD_OUTPUT_CLK_SOURCE_SWITCH 0x354
49 #define O2_SD_UHS2_L1_CTRL 0x35C
50 #define O2_SD_FUNC_REG3 0x3E0
51 #define O2_SD_FUNC_REG4 0x3E4
52 #define O2_SD_LED_ENABLE BIT(6)
53 #define O2_SD_FREG0_LEDOFF BIT(13)
54 #define O2_SD_SEL_DLL BIT(16)
55 #define O2_SD_FREG4_ENABLE_CLK_SET BIT(22)
56 #define O2_SD_PHASE_MASK GENMASK(23, 20)
57 #define O2_SD_FIX_PHASE FIELD_PREP(O2_SD_PHASE_MASK, 0x9)
58
59 #define O2_SD_VENDOR_SETTING 0x110
60 #define O2_SD_VENDOR_SETTING2 0x1C8
61 #define O2_SD_HW_TUNING_DISABLE BIT(4)
62
63 #define O2_PLL_DLL_WDT_CONTROL1 0x1CC
64 #define O2_PLL_FORCE_ACTIVE BIT(18)
65 #define O2_PLL_LOCK_STATUS BIT(14)
66 #define O2_PLL_SOFT_RESET BIT(12)
67 #define O2_DLL_LOCK_STATUS BIT(11)
68
69 #define O2_SD_DETECT_SETTING 0x324
70
71 static const u32 dmdn_table[] = {0x2B1C0000,
72 0x2C1A0000, 0x371B0000, 0x35100000};
73 #define DMDN_SZ ARRAY_SIZE(dmdn_table)
74
75 struct o2_host {
76 u8 dll_adjust_count;
77 };
78
sdhci_o2_wait_card_detect_stable(struct sdhci_host * host)79 static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host)
80 {
81 ktime_t timeout;
82 u32 scratch32;
83
84 /* Wait max 50 ms */
85 timeout = ktime_add_ms(ktime_get(), 50);
86 while (1) {
87 bool timedout = ktime_after(ktime_get(), timeout);
88
89 scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE);
90 if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT
91 == (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT)
92 break;
93
94 if (timedout) {
95 pr_err("%s: Card Detect debounce never finished.\n",
96 mmc_hostname(host->mmc));
97 sdhci_dumpregs(host);
98 return;
99 }
100 udelay(10);
101 }
102 }
103
sdhci_o2_enable_internal_clock(struct sdhci_host * host)104 static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)
105 {
106 ktime_t timeout;
107 u16 scratch;
108 u32 scratch32;
109
110 /* PLL software reset */
111 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
112 scratch32 |= O2_PLL_SOFT_RESET;
113 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
114 udelay(1);
115 scratch32 &= ~(O2_PLL_SOFT_RESET);
116 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
117
118 /* PLL force active */
119 scratch32 |= O2_PLL_FORCE_ACTIVE;
120 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
121
122 /* Wait max 20 ms */
123 timeout = ktime_add_ms(ktime_get(), 20);
124 while (1) {
125 bool timedout = ktime_after(ktime_get(), timeout);
126
127 scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1);
128 if (scratch & O2_PLL_LOCK_STATUS)
129 break;
130 if (timedout) {
131 pr_err("%s: Internal clock never stabilised.\n",
132 mmc_hostname(host->mmc));
133 sdhci_dumpregs(host);
134 goto out;
135 }
136 udelay(10);
137 }
138
139 /* Wait for card detect finish */
140 udelay(1);
141 sdhci_o2_wait_card_detect_stable(host);
142
143 out:
144 /* Cancel PLL force active */
145 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
146 scratch32 &= ~O2_PLL_FORCE_ACTIVE;
147 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
148 }
149
sdhci_o2_get_cd(struct mmc_host * mmc)150 static int sdhci_o2_get_cd(struct mmc_host *mmc)
151 {
152 struct sdhci_host *host = mmc_priv(mmc);
153
154 if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS))
155 sdhci_o2_enable_internal_clock(host);
156 else
157 sdhci_o2_wait_card_detect_stable(host);
158
159 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
160 }
161
o2_pci_set_baseclk(struct sdhci_pci_chip * chip,u32 value)162 static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
163 {
164 u32 scratch_32;
165
166 pci_read_config_dword(chip->pdev,
167 O2_SD_PLL_SETTING, &scratch_32);
168
169 scratch_32 &= 0x0000FFFF;
170 scratch_32 |= value;
171
172 pci_write_config_dword(chip->pdev,
173 O2_SD_PLL_SETTING, scratch_32);
174 }
175
sdhci_o2_pll_dll_wdt_control(struct sdhci_host * host)176 static u32 sdhci_o2_pll_dll_wdt_control(struct sdhci_host *host)
177 {
178 return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
179 }
180
181 /*
182 * This function is used to detect dll lock status.
183 * Since the dll lock status bit will toggle randomly
184 * with very short interval which needs to be polled
185 * as fast as possible. Set sleep_us as 1 microsecond.
186 */
sdhci_o2_wait_dll_detect_lock(struct sdhci_host * host)187 static int sdhci_o2_wait_dll_detect_lock(struct sdhci_host *host)
188 {
189 u32 scratch32 = 0;
190
191 return readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host,
192 scratch32, !(scratch32 & O2_DLL_LOCK_STATUS), 1, 1000000);
193 }
194
sdhci_o2_set_tuning_mode(struct sdhci_host * host)195 static void sdhci_o2_set_tuning_mode(struct sdhci_host *host)
196 {
197 u16 reg;
198
199 /* enable hardware tuning */
200 reg = sdhci_readw(host, O2_SD_VENDOR_SETTING);
201 reg &= ~O2_SD_HW_TUNING_DISABLE;
202 sdhci_writew(host, reg, O2_SD_VENDOR_SETTING);
203 }
204
__sdhci_o2_execute_tuning(struct sdhci_host * host,u32 opcode)205 static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode)
206 {
207 int i;
208
209 sdhci_send_tuning(host, opcode);
210
211 for (i = 0; i < 150; i++) {
212 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
213
214 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
215 if (ctrl & SDHCI_CTRL_TUNED_CLK) {
216 host->tuning_done = true;
217 return;
218 }
219 pr_warn("%s: HW tuning failed !\n",
220 mmc_hostname(host->mmc));
221 break;
222 }
223
224 mdelay(1);
225 }
226
227 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
228 mmc_hostname(host->mmc));
229 sdhci_reset_tuning(host);
230 }
231
232 /*
233 * This function is used to fix o2 dll shift issue.
234 * It isn't necessary to detect card present before recovery.
235 * Firstly, it is used by bht emmc card, which is embedded.
236 * Second, before call recovery card present will be detected
237 * outside of the execute tuning function.
238 */
sdhci_o2_dll_recovery(struct sdhci_host * host)239 static int sdhci_o2_dll_recovery(struct sdhci_host *host)
240 {
241 int ret = 0;
242 u8 scratch_8 = 0;
243 u32 scratch_32 = 0;
244 struct sdhci_pci_slot *slot = sdhci_priv(host);
245 struct sdhci_pci_chip *chip = slot->chip;
246 struct o2_host *o2_host = sdhci_pci_priv(slot);
247
248 /* UnLock WP */
249 pci_read_config_byte(chip->pdev,
250 O2_SD_LOCK_WP, &scratch_8);
251 scratch_8 &= 0x7f;
252 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
253 while (o2_host->dll_adjust_count < DMDN_SZ && !ret) {
254 /* Disable clock */
255 sdhci_writeb(host, 0, SDHCI_CLOCK_CONTROL);
256
257 /* PLL software reset */
258 scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
259 scratch_32 |= O2_PLL_SOFT_RESET;
260 sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1);
261
262 pci_read_config_dword(chip->pdev,
263 O2_SD_FUNC_REG4,
264 &scratch_32);
265 /* Enable Base Clk setting change */
266 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
267 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32);
268 o2_pci_set_baseclk(chip, dmdn_table[o2_host->dll_adjust_count]);
269
270 /* Enable internal clock */
271 scratch_8 = SDHCI_CLOCK_INT_EN;
272 sdhci_writeb(host, scratch_8, SDHCI_CLOCK_CONTROL);
273
274 if (sdhci_o2_get_cd(host->mmc)) {
275 /*
276 * need wait at least 5ms for dll status stable,
277 * after enable internal clock
278 */
279 usleep_range(5000, 6000);
280 if (sdhci_o2_wait_dll_detect_lock(host)) {
281 scratch_8 |= SDHCI_CLOCK_CARD_EN;
282 sdhci_writeb(host, scratch_8,
283 SDHCI_CLOCK_CONTROL);
284 ret = 1;
285 } else {
286 pr_warn("%s: DLL unlocked when dll_adjust_count is %d.\n",
287 mmc_hostname(host->mmc),
288 o2_host->dll_adjust_count);
289 }
290 } else {
291 pr_err("%s: card present detect failed.\n",
292 mmc_hostname(host->mmc));
293 break;
294 }
295
296 o2_host->dll_adjust_count++;
297 }
298 if (!ret && o2_host->dll_adjust_count == DMDN_SZ)
299 pr_err("%s: DLL adjust over max times\n",
300 mmc_hostname(host->mmc));
301 /* Lock WP */
302 pci_read_config_byte(chip->pdev,
303 O2_SD_LOCK_WP, &scratch_8);
304 scratch_8 |= 0x80;
305 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
306 return ret;
307 }
308
sdhci_o2_execute_tuning(struct mmc_host * mmc,u32 opcode)309 static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
310 {
311 struct sdhci_host *host = mmc_priv(mmc);
312 struct sdhci_pci_slot *slot = sdhci_priv(host);
313 struct sdhci_pci_chip *chip = slot->chip;
314 int current_bus_width = 0;
315 u32 scratch32 = 0;
316 u16 scratch = 0;
317 u8 scratch_8 = 0;
318 u32 reg_val;
319
320 /*
321 * This handler implements the hardware tuning that is specific to
322 * this controller. Fall back to the standard method for other TIMING.
323 */
324 if ((host->timing != MMC_TIMING_MMC_HS200) &&
325 (host->timing != MMC_TIMING_UHS_SDR104) &&
326 (host->timing != MMC_TIMING_UHS_SDR50))
327 return sdhci_execute_tuning(mmc, opcode);
328
329 if (WARN_ON((opcode != MMC_SEND_TUNING_BLOCK_HS200) &&
330 (opcode != MMC_SEND_TUNING_BLOCK)))
331 return -EINVAL;
332
333 /* Force power mode enter L0 */
334 scratch = sdhci_readw(host, O2_SD_MISC_CTRL);
335 scratch |= O2_SD_PWR_FORCE_L0;
336 sdhci_writew(host, scratch, O2_SD_MISC_CTRL);
337
338 /* Stop clk */
339 reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
340 reg_val &= ~SDHCI_CLOCK_CARD_EN;
341 sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL);
342
343 /* UnLock WP */
344 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
345 scratch_8 &= 0x7f;
346 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
347
348 /* Set pcr 0x354[16] to choose dll clock, and set the default phase */
349 pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, ®_val);
350 reg_val &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK);
351 reg_val |= (O2_SD_SEL_DLL | O2_SD_FIX_PHASE);
352 pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, reg_val);
353
354 /* Lock WP */
355 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch_8);
356 scratch_8 |= 0x80;
357 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
358
359 /* Start clk */
360 reg_val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
361 reg_val |= SDHCI_CLOCK_CARD_EN;
362 sdhci_writew(host, reg_val, SDHCI_CLOCK_CONTROL);
363
364 /* wait DLL lock, timeout value 5ms */
365 if (readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host,
366 scratch32, (scratch32 & O2_DLL_LOCK_STATUS), 1, 5000))
367 pr_warn("%s: DLL can't lock in 5ms after force L0 during tuning.\n",
368 mmc_hostname(host->mmc));
369 /*
370 * Judge the tuning reason, whether caused by dll shift
371 * If cause by dll shift, should call sdhci_o2_dll_recovery
372 */
373 if (!sdhci_o2_wait_dll_detect_lock(host))
374 if (!sdhci_o2_dll_recovery(host)) {
375 pr_err("%s: o2 dll recovery failed\n",
376 mmc_hostname(host->mmc));
377 return -EINVAL;
378 }
379 /*
380 * o2 sdhci host didn't support 8bit emmc tuning
381 */
382 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
383 current_bus_width = mmc->ios.bus_width;
384 mmc->ios.bus_width = MMC_BUS_WIDTH_4;
385 sdhci_set_bus_width(host, MMC_BUS_WIDTH_4);
386 }
387
388 sdhci_o2_set_tuning_mode(host);
389
390 sdhci_start_tuning(host);
391
392 __sdhci_o2_execute_tuning(host, opcode);
393
394 sdhci_end_tuning(host);
395
396 if (current_bus_width == MMC_BUS_WIDTH_8) {
397 mmc->ios.bus_width = MMC_BUS_WIDTH_8;
398 sdhci_set_bus_width(host, current_bus_width);
399 }
400
401 /* Cancel force power mode enter L0 */
402 scratch = sdhci_readw(host, O2_SD_MISC_CTRL);
403 scratch &= ~(O2_SD_PWR_FORCE_L0);
404 sdhci_writew(host, scratch, O2_SD_MISC_CTRL);
405
406 sdhci_reset(host, SDHCI_RESET_CMD);
407 sdhci_reset(host, SDHCI_RESET_DATA);
408
409 host->flags &= ~SDHCI_HS400_TUNING;
410 return 0;
411 }
412
o2_pci_led_enable(struct sdhci_pci_chip * chip)413 static void o2_pci_led_enable(struct sdhci_pci_chip *chip)
414 {
415 int ret;
416 u32 scratch_32;
417
418 /* Set led of SD host function enable */
419 ret = pci_read_config_dword(chip->pdev,
420 O2_SD_FUNC_REG0, &scratch_32);
421 if (ret)
422 return;
423
424 scratch_32 &= ~O2_SD_FREG0_LEDOFF;
425 pci_write_config_dword(chip->pdev,
426 O2_SD_FUNC_REG0, scratch_32);
427
428 ret = pci_read_config_dword(chip->pdev,
429 O2_SD_TEST_REG, &scratch_32);
430 if (ret)
431 return;
432
433 scratch_32 |= O2_SD_LED_ENABLE;
434 pci_write_config_dword(chip->pdev,
435 O2_SD_TEST_REG, scratch_32);
436 }
437
sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip * chip)438 static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
439 {
440 u32 scratch_32;
441 int ret;
442 /* Improve write performance for SD3.0 */
443 ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
444 if (ret)
445 return;
446 scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
447 pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
448
449 /* Enable Link abnormal reset generating Reset */
450 ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
451 if (ret)
452 return;
453 scratch_32 &= ~((1 << 19) | (1 << 11));
454 scratch_32 |= (1 << 10);
455 pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
456
457 /* set card power over current protection */
458 ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
459 if (ret)
460 return;
461 scratch_32 |= (1 << 4);
462 pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
463
464 /* adjust the output delay for SD mode */
465 pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492);
466
467 /* Set the output voltage setting of Aux 1.2v LDO */
468 ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
469 if (ret)
470 return;
471 scratch_32 &= ~(3 << 12);
472 pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
473
474 /* Set Max power supply capability of SD host */
475 ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
476 if (ret)
477 return;
478 scratch_32 &= ~(0x01FE);
479 scratch_32 |= 0x00CC;
480 pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
481 /* Set DLL Tuning Window */
482 ret = pci_read_config_dword(chip->pdev,
483 O2_SD_TUNING_CTRL, &scratch_32);
484 if (ret)
485 return;
486 scratch_32 &= ~(0x000000FF);
487 scratch_32 |= 0x00000066;
488 pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
489
490 /* Set UHS2 T_EIDLE */
491 ret = pci_read_config_dword(chip->pdev,
492 O2_SD_UHS2_L1_CTRL, &scratch_32);
493 if (ret)
494 return;
495 scratch_32 &= ~(0x000000FC);
496 scratch_32 |= 0x00000084;
497 pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
498
499 /* Set UHS2 Termination */
500 ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
501 if (ret)
502 return;
503 scratch_32 &= ~((1 << 21) | (1 << 30));
504
505 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
506
507 /* Set L1 Entrance Timer */
508 ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
509 if (ret)
510 return;
511 scratch_32 &= ~(0xf0000000);
512 scratch_32 |= 0x30000000;
513 pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
514
515 ret = pci_read_config_dword(chip->pdev,
516 O2_SD_MISC_CTRL4, &scratch_32);
517 if (ret)
518 return;
519 scratch_32 &= ~(0x000f0000);
520 scratch_32 |= 0x00080000;
521 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
522 }
523
sdhci_pci_o2_enable_msi(struct sdhci_pci_chip * chip,struct sdhci_host * host)524 static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip,
525 struct sdhci_host *host)
526 {
527 int ret;
528
529 ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI);
530 if (!ret) {
531 pr_info("%s: unsupported MSI, use INTx irq\n",
532 mmc_hostname(host->mmc));
533 return;
534 }
535
536 ret = pci_alloc_irq_vectors(chip->pdev, 1, 1,
537 PCI_IRQ_MSI | PCI_IRQ_MSIX);
538 if (ret < 0) {
539 pr_err("%s: enable PCI MSI failed, err=%d\n",
540 mmc_hostname(host->mmc), ret);
541 return;
542 }
543
544 host->irq = pci_irq_vector(chip->pdev, 0);
545 }
546
sdhci_o2_enable_clk(struct sdhci_host * host,u16 clk)547 static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk)
548 {
549 /* Enable internal clock */
550 clk |= SDHCI_CLOCK_INT_EN;
551 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
552
553 sdhci_o2_enable_internal_clock(host);
554 if (sdhci_o2_get_cd(host->mmc)) {
555 clk |= SDHCI_CLOCK_CARD_EN;
556 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
557 }
558 }
559
sdhci_pci_o2_set_clock(struct sdhci_host * host,unsigned int clock)560 static void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock)
561 {
562 u16 clk;
563 u8 scratch;
564 u32 scratch_32;
565 struct sdhci_pci_slot *slot = sdhci_priv(host);
566 struct sdhci_pci_chip *chip = slot->chip;
567
568 host->mmc->actual_clock = 0;
569
570 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
571
572 if (clock == 0)
573 return;
574
575 /* UnLock WP */
576 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
577 scratch &= 0x7f;
578 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
579
580 if ((host->timing == MMC_TIMING_UHS_SDR104) && (clock == 200000000)) {
581 pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32);
582
583 if ((scratch_32 & 0xFFFF0000) != 0x2c280000)
584 o2_pci_set_baseclk(chip, 0x2c280000);
585 } else {
586 pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32);
587
588 if ((scratch_32 & 0xFFFF0000) != 0x25100000)
589 o2_pci_set_baseclk(chip, 0x25100000);
590 }
591
592 pci_read_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, &scratch_32);
593 scratch_32 &= ~(O2_SD_SEL_DLL | O2_SD_PHASE_MASK);
594 pci_write_config_dword(chip->pdev, O2_SD_OUTPUT_CLK_SOURCE_SWITCH, scratch_32);
595
596 /* Lock WP */
597 pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch);
598 scratch |= 0x80;
599 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
600
601 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
602 sdhci_o2_enable_clk(host, clk);
603 }
604
sdhci_pci_o2_probe_slot(struct sdhci_pci_slot * slot)605 static int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
606 {
607 struct sdhci_pci_chip *chip;
608 struct sdhci_host *host;
609 struct o2_host *o2_host = sdhci_pci_priv(slot);
610 u32 reg, caps;
611 int ret;
612
613 chip = slot->chip;
614 host = slot->host;
615
616 o2_host->dll_adjust_count = 0;
617 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
618
619 /*
620 * mmc_select_bus_width() will test the bus to determine the actual bus
621 * width.
622 */
623 if (caps & SDHCI_CAN_DO_8BIT)
624 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
625
626 switch (chip->pdev->device) {
627 case PCI_DEVICE_ID_O2_SDS0:
628 case PCI_DEVICE_ID_O2_SEABIRD0:
629 case PCI_DEVICE_ID_O2_SEABIRD1:
630 case PCI_DEVICE_ID_O2_SDS1:
631 case PCI_DEVICE_ID_O2_FUJIN2:
632 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
633 if (reg & 0x1)
634 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
635
636 host->quirks2 |= SDHCI_QUIRK2_BROKEN_DDR50;
637
638 sdhci_pci_o2_enable_msi(chip, host);
639
640 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) {
641 ret = pci_read_config_dword(chip->pdev,
642 O2_SD_MISC_SETTING, ®);
643 if (ret)
644 return -EIO;
645 if (reg & (1 << 4)) {
646 pr_info("%s: emmc 1.8v flag is set, force 1.8v signaling voltage\n",
647 mmc_hostname(host->mmc));
648 host->flags &= ~SDHCI_SIGNALING_330;
649 host->flags |= SDHCI_SIGNALING_180;
650 host->mmc->caps2 |= MMC_CAP2_NO_SD;
651 host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
652 pci_write_config_dword(chip->pdev,
653 O2_SD_DETECT_SETTING, 3);
654 }
655
656 slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
657 }
658
659 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD1) {
660 slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
661 host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
662 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
663 }
664
665 host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning;
666
667 if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2)
668 break;
669 /* set dll watch dog timer */
670 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
671 reg |= (1 << 12);
672 sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);
673
674 break;
675 default:
676 break;
677 }
678
679 return 0;
680 }
681
sdhci_pci_o2_probe(struct sdhci_pci_chip * chip)682 static int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
683 {
684 int ret;
685 u8 scratch;
686 u32 scratch_32;
687
688 switch (chip->pdev->device) {
689 case PCI_DEVICE_ID_O2_8220:
690 case PCI_DEVICE_ID_O2_8221:
691 case PCI_DEVICE_ID_O2_8320:
692 case PCI_DEVICE_ID_O2_8321:
693 /* This extra setup is required due to broken ADMA. */
694 ret = pci_read_config_byte(chip->pdev,
695 O2_SD_LOCK_WP, &scratch);
696 if (ret)
697 return ret;
698 scratch &= 0x7f;
699 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
700
701 /* Set Multi 3 to VCC3V# */
702 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
703
704 /* Disable CLK_REQ# support after media DET */
705 ret = pci_read_config_byte(chip->pdev,
706 O2_SD_CLKREQ, &scratch);
707 if (ret)
708 return ret;
709 scratch |= 0x20;
710 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
711
712 /* Choose capabilities, enable SDMA. We have to write 0x01
713 * to the capabilities register first to unlock it.
714 */
715 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
716 if (ret)
717 return ret;
718 scratch |= 0x01;
719 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
720 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
721
722 /* Disable ADMA1/2 */
723 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
724 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
725
726 /* Disable the infinite transfer mode */
727 ret = pci_read_config_byte(chip->pdev,
728 O2_SD_INF_MOD, &scratch);
729 if (ret)
730 return ret;
731 scratch |= 0x08;
732 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
733
734 /* Lock WP */
735 ret = pci_read_config_byte(chip->pdev,
736 O2_SD_LOCK_WP, &scratch);
737 if (ret)
738 return ret;
739 scratch |= 0x80;
740 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
741 break;
742 case PCI_DEVICE_ID_O2_SDS0:
743 case PCI_DEVICE_ID_O2_SDS1:
744 case PCI_DEVICE_ID_O2_FUJIN2:
745 /* UnLock WP */
746 ret = pci_read_config_byte(chip->pdev,
747 O2_SD_LOCK_WP, &scratch);
748 if (ret)
749 return ret;
750
751 scratch &= 0x7f;
752 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
753
754 /* DevId=8520 subId= 0x11 or 0x12 Type Chip support */
755 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) {
756 ret = pci_read_config_dword(chip->pdev,
757 O2_SD_FUNC_REG0,
758 &scratch_32);
759 if (ret)
760 return ret;
761 scratch_32 = ((scratch_32 & 0xFF000000) >> 24);
762
763 /* Check Whether subId is 0x11 or 0x12 */
764 if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {
765 scratch_32 = 0x25100000;
766
767 o2_pci_set_baseclk(chip, scratch_32);
768 ret = pci_read_config_dword(chip->pdev,
769 O2_SD_FUNC_REG4,
770 &scratch_32);
771 if (ret)
772 return ret;
773
774 /* Enable Base Clk setting change */
775 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
776 pci_write_config_dword(chip->pdev,
777 O2_SD_FUNC_REG4,
778 scratch_32);
779
780 /* Set Tuning Window to 4 */
781 pci_write_config_byte(chip->pdev,
782 O2_SD_TUNING_CTRL, 0x44);
783
784 break;
785 }
786 }
787
788 /* Enable 8520 led function */
789 o2_pci_led_enable(chip);
790
791 /* Set timeout CLK */
792 ret = pci_read_config_dword(chip->pdev,
793 O2_SD_CLK_SETTING, &scratch_32);
794 if (ret)
795 return ret;
796
797 scratch_32 &= ~(0xFF00);
798 scratch_32 |= 0x07E0C800;
799 pci_write_config_dword(chip->pdev,
800 O2_SD_CLK_SETTING, scratch_32);
801
802 ret = pci_read_config_dword(chip->pdev,
803 O2_SD_CLKREQ, &scratch_32);
804 if (ret)
805 return ret;
806 scratch_32 |= 0x3;
807 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
808
809 ret = pci_read_config_dword(chip->pdev,
810 O2_SD_PLL_SETTING, &scratch_32);
811 if (ret)
812 return ret;
813
814 scratch_32 &= ~(0x1F3F070E);
815 scratch_32 |= 0x18270106;
816 pci_write_config_dword(chip->pdev,
817 O2_SD_PLL_SETTING, scratch_32);
818
819 /* Disable UHS1 funciton */
820 ret = pci_read_config_dword(chip->pdev,
821 O2_SD_CAP_REG2, &scratch_32);
822 if (ret)
823 return ret;
824 scratch_32 &= ~(0xE0);
825 pci_write_config_dword(chip->pdev,
826 O2_SD_CAP_REG2, scratch_32);
827
828 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2)
829 sdhci_pci_o2_fujin2_pci_init(chip);
830
831 /* Lock WP */
832 ret = pci_read_config_byte(chip->pdev,
833 O2_SD_LOCK_WP, &scratch);
834 if (ret)
835 return ret;
836 scratch |= 0x80;
837 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
838 break;
839 case PCI_DEVICE_ID_O2_SEABIRD0:
840 case PCI_DEVICE_ID_O2_SEABIRD1:
841 /* UnLock WP */
842 ret = pci_read_config_byte(chip->pdev,
843 O2_SD_LOCK_WP, &scratch);
844 if (ret)
845 return ret;
846
847 scratch &= 0x7f;
848 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
849
850 ret = pci_read_config_dword(chip->pdev,
851 O2_SD_PLL_SETTING, &scratch_32);
852 if (ret)
853 return ret;
854
855 if ((scratch_32 & 0xff000000) == 0x01000000) {
856 scratch_32 &= 0x0000FFFF;
857 scratch_32 |= 0x1F340000;
858
859 pci_write_config_dword(chip->pdev,
860 O2_SD_PLL_SETTING, scratch_32);
861 } else {
862 scratch_32 &= 0x0000FFFF;
863 scratch_32 |= 0x25100000;
864
865 pci_write_config_dword(chip->pdev,
866 O2_SD_PLL_SETTING, scratch_32);
867
868 ret = pci_read_config_dword(chip->pdev,
869 O2_SD_FUNC_REG4,
870 &scratch_32);
871 if (ret)
872 return ret;
873 scratch_32 |= (1 << 22);
874 pci_write_config_dword(chip->pdev,
875 O2_SD_FUNC_REG4, scratch_32);
876 }
877
878 /* Set Tuning Windows to 5 */
879 pci_write_config_byte(chip->pdev,
880 O2_SD_TUNING_CTRL, 0x55);
881 //Adjust 1st and 2nd CD debounce time
882 pci_read_config_dword(chip->pdev, O2_SD_MISC_CTRL2, &scratch_32);
883 scratch_32 &= 0xFFE7FFFF;
884 scratch_32 |= 0x00180000;
885 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL2, scratch_32);
886 pci_write_config_dword(chip->pdev, O2_SD_DETECT_SETTING, 1);
887 /* Lock WP */
888 ret = pci_read_config_byte(chip->pdev,
889 O2_SD_LOCK_WP, &scratch);
890 if (ret)
891 return ret;
892 scratch |= 0x80;
893 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
894 break;
895 }
896
897 return 0;
898 }
899
900 #ifdef CONFIG_PM_SLEEP
sdhci_pci_o2_resume(struct sdhci_pci_chip * chip)901 static int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
902 {
903 sdhci_pci_o2_probe(chip);
904 return sdhci_pci_resume_host(chip);
905 }
906 #endif
907
908 static const struct sdhci_ops sdhci_pci_o2_ops = {
909 .set_clock = sdhci_pci_o2_set_clock,
910 .enable_dma = sdhci_pci_enable_dma,
911 .set_bus_width = sdhci_set_bus_width,
912 .reset = sdhci_reset,
913 .set_uhs_signaling = sdhci_set_uhs_signaling,
914 };
915
916 const struct sdhci_pci_fixes sdhci_o2 = {
917 .probe = sdhci_pci_o2_probe,
918 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
919 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
920 .probe_slot = sdhci_pci_o2_probe_slot,
921 #ifdef CONFIG_PM_SLEEP
922 .resume = sdhci_pci_o2_resume,
923 #endif
924 .ops = &sdhci_pci_o2_ops,
925 .priv_size = sizeof(struct o2_host),
926 };
927
