1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013 BayHub Technology Ltd.
4 *
5 * Authors: Peter Guo <peter.guo@bayhubtech.com>
6 * Adam Lee <adam.lee@canonical.com>
7 * Ernest Zhang <ernest.zhang@bayhubtech.com>
8 */
9
10 #include <linux/pci.h>
11 #include <linux/mmc/host.h>
12 #include <linux/mmc/mmc.h>
13 #include <linux/delay.h>
14 #include <linux/iopoll.h>
15
16 #include "sdhci.h"
17 #include "sdhci-pci.h"
18
19 /*
20 * O2Micro device registers
21 */
22
23 #define O2_SD_MISC_REG5 0x64
24 #define O2_SD_LD0_CTRL 0x68
25 #define O2_SD_DEV_CTRL 0x88
26 #define O2_SD_LOCK_WP 0xD3
27 #define O2_SD_TEST_REG 0xD4
28 #define O2_SD_FUNC_REG0 0xDC
29 #define O2_SD_MULTI_VCC3V 0xEE
30 #define O2_SD_CLKREQ 0xEC
31 #define O2_SD_CAPS 0xE0
32 #define O2_SD_ADMA1 0xE2
33 #define O2_SD_ADMA2 0xE7
34 #define O2_SD_INF_MOD 0xF1
35 #define O2_SD_MISC_CTRL4 0xFC
36 #define O2_SD_TUNING_CTRL 0x300
37 #define O2_SD_PLL_SETTING 0x304
38 #define O2_SD_MISC_SETTING 0x308
39 #define O2_SD_CLK_SETTING 0x328
40 #define O2_SD_CAP_REG2 0x330
41 #define O2_SD_CAP_REG0 0x334
42 #define O2_SD_UHS1_CAP_SETTING 0x33C
43 #define O2_SD_DELAY_CTRL 0x350
44 #define O2_SD_UHS2_L1_CTRL 0x35C
45 #define O2_SD_FUNC_REG3 0x3E0
46 #define O2_SD_FUNC_REG4 0x3E4
47 #define O2_SD_LED_ENABLE BIT(6)
48 #define O2_SD_FREG0_LEDOFF BIT(13)
49 #define O2_SD_FREG4_ENABLE_CLK_SET BIT(22)
50
51 #define O2_SD_VENDOR_SETTING 0x110
52 #define O2_SD_VENDOR_SETTING2 0x1C8
53 #define O2_SD_HW_TUNING_DISABLE BIT(4)
54
55 #define O2_PLL_DLL_WDT_CONTROL1 0x1CC
56 #define O2_PLL_FORCE_ACTIVE BIT(18)
57 #define O2_PLL_LOCK_STATUS BIT(14)
58 #define O2_PLL_SOFT_RESET BIT(12)
59 #define O2_DLL_LOCK_STATUS BIT(11)
60
61 #define O2_SD_DETECT_SETTING 0x324
62
63 static const u32 dmdn_table[] = {0x2B1C0000,
64 0x2C1A0000, 0x371B0000, 0x35100000};
65 #define DMDN_SZ ARRAY_SIZE(dmdn_table)
66
67 struct o2_host {
68 u8 dll_adjust_count;
69 };
70
sdhci_o2_wait_card_detect_stable(struct sdhci_host * host)71 static void sdhci_o2_wait_card_detect_stable(struct sdhci_host *host)
72 {
73 ktime_t timeout;
74 u32 scratch32;
75
76 /* Wait max 50 ms */
77 timeout = ktime_add_ms(ktime_get(), 50);
78 while (1) {
79 bool timedout = ktime_after(ktime_get(), timeout);
80
81 scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE);
82 if ((scratch32 & SDHCI_CARD_PRESENT) >> SDHCI_CARD_PRES_SHIFT
83 == (scratch32 & SDHCI_CD_LVL) >> SDHCI_CD_LVL_SHIFT)
84 break;
85
86 if (timedout) {
87 pr_err("%s: Card Detect debounce never finished.\n",
88 mmc_hostname(host->mmc));
89 sdhci_dumpregs(host);
90 return;
91 }
92 udelay(10);
93 }
94 }
95
sdhci_o2_enable_internal_clock(struct sdhci_host * host)96 static void sdhci_o2_enable_internal_clock(struct sdhci_host *host)
97 {
98 ktime_t timeout;
99 u16 scratch;
100 u32 scratch32;
101
102 /* PLL software reset */
103 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
104 scratch32 |= O2_PLL_SOFT_RESET;
105 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
106 udelay(1);
107 scratch32 &= ~(O2_PLL_SOFT_RESET);
108 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
109
110 /* PLL force active */
111 scratch32 |= O2_PLL_FORCE_ACTIVE;
112 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
113
114 /* Wait max 20 ms */
115 timeout = ktime_add_ms(ktime_get(), 20);
116 while (1) {
117 bool timedout = ktime_after(ktime_get(), timeout);
118
119 scratch = sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1);
120 if (scratch & O2_PLL_LOCK_STATUS)
121 break;
122 if (timedout) {
123 pr_err("%s: Internal clock never stabilised.\n",
124 mmc_hostname(host->mmc));
125 sdhci_dumpregs(host);
126 goto out;
127 }
128 udelay(10);
129 }
130
131 /* Wait for card detect finish */
132 udelay(1);
133 sdhci_o2_wait_card_detect_stable(host);
134
135 out:
136 /* Cancel PLL force active */
137 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
138 scratch32 &= ~O2_PLL_FORCE_ACTIVE;
139 sdhci_writel(host, scratch32, O2_PLL_DLL_WDT_CONTROL1);
140 }
141
sdhci_o2_get_cd(struct mmc_host * mmc)142 static int sdhci_o2_get_cd(struct mmc_host *mmc)
143 {
144 struct sdhci_host *host = mmc_priv(mmc);
145
146 if (!(sdhci_readw(host, O2_PLL_DLL_WDT_CONTROL1) & O2_PLL_LOCK_STATUS))
147 sdhci_o2_enable_internal_clock(host);
148
149 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
150 }
151
o2_pci_set_baseclk(struct sdhci_pci_chip * chip,u32 value)152 static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
153 {
154 u32 scratch_32;
155
156 pci_read_config_dword(chip->pdev,
157 O2_SD_PLL_SETTING, &scratch_32);
158
159 scratch_32 &= 0x0000FFFF;
160 scratch_32 |= value;
161
162 pci_write_config_dword(chip->pdev,
163 O2_SD_PLL_SETTING, scratch_32);
164 }
165
sdhci_o2_pll_dll_wdt_control(struct sdhci_host * host)166 static u32 sdhci_o2_pll_dll_wdt_control(struct sdhci_host *host)
167 {
168 return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
169 }
170
171 /*
172 * This function is used to detect dll lock status.
173 * Since the dll lock status bit will toggle randomly
174 * with very short interval which needs to be polled
175 * as fast as possible. Set sleep_us as 1 microsecond.
176 */
sdhci_o2_wait_dll_detect_lock(struct sdhci_host * host)177 static int sdhci_o2_wait_dll_detect_lock(struct sdhci_host *host)
178 {
179 u32 scratch32 = 0;
180
181 return readx_poll_timeout(sdhci_o2_pll_dll_wdt_control, host,
182 scratch32, !(scratch32 & O2_DLL_LOCK_STATUS), 1, 1000000);
183 }
184
sdhci_o2_set_tuning_mode(struct sdhci_host * host)185 static void sdhci_o2_set_tuning_mode(struct sdhci_host *host)
186 {
187 u16 reg;
188
189 /* enable hardware tuning */
190 reg = sdhci_readw(host, O2_SD_VENDOR_SETTING);
191 reg &= ~O2_SD_HW_TUNING_DISABLE;
192 sdhci_writew(host, reg, O2_SD_VENDOR_SETTING);
193 }
194
__sdhci_o2_execute_tuning(struct sdhci_host * host,u32 opcode)195 static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode)
196 {
197 int i;
198
199 sdhci_send_tuning(host, MMC_SEND_TUNING_BLOCK_HS200);
200
201 for (i = 0; i < 150; i++) {
202 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
203
204 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
205 if (ctrl & SDHCI_CTRL_TUNED_CLK) {
206 host->tuning_done = true;
207 return;
208 }
209 pr_warn("%s: HW tuning failed !\n",
210 mmc_hostname(host->mmc));
211 break;
212 }
213
214 mdelay(1);
215 }
216
217 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
218 mmc_hostname(host->mmc));
219 sdhci_reset_tuning(host);
220 }
221
222 /*
223 * This function is used to fix o2 dll shift issue.
224 * It isn't necessary to detect card present before recovery.
225 * Firstly, it is used by bht emmc card, which is embedded.
226 * Second, before call recovery card present will be detected
227 * outside of the execute tuning function.
228 */
sdhci_o2_dll_recovery(struct sdhci_host * host)229 static int sdhci_o2_dll_recovery(struct sdhci_host *host)
230 {
231 int ret = 0;
232 u8 scratch_8 = 0;
233 u32 scratch_32 = 0;
234 struct sdhci_pci_slot *slot = sdhci_priv(host);
235 struct sdhci_pci_chip *chip = slot->chip;
236 struct o2_host *o2_host = sdhci_pci_priv(slot);
237
238 /* UnLock WP */
239 pci_read_config_byte(chip->pdev,
240 O2_SD_LOCK_WP, &scratch_8);
241 scratch_8 &= 0x7f;
242 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
243 while (o2_host->dll_adjust_count < DMDN_SZ && !ret) {
244 /* Disable clock */
245 sdhci_writeb(host, 0, SDHCI_CLOCK_CONTROL);
246
247 /* PLL software reset */
248 scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1);
249 scratch_32 |= O2_PLL_SOFT_RESET;
250 sdhci_writel(host, scratch_32, O2_PLL_DLL_WDT_CONTROL1);
251
252 pci_read_config_dword(chip->pdev,
253 O2_SD_FUNC_REG4,
254 &scratch_32);
255 /* Enable Base Clk setting change */
256 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
257 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG4, scratch_32);
258 o2_pci_set_baseclk(chip, dmdn_table[o2_host->dll_adjust_count]);
259
260 /* Enable internal clock */
261 scratch_8 = SDHCI_CLOCK_INT_EN;
262 sdhci_writeb(host, scratch_8, SDHCI_CLOCK_CONTROL);
263
264 if (sdhci_o2_get_cd(host->mmc)) {
265 /*
266 * need wait at least 5ms for dll status stable,
267 * after enable internal clock
268 */
269 usleep_range(5000, 6000);
270 if (sdhci_o2_wait_dll_detect_lock(host)) {
271 scratch_8 |= SDHCI_CLOCK_CARD_EN;
272 sdhci_writeb(host, scratch_8,
273 SDHCI_CLOCK_CONTROL);
274 ret = 1;
275 } else {
276 pr_warn("%s: DLL unlocked when dll_adjust_count is %d.\n",
277 mmc_hostname(host->mmc),
278 o2_host->dll_adjust_count);
279 }
280 } else {
281 pr_err("%s: card present detect failed.\n",
282 mmc_hostname(host->mmc));
283 break;
284 }
285
286 o2_host->dll_adjust_count++;
287 }
288 if (!ret && o2_host->dll_adjust_count == DMDN_SZ)
289 pr_err("%s: DLL adjust over max times\n",
290 mmc_hostname(host->mmc));
291 /* Lock WP */
292 pci_read_config_byte(chip->pdev,
293 O2_SD_LOCK_WP, &scratch_8);
294 scratch_8 |= 0x80;
295 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch_8);
296 return ret;
297 }
298
sdhci_o2_execute_tuning(struct mmc_host * mmc,u32 opcode)299 static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
300 {
301 struct sdhci_host *host = mmc_priv(mmc);
302 int current_bus_width = 0;
303
304 /*
305 * This handler only implements the eMMC tuning that is specific to
306 * this controller. Fall back to the standard method for other TIMING.
307 */
308 if (host->timing != MMC_TIMING_MMC_HS200)
309 return sdhci_execute_tuning(mmc, opcode);
310
311 if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200))
312 return -EINVAL;
313 /*
314 * Judge the tuning reason, whether caused by dll shift
315 * If cause by dll shift, should call sdhci_o2_dll_recovery
316 */
317 if (!sdhci_o2_wait_dll_detect_lock(host))
318 if (!sdhci_o2_dll_recovery(host)) {
319 pr_err("%s: o2 dll recovery failed\n",
320 mmc_hostname(host->mmc));
321 return -EINVAL;
322 }
323 /*
324 * o2 sdhci host didn't support 8bit emmc tuning
325 */
326 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
327 current_bus_width = mmc->ios.bus_width;
328 mmc->ios.bus_width = MMC_BUS_WIDTH_4;
329 sdhci_set_bus_width(host, MMC_BUS_WIDTH_4);
330 }
331
332 sdhci_o2_set_tuning_mode(host);
333
334 sdhci_start_tuning(host);
335
336 __sdhci_o2_execute_tuning(host, opcode);
337
338 sdhci_end_tuning(host);
339
340 if (current_bus_width == MMC_BUS_WIDTH_8) {
341 mmc->ios.bus_width = MMC_BUS_WIDTH_8;
342 sdhci_set_bus_width(host, current_bus_width);
343 }
344
345 host->flags &= ~SDHCI_HS400_TUNING;
346 return 0;
347 }
348
o2_pci_led_enable(struct sdhci_pci_chip * chip)349 static void o2_pci_led_enable(struct sdhci_pci_chip *chip)
350 {
351 int ret;
352 u32 scratch_32;
353
354 /* Set led of SD host function enable */
355 ret = pci_read_config_dword(chip->pdev,
356 O2_SD_FUNC_REG0, &scratch_32);
357 if (ret)
358 return;
359
360 scratch_32 &= ~O2_SD_FREG0_LEDOFF;
361 pci_write_config_dword(chip->pdev,
362 O2_SD_FUNC_REG0, scratch_32);
363
364 ret = pci_read_config_dword(chip->pdev,
365 O2_SD_TEST_REG, &scratch_32);
366 if (ret)
367 return;
368
369 scratch_32 |= O2_SD_LED_ENABLE;
370 pci_write_config_dword(chip->pdev,
371 O2_SD_TEST_REG, scratch_32);
372
373 }
374
sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip * chip)375 static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
376 {
377 u32 scratch_32;
378 int ret;
379 /* Improve write performance for SD3.0 */
380 ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
381 if (ret)
382 return;
383 scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
384 pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
385
386 /* Enable Link abnormal reset generating Reset */
387 ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
388 if (ret)
389 return;
390 scratch_32 &= ~((1 << 19) | (1 << 11));
391 scratch_32 |= (1 << 10);
392 pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
393
394 /* set card power over current protection */
395 ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
396 if (ret)
397 return;
398 scratch_32 |= (1 << 4);
399 pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
400
401 /* adjust the output delay for SD mode */
402 pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492);
403
404 /* Set the output voltage setting of Aux 1.2v LDO */
405 ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
406 if (ret)
407 return;
408 scratch_32 &= ~(3 << 12);
409 pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
410
411 /* Set Max power supply capability of SD host */
412 ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
413 if (ret)
414 return;
415 scratch_32 &= ~(0x01FE);
416 scratch_32 |= 0x00CC;
417 pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
418 /* Set DLL Tuning Window */
419 ret = pci_read_config_dword(chip->pdev,
420 O2_SD_TUNING_CTRL, &scratch_32);
421 if (ret)
422 return;
423 scratch_32 &= ~(0x000000FF);
424 scratch_32 |= 0x00000066;
425 pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
426
427 /* Set UHS2 T_EIDLE */
428 ret = pci_read_config_dword(chip->pdev,
429 O2_SD_UHS2_L1_CTRL, &scratch_32);
430 if (ret)
431 return;
432 scratch_32 &= ~(0x000000FC);
433 scratch_32 |= 0x00000084;
434 pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
435
436 /* Set UHS2 Termination */
437 ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
438 if (ret)
439 return;
440 scratch_32 &= ~((1 << 21) | (1 << 30));
441
442 pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
443
444 /* Set L1 Entrance Timer */
445 ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
446 if (ret)
447 return;
448 scratch_32 &= ~(0xf0000000);
449 scratch_32 |= 0x30000000;
450 pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
451
452 ret = pci_read_config_dword(chip->pdev,
453 O2_SD_MISC_CTRL4, &scratch_32);
454 if (ret)
455 return;
456 scratch_32 &= ~(0x000f0000);
457 scratch_32 |= 0x00080000;
458 pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
459 }
460
sdhci_pci_o2_enable_msi(struct sdhci_pci_chip * chip,struct sdhci_host * host)461 static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip,
462 struct sdhci_host *host)
463 {
464 int ret;
465
466 ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI);
467 if (!ret) {
468 pr_info("%s: unsupport msi, use INTx irq\n",
469 mmc_hostname(host->mmc));
470 return;
471 }
472
473 ret = pci_alloc_irq_vectors(chip->pdev, 1, 1,
474 PCI_IRQ_MSI | PCI_IRQ_MSIX);
475 if (ret < 0) {
476 pr_err("%s: enable PCI MSI failed, err=%d\n",
477 mmc_hostname(host->mmc), ret);
478 return;
479 }
480
481 host->irq = pci_irq_vector(chip->pdev, 0);
482 }
483
sdhci_o2_enable_clk(struct sdhci_host * host,u16 clk)484 static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk)
485 {
486 /* Enable internal clock */
487 clk |= SDHCI_CLOCK_INT_EN;
488 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
489
490 sdhci_o2_enable_internal_clock(host);
491 if (sdhci_o2_get_cd(host->mmc)) {
492 clk |= SDHCI_CLOCK_CARD_EN;
493 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
494 }
495 }
496
sdhci_pci_o2_set_clock(struct sdhci_host * host,unsigned int clock)497 void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock)
498 {
499 u16 clk;
500
501 host->mmc->actual_clock = 0;
502
503 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
504
505 if (clock == 0)
506 return;
507
508 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
509 sdhci_o2_enable_clk(host, clk);
510 }
511
sdhci_pci_o2_probe_slot(struct sdhci_pci_slot * slot)512 int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
513 {
514 struct sdhci_pci_chip *chip;
515 struct sdhci_host *host;
516 struct o2_host *o2_host = sdhci_pci_priv(slot);
517 u32 reg, caps;
518 int ret;
519
520 chip = slot->chip;
521 host = slot->host;
522
523 o2_host->dll_adjust_count = 0;
524 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
525
526 /*
527 * mmc_select_bus_width() will test the bus to determine the actual bus
528 * width.
529 */
530 if (caps & SDHCI_CAN_DO_8BIT)
531 host->mmc->caps |= MMC_CAP_8_BIT_DATA;
532
533 switch (chip->pdev->device) {
534 case PCI_DEVICE_ID_O2_SDS0:
535 case PCI_DEVICE_ID_O2_SEABIRD0:
536 case PCI_DEVICE_ID_O2_SEABIRD1:
537 case PCI_DEVICE_ID_O2_SDS1:
538 case PCI_DEVICE_ID_O2_FUJIN2:
539 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
540 if (reg & 0x1)
541 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
542
543 sdhci_pci_o2_enable_msi(chip, host);
544
545 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) {
546 ret = pci_read_config_dword(chip->pdev,
547 O2_SD_MISC_SETTING, ®);
548 if (ret)
549 return -EIO;
550 if (reg & (1 << 4)) {
551 pr_info("%s: emmc 1.8v flag is set, force 1.8v signaling voltage\n",
552 mmc_hostname(host->mmc));
553 host->flags &= ~SDHCI_SIGNALING_330;
554 host->flags |= SDHCI_SIGNALING_180;
555 host->mmc->caps2 |= MMC_CAP2_NO_SD;
556 host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
557 pci_write_config_dword(chip->pdev,
558 O2_SD_DETECT_SETTING, 3);
559 }
560
561 slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd;
562 }
563
564 host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning;
565
566 if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2)
567 break;
568 /* set dll watch dog timer */
569 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
570 reg |= (1 << 12);
571 sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);
572
573 break;
574 default:
575 break;
576 }
577
578 return 0;
579 }
580
sdhci_pci_o2_probe(struct sdhci_pci_chip * chip)581 int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
582 {
583 int ret;
584 u8 scratch;
585 u32 scratch_32;
586
587 switch (chip->pdev->device) {
588 case PCI_DEVICE_ID_O2_8220:
589 case PCI_DEVICE_ID_O2_8221:
590 case PCI_DEVICE_ID_O2_8320:
591 case PCI_DEVICE_ID_O2_8321:
592 /* This extra setup is required due to broken ADMA. */
593 ret = pci_read_config_byte(chip->pdev,
594 O2_SD_LOCK_WP, &scratch);
595 if (ret)
596 return ret;
597 scratch &= 0x7f;
598 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
599
600 /* Set Multi 3 to VCC3V# */
601 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
602
603 /* Disable CLK_REQ# support after media DET */
604 ret = pci_read_config_byte(chip->pdev,
605 O2_SD_CLKREQ, &scratch);
606 if (ret)
607 return ret;
608 scratch |= 0x20;
609 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
610
611 /* Choose capabilities, enable SDMA. We have to write 0x01
612 * to the capabilities register first to unlock it.
613 */
614 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
615 if (ret)
616 return ret;
617 scratch |= 0x01;
618 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
619 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
620
621 /* Disable ADMA1/2 */
622 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
623 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
624
625 /* Disable the infinite transfer mode */
626 ret = pci_read_config_byte(chip->pdev,
627 O2_SD_INF_MOD, &scratch);
628 if (ret)
629 return ret;
630 scratch |= 0x08;
631 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
632
633 /* Lock WP */
634 ret = pci_read_config_byte(chip->pdev,
635 O2_SD_LOCK_WP, &scratch);
636 if (ret)
637 return ret;
638 scratch |= 0x80;
639 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
640 break;
641 case PCI_DEVICE_ID_O2_SDS0:
642 case PCI_DEVICE_ID_O2_SDS1:
643 case PCI_DEVICE_ID_O2_FUJIN2:
644 /* UnLock WP */
645 ret = pci_read_config_byte(chip->pdev,
646 O2_SD_LOCK_WP, &scratch);
647 if (ret)
648 return ret;
649
650 scratch &= 0x7f;
651 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
652
653 /* DevId=8520 subId= 0x11 or 0x12 Type Chip support */
654 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) {
655 ret = pci_read_config_dword(chip->pdev,
656 O2_SD_FUNC_REG0,
657 &scratch_32);
658 scratch_32 = ((scratch_32 & 0xFF000000) >> 24);
659
660 /* Check Whether subId is 0x11 or 0x12 */
661 if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {
662 scratch_32 = 0x25100000;
663
664 o2_pci_set_baseclk(chip, scratch_32);
665 ret = pci_read_config_dword(chip->pdev,
666 O2_SD_FUNC_REG4,
667 &scratch_32);
668
669 /* Enable Base Clk setting change */
670 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
671 pci_write_config_dword(chip->pdev,
672 O2_SD_FUNC_REG4,
673 scratch_32);
674
675 /* Set Tuning Window to 4 */
676 pci_write_config_byte(chip->pdev,
677 O2_SD_TUNING_CTRL, 0x44);
678
679 break;
680 }
681 }
682
683 /* Enable 8520 led function */
684 o2_pci_led_enable(chip);
685
686 /* Set timeout CLK */
687 ret = pci_read_config_dword(chip->pdev,
688 O2_SD_CLK_SETTING, &scratch_32);
689 if (ret)
690 return ret;
691
692 scratch_32 &= ~(0xFF00);
693 scratch_32 |= 0x07E0C800;
694 pci_write_config_dword(chip->pdev,
695 O2_SD_CLK_SETTING, scratch_32);
696
697 ret = pci_read_config_dword(chip->pdev,
698 O2_SD_CLKREQ, &scratch_32);
699 if (ret)
700 return ret;
701 scratch_32 |= 0x3;
702 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
703
704 ret = pci_read_config_dword(chip->pdev,
705 O2_SD_PLL_SETTING, &scratch_32);
706 if (ret)
707 return ret;
708
709 scratch_32 &= ~(0x1F3F070E);
710 scratch_32 |= 0x18270106;
711 pci_write_config_dword(chip->pdev,
712 O2_SD_PLL_SETTING, scratch_32);
713
714 /* Disable UHS1 funciton */
715 ret = pci_read_config_dword(chip->pdev,
716 O2_SD_CAP_REG2, &scratch_32);
717 if (ret)
718 return ret;
719 scratch_32 &= ~(0xE0);
720 pci_write_config_dword(chip->pdev,
721 O2_SD_CAP_REG2, scratch_32);
722
723 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2)
724 sdhci_pci_o2_fujin2_pci_init(chip);
725
726 /* Lock WP */
727 ret = pci_read_config_byte(chip->pdev,
728 O2_SD_LOCK_WP, &scratch);
729 if (ret)
730 return ret;
731 scratch |= 0x80;
732 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
733 break;
734 case PCI_DEVICE_ID_O2_SEABIRD0:
735 case PCI_DEVICE_ID_O2_SEABIRD1:
736 /* UnLock WP */
737 ret = pci_read_config_byte(chip->pdev,
738 O2_SD_LOCK_WP, &scratch);
739 if (ret)
740 return ret;
741
742 scratch &= 0x7f;
743 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
744
745 ret = pci_read_config_dword(chip->pdev,
746 O2_SD_PLL_SETTING, &scratch_32);
747
748 if ((scratch_32 & 0xff000000) == 0x01000000) {
749 scratch_32 &= 0x0000FFFF;
750 scratch_32 |= 0x1F340000;
751
752 pci_write_config_dword(chip->pdev,
753 O2_SD_PLL_SETTING, scratch_32);
754 } else {
755 scratch_32 &= 0x0000FFFF;
756 scratch_32 |= 0x25100000;
757
758 pci_write_config_dword(chip->pdev,
759 O2_SD_PLL_SETTING, scratch_32);
760
761 ret = pci_read_config_dword(chip->pdev,
762 O2_SD_FUNC_REG4,
763 &scratch_32);
764 scratch_32 |= (1 << 22);
765 pci_write_config_dword(chip->pdev,
766 O2_SD_FUNC_REG4, scratch_32);
767 }
768
769 /* Set Tuning Windows to 5 */
770 pci_write_config_byte(chip->pdev,
771 O2_SD_TUNING_CTRL, 0x55);
772 /* Lock WP */
773 ret = pci_read_config_byte(chip->pdev,
774 O2_SD_LOCK_WP, &scratch);
775 if (ret)
776 return ret;
777 scratch |= 0x80;
778 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
779 break;
780 }
781
782 return 0;
783 }
784
785 #ifdef CONFIG_PM_SLEEP
sdhci_pci_o2_resume(struct sdhci_pci_chip * chip)786 int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
787 {
788 sdhci_pci_o2_probe(chip);
789 return sdhci_pci_resume_host(chip);
790 }
791 #endif
792
793 static const struct sdhci_ops sdhci_pci_o2_ops = {
794 .set_clock = sdhci_pci_o2_set_clock,
795 .enable_dma = sdhci_pci_enable_dma,
796 .set_bus_width = sdhci_set_bus_width,
797 .reset = sdhci_reset,
798 .set_uhs_signaling = sdhci_set_uhs_signaling,
799 };
800
801 const struct sdhci_pci_fixes sdhci_o2 = {
802 .probe = sdhci_pci_o2_probe,
803 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
804 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
805 .probe_slot = sdhci_pci_o2_probe_slot,
806 #ifdef CONFIG_PM_SLEEP
807 .resume = sdhci_pci_o2_resume,
808 #endif
809 .ops = &sdhci_pci_o2_ops,
810 .priv_size = sizeof(struct o2_host),
811 };
812
