1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef _SMU7_HWMGR_H 25 #define _SMU7_HWMGR_H 26 27 #include "hwmgr.h" 28 #include "ppatomctrl.h" 29 30 #define SMU7_MAX_HARDWARE_POWERLEVELS 2 31 32 #define SMU7_VOLTAGE_CONTROL_NONE 0x0 33 #define SMU7_VOLTAGE_CONTROL_BY_GPIO 0x1 34 #define SMU7_VOLTAGE_CONTROL_BY_SVID2 0x2 35 #define SMU7_VOLTAGE_CONTROL_MERGED 0x3 36 37 enum gpu_pt_config_reg_type { 38 GPU_CONFIGREG_MMR = 0, 39 GPU_CONFIGREG_SMC_IND, 40 GPU_CONFIGREG_DIDT_IND, 41 GPU_CONFIGREG_GC_CAC_IND, 42 GPU_CONFIGREG_CACHE, 43 GPU_CONFIGREG_MAX 44 }; 45 46 struct gpu_pt_config_reg { 47 uint32_t offset; 48 uint32_t mask; 49 uint32_t shift; 50 uint32_t value; 51 enum gpu_pt_config_reg_type type; 52 }; 53 54 struct smu7_performance_level { 55 uint32_t memory_clock; 56 uint32_t engine_clock; 57 uint16_t pcie_gen; 58 uint16_t pcie_lane; 59 }; 60 61 struct smu7_thermal_temperature_setting { 62 long temperature_low; 63 long temperature_high; 64 long temperature_shutdown; 65 }; 66 67 struct smu7_uvd_clocks { 68 uint32_t vclk; 69 uint32_t dclk; 70 }; 71 72 struct smu7_vce_clocks { 73 uint32_t evclk; 74 uint32_t ecclk; 75 }; 76 77 struct smu7_power_state { 78 uint32_t magic; 79 struct smu7_uvd_clocks uvd_clks; 80 struct smu7_vce_clocks vce_clks; 81 uint32_t sam_clk; 82 uint16_t performance_level_count; 83 bool dc_compatible; 84 uint32_t sclk_threshold; 85 struct smu7_performance_level performance_levels[SMU7_MAX_HARDWARE_POWERLEVELS]; 86 }; 87 88 struct smu7_dpm_level { 89 bool enabled; 90 uint32_t value; 91 uint32_t param1; 92 }; 93 94 #define SMU7_MAX_DEEPSLEEP_DIVIDER_ID 5 95 #define MAX_REGULAR_DPM_NUMBER 8 96 #define SMU7_MINIMUM_ENGINE_CLOCK 2500 97 98 struct smu7_single_dpm_table { 99 uint32_t count; 100 struct smu7_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; 101 }; 102 103 struct smu7_dpm_table { 104 struct smu7_single_dpm_table sclk_table; 105 struct smu7_single_dpm_table mclk_table; 106 struct smu7_single_dpm_table pcie_speed_table; 107 struct smu7_single_dpm_table vddc_table; 108 struct smu7_single_dpm_table vddci_table; 109 struct smu7_single_dpm_table mvdd_table; 110 }; 111 112 struct smu7_clock_registers { 113 uint32_t vCG_SPLL_FUNC_CNTL; 114 uint32_t vCG_SPLL_FUNC_CNTL_2; 115 uint32_t vCG_SPLL_FUNC_CNTL_3; 116 uint32_t vCG_SPLL_FUNC_CNTL_4; 117 uint32_t vCG_SPLL_SPREAD_SPECTRUM; 118 uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; 119 uint32_t vDLL_CNTL; 120 uint32_t vMCLK_PWRMGT_CNTL; 121 uint32_t vMPLL_AD_FUNC_CNTL; 122 uint32_t vMPLL_DQ_FUNC_CNTL; 123 uint32_t vMPLL_FUNC_CNTL; 124 uint32_t vMPLL_FUNC_CNTL_1; 125 uint32_t vMPLL_FUNC_CNTL_2; 126 uint32_t vMPLL_SS1; 127 uint32_t vMPLL_SS2; 128 }; 129 130 #define DISABLE_MC_LOADMICROCODE 1 131 #define DISABLE_MC_CFGPROGRAMMING 2 132 133 struct smu7_voltage_smio_registers { 134 uint32_t vS0_VID_LOWER_SMIO_CNTL; 135 }; 136 137 #define SMU7_MAX_LEAKAGE_COUNT 8 138 139 struct smu7_leakage_voltage { 140 uint16_t count; 141 uint16_t leakage_id[SMU7_MAX_LEAKAGE_COUNT]; 142 uint16_t actual_voltage[SMU7_MAX_LEAKAGE_COUNT]; 143 }; 144 145 struct smu7_vbios_boot_state { 146 uint16_t mvdd_bootup_value; 147 uint16_t vddc_bootup_value; 148 uint16_t vddci_bootup_value; 149 uint16_t vddgfx_bootup_value; 150 uint32_t sclk_bootup_value; 151 uint32_t mclk_bootup_value; 152 uint16_t pcie_gen_bootup_value; 153 uint16_t pcie_lane_bootup_value; 154 }; 155 156 struct smu7_display_timing { 157 uint32_t min_clock_in_sr; 158 uint32_t num_existing_displays; 159 }; 160 161 struct smu7_dpmlevel_enable_mask { 162 uint32_t uvd_dpm_enable_mask; 163 uint32_t vce_dpm_enable_mask; 164 uint32_t acp_dpm_enable_mask; 165 uint32_t samu_dpm_enable_mask; 166 uint32_t sclk_dpm_enable_mask; 167 uint32_t mclk_dpm_enable_mask; 168 uint32_t pcie_dpm_enable_mask; 169 }; 170 171 struct smu7_pcie_perf_range { 172 uint16_t max; 173 uint16_t min; 174 }; 175 176 struct smu7_odn_clock_voltage_dependency_table { 177 uint32_t count; 178 phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER]; 179 }; 180 181 struct smu7_odn_dpm_table { 182 struct phm_odn_clock_levels odn_core_clock_dpm_levels; 183 struct phm_odn_clock_levels odn_memory_clock_dpm_levels; 184 struct smu7_odn_clock_voltage_dependency_table vdd_dependency_on_sclk; 185 struct smu7_odn_clock_voltage_dependency_table vdd_dependency_on_mclk; 186 uint32_t odn_mclk_min_limit; 187 uint32_t min_vddc; 188 uint32_t max_vddc; 189 }; 190 191 struct profile_mode_setting { 192 uint8_t bupdate_sclk; 193 uint8_t sclk_up_hyst; 194 uint8_t sclk_down_hyst; 195 uint16_t sclk_activity; 196 uint8_t bupdate_mclk; 197 uint8_t mclk_up_hyst; 198 uint8_t mclk_down_hyst; 199 uint16_t mclk_activity; 200 }; 201 202 struct smu7_hwmgr { 203 struct smu7_dpm_table dpm_table; 204 struct smu7_dpm_table golden_dpm_table; 205 struct smu7_odn_dpm_table odn_dpm_table; 206 207 uint32_t voting_rights_clients[8]; 208 uint32_t static_screen_threshold_unit; 209 uint32_t static_screen_threshold; 210 uint32_t voltage_control; 211 uint32_t vdd_gfx_control; 212 uint32_t vddc_vddgfx_delta; 213 uint32_t active_auto_throttle_sources; 214 215 struct smu7_clock_registers clock_registers; 216 217 bool is_memory_gddr5; 218 uint16_t acpi_vddc; 219 bool pspp_notify_required; 220 uint16_t force_pcie_gen; 221 uint16_t acpi_pcie_gen; 222 uint32_t pcie_gen_cap; 223 uint32_t pcie_lane_cap; 224 uint32_t pcie_spc_cap; 225 struct smu7_leakage_voltage vddc_leakage; 226 struct smu7_leakage_voltage vddci_leakage; 227 struct smu7_leakage_voltage vddcgfx_leakage; 228 229 uint32_t mvdd_control; 230 uint32_t vddc_mask_low; 231 uint32_t mvdd_mask_low; 232 uint16_t max_vddc_in_pptable; 233 uint16_t min_vddc_in_pptable; 234 uint16_t max_vddci_in_pptable; 235 uint16_t min_vddci_in_pptable; 236 bool is_uvd_enabled; 237 struct smu7_vbios_boot_state vbios_boot_state; 238 239 bool pcie_performance_request; 240 bool battery_state; 241 bool is_tlu_enabled; 242 bool disable_handshake; 243 bool smc_voltage_control_enabled; 244 bool vbi_time_out_support; 245 246 uint32_t soft_regs_start; 247 /* ---- Stuff originally coming from Evergreen ---- */ 248 uint32_t vddci_control; 249 struct pp_atomctrl_voltage_table vddc_voltage_table; 250 struct pp_atomctrl_voltage_table vddci_voltage_table; 251 struct pp_atomctrl_voltage_table mvdd_voltage_table; 252 struct pp_atomctrl_voltage_table vddgfx_voltage_table; 253 254 uint32_t mgcg_cgtt_local2; 255 uint32_t mgcg_cgtt_local3; 256 uint32_t gpio_debug; 257 uint32_t mc_micro_code_feature; 258 uint32_t highest_mclk; 259 uint16_t acpi_vddci; 260 uint8_t mvdd_high_index; 261 uint8_t mvdd_low_index; 262 bool dll_default_on; 263 bool performance_request_registered; 264 265 /* ---- Low Power Features ---- */ 266 bool ulv_supported; 267 268 /* ---- CAC Stuff ---- */ 269 uint32_t cac_table_start; 270 bool cac_configuration_required; 271 bool driver_calculate_cac_leakage; 272 bool cac_enabled; 273 274 /* ---- DPM2 Parameters ---- */ 275 uint32_t power_containment_features; 276 bool enable_dte_feature; 277 bool enable_tdc_limit_feature; 278 bool enable_pkg_pwr_tracking_feature; 279 bool disable_uvd_power_tune_feature; 280 281 282 uint32_t dte_tj_offset; 283 uint32_t fast_watermark_threshold; 284 285 /* ---- Phase Shedding ---- */ 286 uint8_t vddc_phase_shed_control; 287 288 /* ---- DI/DT ---- */ 289 struct smu7_display_timing display_timing; 290 291 /* ---- Thermal Temperature Setting ---- */ 292 struct smu7_thermal_temperature_setting thermal_temp_setting; 293 struct smu7_dpmlevel_enable_mask dpm_level_enable_mask; 294 uint32_t need_update_smu7_dpm_table; 295 uint32_t sclk_dpm_key_disabled; 296 uint32_t mclk_dpm_key_disabled; 297 uint32_t pcie_dpm_key_disabled; 298 uint32_t min_engine_clocks; 299 struct smu7_pcie_perf_range pcie_gen_performance; 300 struct smu7_pcie_perf_range pcie_lane_performance; 301 struct smu7_pcie_perf_range pcie_gen_power_saving; 302 struct smu7_pcie_perf_range pcie_lane_power_saving; 303 bool use_pcie_performance_levels; 304 bool use_pcie_power_saving_levels; 305 uint32_t mclk_dpm0_activity_target; 306 uint32_t low_sclk_interrupt_threshold; 307 uint32_t last_mclk_dpm_enable_mask; 308 bool uvd_enabled; 309 310 /* ---- Power Gating States ---- */ 311 bool uvd_power_gated; 312 bool vce_power_gated; 313 bool need_long_memory_training; 314 315 /* Application power optimization parameters */ 316 bool update_up_hyst; 317 bool update_down_hyst; 318 uint32_t down_hyst; 319 uint32_t up_hyst; 320 uint32_t disable_dpm_mask; 321 bool apply_optimized_settings; 322 323 uint32_t avfs_vdroop_override_setting; 324 bool apply_avfs_cks_off_voltage; 325 uint32_t frame_time_x2; 326 uint16_t mem_latency_high; 327 uint16_t mem_latency_low; 328 uint32_t vr_config; 329 struct profile_mode_setting current_profile_setting; 330 }; 331 332 /* To convert to Q8.8 format for firmware */ 333 #define SMU7_Q88_FORMAT_CONVERSION_UNIT 256 334 335 enum SMU7_I2CLineID { 336 SMU7_I2CLineID_DDC1 = 0x90, 337 SMU7_I2CLineID_DDC2 = 0x91, 338 SMU7_I2CLineID_DDC3 = 0x92, 339 SMU7_I2CLineID_DDC4 = 0x93, 340 SMU7_I2CLineID_DDC5 = 0x94, 341 SMU7_I2CLineID_DDC6 = 0x95, 342 SMU7_I2CLineID_SCLSDA = 0x96, 343 SMU7_I2CLineID_DDCVGA = 0x97 344 }; 345 346 #define SMU7_I2C_DDC1DATA 0 347 #define SMU7_I2C_DDC1CLK 1 348 #define SMU7_I2C_DDC2DATA 2 349 #define SMU7_I2C_DDC2CLK 3 350 #define SMU7_I2C_DDC3DATA 4 351 #define SMU7_I2C_DDC3CLK 5 352 #define SMU7_I2C_SDA 40 353 #define SMU7_I2C_SCL 41 354 #define SMU7_I2C_DDC4DATA 65 355 #define SMU7_I2C_DDC4CLK 66 356 #define SMU7_I2C_DDC5DATA 0x48 357 #define SMU7_I2C_DDC5CLK 0x49 358 #define SMU7_I2C_DDC6DATA 0x4a 359 #define SMU7_I2C_DDC6CLK 0x4b 360 #define SMU7_I2C_DDCVGADATA 0x4c 361 #define SMU7_I2C_DDCVGACLK 0x4d 362 363 #define SMU7_UNUSED_GPIO_PIN 0x7F 364 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock, 365 uint32_t clock_insr); 366 #endif 367 368
