1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * samsung - Common hr-timer support (s3c and s5p)
7 */
8
9 #include <linux/interrupt.h>
10 #include <linux/irq.h>
11 #include <linux/err.h>
12 #include <linux/clk.h>
13 #include <linux/clockchips.h>
14 #include <linux/list.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/of_address.h>
18 #include <linux/of_irq.h>
19 #include <linux/platform_device.h>
20 #include <linux/slab.h>
21 #include <linux/sched_clock.h>
22
23 #include <clocksource/samsung_pwm.h>
24
25
26 /*
27 * Clocksource driver
28 */
29
30 #define REG_TCFG0 0x00
31 #define REG_TCFG1 0x04
32 #define REG_TCON 0x08
33 #define REG_TINT_CSTAT 0x44
34
35 #define REG_TCNTB(chan) (0x0c + 12 * (chan))
36 #define REG_TCMPB(chan) (0x10 + 12 * (chan))
37
38 #define TCFG0_PRESCALER_MASK 0xff
39 #define TCFG0_PRESCALER1_SHIFT 8
40
41 #define TCFG1_SHIFT(x) ((x) * 4)
42 #define TCFG1_MUX_MASK 0xf
43
44 /*
45 * Each channel occupies 4 bits in TCON register, but there is a gap of 4
46 * bits (one channel) after channel 0, so channels have different numbering
47 * when accessing TCON register.
48 *
49 * In addition, the location of autoreload bit for channel 4 (TCON channel 5)
50 * in its set of bits is 2 as opposed to 3 for other channels.
51 */
52 #define TCON_START(chan) (1 << (4 * (chan) + 0))
53 #define TCON_MANUALUPDATE(chan) (1 << (4 * (chan) + 1))
54 #define TCON_INVERT(chan) (1 << (4 * (chan) + 2))
55 #define _TCON_AUTORELOAD(chan) (1 << (4 * (chan) + 3))
56 #define _TCON_AUTORELOAD4(chan) (1 << (4 * (chan) + 2))
57 #define TCON_AUTORELOAD(chan) \
58 ((chan < 5) ? _TCON_AUTORELOAD(chan) : _TCON_AUTORELOAD4(chan))
59
60 DEFINE_SPINLOCK(samsung_pwm_lock);
61 EXPORT_SYMBOL(samsung_pwm_lock);
62
63 struct samsung_pwm_clocksource {
64 void __iomem *base;
65 void __iomem *source_reg;
66 unsigned int irq[SAMSUNG_PWM_NUM];
67 struct samsung_pwm_variant variant;
68
69 struct clk *timerclk;
70
71 unsigned int event_id;
72 unsigned int source_id;
73 unsigned int tcnt_max;
74 unsigned int tscaler_div;
75 unsigned int tdiv;
76
77 unsigned long clock_count_per_tick;
78 };
79
80 static struct samsung_pwm_clocksource pwm;
81
samsung_timer_set_prescale(unsigned int channel,u16 prescale)82 static void samsung_timer_set_prescale(unsigned int channel, u16 prescale)
83 {
84 unsigned long flags;
85 u8 shift = 0;
86 u32 reg;
87
88 if (channel >= 2)
89 shift = TCFG0_PRESCALER1_SHIFT;
90
91 spin_lock_irqsave(&samsung_pwm_lock, flags);
92
93 reg = readl(pwm.base + REG_TCFG0);
94 reg &= ~(TCFG0_PRESCALER_MASK << shift);
95 reg |= (prescale - 1) << shift;
96 writel(reg, pwm.base + REG_TCFG0);
97
98 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
99 }
100
samsung_timer_set_divisor(unsigned int channel,u8 divisor)101 static void samsung_timer_set_divisor(unsigned int channel, u8 divisor)
102 {
103 u8 shift = TCFG1_SHIFT(channel);
104 unsigned long flags;
105 u32 reg;
106 u8 bits;
107
108 bits = (fls(divisor) - 1) - pwm.variant.div_base;
109
110 spin_lock_irqsave(&samsung_pwm_lock, flags);
111
112 reg = readl(pwm.base + REG_TCFG1);
113 reg &= ~(TCFG1_MUX_MASK << shift);
114 reg |= bits << shift;
115 writel(reg, pwm.base + REG_TCFG1);
116
117 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
118 }
119
samsung_time_stop(unsigned int channel)120 static void samsung_time_stop(unsigned int channel)
121 {
122 unsigned long tcon;
123 unsigned long flags;
124
125 if (channel > 0)
126 ++channel;
127
128 spin_lock_irqsave(&samsung_pwm_lock, flags);
129
130 tcon = readl_relaxed(pwm.base + REG_TCON);
131 tcon &= ~TCON_START(channel);
132 writel_relaxed(tcon, pwm.base + REG_TCON);
133
134 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
135 }
136
samsung_time_setup(unsigned int channel,unsigned long tcnt)137 static void samsung_time_setup(unsigned int channel, unsigned long tcnt)
138 {
139 unsigned long tcon;
140 unsigned long flags;
141 unsigned int tcon_chan = channel;
142
143 if (tcon_chan > 0)
144 ++tcon_chan;
145
146 spin_lock_irqsave(&samsung_pwm_lock, flags);
147
148 tcon = readl_relaxed(pwm.base + REG_TCON);
149
150 tcon &= ~(TCON_START(tcon_chan) | TCON_AUTORELOAD(tcon_chan));
151 tcon |= TCON_MANUALUPDATE(tcon_chan);
152
153 writel_relaxed(tcnt, pwm.base + REG_TCNTB(channel));
154 writel_relaxed(tcnt, pwm.base + REG_TCMPB(channel));
155 writel_relaxed(tcon, pwm.base + REG_TCON);
156
157 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
158 }
159
samsung_time_start(unsigned int channel,bool periodic)160 static void samsung_time_start(unsigned int channel, bool periodic)
161 {
162 unsigned long tcon;
163 unsigned long flags;
164
165 if (channel > 0)
166 ++channel;
167
168 spin_lock_irqsave(&samsung_pwm_lock, flags);
169
170 tcon = readl_relaxed(pwm.base + REG_TCON);
171
172 tcon &= ~TCON_MANUALUPDATE(channel);
173 tcon |= TCON_START(channel);
174
175 if (periodic)
176 tcon |= TCON_AUTORELOAD(channel);
177 else
178 tcon &= ~TCON_AUTORELOAD(channel);
179
180 writel_relaxed(tcon, pwm.base + REG_TCON);
181
182 spin_unlock_irqrestore(&samsung_pwm_lock, flags);
183 }
184
samsung_set_next_event(unsigned long cycles,struct clock_event_device * evt)185 static int samsung_set_next_event(unsigned long cycles,
186 struct clock_event_device *evt)
187 {
188 /*
189 * This check is needed to account for internal rounding
190 * errors inside clockevents core, which might result in
191 * passing cycles = 0, which in turn would not generate any
192 * timer interrupt and hang the system.
193 *
194 * Another solution would be to set up the clockevent device
195 * with min_delta = 2, but this would unnecessarily increase
196 * the minimum sleep period.
197 */
198 if (!cycles)
199 cycles = 1;
200
201 samsung_time_setup(pwm.event_id, cycles);
202 samsung_time_start(pwm.event_id, false);
203
204 return 0;
205 }
206
samsung_shutdown(struct clock_event_device * evt)207 static int samsung_shutdown(struct clock_event_device *evt)
208 {
209 samsung_time_stop(pwm.event_id);
210 return 0;
211 }
212
samsung_set_periodic(struct clock_event_device * evt)213 static int samsung_set_periodic(struct clock_event_device *evt)
214 {
215 samsung_time_stop(pwm.event_id);
216 samsung_time_setup(pwm.event_id, pwm.clock_count_per_tick - 1);
217 samsung_time_start(pwm.event_id, true);
218 return 0;
219 }
220
samsung_clockevent_resume(struct clock_event_device * cev)221 static void samsung_clockevent_resume(struct clock_event_device *cev)
222 {
223 samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
224 samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);
225
226 if (pwm.variant.has_tint_cstat) {
227 u32 mask = (1 << pwm.event_id);
228 writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
229 }
230 }
231
232 static struct clock_event_device time_event_device = {
233 .name = "samsung_event_timer",
234 .features = CLOCK_EVT_FEAT_PERIODIC |
235 CLOCK_EVT_FEAT_ONESHOT,
236 .rating = 200,
237 .set_next_event = samsung_set_next_event,
238 .set_state_shutdown = samsung_shutdown,
239 .set_state_periodic = samsung_set_periodic,
240 .set_state_oneshot = samsung_shutdown,
241 .tick_resume = samsung_shutdown,
242 .resume = samsung_clockevent_resume,
243 };
244
samsung_clock_event_isr(int irq,void * dev_id)245 static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id)
246 {
247 struct clock_event_device *evt = dev_id;
248
249 if (pwm.variant.has_tint_cstat) {
250 u32 mask = (1 << pwm.event_id);
251 writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
252 }
253
254 evt->event_handler(evt);
255
256 return IRQ_HANDLED;
257 }
258
259 static struct irqaction samsung_clock_event_irq = {
260 .name = "samsung_time_irq",
261 .flags = IRQF_TIMER | IRQF_IRQPOLL,
262 .handler = samsung_clock_event_isr,
263 .dev_id = &time_event_device,
264 };
265
samsung_clockevent_init(void)266 static void __init samsung_clockevent_init(void)
267 {
268 unsigned long pclk;
269 unsigned long clock_rate;
270 unsigned int irq_number;
271
272 pclk = clk_get_rate(pwm.timerclk);
273
274 samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
275 samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);
276
277 clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
278 pwm.clock_count_per_tick = clock_rate / HZ;
279
280 time_event_device.cpumask = cpumask_of(0);
281 clockevents_config_and_register(&time_event_device,
282 clock_rate, 1, pwm.tcnt_max);
283
284 irq_number = pwm.irq[pwm.event_id];
285 setup_irq(irq_number, &samsung_clock_event_irq);
286
287 if (pwm.variant.has_tint_cstat) {
288 u32 mask = (1 << pwm.event_id);
289 writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
290 }
291 }
292
samsung_clocksource_suspend(struct clocksource * cs)293 static void samsung_clocksource_suspend(struct clocksource *cs)
294 {
295 samsung_time_stop(pwm.source_id);
296 }
297
samsung_clocksource_resume(struct clocksource * cs)298 static void samsung_clocksource_resume(struct clocksource *cs)
299 {
300 samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
301 samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);
302
303 samsung_time_setup(pwm.source_id, pwm.tcnt_max);
304 samsung_time_start(pwm.source_id, true);
305 }
306
samsung_clocksource_read(struct clocksource * c)307 static u64 notrace samsung_clocksource_read(struct clocksource *c)
308 {
309 return ~readl_relaxed(pwm.source_reg);
310 }
311
312 static struct clocksource samsung_clocksource = {
313 .name = "samsung_clocksource_timer",
314 .rating = 250,
315 .read = samsung_clocksource_read,
316 .suspend = samsung_clocksource_suspend,
317 .resume = samsung_clocksource_resume,
318 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
319 };
320
321 /*
322 * Override the global weak sched_clock symbol with this
323 * local implementation which uses the clocksource to get some
324 * better resolution when scheduling the kernel. We accept that
325 * this wraps around for now, since it is just a relative time
326 * stamp. (Inspired by U300 implementation.)
327 */
samsung_read_sched_clock(void)328 static u64 notrace samsung_read_sched_clock(void)
329 {
330 return samsung_clocksource_read(NULL);
331 }
332
samsung_clocksource_init(void)333 static int __init samsung_clocksource_init(void)
334 {
335 unsigned long pclk;
336 unsigned long clock_rate;
337
338 pclk = clk_get_rate(pwm.timerclk);
339
340 samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
341 samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);
342
343 clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
344
345 samsung_time_setup(pwm.source_id, pwm.tcnt_max);
346 samsung_time_start(pwm.source_id, true);
347
348 if (pwm.source_id == 4)
349 pwm.source_reg = pwm.base + 0x40;
350 else
351 pwm.source_reg = pwm.base + pwm.source_id * 0x0c + 0x14;
352
353 sched_clock_register(samsung_read_sched_clock,
354 pwm.variant.bits, clock_rate);
355
356 samsung_clocksource.mask = CLOCKSOURCE_MASK(pwm.variant.bits);
357 return clocksource_register_hz(&samsung_clocksource, clock_rate);
358 }
359
samsung_timer_resources(void)360 static void __init samsung_timer_resources(void)
361 {
362 clk_prepare_enable(pwm.timerclk);
363
364 pwm.tcnt_max = (1UL << pwm.variant.bits) - 1;
365 if (pwm.variant.bits == 16) {
366 pwm.tscaler_div = 25;
367 pwm.tdiv = 2;
368 } else {
369 pwm.tscaler_div = 2;
370 pwm.tdiv = 1;
371 }
372 }
373
374 /*
375 * PWM master driver
376 */
_samsung_pwm_clocksource_init(void)377 static int __init _samsung_pwm_clocksource_init(void)
378 {
379 u8 mask;
380 int channel;
381
382 mask = ~pwm.variant.output_mask & ((1 << SAMSUNG_PWM_NUM) - 1);
383 channel = fls(mask) - 1;
384 if (channel < 0) {
385 pr_crit("failed to find PWM channel for clocksource\n");
386 return -EINVAL;
387 }
388 pwm.source_id = channel;
389
390 mask &= ~(1 << channel);
391 channel = fls(mask) - 1;
392 if (channel < 0) {
393 pr_crit("failed to find PWM channel for clock event\n");
394 return -EINVAL;
395 }
396 pwm.event_id = channel;
397
398 samsung_timer_resources();
399 samsung_clockevent_init();
400
401 return samsung_clocksource_init();
402 }
403
samsung_pwm_clocksource_init(void __iomem * base,unsigned int * irqs,struct samsung_pwm_variant * variant)404 void __init samsung_pwm_clocksource_init(void __iomem *base,
405 unsigned int *irqs, struct samsung_pwm_variant *variant)
406 {
407 pwm.base = base;
408 memcpy(&pwm.variant, variant, sizeof(pwm.variant));
409 memcpy(pwm.irq, irqs, SAMSUNG_PWM_NUM * sizeof(*irqs));
410
411 pwm.timerclk = clk_get(NULL, "timers");
412 if (IS_ERR(pwm.timerclk))
413 panic("failed to get timers clock for timer");
414
415 _samsung_pwm_clocksource_init();
416 }
417
418 #ifdef CONFIG_TIMER_OF
samsung_pwm_alloc(struct device_node * np,const struct samsung_pwm_variant * variant)419 static int __init samsung_pwm_alloc(struct device_node *np,
420 const struct samsung_pwm_variant *variant)
421 {
422 struct property *prop;
423 const __be32 *cur;
424 u32 val;
425 int i;
426
427 memcpy(&pwm.variant, variant, sizeof(pwm.variant));
428 for (i = 0; i < SAMSUNG_PWM_NUM; ++i)
429 pwm.irq[i] = irq_of_parse_and_map(np, i);
430
431 of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
432 if (val >= SAMSUNG_PWM_NUM) {
433 pr_warning("%s: invalid channel index in samsung,pwm-outputs property\n",
434 __func__);
435 continue;
436 }
437 pwm.variant.output_mask |= 1 << val;
438 }
439
440 pwm.base = of_iomap(np, 0);
441 if (!pwm.base) {
442 pr_err("%s: failed to map PWM registers\n", __func__);
443 return -ENXIO;
444 }
445
446 pwm.timerclk = of_clk_get_by_name(np, "timers");
447 if (IS_ERR(pwm.timerclk)) {
448 pr_crit("failed to get timers clock for timer\n");
449 return PTR_ERR(pwm.timerclk);
450 }
451
452 return _samsung_pwm_clocksource_init();
453 }
454
455 static const struct samsung_pwm_variant s3c24xx_variant = {
456 .bits = 16,
457 .div_base = 1,
458 .has_tint_cstat = false,
459 .tclk_mask = (1 << 4),
460 };
461
s3c2410_pwm_clocksource_init(struct device_node * np)462 static int __init s3c2410_pwm_clocksource_init(struct device_node *np)
463 {
464 return samsung_pwm_alloc(np, &s3c24xx_variant);
465 }
466 TIMER_OF_DECLARE(s3c2410_pwm, "samsung,s3c2410-pwm", s3c2410_pwm_clocksource_init);
467
468 static const struct samsung_pwm_variant s3c64xx_variant = {
469 .bits = 32,
470 .div_base = 0,
471 .has_tint_cstat = true,
472 .tclk_mask = (1 << 7) | (1 << 6) | (1 << 5),
473 };
474
s3c64xx_pwm_clocksource_init(struct device_node * np)475 static int __init s3c64xx_pwm_clocksource_init(struct device_node *np)
476 {
477 return samsung_pwm_alloc(np, &s3c64xx_variant);
478 }
479 TIMER_OF_DECLARE(s3c6400_pwm, "samsung,s3c6400-pwm", s3c64xx_pwm_clocksource_init);
480
481 static const struct samsung_pwm_variant s5p64x0_variant = {
482 .bits = 32,
483 .div_base = 0,
484 .has_tint_cstat = true,
485 .tclk_mask = 0,
486 };
487
s5p64x0_pwm_clocksource_init(struct device_node * np)488 static int __init s5p64x0_pwm_clocksource_init(struct device_node *np)
489 {
490 return samsung_pwm_alloc(np, &s5p64x0_variant);
491 }
492 TIMER_OF_DECLARE(s5p6440_pwm, "samsung,s5p6440-pwm", s5p64x0_pwm_clocksource_init);
493
494 static const struct samsung_pwm_variant s5p_variant = {
495 .bits = 32,
496 .div_base = 0,
497 .has_tint_cstat = true,
498 .tclk_mask = (1 << 5),
499 };
500
s5p_pwm_clocksource_init(struct device_node * np)501 static int __init s5p_pwm_clocksource_init(struct device_node *np)
502 {
503 return samsung_pwm_alloc(np, &s5p_variant);
504 }
505 TIMER_OF_DECLARE(s5pc100_pwm, "samsung,s5pc100-pwm", s5p_pwm_clocksource_init);
506 #endif
507
