1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * S3C24XX IRQ handling
4 *
5 * Copyright (c) 2003-2004 Simtec Electronics
6 * Ben Dooks <ben@simtec.co.uk>
7 * Copyright (c) 2012 Heiko Stuebner <heiko@sntech.de>
8 */
9
10 #include <linux/init.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/io.h>
14 #include <linux/err.h>
15 #include <linux/interrupt.h>
16 #include <linux/ioport.h>
17 #include <linux/device.h>
18 #include <linux/irqdomain.h>
19 #include <linux/irqchip.h>
20 #include <linux/irqchip/chained_irq.h>
21 #include <linux/of.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_address.h>
24 #include <linux/spi/s3c24xx.h>
25
26 #include <asm/exception.h>
27 #include <asm/mach/irq.h>
28
29 #include <mach/irqs.h>
30 #include "regs-irq.h"
31 #include "regs-gpio.h"
32
33 #include "cpu.h"
34 #include "regs-irqtype.h"
35 #include "pm.h"
36 #include "s3c24xx.h"
37
38 #define S3C_IRQTYPE_NONE 0
39 #define S3C_IRQTYPE_EINT 1
40 #define S3C_IRQTYPE_EDGE 2
41 #define S3C_IRQTYPE_LEVEL 3
42
43 struct s3c_irq_data {
44 unsigned int type;
45 unsigned long offset;
46 unsigned long parent_irq;
47
48 /* data gets filled during init */
49 struct s3c_irq_intc *intc;
50 unsigned long sub_bits;
51 struct s3c_irq_intc *sub_intc;
52 };
53
54 /*
55 * Structure holding the controller data
56 * @reg_pending register holding pending irqs
57 * @reg_intpnd special register intpnd in main intc
58 * @reg_mask mask register
59 * @domain irq_domain of the controller
60 * @parent parent controller for ext and sub irqs
61 * @irqs irq-data, always s3c_irq_data[32]
62 */
63 struct s3c_irq_intc {
64 void __iomem *reg_pending;
65 void __iomem *reg_intpnd;
66 void __iomem *reg_mask;
67 struct irq_domain *domain;
68 struct s3c_irq_intc *parent;
69 struct s3c_irq_data *irqs;
70 };
71
72 /*
73 * Array holding pointers to the global controller structs
74 * [0] ... main_intc
75 * [1] ... sub_intc
76 * [2] ... main_intc2 on s3c2416
77 */
78 static struct s3c_irq_intc *s3c_intc[3];
79
s3c_irq_mask(struct irq_data * data)80 static void s3c_irq_mask(struct irq_data *data)
81 {
82 struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
83 struct s3c_irq_intc *intc = irq_data->intc;
84 struct s3c_irq_intc *parent_intc = intc->parent;
85 struct s3c_irq_data *parent_data;
86 unsigned long mask;
87 unsigned int irqno;
88
89 mask = readl_relaxed(intc->reg_mask);
90 mask |= (1UL << irq_data->offset);
91 writel_relaxed(mask, intc->reg_mask);
92
93 if (parent_intc) {
94 parent_data = &parent_intc->irqs[irq_data->parent_irq];
95
96 /* check to see if we need to mask the parent IRQ
97 * The parent_irq is always in main_intc, so the hwirq
98 * for find_mapping does not need an offset in any case.
99 */
100 if ((mask & parent_data->sub_bits) == parent_data->sub_bits) {
101 irqno = irq_find_mapping(parent_intc->domain,
102 irq_data->parent_irq);
103 s3c_irq_mask(irq_get_irq_data(irqno));
104 }
105 }
106 }
107
s3c_irq_unmask(struct irq_data * data)108 static void s3c_irq_unmask(struct irq_data *data)
109 {
110 struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
111 struct s3c_irq_intc *intc = irq_data->intc;
112 struct s3c_irq_intc *parent_intc = intc->parent;
113 unsigned long mask;
114 unsigned int irqno;
115
116 mask = readl_relaxed(intc->reg_mask);
117 mask &= ~(1UL << irq_data->offset);
118 writel_relaxed(mask, intc->reg_mask);
119
120 if (parent_intc) {
121 irqno = irq_find_mapping(parent_intc->domain,
122 irq_data->parent_irq);
123 s3c_irq_unmask(irq_get_irq_data(irqno));
124 }
125 }
126
s3c_irq_ack(struct irq_data * data)127 static inline void s3c_irq_ack(struct irq_data *data)
128 {
129 struct s3c_irq_data *irq_data = irq_data_get_irq_chip_data(data);
130 struct s3c_irq_intc *intc = irq_data->intc;
131 unsigned long bitval = 1UL << irq_data->offset;
132
133 writel_relaxed(bitval, intc->reg_pending);
134 if (intc->reg_intpnd)
135 writel_relaxed(bitval, intc->reg_intpnd);
136 }
137
s3c_irq_type(struct irq_data * data,unsigned int type)138 static int s3c_irq_type(struct irq_data *data, unsigned int type)
139 {
140 switch (type) {
141 case IRQ_TYPE_NONE:
142 break;
143 case IRQ_TYPE_EDGE_RISING:
144 case IRQ_TYPE_EDGE_FALLING:
145 case IRQ_TYPE_EDGE_BOTH:
146 irq_set_handler(data->irq, handle_edge_irq);
147 break;
148 case IRQ_TYPE_LEVEL_LOW:
149 case IRQ_TYPE_LEVEL_HIGH:
150 irq_set_handler(data->irq, handle_level_irq);
151 break;
152 default:
153 pr_err("No such irq type %d\n", type);
154 return -EINVAL;
155 }
156
157 return 0;
158 }
159
s3c_irqext_type_set(void __iomem * gpcon_reg,void __iomem * extint_reg,unsigned long gpcon_offset,unsigned long extint_offset,unsigned int type)160 static int s3c_irqext_type_set(void __iomem *gpcon_reg,
161 void __iomem *extint_reg,
162 unsigned long gpcon_offset,
163 unsigned long extint_offset,
164 unsigned int type)
165 {
166 unsigned long newvalue = 0, value;
167
168 /* Set the GPIO to external interrupt mode */
169 value = readl_relaxed(gpcon_reg);
170 value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
171 writel_relaxed(value, gpcon_reg);
172
173 /* Set the external interrupt to pointed trigger type */
174 switch (type)
175 {
176 case IRQ_TYPE_NONE:
177 pr_warn("No edge setting!\n");
178 break;
179
180 case IRQ_TYPE_EDGE_RISING:
181 newvalue = S3C2410_EXTINT_RISEEDGE;
182 break;
183
184 case IRQ_TYPE_EDGE_FALLING:
185 newvalue = S3C2410_EXTINT_FALLEDGE;
186 break;
187
188 case IRQ_TYPE_EDGE_BOTH:
189 newvalue = S3C2410_EXTINT_BOTHEDGE;
190 break;
191
192 case IRQ_TYPE_LEVEL_LOW:
193 newvalue = S3C2410_EXTINT_LOWLEV;
194 break;
195
196 case IRQ_TYPE_LEVEL_HIGH:
197 newvalue = S3C2410_EXTINT_HILEV;
198 break;
199
200 default:
201 pr_err("No such irq type %d\n", type);
202 return -EINVAL;
203 }
204
205 value = readl_relaxed(extint_reg);
206 value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
207 writel_relaxed(value, extint_reg);
208
209 return 0;
210 }
211
s3c_irqext_type(struct irq_data * data,unsigned int type)212 static int s3c_irqext_type(struct irq_data *data, unsigned int type)
213 {
214 void __iomem *extint_reg;
215 void __iomem *gpcon_reg;
216 unsigned long gpcon_offset, extint_offset;
217
218 if ((data->hwirq >= 4) && (data->hwirq <= 7)) {
219 gpcon_reg = S3C2410_GPFCON;
220 extint_reg = S3C24XX_EXTINT0;
221 gpcon_offset = (data->hwirq) * 2;
222 extint_offset = (data->hwirq) * 4;
223 } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) {
224 gpcon_reg = S3C2410_GPGCON;
225 extint_reg = S3C24XX_EXTINT1;
226 gpcon_offset = (data->hwirq - 8) * 2;
227 extint_offset = (data->hwirq - 8) * 4;
228 } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) {
229 gpcon_reg = S3C2410_GPGCON;
230 extint_reg = S3C24XX_EXTINT2;
231 gpcon_offset = (data->hwirq - 8) * 2;
232 extint_offset = (data->hwirq - 16) * 4;
233 } else {
234 return -EINVAL;
235 }
236
237 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
238 extint_offset, type);
239 }
240
s3c_irqext0_type(struct irq_data * data,unsigned int type)241 static int s3c_irqext0_type(struct irq_data *data, unsigned int type)
242 {
243 void __iomem *extint_reg;
244 void __iomem *gpcon_reg;
245 unsigned long gpcon_offset, extint_offset;
246
247 if (data->hwirq <= 3) {
248 gpcon_reg = S3C2410_GPFCON;
249 extint_reg = S3C24XX_EXTINT0;
250 gpcon_offset = (data->hwirq) * 2;
251 extint_offset = (data->hwirq) * 4;
252 } else {
253 return -EINVAL;
254 }
255
256 return s3c_irqext_type_set(gpcon_reg, extint_reg, gpcon_offset,
257 extint_offset, type);
258 }
259
260 static struct irq_chip s3c_irq_chip = {
261 .name = "s3c",
262 .irq_ack = s3c_irq_ack,
263 .irq_mask = s3c_irq_mask,
264 .irq_unmask = s3c_irq_unmask,
265 .irq_set_type = s3c_irq_type,
266 .irq_set_wake = s3c_irq_wake
267 };
268
269 static struct irq_chip s3c_irq_level_chip = {
270 .name = "s3c-level",
271 .irq_mask = s3c_irq_mask,
272 .irq_unmask = s3c_irq_unmask,
273 .irq_ack = s3c_irq_ack,
274 .irq_set_type = s3c_irq_type,
275 };
276
277 static struct irq_chip s3c_irqext_chip = {
278 .name = "s3c-ext",
279 .irq_mask = s3c_irq_mask,
280 .irq_unmask = s3c_irq_unmask,
281 .irq_ack = s3c_irq_ack,
282 .irq_set_type = s3c_irqext_type,
283 .irq_set_wake = s3c_irqext_wake
284 };
285
286 static struct irq_chip s3c_irq_eint0t4 = {
287 .name = "s3c-ext0",
288 .irq_ack = s3c_irq_ack,
289 .irq_mask = s3c_irq_mask,
290 .irq_unmask = s3c_irq_unmask,
291 .irq_set_wake = s3c_irq_wake,
292 .irq_set_type = s3c_irqext0_type,
293 };
294
s3c_irq_demux(struct irq_desc * desc)295 static void s3c_irq_demux(struct irq_desc *desc)
296 {
297 struct irq_chip *chip = irq_desc_get_chip(desc);
298 struct s3c_irq_data *irq_data = irq_desc_get_chip_data(desc);
299 struct s3c_irq_intc *intc = irq_data->intc;
300 struct s3c_irq_intc *sub_intc = irq_data->sub_intc;
301 unsigned int n, offset;
302 unsigned long src, msk;
303
304 /* we're using individual domains for the non-dt case
305 * and one big domain for the dt case where the subintc
306 * starts at hwirq number 32.
307 */
308 offset = irq_domain_get_of_node(intc->domain) ? 32 : 0;
309
310 chained_irq_enter(chip, desc);
311
312 src = readl_relaxed(sub_intc->reg_pending);
313 msk = readl_relaxed(sub_intc->reg_mask);
314
315 src &= ~msk;
316 src &= irq_data->sub_bits;
317
318 while (src) {
319 n = __ffs(src);
320 src &= ~(1 << n);
321 generic_handle_domain_irq(sub_intc->domain, offset + n);
322 }
323
324 chained_irq_exit(chip, desc);
325 }
326
s3c24xx_handle_intc(struct s3c_irq_intc * intc,struct pt_regs * regs,int intc_offset)327 static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
328 struct pt_regs *regs, int intc_offset)
329 {
330 int pnd;
331 int offset;
332
333 pnd = readl_relaxed(intc->reg_intpnd);
334 if (!pnd)
335 return false;
336
337 /* non-dt machines use individual domains */
338 if (!irq_domain_get_of_node(intc->domain))
339 intc_offset = 0;
340
341 /* We have a problem that the INTOFFSET register does not always
342 * show one interrupt. Occasionally we get two interrupts through
343 * the prioritiser, and this causes the INTOFFSET register to show
344 * what looks like the logical-or of the two interrupt numbers.
345 *
346 * Thanks to Klaus, Shannon, et al for helping to debug this problem
347 */
348 offset = readl_relaxed(intc->reg_intpnd + 4);
349
350 /* Find the bit manually, when the offset is wrong.
351 * The pending register only ever contains the one bit of the next
352 * interrupt to handle.
353 */
354 if (!(pnd & (1 << offset)))
355 offset = __ffs(pnd);
356
357 handle_domain_irq(intc->domain, intc_offset + offset, regs);
358 return true;
359 }
360
s3c24xx_handle_irq(struct pt_regs * regs)361 static asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs)
362 {
363 do {
364 if (likely(s3c_intc[0]))
365 if (s3c24xx_handle_intc(s3c_intc[0], regs, 0))
366 continue;
367
368 if (s3c_intc[2])
369 if (s3c24xx_handle_intc(s3c_intc[2], regs, 64))
370 continue;
371
372 break;
373 } while (1);
374 }
375
376 #ifdef CONFIG_FIQ
377 /**
378 * s3c24xx_set_fiq - set the FIQ routing
379 * @irq: IRQ number to route to FIQ on processor.
380 * @ack_ptr: pointer to a location for storing the bit mask
381 * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
382 *
383 * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
384 * @on is true, the @irq is checked to see if it can be routed and the
385 * interrupt controller updated to route the IRQ. If @on is false, the FIQ
386 * routing is cleared, regardless of which @irq is specified.
387 *
388 * returns the mask value for the register.
389 */
s3c24xx_set_fiq(unsigned int irq,u32 * ack_ptr,bool on)390 int s3c24xx_set_fiq(unsigned int irq, u32 *ack_ptr, bool on)
391 {
392 u32 intmod;
393 unsigned offs;
394
395 if (on) {
396 offs = irq - FIQ_START;
397 if (offs > 31)
398 return 0;
399
400 intmod = 1 << offs;
401 } else {
402 intmod = 0;
403 }
404
405 if (ack_ptr)
406 *ack_ptr = intmod;
407 writel_relaxed(intmod, S3C2410_INTMOD);
408
409 return intmod;
410 }
411
412 EXPORT_SYMBOL_GPL(s3c24xx_set_fiq);
413 #endif
414
s3c24xx_irq_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw)415 static int s3c24xx_irq_map(struct irq_domain *h, unsigned int virq,
416 irq_hw_number_t hw)
417 {
418 struct s3c_irq_intc *intc = h->host_data;
419 struct s3c_irq_data *irq_data = &intc->irqs[hw];
420 struct s3c_irq_intc *parent_intc;
421 struct s3c_irq_data *parent_irq_data;
422 unsigned int irqno;
423
424 /* attach controller pointer to irq_data */
425 irq_data->intc = intc;
426 irq_data->offset = hw;
427
428 parent_intc = intc->parent;
429
430 /* set handler and flags */
431 switch (irq_data->type) {
432 case S3C_IRQTYPE_NONE:
433 return 0;
434 case S3C_IRQTYPE_EINT:
435 /* On the S3C2412, the EINT0to3 have a parent irq
436 * but need the s3c_irq_eint0t4 chip
437 */
438 if (parent_intc && (!soc_is_s3c2412() || hw >= 4))
439 irq_set_chip_and_handler(virq, &s3c_irqext_chip,
440 handle_edge_irq);
441 else
442 irq_set_chip_and_handler(virq, &s3c_irq_eint0t4,
443 handle_edge_irq);
444 break;
445 case S3C_IRQTYPE_EDGE:
446 if (parent_intc || intc->reg_pending == S3C2416_SRCPND2)
447 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
448 handle_edge_irq);
449 else
450 irq_set_chip_and_handler(virq, &s3c_irq_chip,
451 handle_edge_irq);
452 break;
453 case S3C_IRQTYPE_LEVEL:
454 if (parent_intc)
455 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
456 handle_level_irq);
457 else
458 irq_set_chip_and_handler(virq, &s3c_irq_chip,
459 handle_level_irq);
460 break;
461 default:
462 pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type);
463 return -EINVAL;
464 }
465
466 irq_set_chip_data(virq, irq_data);
467
468 if (parent_intc && irq_data->type != S3C_IRQTYPE_NONE) {
469 if (irq_data->parent_irq > 31) {
470 pr_err("irq-s3c24xx: parent irq %lu is out of range\n",
471 irq_data->parent_irq);
472 return -EINVAL;
473 }
474
475 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
476 parent_irq_data->sub_intc = intc;
477 parent_irq_data->sub_bits |= (1UL << hw);
478
479 /* attach the demuxer to the parent irq */
480 irqno = irq_find_mapping(parent_intc->domain,
481 irq_data->parent_irq);
482 if (!irqno) {
483 pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n",
484 irq_data->parent_irq);
485 return -EINVAL;
486 }
487 irq_set_chained_handler(irqno, s3c_irq_demux);
488 }
489
490 return 0;
491 }
492
493 static const struct irq_domain_ops s3c24xx_irq_ops = {
494 .map = s3c24xx_irq_map,
495 .xlate = irq_domain_xlate_twocell,
496 };
497
s3c24xx_clear_intc(struct s3c_irq_intc * intc)498 static void s3c24xx_clear_intc(struct s3c_irq_intc *intc)
499 {
500 void __iomem *reg_source;
501 unsigned long pend;
502 unsigned long last;
503 int i;
504
505 /* if intpnd is set, read the next pending irq from there */
506 reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending;
507
508 last = 0;
509 for (i = 0; i < 4; i++) {
510 pend = readl_relaxed(reg_source);
511
512 if (pend == 0 || pend == last)
513 break;
514
515 writel_relaxed(pend, intc->reg_pending);
516 if (intc->reg_intpnd)
517 writel_relaxed(pend, intc->reg_intpnd);
518
519 pr_info("irq: clearing pending status %08x\n", (int)pend);
520 last = pend;
521 }
522 }
523
s3c24xx_init_intc(struct device_node * np,struct s3c_irq_data * irq_data,struct s3c_irq_intc * parent,unsigned long address)524 static struct s3c_irq_intc * __init s3c24xx_init_intc(struct device_node *np,
525 struct s3c_irq_data *irq_data,
526 struct s3c_irq_intc *parent,
527 unsigned long address)
528 {
529 struct s3c_irq_intc *intc;
530 void __iomem *base = (void *)0xf6000000; /* static mapping */
531 int irq_num;
532 int irq_start;
533 int ret;
534
535 intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
536 if (!intc)
537 return ERR_PTR(-ENOMEM);
538
539 intc->irqs = irq_data;
540
541 if (parent)
542 intc->parent = parent;
543
544 /* select the correct data for the controller.
545 * Need to hard code the irq num start and offset
546 * to preserve the static mapping for now
547 */
548 switch (address) {
549 case 0x4a000000:
550 pr_debug("irq: found main intc\n");
551 intc->reg_pending = base;
552 intc->reg_mask = base + 0x08;
553 intc->reg_intpnd = base + 0x10;
554 irq_num = 32;
555 irq_start = S3C2410_IRQ(0);
556 break;
557 case 0x4a000018:
558 pr_debug("irq: found subintc\n");
559 intc->reg_pending = base + 0x18;
560 intc->reg_mask = base + 0x1c;
561 irq_num = 29;
562 irq_start = S3C2410_IRQSUB(0);
563 break;
564 case 0x4a000040:
565 pr_debug("irq: found intc2\n");
566 intc->reg_pending = base + 0x40;
567 intc->reg_mask = base + 0x48;
568 intc->reg_intpnd = base + 0x50;
569 irq_num = 8;
570 irq_start = S3C2416_IRQ(0);
571 break;
572 case 0x560000a4:
573 pr_debug("irq: found eintc\n");
574 base = (void *)0xfd000000;
575
576 intc->reg_mask = base + 0xa4;
577 intc->reg_pending = base + 0xa8;
578 irq_num = 24;
579 irq_start = S3C2410_IRQ(32);
580 break;
581 default:
582 pr_err("irq: unsupported controller address\n");
583 ret = -EINVAL;
584 goto err;
585 }
586
587 /* now that all the data is complete, init the irq-domain */
588 s3c24xx_clear_intc(intc);
589 intc->domain = irq_domain_add_legacy(np, irq_num, irq_start,
590 0, &s3c24xx_irq_ops,
591 intc);
592 if (!intc->domain) {
593 pr_err("irq: could not create irq-domain\n");
594 ret = -EINVAL;
595 goto err;
596 }
597
598 set_handle_irq(s3c24xx_handle_irq);
599
600 return intc;
601
602 err:
603 kfree(intc);
604 return ERR_PTR(ret);
605 }
606
607 static struct s3c_irq_data __maybe_unused init_eint[32] = {
608 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
609 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
610 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
611 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
612 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
613 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
614 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
615 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
616 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
617 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
618 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
619 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
620 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
621 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
622 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
623 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
624 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
625 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
626 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
627 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
628 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
629 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
630 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
631 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
632 };
633
634 #ifdef CONFIG_CPU_S3C2410
635 static struct s3c_irq_data init_s3c2410base[32] = {
636 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
637 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
638 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
639 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
640 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
641 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
642 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
643 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
644 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
645 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
646 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
647 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
648 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
649 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
650 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
651 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
652 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
653 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
654 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
655 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
656 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
657 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
658 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
659 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
660 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
661 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
662 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
663 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
664 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
665 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
666 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
667 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
668 };
669
670 static struct s3c_irq_data init_s3c2410subint[32] = {
671 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
672 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
673 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
674 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
675 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
676 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
677 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
678 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
679 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
680 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
681 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
682 };
683
s3c2410_init_irq(void)684 void __init s3c2410_init_irq(void)
685 {
686 #ifdef CONFIG_FIQ
687 init_FIQ(FIQ_START);
688 #endif
689
690 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2410base[0], NULL,
691 0x4a000000);
692 if (IS_ERR(s3c_intc[0])) {
693 pr_err("irq: could not create main interrupt controller\n");
694 return;
695 }
696
697 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2410subint[0],
698 s3c_intc[0], 0x4a000018);
699 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
700 }
701 #endif
702
703 #ifdef CONFIG_CPU_S3C2412
704 static struct s3c_irq_data init_s3c2412base[32] = {
705 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT0 */
706 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT1 */
707 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT2 */
708 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT3 */
709 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
710 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
711 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
712 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
713 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
714 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
715 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
716 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
717 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
718 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
719 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
720 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
721 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
722 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
723 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
724 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
725 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
726 { .type = S3C_IRQTYPE_LEVEL, }, /* SDI/CF */
727 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
728 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
729 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
730 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
731 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
732 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
733 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
734 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
735 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
736 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
737 };
738
739 static struct s3c_irq_data init_s3c2412eint[32] = {
740 { .type = S3C_IRQTYPE_EINT, .parent_irq = 0 }, /* EINT0 */
741 { .type = S3C_IRQTYPE_EINT, .parent_irq = 1 }, /* EINT1 */
742 { .type = S3C_IRQTYPE_EINT, .parent_irq = 2 }, /* EINT2 */
743 { .type = S3C_IRQTYPE_EINT, .parent_irq = 3 }, /* EINT3 */
744 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT4 */
745 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT5 */
746 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT6 */
747 { .type = S3C_IRQTYPE_EINT, .parent_irq = 4 }, /* EINT7 */
748 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT8 */
749 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT9 */
750 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT10 */
751 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT11 */
752 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT12 */
753 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT13 */
754 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT14 */
755 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT15 */
756 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT16 */
757 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT17 */
758 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT18 */
759 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT19 */
760 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT20 */
761 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT21 */
762 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT22 */
763 { .type = S3C_IRQTYPE_EINT, .parent_irq = 5 }, /* EINT23 */
764 };
765
766 static struct s3c_irq_data init_s3c2412subint[32] = {
767 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
768 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
769 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
770 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
771 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
772 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
773 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
774 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
775 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
776 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
777 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
778 { .type = S3C_IRQTYPE_NONE, },
779 { .type = S3C_IRQTYPE_NONE, },
780 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* SDI */
781 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 21 }, /* CF */
782 };
783
s3c2412_init_irq(void)784 void __init s3c2412_init_irq(void)
785 {
786 pr_info("S3C2412: IRQ Support\n");
787
788 #ifdef CONFIG_FIQ
789 init_FIQ(FIQ_START);
790 #endif
791
792 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2412base[0], NULL,
793 0x4a000000);
794 if (IS_ERR(s3c_intc[0])) {
795 pr_err("irq: could not create main interrupt controller\n");
796 return;
797 }
798
799 s3c24xx_init_intc(NULL, &init_s3c2412eint[0], s3c_intc[0], 0x560000a4);
800 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2412subint[0],
801 s3c_intc[0], 0x4a000018);
802 }
803 #endif
804
805 #ifdef CONFIG_CPU_S3C2416
806 static struct s3c_irq_data init_s3c2416base[32] = {
807 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
808 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
809 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
810 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
811 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
812 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
813 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
814 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
815 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
816 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
817 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
818 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
819 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
820 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
821 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
822 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
823 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
824 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
825 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
826 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
827 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
828 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
829 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
830 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
831 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
832 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
833 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
834 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
835 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
836 { .type = S3C_IRQTYPE_NONE, },
837 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
838 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
839 };
840
841 static struct s3c_irq_data init_s3c2416subint[32] = {
842 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
843 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
844 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
845 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
846 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
847 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
848 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
849 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
850 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
851 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
852 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
853 { .type = S3C_IRQTYPE_NONE }, /* reserved */
854 { .type = S3C_IRQTYPE_NONE }, /* reserved */
855 { .type = S3C_IRQTYPE_NONE }, /* reserved */
856 { .type = S3C_IRQTYPE_NONE }, /* reserved */
857 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
858 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
859 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
860 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
861 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
862 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
863 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
864 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
865 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
866 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
867 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
868 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
869 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
870 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
871 };
872
873 static struct s3c_irq_data init_s3c2416_second[32] = {
874 { .type = S3C_IRQTYPE_EDGE }, /* 2D */
875 { .type = S3C_IRQTYPE_NONE }, /* reserved */
876 { .type = S3C_IRQTYPE_NONE }, /* reserved */
877 { .type = S3C_IRQTYPE_NONE }, /* reserved */
878 { .type = S3C_IRQTYPE_EDGE }, /* PCM0 */
879 { .type = S3C_IRQTYPE_NONE }, /* reserved */
880 { .type = S3C_IRQTYPE_EDGE }, /* I2S0 */
881 };
882
s3c2416_init_irq(void)883 void __init s3c2416_init_irq(void)
884 {
885 pr_info("S3C2416: IRQ Support\n");
886
887 #ifdef CONFIG_FIQ
888 init_FIQ(FIQ_START);
889 #endif
890
891 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2416base[0], NULL,
892 0x4a000000);
893 if (IS_ERR(s3c_intc[0])) {
894 pr_err("irq: could not create main interrupt controller\n");
895 return;
896 }
897
898 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
899 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2416subint[0],
900 s3c_intc[0], 0x4a000018);
901
902 s3c_intc[2] = s3c24xx_init_intc(NULL, &init_s3c2416_second[0],
903 NULL, 0x4a000040);
904 }
905
906 #endif
907
908 #ifdef CONFIG_CPU_S3C2440
909 static struct s3c_irq_data init_s3c2440base[32] = {
910 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
911 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
912 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
913 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
914 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
915 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
916 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
917 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
918 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
919 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
920 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
921 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
922 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
923 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
924 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
925 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
926 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
927 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
928 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
929 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
930 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
931 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
932 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
933 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
934 { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
935 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
936 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
937 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
938 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
939 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
940 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
941 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
942 };
943
944 static struct s3c_irq_data init_s3c2440subint[32] = {
945 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
946 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
947 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
948 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
949 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
950 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
951 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
952 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
953 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
954 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
955 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
956 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
957 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
958 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
959 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
960 };
961
s3c2440_init_irq(void)962 void __init s3c2440_init_irq(void)
963 {
964 pr_info("S3C2440: IRQ Support\n");
965
966 #ifdef CONFIG_FIQ
967 init_FIQ(FIQ_START);
968 #endif
969
970 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2440base[0], NULL,
971 0x4a000000);
972 if (IS_ERR(s3c_intc[0])) {
973 pr_err("irq: could not create main interrupt controller\n");
974 return;
975 }
976
977 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
978 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2440subint[0],
979 s3c_intc[0], 0x4a000018);
980 }
981 #endif
982
983 #ifdef CONFIG_CPU_S3C2442
984 static struct s3c_irq_data init_s3c2442base[32] = {
985 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
986 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
987 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
988 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
989 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
990 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
991 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
992 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
993 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
994 { .type = S3C_IRQTYPE_EDGE, }, /* WDT */
995 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
996 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
997 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
998 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
999 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
1000 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
1001 { .type = S3C_IRQTYPE_EDGE, }, /* LCD */
1002 { .type = S3C_IRQTYPE_EDGE, }, /* DMA0 */
1003 { .type = S3C_IRQTYPE_EDGE, }, /* DMA1 */
1004 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */
1005 { .type = S3C_IRQTYPE_EDGE, }, /* DMA3 */
1006 { .type = S3C_IRQTYPE_EDGE, }, /* SDI */
1007 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
1008 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
1009 { .type = S3C_IRQTYPE_LEVEL, }, /* NFCON */
1010 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
1011 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
1012 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
1013 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
1014 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
1015 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
1016 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
1017 };
1018
1019 static struct s3c_irq_data init_s3c2442subint[32] = {
1020 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1021 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1022 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1023 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1024 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1025 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1026 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1027 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1028 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1029 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
1030 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
1031 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
1032 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
1033 };
1034
s3c2442_init_irq(void)1035 void __init s3c2442_init_irq(void)
1036 {
1037 pr_info("S3C2442: IRQ Support\n");
1038
1039 #ifdef CONFIG_FIQ
1040 init_FIQ(FIQ_START);
1041 #endif
1042
1043 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2442base[0], NULL,
1044 0x4a000000);
1045 if (IS_ERR(s3c_intc[0])) {
1046 pr_err("irq: could not create main interrupt controller\n");
1047 return;
1048 }
1049
1050 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
1051 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2442subint[0],
1052 s3c_intc[0], 0x4a000018);
1053 }
1054 #endif
1055
1056 #ifdef CONFIG_CPU_S3C2443
1057 static struct s3c_irq_data init_s3c2443base[32] = {
1058 { .type = S3C_IRQTYPE_EINT, }, /* EINT0 */
1059 { .type = S3C_IRQTYPE_EINT, }, /* EINT1 */
1060 { .type = S3C_IRQTYPE_EINT, }, /* EINT2 */
1061 { .type = S3C_IRQTYPE_EINT, }, /* EINT3 */
1062 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT4to7 */
1063 { .type = S3C_IRQTYPE_LEVEL, }, /* EINT8to23 */
1064 { .type = S3C_IRQTYPE_LEVEL, }, /* CAM */
1065 { .type = S3C_IRQTYPE_EDGE, }, /* nBATT_FLT */
1066 { .type = S3C_IRQTYPE_EDGE, }, /* TICK */
1067 { .type = S3C_IRQTYPE_LEVEL, }, /* WDT/AC97 */
1068 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER0 */
1069 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER1 */
1070 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER2 */
1071 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER3 */
1072 { .type = S3C_IRQTYPE_EDGE, }, /* TIMER4 */
1073 { .type = S3C_IRQTYPE_LEVEL, }, /* UART2 */
1074 { .type = S3C_IRQTYPE_LEVEL, }, /* LCD */
1075 { .type = S3C_IRQTYPE_LEVEL, }, /* DMA */
1076 { .type = S3C_IRQTYPE_LEVEL, }, /* UART3 */
1077 { .type = S3C_IRQTYPE_EDGE, }, /* CFON */
1078 { .type = S3C_IRQTYPE_EDGE, }, /* SDI1 */
1079 { .type = S3C_IRQTYPE_EDGE, }, /* SDI0 */
1080 { .type = S3C_IRQTYPE_EDGE, }, /* SPI0 */
1081 { .type = S3C_IRQTYPE_LEVEL, }, /* UART1 */
1082 { .type = S3C_IRQTYPE_EDGE, }, /* NAND */
1083 { .type = S3C_IRQTYPE_EDGE, }, /* USBD */
1084 { .type = S3C_IRQTYPE_EDGE, }, /* USBH */
1085 { .type = S3C_IRQTYPE_EDGE, }, /* IIC */
1086 { .type = S3C_IRQTYPE_LEVEL, }, /* UART0 */
1087 { .type = S3C_IRQTYPE_EDGE, }, /* SPI1 */
1088 { .type = S3C_IRQTYPE_EDGE, }, /* RTC */
1089 { .type = S3C_IRQTYPE_LEVEL, }, /* ADCPARENT */
1090 };
1091
1092
1093 static struct s3c_irq_data init_s3c2443subint[32] = {
1094 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1095 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1096 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1097 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1098 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1099 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1100 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1101 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1102 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1103 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* TC */
1104 { .type = S3C_IRQTYPE_EDGE, .parent_irq = 31 }, /* ADC */
1105 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_C */
1106 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 6 }, /* CAM_P */
1107 { .type = S3C_IRQTYPE_NONE }, /* reserved */
1108 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD1 */
1109 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD2 */
1110 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD3 */
1111 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 16 }, /* LCD4 */
1112 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA0 */
1113 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA1 */
1114 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
1115 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA3 */
1116 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA4 */
1117 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA5 */
1118 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
1119 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
1120 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
1121 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* WDT */
1122 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 9 }, /* AC97 */
1123 };
1124
s3c2443_init_irq(void)1125 void __init s3c2443_init_irq(void)
1126 {
1127 pr_info("S3C2443: IRQ Support\n");
1128
1129 #ifdef CONFIG_FIQ
1130 init_FIQ(FIQ_START);
1131 #endif
1132
1133 s3c_intc[0] = s3c24xx_init_intc(NULL, &init_s3c2443base[0], NULL,
1134 0x4a000000);
1135 if (IS_ERR(s3c_intc[0])) {
1136 pr_err("irq: could not create main interrupt controller\n");
1137 return;
1138 }
1139
1140 s3c24xx_init_intc(NULL, &init_eint[0], s3c_intc[0], 0x560000a4);
1141 s3c_intc[1] = s3c24xx_init_intc(NULL, &init_s3c2443subint[0],
1142 s3c_intc[0], 0x4a000018);
1143 }
1144 #endif
1145
1146 #ifdef CONFIG_OF
s3c24xx_irq_map_of(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw)1147 static int s3c24xx_irq_map_of(struct irq_domain *h, unsigned int virq,
1148 irq_hw_number_t hw)
1149 {
1150 unsigned int ctrl_num = hw / 32;
1151 unsigned int intc_hw = hw % 32;
1152 struct s3c_irq_intc *intc = s3c_intc[ctrl_num];
1153 struct s3c_irq_intc *parent_intc = intc->parent;
1154 struct s3c_irq_data *irq_data = &intc->irqs[intc_hw];
1155
1156 /* attach controller pointer to irq_data */
1157 irq_data->intc = intc;
1158 irq_data->offset = intc_hw;
1159
1160 if (!parent_intc)
1161 irq_set_chip_and_handler(virq, &s3c_irq_chip, handle_edge_irq);
1162 else
1163 irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
1164 handle_edge_irq);
1165
1166 irq_set_chip_data(virq, irq_data);
1167
1168 return 0;
1169 }
1170
1171 /* Translate our of irq notation
1172 * format: <ctrl_num ctrl_irq parent_irq type>
1173 */
s3c24xx_irq_xlate_of(struct irq_domain * d,struct device_node * n,const u32 * intspec,unsigned int intsize,irq_hw_number_t * out_hwirq,unsigned int * out_type)1174 static int s3c24xx_irq_xlate_of(struct irq_domain *d, struct device_node *n,
1175 const u32 *intspec, unsigned int intsize,
1176 irq_hw_number_t *out_hwirq, unsigned int *out_type)
1177 {
1178 struct s3c_irq_intc *intc;
1179 struct s3c_irq_intc *parent_intc;
1180 struct s3c_irq_data *irq_data;
1181 struct s3c_irq_data *parent_irq_data;
1182 int irqno;
1183
1184 if (WARN_ON(intsize < 4))
1185 return -EINVAL;
1186
1187 if (intspec[0] > 2 || !s3c_intc[intspec[0]]) {
1188 pr_err("controller number %d invalid\n", intspec[0]);
1189 return -EINVAL;
1190 }
1191 intc = s3c_intc[intspec[0]];
1192
1193 *out_hwirq = intspec[0] * 32 + intspec[2];
1194 *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK;
1195
1196 parent_intc = intc->parent;
1197 if (parent_intc) {
1198 irq_data = &intc->irqs[intspec[2]];
1199 irq_data->parent_irq = intspec[1];
1200 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq];
1201 parent_irq_data->sub_intc = intc;
1202 parent_irq_data->sub_bits |= (1UL << intspec[2]);
1203
1204 /* parent_intc is always s3c_intc[0], so no offset */
1205 irqno = irq_create_mapping(parent_intc->domain, intspec[1]);
1206 if (irqno < 0) {
1207 pr_err("irq: could not map parent interrupt\n");
1208 return irqno;
1209 }
1210
1211 irq_set_chained_handler(irqno, s3c_irq_demux);
1212 }
1213
1214 return 0;
1215 }
1216
1217 static const struct irq_domain_ops s3c24xx_irq_ops_of = {
1218 .map = s3c24xx_irq_map_of,
1219 .xlate = s3c24xx_irq_xlate_of,
1220 };
1221
1222 struct s3c24xx_irq_of_ctrl {
1223 char *name;
1224 unsigned long offset;
1225 struct s3c_irq_intc **handle;
1226 struct s3c_irq_intc **parent;
1227 struct irq_domain_ops *ops;
1228 };
1229
s3c_init_intc_of(struct device_node * np,struct device_node * interrupt_parent,struct s3c24xx_irq_of_ctrl * s3c_ctrl,int num_ctrl)1230 static int __init s3c_init_intc_of(struct device_node *np,
1231 struct device_node *interrupt_parent,
1232 struct s3c24xx_irq_of_ctrl *s3c_ctrl, int num_ctrl)
1233 {
1234 struct s3c_irq_intc *intc;
1235 struct s3c24xx_irq_of_ctrl *ctrl;
1236 struct irq_domain *domain;
1237 void __iomem *reg_base;
1238 int i;
1239
1240 reg_base = of_iomap(np, 0);
1241 if (!reg_base) {
1242 pr_err("irq-s3c24xx: could not map irq registers\n");
1243 return -EINVAL;
1244 }
1245
1246 domain = irq_domain_add_linear(np, num_ctrl * 32,
1247 &s3c24xx_irq_ops_of, NULL);
1248 if (!domain) {
1249 pr_err("irq: could not create irq-domain\n");
1250 return -EINVAL;
1251 }
1252
1253 for (i = 0; i < num_ctrl; i++) {
1254 ctrl = &s3c_ctrl[i];
1255
1256 pr_debug("irq: found controller %s\n", ctrl->name);
1257
1258 intc = kzalloc(sizeof(struct s3c_irq_intc), GFP_KERNEL);
1259 if (!intc)
1260 return -ENOMEM;
1261
1262 intc->domain = domain;
1263 intc->irqs = kcalloc(32, sizeof(struct s3c_irq_data),
1264 GFP_KERNEL);
1265 if (!intc->irqs) {
1266 kfree(intc);
1267 return -ENOMEM;
1268 }
1269
1270 if (ctrl->parent) {
1271 intc->reg_pending = reg_base + ctrl->offset;
1272 intc->reg_mask = reg_base + ctrl->offset + 0x4;
1273
1274 if (*(ctrl->parent)) {
1275 intc->parent = *(ctrl->parent);
1276 } else {
1277 pr_warn("irq: parent of %s missing\n",
1278 ctrl->name);
1279 kfree(intc->irqs);
1280 kfree(intc);
1281 continue;
1282 }
1283 } else {
1284 intc->reg_pending = reg_base + ctrl->offset;
1285 intc->reg_mask = reg_base + ctrl->offset + 0x08;
1286 intc->reg_intpnd = reg_base + ctrl->offset + 0x10;
1287 }
1288
1289 s3c24xx_clear_intc(intc);
1290 s3c_intc[i] = intc;
1291 }
1292
1293 set_handle_irq(s3c24xx_handle_irq);
1294
1295 return 0;
1296 }
1297
1298 static struct s3c24xx_irq_of_ctrl s3c2410_ctrl[] = {
1299 {
1300 .name = "intc",
1301 .offset = 0,
1302 }, {
1303 .name = "subintc",
1304 .offset = 0x18,
1305 .parent = &s3c_intc[0],
1306 }
1307 };
1308
s3c2410_init_intc_of(struct device_node * np,struct device_node * interrupt_parent)1309 static int __init s3c2410_init_intc_of(struct device_node *np,
1310 struct device_node *interrupt_parent)
1311 {
1312 return s3c_init_intc_of(np, interrupt_parent,
1313 s3c2410_ctrl, ARRAY_SIZE(s3c2410_ctrl));
1314 }
1315 IRQCHIP_DECLARE(s3c2410_irq, "samsung,s3c2410-irq", s3c2410_init_intc_of);
1316
1317 static struct s3c24xx_irq_of_ctrl s3c2416_ctrl[] = {
1318 {
1319 .name = "intc",
1320 .offset = 0,
1321 }, {
1322 .name = "subintc",
1323 .offset = 0x18,
1324 .parent = &s3c_intc[0],
1325 }, {
1326 .name = "intc2",
1327 .offset = 0x40,
1328 }
1329 };
1330
s3c2416_init_intc_of(struct device_node * np,struct device_node * interrupt_parent)1331 static int __init s3c2416_init_intc_of(struct device_node *np,
1332 struct device_node *interrupt_parent)
1333 {
1334 return s3c_init_intc_of(np, interrupt_parent,
1335 s3c2416_ctrl, ARRAY_SIZE(s3c2416_ctrl));
1336 }
1337 IRQCHIP_DECLARE(s3c2416_irq, "samsung,s3c2416-irq", s3c2416_init_intc_of);
1338 #endif
1339
