1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
4 *
5 * Common Clock Framework support for S3C2412 and S3C2413.
6 */
7
8 #include <linux/clk-provider.h>
9 #include <linux/io.h>
10 #include <linux/of.h>
11 #include <linux/of_address.h>
12 #include <linux/reboot.h>
13
14 #include <dt-bindings/clock/s3c2412.h>
15
16 #include "clk.h"
17 #include "clk-pll.h"
18
19 #define LOCKTIME 0x00
20 #define MPLLCON 0x04
21 #define UPLLCON 0x08
22 #define CLKCON 0x0c
23 #define CLKDIVN 0x14
24 #define CLKSRC 0x1c
25 #define SWRST 0x30
26
27 static void __iomem *reg_base;
28
29 /*
30 * list of controller registers to be saved and restored during a
31 * suspend/resume cycle.
32 */
33 static unsigned long s3c2412_clk_regs[] __initdata = {
34 LOCKTIME,
35 MPLLCON,
36 UPLLCON,
37 CLKCON,
38 CLKDIVN,
39 CLKSRC,
40 };
41
42 static struct clk_div_table divxti_d[] = {
43 { .val = 0, .div = 1 },
44 { .val = 1, .div = 2 },
45 { .val = 2, .div = 4 },
46 { .val = 3, .div = 6 },
47 { .val = 4, .div = 8 },
48 { .val = 5, .div = 10 },
49 { .val = 6, .div = 12 },
50 { .val = 7, .div = 14 },
51 { /* sentinel */ },
52 };
53
54 static struct samsung_div_clock s3c2412_dividers[] __initdata = {
55 DIV_T(0, "div_xti", "xti", CLKSRC, 0, 3, divxti_d),
56 DIV(0, "div_cam", "mux_cam", CLKDIVN, 16, 4),
57 DIV(0, "div_i2s", "mux_i2s", CLKDIVN, 12, 4),
58 DIV(0, "div_uart", "mux_uart", CLKDIVN, 8, 4),
59 DIV(0, "div_usb", "mux_usb", CLKDIVN, 6, 1),
60 DIV(0, "div_hclk_half", "hclk", CLKDIVN, 5, 1),
61 DIV(ARMDIV, "armdiv", "msysclk", CLKDIVN, 3, 1),
62 DIV(PCLK, "pclk", "hclk", CLKDIVN, 2, 1),
63 DIV(HCLK, "hclk", "armdiv", CLKDIVN, 0, 2),
64 };
65
66 static struct samsung_fixed_factor_clock s3c2412_ffactor[] __initdata = {
67 FFACTOR(0, "ff_hclk", "hclk", 2, 1, CLK_SET_RATE_PARENT),
68 };
69
70 /*
71 * The first two use the OM[4] setting, which is not readable from
72 * software, so assume it is set to xti.
73 */
74 PNAME(erefclk_p) = { "xti", "xti", "xti", "ext" };
75 PNAME(urefclk_p) = { "xti", "xti", "xti", "ext" };
76
77 PNAME(camclk_p) = { "usysclk", "hclk" };
78 PNAME(usbclk_p) = { "usysclk", "hclk" };
79 PNAME(i2sclk_p) = { "erefclk", "mpll" };
80 PNAME(uartclk_p) = { "erefclk", "mpll" };
81 PNAME(usysclk_p) = { "urefclk", "upll" };
82 PNAME(msysclk_p) = { "mdivclk", "mpll" };
83 PNAME(mdivclk_p) = { "xti", "div_xti" };
84 PNAME(armclk_p) = { "armdiv", "hclk" };
85
86 static struct samsung_mux_clock s3c2412_muxes[] __initdata = {
87 MUX(0, "erefclk", erefclk_p, CLKSRC, 14, 2),
88 MUX(0, "urefclk", urefclk_p, CLKSRC, 12, 2),
89 MUX(0, "mux_cam", camclk_p, CLKSRC, 11, 1),
90 MUX(0, "mux_usb", usbclk_p, CLKSRC, 10, 1),
91 MUX(0, "mux_i2s", i2sclk_p, CLKSRC, 9, 1),
92 MUX(0, "mux_uart", uartclk_p, CLKSRC, 8, 1),
93 MUX(USYSCLK, "usysclk", usysclk_p, CLKSRC, 5, 1),
94 MUX(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1),
95 MUX(MDIVCLK, "mdivclk", mdivclk_p, CLKSRC, 3, 1),
96 MUX(ARMCLK, "armclk", armclk_p, CLKDIVN, 4, 1),
97 };
98
99 static struct samsung_pll_clock s3c2412_plls[] __initdata = {
100 PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti", LOCKTIME, MPLLCON, NULL),
101 PLL(pll_s3c2410_upll, UPLL, "upll", "urefclk", LOCKTIME, UPLLCON, NULL),
102 };
103
104 static struct samsung_gate_clock s3c2412_gates[] __initdata = {
105 GATE(PCLK_WDT, "wdt", "pclk", CLKCON, 28, 0, 0),
106 GATE(PCLK_SPI, "spi", "pclk", CLKCON, 27, 0, 0),
107 GATE(PCLK_I2S, "i2s", "pclk", CLKCON, 26, 0, 0),
108 GATE(PCLK_I2C, "i2c", "pclk", CLKCON, 25, 0, 0),
109 GATE(PCLK_ADC, "adc", "pclk", CLKCON, 24, 0, 0),
110 GATE(PCLK_RTC, "rtc", "pclk", CLKCON, 23, 0, 0),
111 GATE(PCLK_GPIO, "gpio", "pclk", CLKCON, 22, CLK_IGNORE_UNUSED, 0),
112 GATE(PCLK_UART2, "uart2", "pclk", CLKCON, 21, 0, 0),
113 GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 20, 0, 0),
114 GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 19, 0, 0),
115 GATE(PCLK_SDI, "sdi", "pclk", CLKCON, 18, 0, 0),
116 GATE(PCLK_PWM, "pwm", "pclk", CLKCON, 17, 0, 0),
117 GATE(PCLK_USBD, "usb-device", "pclk", CLKCON, 16, 0, 0),
118 GATE(SCLK_CAM, "sclk_cam", "div_cam", CLKCON, 15, 0, 0),
119 GATE(SCLK_UART, "sclk_uart", "div_uart", CLKCON, 14, 0, 0),
120 GATE(SCLK_I2S, "sclk_i2s", "div_i2s", CLKCON, 13, 0, 0),
121 GATE(SCLK_USBH, "sclk_usbh", "div_usb", CLKCON, 12, 0, 0),
122 GATE(SCLK_USBD, "sclk_usbd", "div_usb", CLKCON, 11, 0, 0),
123 GATE(HCLK_HALF, "hclk_half", "div_hclk_half", CLKCON, 10, CLK_IGNORE_UNUSED, 0),
124 GATE(HCLK_X2, "hclkx2", "ff_hclk", CLKCON, 9, CLK_IGNORE_UNUSED, 0),
125 GATE(HCLK_SDRAM, "sdram", "hclk", CLKCON, 8, CLK_IGNORE_UNUSED, 0),
126 GATE(HCLK_USBH, "usb-host", "hclk", CLKCON, 6, 0, 0),
127 GATE(HCLK_LCD, "lcd", "hclk", CLKCON, 5, 0, 0),
128 GATE(HCLK_NAND, "nand", "hclk", CLKCON, 4, 0, 0),
129 GATE(HCLK_DMA3, "dma3", "hclk", CLKCON, 3, CLK_IGNORE_UNUSED, 0),
130 GATE(HCLK_DMA2, "dma2", "hclk", CLKCON, 2, CLK_IGNORE_UNUSED, 0),
131 GATE(HCLK_DMA1, "dma1", "hclk", CLKCON, 1, CLK_IGNORE_UNUSED, 0),
132 GATE(HCLK_DMA0, "dma0", "hclk", CLKCON, 0, CLK_IGNORE_UNUSED, 0),
133 };
134
135 static struct samsung_clock_alias s3c2412_aliases[] __initdata = {
136 ALIAS(PCLK_UART0, "s3c2412-uart.0", "uart"),
137 ALIAS(PCLK_UART1, "s3c2412-uart.1", "uart"),
138 ALIAS(PCLK_UART2, "s3c2412-uart.2", "uart"),
139 ALIAS(PCLK_UART0, "s3c2412-uart.0", "clk_uart_baud2"),
140 ALIAS(PCLK_UART1, "s3c2412-uart.1", "clk_uart_baud2"),
141 ALIAS(PCLK_UART2, "s3c2412-uart.2", "clk_uart_baud2"),
142 ALIAS(SCLK_UART, NULL, "clk_uart_baud3"),
143 ALIAS(PCLK_I2C, "s3c2410-i2c.0", "i2c"),
144 ALIAS(PCLK_ADC, NULL, "adc"),
145 ALIAS(PCLK_RTC, NULL, "rtc"),
146 ALIAS(PCLK_PWM, NULL, "timers"),
147 ALIAS(HCLK_LCD, NULL, "lcd"),
148 ALIAS(PCLK_USBD, NULL, "usb-device"),
149 ALIAS(SCLK_USBD, NULL, "usb-bus-gadget"),
150 ALIAS(HCLK_USBH, NULL, "usb-host"),
151 ALIAS(SCLK_USBH, NULL, "usb-bus-host"),
152 ALIAS(ARMCLK, NULL, "armclk"),
153 ALIAS(HCLK, NULL, "hclk"),
154 ALIAS(MPLL, NULL, "mpll"),
155 ALIAS(MSYSCLK, NULL, "fclk"),
156 };
157
s3c2412_restart(struct notifier_block * this,unsigned long mode,void * cmd)158 static int s3c2412_restart(struct notifier_block *this,
159 unsigned long mode, void *cmd)
160 {
161 /* errata "Watch-dog/Software Reset Problem" specifies that
162 * this reset must be done with the SYSCLK sourced from
163 * EXTCLK instead of FOUT to avoid a glitch in the reset
164 * mechanism.
165 *
166 * See the watchdog section of the S3C2412 manual for more
167 * information on this fix.
168 */
169
170 __raw_writel(0x00, reg_base + CLKSRC);
171 __raw_writel(0x533C2412, reg_base + SWRST);
172 return NOTIFY_DONE;
173 }
174
175 static struct notifier_block s3c2412_restart_handler = {
176 .notifier_call = s3c2412_restart,
177 .priority = 129,
178 };
179
180 /*
181 * fixed rate clocks generated outside the soc
182 * Only necessary until the devicetree-move is complete
183 */
184 #define XTI 1
185 static struct samsung_fixed_rate_clock s3c2412_common_frate_clks[] __initdata = {
186 FRATE(XTI, "xti", NULL, 0, 0),
187 FRATE(0, "ext", NULL, 0, 0),
188 };
189
s3c2412_common_clk_register_fixed_ext(struct samsung_clk_provider * ctx,unsigned long xti_f,unsigned long ext_f)190 static void __init s3c2412_common_clk_register_fixed_ext(
191 struct samsung_clk_provider *ctx,
192 unsigned long xti_f, unsigned long ext_f)
193 {
194 /* xtal alias is necessary for the current cpufreq driver */
195 struct samsung_clock_alias xti_alias = ALIAS(XTI, NULL, "xtal");
196
197 s3c2412_common_frate_clks[0].fixed_rate = xti_f;
198 s3c2412_common_frate_clks[1].fixed_rate = ext_f;
199 samsung_clk_register_fixed_rate(ctx, s3c2412_common_frate_clks,
200 ARRAY_SIZE(s3c2412_common_frate_clks));
201
202 samsung_clk_register_alias(ctx, &xti_alias, 1);
203 }
204
s3c2412_common_clk_init(struct device_node * np,unsigned long xti_f,unsigned long ext_f,void __iomem * base)205 void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f,
206 unsigned long ext_f, void __iomem *base)
207 {
208 struct samsung_clk_provider *ctx;
209 int ret;
210 reg_base = base;
211
212 if (np) {
213 reg_base = of_iomap(np, 0);
214 if (!reg_base)
215 panic("%s: failed to map registers\n", __func__);
216 }
217
218 ctx = samsung_clk_init(np, reg_base, NR_CLKS);
219
220 /* Register external clocks only in non-dt cases */
221 if (!np)
222 s3c2412_common_clk_register_fixed_ext(ctx, xti_f, ext_f);
223
224 /* Register PLLs. */
225 samsung_clk_register_pll(ctx, s3c2412_plls, ARRAY_SIZE(s3c2412_plls),
226 reg_base);
227
228 /* Register common internal clocks. */
229 samsung_clk_register_mux(ctx, s3c2412_muxes, ARRAY_SIZE(s3c2412_muxes));
230 samsung_clk_register_div(ctx, s3c2412_dividers,
231 ARRAY_SIZE(s3c2412_dividers));
232 samsung_clk_register_gate(ctx, s3c2412_gates,
233 ARRAY_SIZE(s3c2412_gates));
234 samsung_clk_register_fixed_factor(ctx, s3c2412_ffactor,
235 ARRAY_SIZE(s3c2412_ffactor));
236 samsung_clk_register_alias(ctx, s3c2412_aliases,
237 ARRAY_SIZE(s3c2412_aliases));
238
239 samsung_clk_sleep_init(reg_base, s3c2412_clk_regs,
240 ARRAY_SIZE(s3c2412_clk_regs));
241
242 samsung_clk_of_add_provider(np, ctx);
243
244 ret = register_restart_handler(&s3c2412_restart_handler);
245 if (ret)
246 pr_warn("cannot register restart handler, %d\n", ret);
247 }
248
s3c2412_clk_init(struct device_node * np)249 static void __init s3c2412_clk_init(struct device_node *np)
250 {
251 s3c2412_common_clk_init(np, 0, 0, NULL);
252 }
253 CLK_OF_DECLARE(s3c2412_clk, "samsung,s3c2412-clock", s3c2412_clk_init);
254
