1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
4 *
5 * Common Clock Framework support for S3C2410 and following SoCs.
6 */
7
8 #include <linux/clk-provider.h>
9 #include <linux/of.h>
10 #include <linux/of_address.h>
11
12 #include <dt-bindings/clock/s3c2410.h>
13
14 #include "clk.h"
15 #include "clk-pll.h"
16
17 #define LOCKTIME 0x00
18 #define MPLLCON 0x04
19 #define UPLLCON 0x08
20 #define CLKCON 0x0c
21 #define CLKSLOW 0x10
22 #define CLKDIVN 0x14
23 #define CAMDIVN 0x18
24
25 /* the soc types */
26 enum supported_socs {
27 S3C2410,
28 S3C2440,
29 S3C2442,
30 };
31
32 /* list of PLLs to be registered */
33 enum s3c2410_plls {
34 mpll, upll,
35 };
36
37 static void __iomem *reg_base;
38
39 /*
40 * list of controller registers to be saved and restored during a
41 * suspend/resume cycle.
42 */
43 static unsigned long s3c2410_clk_regs[] __initdata = {
44 LOCKTIME,
45 MPLLCON,
46 UPLLCON,
47 CLKCON,
48 CLKSLOW,
49 CLKDIVN,
50 CAMDIVN,
51 };
52
53 PNAME(fclk_p) = { "mpll", "div_slow" };
54
55 static struct samsung_mux_clock s3c2410_common_muxes[] __initdata = {
56 MUX(FCLK, "fclk", fclk_p, CLKSLOW, 4, 1),
57 };
58
59 static struct clk_div_table divslow_d[] = {
60 { .val = 0, .div = 1 },
61 { .val = 1, .div = 2 },
62 { .val = 2, .div = 4 },
63 { .val = 3, .div = 6 },
64 { .val = 4, .div = 8 },
65 { .val = 5, .div = 10 },
66 { .val = 6, .div = 12 },
67 { .val = 7, .div = 14 },
68 { /* sentinel */ },
69 };
70
71 static struct samsung_div_clock s3c2410_common_dividers[] __initdata = {
72 DIV_T(0, "div_slow", "xti", CLKSLOW, 0, 3, divslow_d),
73 DIV(PCLK, "pclk", "hclk", CLKDIVN, 0, 1),
74 };
75
76 static struct samsung_gate_clock s3c2410_common_gates[] __initdata = {
77 GATE(PCLK_SPI, "spi", "pclk", CLKCON, 18, 0, 0),
78 GATE(PCLK_I2S, "i2s", "pclk", CLKCON, 17, 0, 0),
79 GATE(PCLK_I2C, "i2c", "pclk", CLKCON, 16, 0, 0),
80 GATE(PCLK_ADC, "adc", "pclk", CLKCON, 15, 0, 0),
81 GATE(PCLK_RTC, "rtc", "pclk", CLKCON, 14, 0, 0),
82 GATE(PCLK_GPIO, "gpio", "pclk", CLKCON, 13, CLK_IGNORE_UNUSED, 0),
83 GATE(PCLK_UART2, "uart2", "pclk", CLKCON, 12, 0, 0),
84 GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 11, 0, 0),
85 GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 10, 0, 0),
86 GATE(PCLK_SDI, "sdi", "pclk", CLKCON, 9, 0, 0),
87 GATE(PCLK_PWM, "pwm", "pclk", CLKCON, 8, 0, 0),
88 GATE(HCLK_USBD, "usb-device", "hclk", CLKCON, 7, 0, 0),
89 GATE(HCLK_USBH, "usb-host", "hclk", CLKCON, 6, 0, 0),
90 GATE(HCLK_LCD, "lcd", "hclk", CLKCON, 5, 0, 0),
91 GATE(HCLK_NAND, "nand", "hclk", CLKCON, 4, 0, 0),
92 };
93
94 /* should be added _after_ the soc-specific clocks are created */
95 static struct samsung_clock_alias s3c2410_common_aliases[] __initdata = {
96 ALIAS(PCLK_I2C, "s3c2410-i2c.0", "i2c"),
97 ALIAS(PCLK_ADC, NULL, "adc"),
98 ALIAS(PCLK_RTC, NULL, "rtc"),
99 ALIAS(PCLK_PWM, NULL, "timers"),
100 ALIAS(HCLK_LCD, NULL, "lcd"),
101 ALIAS(HCLK_USBD, NULL, "usb-device"),
102 ALIAS(HCLK_USBH, NULL, "usb-host"),
103 ALIAS(UCLK, NULL, "usb-bus-host"),
104 ALIAS(UCLK, NULL, "usb-bus-gadget"),
105 ALIAS(ARMCLK, NULL, "armclk"),
106 ALIAS(UCLK, NULL, "uclk"),
107 ALIAS(HCLK, NULL, "hclk"),
108 ALIAS(MPLL, NULL, "mpll"),
109 ALIAS(FCLK, NULL, "fclk"),
110 ALIAS(PCLK, NULL, "watchdog"),
111 ALIAS(PCLK_SDI, NULL, "sdi"),
112 ALIAS(HCLK_NAND, NULL, "nand"),
113 ALIAS(PCLK_I2S, NULL, "iis"),
114 ALIAS(PCLK_I2C, NULL, "i2c"),
115 };
116
117 /* S3C2410 specific clocks */
118
119 static struct samsung_pll_rate_table pll_s3c2410_12mhz_tbl[] __initdata = {
120 /* sorted in descending order */
121 /* 2410A extras */
122 PLL_S3C2410_MPLL_RATE(12 * MHZ, 270000000, 127, 1, 1),
123 PLL_S3C2410_MPLL_RATE(12 * MHZ, 268000000, 126, 1, 1),
124 PLL_S3C2410_MPLL_RATE(12 * MHZ, 266000000, 125, 1, 1),
125 PLL_S3C2410_MPLL_RATE(12 * MHZ, 226000000, 105, 1, 1),
126 PLL_S3C2410_MPLL_RATE(12 * MHZ, 210000000, 132, 2, 1),
127 /* 2410 common */
128 PLL_S3C2410_MPLL_RATE(12 * MHZ, 202800000, 161, 3, 1),
129 PLL_S3C2410_MPLL_RATE(12 * MHZ, 192000000, 88, 1, 1),
130 PLL_S3C2410_MPLL_RATE(12 * MHZ, 186000000, 85, 1, 1),
131 PLL_S3C2410_MPLL_RATE(12 * MHZ, 180000000, 82, 1, 1),
132 PLL_S3C2410_MPLL_RATE(12 * MHZ, 170000000, 77, 1, 1),
133 PLL_S3C2410_MPLL_RATE(12 * MHZ, 158000000, 71, 1, 1),
134 PLL_S3C2410_MPLL_RATE(12 * MHZ, 152000000, 68, 1, 1),
135 PLL_S3C2410_MPLL_RATE(12 * MHZ, 147000000, 90, 2, 1),
136 PLL_S3C2410_MPLL_RATE(12 * MHZ, 135000000, 82, 2, 1),
137 PLL_S3C2410_MPLL_RATE(12 * MHZ, 124000000, 116, 1, 2),
138 PLL_S3C2410_MPLL_RATE(12 * MHZ, 118500000, 150, 2, 2),
139 PLL_S3C2410_MPLL_RATE(12 * MHZ, 113000000, 105, 1, 2),
140 PLL_S3C2410_MPLL_RATE(12 * MHZ, 101250000, 127, 2, 2),
141 PLL_S3C2410_MPLL_RATE(12 * MHZ, 90000000, 112, 2, 2),
142 PLL_S3C2410_MPLL_RATE(12 * MHZ, 84750000, 105, 2, 2),
143 PLL_S3C2410_MPLL_RATE(12 * MHZ, 79000000, 71, 1, 2),
144 PLL_S3C2410_MPLL_RATE(12 * MHZ, 67500000, 82, 2, 2),
145 PLL_S3C2410_MPLL_RATE(12 * MHZ, 56250000, 142, 2, 3),
146 PLL_S3C2410_MPLL_RATE(12 * MHZ, 48000000, 120, 2, 3),
147 PLL_S3C2410_MPLL_RATE(12 * MHZ, 50700000, 161, 3, 3),
148 PLL_S3C2410_MPLL_RATE(12 * MHZ, 45000000, 82, 1, 3),
149 PLL_S3C2410_MPLL_RATE(12 * MHZ, 33750000, 82, 2, 3),
150 { /* sentinel */ },
151 };
152
153 static struct samsung_pll_clock s3c2410_plls[] __initdata = {
154 [mpll] = PLL(pll_s3c2410_mpll, MPLL, "mpll", "xti",
155 LOCKTIME, MPLLCON, NULL),
156 [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
157 LOCKTIME, UPLLCON, NULL),
158 };
159
160 static struct samsung_div_clock s3c2410_dividers[] __initdata = {
161 DIV(HCLK, "hclk", "mpll", CLKDIVN, 1, 1),
162 };
163
164 static struct samsung_fixed_factor_clock s3c2410_ffactor[] __initdata = {
165 /*
166 * armclk is directly supplied by the fclk, without
167 * switching possibility like on the s3c244x below.
168 */
169 FFACTOR(ARMCLK, "armclk", "fclk", 1, 1, 0),
170
171 /* uclk is fed from the unmodified upll */
172 FFACTOR(UCLK, "uclk", "upll", 1, 1, 0),
173 };
174
175 static struct samsung_clock_alias s3c2410_aliases[] __initdata = {
176 ALIAS(PCLK_UART0, "s3c2410-uart.0", "uart"),
177 ALIAS(PCLK_UART1, "s3c2410-uart.1", "uart"),
178 ALIAS(PCLK_UART2, "s3c2410-uart.2", "uart"),
179 ALIAS(PCLK_UART0, "s3c2410-uart.0", "clk_uart_baud0"),
180 ALIAS(PCLK_UART1, "s3c2410-uart.1", "clk_uart_baud0"),
181 ALIAS(PCLK_UART2, "s3c2410-uart.2", "clk_uart_baud0"),
182 ALIAS(UCLK, NULL, "clk_uart_baud1"),
183 };
184
185 /* S3C244x specific clocks */
186
187 static struct samsung_pll_rate_table pll_s3c244x_12mhz_tbl[] __initdata = {
188 /* sorted in descending order */
189 PLL_S3C2440_MPLL_RATE(12 * MHZ, 400000000, 0x5c, 1, 1),
190 PLL_S3C2440_MPLL_RATE(12 * MHZ, 390000000, 0x7a, 2, 1),
191 PLL_S3C2440_MPLL_RATE(12 * MHZ, 380000000, 0x57, 1, 1),
192 PLL_S3C2440_MPLL_RATE(12 * MHZ, 370000000, 0xb1, 4, 1),
193 PLL_S3C2440_MPLL_RATE(12 * MHZ, 360000000, 0x70, 2, 1),
194 PLL_S3C2440_MPLL_RATE(12 * MHZ, 350000000, 0xa7, 4, 1),
195 PLL_S3C2440_MPLL_RATE(12 * MHZ, 340000000, 0x4d, 1, 1),
196 PLL_S3C2440_MPLL_RATE(12 * MHZ, 330000000, 0x66, 2, 1),
197 PLL_S3C2440_MPLL_RATE(12 * MHZ, 320000000, 0x98, 4, 1),
198 PLL_S3C2440_MPLL_RATE(12 * MHZ, 310000000, 0x93, 4, 1),
199 PLL_S3C2440_MPLL_RATE(12 * MHZ, 300000000, 0x75, 3, 1),
200 PLL_S3C2440_MPLL_RATE(12 * MHZ, 240000000, 0x70, 1, 2),
201 PLL_S3C2440_MPLL_RATE(12 * MHZ, 230000000, 0x6b, 1, 2),
202 PLL_S3C2440_MPLL_RATE(12 * MHZ, 220000000, 0x66, 1, 2),
203 PLL_S3C2440_MPLL_RATE(12 * MHZ, 210000000, 0x84, 2, 2),
204 PLL_S3C2440_MPLL_RATE(12 * MHZ, 200000000, 0x5c, 1, 2),
205 PLL_S3C2440_MPLL_RATE(12 * MHZ, 190000000, 0x57, 1, 2),
206 PLL_S3C2440_MPLL_RATE(12 * MHZ, 180000000, 0x70, 2, 2),
207 PLL_S3C2440_MPLL_RATE(12 * MHZ, 170000000, 0x4d, 1, 2),
208 PLL_S3C2440_MPLL_RATE(12 * MHZ, 160000000, 0x98, 4, 2),
209 PLL_S3C2440_MPLL_RATE(12 * MHZ, 150000000, 0x75, 3, 2),
210 PLL_S3C2440_MPLL_RATE(12 * MHZ, 120000000, 0x70, 1, 3),
211 PLL_S3C2440_MPLL_RATE(12 * MHZ, 110000000, 0x66, 1, 3),
212 PLL_S3C2440_MPLL_RATE(12 * MHZ, 100000000, 0x5c, 1, 3),
213 PLL_S3C2440_MPLL_RATE(12 * MHZ, 90000000, 0x70, 2, 3),
214 PLL_S3C2440_MPLL_RATE(12 * MHZ, 80000000, 0x98, 4, 3),
215 PLL_S3C2440_MPLL_RATE(12 * MHZ, 75000000, 0x75, 3, 3),
216 { /* sentinel */ },
217 };
218
219 static struct samsung_pll_clock s3c244x_common_plls[] __initdata = {
220 [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
221 LOCKTIME, MPLLCON, NULL),
222 [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
223 LOCKTIME, UPLLCON, NULL),
224 };
225
226 PNAME(hclk_p) = { "fclk", "div_hclk_2", "div_hclk_4", "div_hclk_3" };
227 PNAME(armclk_p) = { "fclk", "hclk" };
228
229 static struct samsung_mux_clock s3c244x_common_muxes[] __initdata = {
230 MUX(HCLK, "hclk", hclk_p, CLKDIVN, 1, 2),
231 MUX(ARMCLK, "armclk", armclk_p, CAMDIVN, 12, 1),
232 };
233
234 static struct samsung_fixed_factor_clock s3c244x_common_ffactor[] __initdata = {
235 FFACTOR(0, "div_hclk_2", "fclk", 1, 2, 0),
236 FFACTOR(0, "ff_cam", "div_cam", 2, 1, CLK_SET_RATE_PARENT),
237 };
238
239 static struct clk_div_table div_hclk_4_d[] = {
240 { .val = 0, .div = 4 },
241 { .val = 1, .div = 8 },
242 { /* sentinel */ },
243 };
244
245 static struct clk_div_table div_hclk_3_d[] = {
246 { .val = 0, .div = 3 },
247 { .val = 1, .div = 6 },
248 { /* sentinel */ },
249 };
250
251 static struct samsung_div_clock s3c244x_common_dividers[] __initdata = {
252 DIV(UCLK, "uclk", "upll", CLKDIVN, 3, 1),
253 DIV(0, "div_hclk", "fclk", CLKDIVN, 1, 1),
254 DIV_T(0, "div_hclk_4", "fclk", CAMDIVN, 9, 1, div_hclk_4_d),
255 DIV_T(0, "div_hclk_3", "fclk", CAMDIVN, 8, 1, div_hclk_3_d),
256 DIV(0, "div_cam", "upll", CAMDIVN, 0, 3),
257 };
258
259 static struct samsung_gate_clock s3c244x_common_gates[] __initdata = {
260 GATE(HCLK_CAM, "cam", "hclk", CLKCON, 19, 0, 0),
261 };
262
263 static struct samsung_clock_alias s3c244x_common_aliases[] __initdata = {
264 ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"),
265 ALIAS(PCLK_UART1, "s3c2440-uart.1", "uart"),
266 ALIAS(PCLK_UART2, "s3c2440-uart.2", "uart"),
267 ALIAS(PCLK_UART0, "s3c2440-uart.0", "clk_uart_baud2"),
268 ALIAS(PCLK_UART1, "s3c2440-uart.1", "clk_uart_baud2"),
269 ALIAS(PCLK_UART2, "s3c2440-uart.2", "clk_uart_baud2"),
270 ALIAS(HCLK_CAM, NULL, "camif"),
271 ALIAS(CAMIF, NULL, "camif-upll"),
272 };
273
274 /* S3C2440 specific clocks */
275
276 PNAME(s3c2440_camif_p) = { "upll", "ff_cam" };
277
278 static struct samsung_mux_clock s3c2440_muxes[] __initdata = {
279 MUX(CAMIF, "camif", s3c2440_camif_p, CAMDIVN, 4, 1),
280 };
281
282 static struct samsung_gate_clock s3c2440_gates[] __initdata = {
283 GATE(PCLK_AC97, "ac97", "pclk", CLKCON, 20, 0, 0),
284 };
285
286 /* S3C2442 specific clocks */
287
288 static struct samsung_fixed_factor_clock s3c2442_ffactor[] __initdata = {
289 FFACTOR(0, "upll_3", "upll", 1, 3, 0),
290 };
291
292 PNAME(s3c2442_camif_p) = { "upll", "ff_cam", "upll", "upll_3" };
293
294 static struct samsung_mux_clock s3c2442_muxes[] __initdata = {
295 MUX(CAMIF, "camif", s3c2442_camif_p, CAMDIVN, 4, 2),
296 };
297
298 /*
299 * fixed rate clocks generated outside the soc
300 * Only necessary until the devicetree-move is complete
301 */
302 #define XTI 1
303 static struct samsung_fixed_rate_clock s3c2410_common_frate_clks[] __initdata = {
304 FRATE(XTI, "xti", NULL, 0, 0),
305 };
306
s3c2410_common_clk_register_fixed_ext(struct samsung_clk_provider * ctx,unsigned long xti_f)307 static void __init s3c2410_common_clk_register_fixed_ext(
308 struct samsung_clk_provider *ctx,
309 unsigned long xti_f)
310 {
311 struct samsung_clock_alias xti_alias = ALIAS(XTI, NULL, "xtal");
312
313 s3c2410_common_frate_clks[0].fixed_rate = xti_f;
314 samsung_clk_register_fixed_rate(ctx, s3c2410_common_frate_clks,
315 ARRAY_SIZE(s3c2410_common_frate_clks));
316
317 samsung_clk_register_alias(ctx, &xti_alias, 1);
318 }
319
s3c2410_common_clk_init(struct device_node * np,unsigned long xti_f,int current_soc,void __iomem * base)320 void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
321 int current_soc,
322 void __iomem *base)
323 {
324 struct samsung_clk_provider *ctx;
325 reg_base = base;
326
327 if (np) {
328 reg_base = of_iomap(np, 0);
329 if (!reg_base)
330 panic("%s: failed to map registers\n", __func__);
331 }
332
333 ctx = samsung_clk_init(np, reg_base, NR_CLKS);
334
335 /* Register external clocks only in non-dt cases */
336 if (!np)
337 s3c2410_common_clk_register_fixed_ext(ctx, xti_f);
338
339 if (current_soc == S3C2410) {
340 if (_get_rate("xti") == 12 * MHZ) {
341 s3c2410_plls[mpll].rate_table = pll_s3c2410_12mhz_tbl;
342 s3c2410_plls[upll].rate_table = pll_s3c2410_12mhz_tbl;
343 }
344
345 /* Register PLLs. */
346 samsung_clk_register_pll(ctx, s3c2410_plls,
347 ARRAY_SIZE(s3c2410_plls), reg_base);
348
349 } else { /* S3C2440, S3C2442 */
350 if (_get_rate("xti") == 12 * MHZ) {
351 /*
352 * plls follow different calculation schemes, with the
353 * upll following the same scheme as the s3c2410 plls
354 */
355 s3c244x_common_plls[mpll].rate_table =
356 pll_s3c244x_12mhz_tbl;
357 s3c244x_common_plls[upll].rate_table =
358 pll_s3c2410_12mhz_tbl;
359 }
360
361 /* Register PLLs. */
362 samsung_clk_register_pll(ctx, s3c244x_common_plls,
363 ARRAY_SIZE(s3c244x_common_plls), reg_base);
364 }
365
366 /* Register common internal clocks. */
367 samsung_clk_register_mux(ctx, s3c2410_common_muxes,
368 ARRAY_SIZE(s3c2410_common_muxes));
369 samsung_clk_register_div(ctx, s3c2410_common_dividers,
370 ARRAY_SIZE(s3c2410_common_dividers));
371 samsung_clk_register_gate(ctx, s3c2410_common_gates,
372 ARRAY_SIZE(s3c2410_common_gates));
373
374 if (current_soc == S3C2440 || current_soc == S3C2442) {
375 samsung_clk_register_div(ctx, s3c244x_common_dividers,
376 ARRAY_SIZE(s3c244x_common_dividers));
377 samsung_clk_register_gate(ctx, s3c244x_common_gates,
378 ARRAY_SIZE(s3c244x_common_gates));
379 samsung_clk_register_mux(ctx, s3c244x_common_muxes,
380 ARRAY_SIZE(s3c244x_common_muxes));
381 samsung_clk_register_fixed_factor(ctx, s3c244x_common_ffactor,
382 ARRAY_SIZE(s3c244x_common_ffactor));
383 }
384
385 /* Register SoC-specific clocks. */
386 switch (current_soc) {
387 case S3C2410:
388 samsung_clk_register_div(ctx, s3c2410_dividers,
389 ARRAY_SIZE(s3c2410_dividers));
390 samsung_clk_register_fixed_factor(ctx, s3c2410_ffactor,
391 ARRAY_SIZE(s3c2410_ffactor));
392 samsung_clk_register_alias(ctx, s3c2410_aliases,
393 ARRAY_SIZE(s3c2410_aliases));
394 break;
395 case S3C2440:
396 samsung_clk_register_mux(ctx, s3c2440_muxes,
397 ARRAY_SIZE(s3c2440_muxes));
398 samsung_clk_register_gate(ctx, s3c2440_gates,
399 ARRAY_SIZE(s3c2440_gates));
400 break;
401 case S3C2442:
402 samsung_clk_register_mux(ctx, s3c2442_muxes,
403 ARRAY_SIZE(s3c2442_muxes));
404 samsung_clk_register_fixed_factor(ctx, s3c2442_ffactor,
405 ARRAY_SIZE(s3c2442_ffactor));
406 break;
407 }
408
409 /*
410 * Register common aliases at the end, as some of the aliased clocks
411 * are SoC specific.
412 */
413 samsung_clk_register_alias(ctx, s3c2410_common_aliases,
414 ARRAY_SIZE(s3c2410_common_aliases));
415
416 if (current_soc == S3C2440 || current_soc == S3C2442) {
417 samsung_clk_register_alias(ctx, s3c244x_common_aliases,
418 ARRAY_SIZE(s3c244x_common_aliases));
419 }
420
421 samsung_clk_sleep_init(reg_base, s3c2410_clk_regs,
422 ARRAY_SIZE(s3c2410_clk_regs));
423
424 samsung_clk_of_add_provider(np, ctx);
425 }
426
s3c2410_clk_init(struct device_node * np)427 static void __init s3c2410_clk_init(struct device_node *np)
428 {
429 s3c2410_common_clk_init(np, 0, S3C2410, NULL);
430 }
431 CLK_OF_DECLARE(s3c2410_clk, "samsung,s3c2410-clock", s3c2410_clk_init);
432
s3c2440_clk_init(struct device_node * np)433 static void __init s3c2440_clk_init(struct device_node *np)
434 {
435 s3c2410_common_clk_init(np, 0, S3C2440, NULL);
436 }
437 CLK_OF_DECLARE(s3c2440_clk, "samsung,s3c2440-clock", s3c2440_clk_init);
438
s3c2442_clk_init(struct device_node * np)439 static void __init s3c2442_clk_init(struct device_node *np)
440 {
441 s3c2410_common_clk_init(np, 0, S3C2442, NULL);
442 }
443 CLK_OF_DECLARE(s3c2442_clk, "samsung,s3c2442-clock", s3c2442_clk_init);
444
