1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell OcteonTx2 RVU Admin Function driver
3 *
4 * Copyright (C) 2018 Marvell International Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #include <linux/module.h>
12 #include <linux/interrupt.h>
13 #include <linux/delay.h>
14 #include <linux/irq.h>
15 #include <linux/pci.h>
16 #include <linux/sysfs.h>
17
18 #include "cgx.h"
19 #include "rvu.h"
20 #include "rvu_reg.h"
21 #include "ptp.h"
22
23 #include "rvu_trace.h"
24
25 #define DRV_NAME "octeontx2-af"
26 #define DRV_STRING "Marvell OcteonTX2 RVU Admin Function Driver"
27
28 static int rvu_get_hwvf(struct rvu *rvu, int pcifunc);
29
30 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
31 struct rvu_block *block, int lf);
32 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
33 struct rvu_block *block, int lf);
34 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc);
35
36 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw,
37 int type, int num,
38 void (mbox_handler)(struct work_struct *),
39 void (mbox_up_handler)(struct work_struct *));
40 enum {
41 TYPE_AFVF,
42 TYPE_AFPF,
43 };
44
45 /* Supported devices */
46 static const struct pci_device_id rvu_id_table[] = {
47 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AF) },
48 { 0, } /* end of table */
49 };
50
51 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>");
52 MODULE_DESCRIPTION(DRV_STRING);
53 MODULE_LICENSE("GPL v2");
54 MODULE_DEVICE_TABLE(pci, rvu_id_table);
55
56 static char *mkex_profile; /* MKEX profile name */
57 module_param(mkex_profile, charp, 0000);
58 MODULE_PARM_DESC(mkex_profile, "MKEX profile name string");
59
rvu_setup_hw_capabilities(struct rvu * rvu)60 static void rvu_setup_hw_capabilities(struct rvu *rvu)
61 {
62 struct rvu_hwinfo *hw = rvu->hw;
63
64 hw->cap.nix_tx_aggr_lvl = NIX_TXSCH_LVL_TL1;
65 hw->cap.nix_fixed_txschq_mapping = false;
66 hw->cap.nix_shaping = true;
67 hw->cap.nix_tx_link_bp = true;
68 hw->cap.nix_rx_multicast = true;
69
70 if (is_rvu_96xx_B0(rvu)) {
71 hw->cap.nix_fixed_txschq_mapping = true;
72 hw->cap.nix_txsch_per_cgx_lmac = 4;
73 hw->cap.nix_txsch_per_lbk_lmac = 132;
74 hw->cap.nix_txsch_per_sdp_lmac = 76;
75 hw->cap.nix_shaping = false;
76 hw->cap.nix_tx_link_bp = false;
77 if (is_rvu_96xx_A0(rvu))
78 hw->cap.nix_rx_multicast = false;
79 }
80 }
81
82 /* Poll a RVU block's register 'offset', for a 'zero'
83 * or 'nonzero' at bits specified by 'mask'
84 */
rvu_poll_reg(struct rvu * rvu,u64 block,u64 offset,u64 mask,bool zero)85 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero)
86 {
87 unsigned long timeout = jiffies + usecs_to_jiffies(10000);
88 void __iomem *reg;
89 u64 reg_val;
90
91 reg = rvu->afreg_base + ((block << 28) | offset);
92 again:
93 reg_val = readq(reg);
94 if (zero && !(reg_val & mask))
95 return 0;
96 if (!zero && (reg_val & mask))
97 return 0;
98 if (time_before(jiffies, timeout)) {
99 usleep_range(1, 5);
100 goto again;
101 }
102 return -EBUSY;
103 }
104
rvu_alloc_rsrc(struct rsrc_bmap * rsrc)105 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc)
106 {
107 int id;
108
109 if (!rsrc->bmap)
110 return -EINVAL;
111
112 id = find_first_zero_bit(rsrc->bmap, rsrc->max);
113 if (id >= rsrc->max)
114 return -ENOSPC;
115
116 __set_bit(id, rsrc->bmap);
117
118 return id;
119 }
120
rvu_alloc_rsrc_contig(struct rsrc_bmap * rsrc,int nrsrc)121 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc)
122 {
123 int start;
124
125 if (!rsrc->bmap)
126 return -EINVAL;
127
128 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0);
129 if (start >= rsrc->max)
130 return -ENOSPC;
131
132 bitmap_set(rsrc->bmap, start, nrsrc);
133 return start;
134 }
135
rvu_free_rsrc_contig(struct rsrc_bmap * rsrc,int nrsrc,int start)136 static void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc, int start)
137 {
138 if (!rsrc->bmap)
139 return;
140 if (start >= rsrc->max)
141 return;
142
143 bitmap_clear(rsrc->bmap, start, nrsrc);
144 }
145
rvu_rsrc_check_contig(struct rsrc_bmap * rsrc,int nrsrc)146 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc)
147 {
148 int start;
149
150 if (!rsrc->bmap)
151 return false;
152
153 start = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, 0, nrsrc, 0);
154 if (start >= rsrc->max)
155 return false;
156
157 return true;
158 }
159
rvu_free_rsrc(struct rsrc_bmap * rsrc,int id)160 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id)
161 {
162 if (!rsrc->bmap)
163 return;
164
165 __clear_bit(id, rsrc->bmap);
166 }
167
rvu_rsrc_free_count(struct rsrc_bmap * rsrc)168 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc)
169 {
170 int used;
171
172 if (!rsrc->bmap)
173 return 0;
174
175 used = bitmap_weight(rsrc->bmap, rsrc->max);
176 return (rsrc->max - used);
177 }
178
rvu_alloc_bitmap(struct rsrc_bmap * rsrc)179 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc)
180 {
181 rsrc->bmap = kcalloc(BITS_TO_LONGS(rsrc->max),
182 sizeof(long), GFP_KERNEL);
183 if (!rsrc->bmap)
184 return -ENOMEM;
185 return 0;
186 }
187
188 /* Get block LF's HW index from a PF_FUNC's block slot number */
rvu_get_lf(struct rvu * rvu,struct rvu_block * block,u16 pcifunc,u16 slot)189 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot)
190 {
191 u16 match = 0;
192 int lf;
193
194 mutex_lock(&rvu->rsrc_lock);
195 for (lf = 0; lf < block->lf.max; lf++) {
196 if (block->fn_map[lf] == pcifunc) {
197 if (slot == match) {
198 mutex_unlock(&rvu->rsrc_lock);
199 return lf;
200 }
201 match++;
202 }
203 }
204 mutex_unlock(&rvu->rsrc_lock);
205 return -ENODEV;
206 }
207
208 /* Convert BLOCK_TYPE_E to a BLOCK_ADDR_E.
209 * Some silicon variants of OcteonTX2 supports
210 * multiple blocks of same type.
211 *
212 * @pcifunc has to be zero when no LF is yet attached.
213 */
rvu_get_blkaddr(struct rvu * rvu,int blktype,u16 pcifunc)214 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc)
215 {
216 int devnum, blkaddr = -ENODEV;
217 u64 cfg, reg;
218 bool is_pf;
219
220 switch (blktype) {
221 case BLKTYPE_NPC:
222 blkaddr = BLKADDR_NPC;
223 goto exit;
224 case BLKTYPE_NPA:
225 blkaddr = BLKADDR_NPA;
226 goto exit;
227 case BLKTYPE_NIX:
228 /* For now assume NIX0 */
229 if (!pcifunc) {
230 blkaddr = BLKADDR_NIX0;
231 goto exit;
232 }
233 break;
234 case BLKTYPE_SSO:
235 blkaddr = BLKADDR_SSO;
236 goto exit;
237 case BLKTYPE_SSOW:
238 blkaddr = BLKADDR_SSOW;
239 goto exit;
240 case BLKTYPE_TIM:
241 blkaddr = BLKADDR_TIM;
242 goto exit;
243 case BLKTYPE_CPT:
244 /* For now assume CPT0 */
245 if (!pcifunc) {
246 blkaddr = BLKADDR_CPT0;
247 goto exit;
248 }
249 break;
250 }
251
252 /* Check if this is a RVU PF or VF */
253 if (pcifunc & RVU_PFVF_FUNC_MASK) {
254 is_pf = false;
255 devnum = rvu_get_hwvf(rvu, pcifunc);
256 } else {
257 is_pf = true;
258 devnum = rvu_get_pf(pcifunc);
259 }
260
261 /* Check if the 'pcifunc' has a NIX LF from 'BLKADDR_NIX0' */
262 if (blktype == BLKTYPE_NIX) {
263 reg = is_pf ? RVU_PRIV_PFX_NIX0_CFG : RVU_PRIV_HWVFX_NIX0_CFG;
264 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
265 if (cfg)
266 blkaddr = BLKADDR_NIX0;
267 }
268
269 /* Check if the 'pcifunc' has a CPT LF from 'BLKADDR_CPT0' */
270 if (blktype == BLKTYPE_CPT) {
271 reg = is_pf ? RVU_PRIV_PFX_CPT0_CFG : RVU_PRIV_HWVFX_CPT0_CFG;
272 cfg = rvu_read64(rvu, BLKADDR_RVUM, reg | (devnum << 16));
273 if (cfg)
274 blkaddr = BLKADDR_CPT0;
275 }
276
277 exit:
278 if (is_block_implemented(rvu->hw, blkaddr))
279 return blkaddr;
280 return -ENODEV;
281 }
282
rvu_update_rsrc_map(struct rvu * rvu,struct rvu_pfvf * pfvf,struct rvu_block * block,u16 pcifunc,u16 lf,bool attach)283 static void rvu_update_rsrc_map(struct rvu *rvu, struct rvu_pfvf *pfvf,
284 struct rvu_block *block, u16 pcifunc,
285 u16 lf, bool attach)
286 {
287 int devnum, num_lfs = 0;
288 bool is_pf;
289 u64 reg;
290
291 if (lf >= block->lf.max) {
292 dev_err(&rvu->pdev->dev,
293 "%s: FATAL: LF %d is >= %s's max lfs i.e %d\n",
294 __func__, lf, block->name, block->lf.max);
295 return;
296 }
297
298 /* Check if this is for a RVU PF or VF */
299 if (pcifunc & RVU_PFVF_FUNC_MASK) {
300 is_pf = false;
301 devnum = rvu_get_hwvf(rvu, pcifunc);
302 } else {
303 is_pf = true;
304 devnum = rvu_get_pf(pcifunc);
305 }
306
307 block->fn_map[lf] = attach ? pcifunc : 0;
308
309 switch (block->type) {
310 case BLKTYPE_NPA:
311 pfvf->npalf = attach ? true : false;
312 num_lfs = pfvf->npalf;
313 break;
314 case BLKTYPE_NIX:
315 pfvf->nixlf = attach ? true : false;
316 num_lfs = pfvf->nixlf;
317 break;
318 case BLKTYPE_SSO:
319 attach ? pfvf->sso++ : pfvf->sso--;
320 num_lfs = pfvf->sso;
321 break;
322 case BLKTYPE_SSOW:
323 attach ? pfvf->ssow++ : pfvf->ssow--;
324 num_lfs = pfvf->ssow;
325 break;
326 case BLKTYPE_TIM:
327 attach ? pfvf->timlfs++ : pfvf->timlfs--;
328 num_lfs = pfvf->timlfs;
329 break;
330 case BLKTYPE_CPT:
331 attach ? pfvf->cptlfs++ : pfvf->cptlfs--;
332 num_lfs = pfvf->cptlfs;
333 break;
334 }
335
336 reg = is_pf ? block->pf_lfcnt_reg : block->vf_lfcnt_reg;
337 rvu_write64(rvu, BLKADDR_RVUM, reg | (devnum << 16), num_lfs);
338 }
339
rvu_get_pf(u16 pcifunc)340 inline int rvu_get_pf(u16 pcifunc)
341 {
342 return (pcifunc >> RVU_PFVF_PF_SHIFT) & RVU_PFVF_PF_MASK;
343 }
344
rvu_get_pf_numvfs(struct rvu * rvu,int pf,int * numvfs,int * hwvf)345 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf)
346 {
347 u64 cfg;
348
349 /* Get numVFs attached to this PF and first HWVF */
350 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
351 *numvfs = (cfg >> 12) & 0xFF;
352 *hwvf = cfg & 0xFFF;
353 }
354
rvu_get_hwvf(struct rvu * rvu,int pcifunc)355 static int rvu_get_hwvf(struct rvu *rvu, int pcifunc)
356 {
357 int pf, func;
358 u64 cfg;
359
360 pf = rvu_get_pf(pcifunc);
361 func = pcifunc & RVU_PFVF_FUNC_MASK;
362
363 /* Get first HWVF attached to this PF */
364 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
365
366 return ((cfg & 0xFFF) + func - 1);
367 }
368
rvu_get_pfvf(struct rvu * rvu,int pcifunc)369 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc)
370 {
371 /* Check if it is a PF or VF */
372 if (pcifunc & RVU_PFVF_FUNC_MASK)
373 return &rvu->hwvf[rvu_get_hwvf(rvu, pcifunc)];
374 else
375 return &rvu->pf[rvu_get_pf(pcifunc)];
376 }
377
is_pf_func_valid(struct rvu * rvu,u16 pcifunc)378 static bool is_pf_func_valid(struct rvu *rvu, u16 pcifunc)
379 {
380 int pf, vf, nvfs;
381 u64 cfg;
382
383 pf = rvu_get_pf(pcifunc);
384 if (pf >= rvu->hw->total_pfs)
385 return false;
386
387 if (!(pcifunc & RVU_PFVF_FUNC_MASK))
388 return true;
389
390 /* Check if VF is within number of VFs attached to this PF */
391 vf = (pcifunc & RVU_PFVF_FUNC_MASK) - 1;
392 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
393 nvfs = (cfg >> 12) & 0xFF;
394 if (vf >= nvfs)
395 return false;
396
397 return true;
398 }
399
is_block_implemented(struct rvu_hwinfo * hw,int blkaddr)400 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr)
401 {
402 struct rvu_block *block;
403
404 if (blkaddr < BLKADDR_RVUM || blkaddr >= BLK_COUNT)
405 return false;
406
407 block = &hw->block[blkaddr];
408 return block->implemented;
409 }
410
rvu_check_block_implemented(struct rvu * rvu)411 static void rvu_check_block_implemented(struct rvu *rvu)
412 {
413 struct rvu_hwinfo *hw = rvu->hw;
414 struct rvu_block *block;
415 int blkid;
416 u64 cfg;
417
418 /* For each block check if 'implemented' bit is set */
419 for (blkid = 0; blkid < BLK_COUNT; blkid++) {
420 block = &hw->block[blkid];
421 cfg = rvupf_read64(rvu, RVU_PF_BLOCK_ADDRX_DISC(blkid));
422 if (cfg & BIT_ULL(11))
423 block->implemented = true;
424 }
425 }
426
rvu_setup_rvum_blk_revid(struct rvu * rvu)427 static void rvu_setup_rvum_blk_revid(struct rvu *rvu)
428 {
429 rvu_write64(rvu, BLKADDR_RVUM,
430 RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM),
431 RVU_BLK_RVUM_REVID);
432 }
433
rvu_clear_rvum_blk_revid(struct rvu * rvu)434 static void rvu_clear_rvum_blk_revid(struct rvu *rvu)
435 {
436 rvu_write64(rvu, BLKADDR_RVUM,
437 RVU_PRIV_BLOCK_TYPEX_REV(BLKTYPE_RVUM), 0x00);
438 }
439
rvu_lf_reset(struct rvu * rvu,struct rvu_block * block,int lf)440 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf)
441 {
442 int err;
443
444 if (!block->implemented)
445 return 0;
446
447 rvu_write64(rvu, block->addr, block->lfreset_reg, lf | BIT_ULL(12));
448 err = rvu_poll_reg(rvu, block->addr, block->lfreset_reg, BIT_ULL(12),
449 true);
450 return err;
451 }
452
rvu_block_reset(struct rvu * rvu,int blkaddr,u64 rst_reg)453 static void rvu_block_reset(struct rvu *rvu, int blkaddr, u64 rst_reg)
454 {
455 struct rvu_block *block = &rvu->hw->block[blkaddr];
456
457 if (!block->implemented)
458 return;
459
460 rvu_write64(rvu, blkaddr, rst_reg, BIT_ULL(0));
461 rvu_poll_reg(rvu, blkaddr, rst_reg, BIT_ULL(63), true);
462 }
463
rvu_reset_all_blocks(struct rvu * rvu)464 static void rvu_reset_all_blocks(struct rvu *rvu)
465 {
466 /* Do a HW reset of all RVU blocks */
467 rvu_block_reset(rvu, BLKADDR_NPA, NPA_AF_BLK_RST);
468 rvu_block_reset(rvu, BLKADDR_NIX0, NIX_AF_BLK_RST);
469 rvu_block_reset(rvu, BLKADDR_NPC, NPC_AF_BLK_RST);
470 rvu_block_reset(rvu, BLKADDR_SSO, SSO_AF_BLK_RST);
471 rvu_block_reset(rvu, BLKADDR_TIM, TIM_AF_BLK_RST);
472 rvu_block_reset(rvu, BLKADDR_CPT0, CPT_AF_BLK_RST);
473 rvu_block_reset(rvu, BLKADDR_NDC_NIX0_RX, NDC_AF_BLK_RST);
474 rvu_block_reset(rvu, BLKADDR_NDC_NIX0_TX, NDC_AF_BLK_RST);
475 rvu_block_reset(rvu, BLKADDR_NDC_NPA0, NDC_AF_BLK_RST);
476 }
477
rvu_scan_block(struct rvu * rvu,struct rvu_block * block)478 static void rvu_scan_block(struct rvu *rvu, struct rvu_block *block)
479 {
480 struct rvu_pfvf *pfvf;
481 u64 cfg;
482 int lf;
483
484 for (lf = 0; lf < block->lf.max; lf++) {
485 cfg = rvu_read64(rvu, block->addr,
486 block->lfcfg_reg | (lf << block->lfshift));
487 if (!(cfg & BIT_ULL(63)))
488 continue;
489
490 /* Set this resource as being used */
491 __set_bit(lf, block->lf.bmap);
492
493 /* Get, to whom this LF is attached */
494 pfvf = rvu_get_pfvf(rvu, (cfg >> 8) & 0xFFFF);
495 rvu_update_rsrc_map(rvu, pfvf, block,
496 (cfg >> 8) & 0xFFFF, lf, true);
497
498 /* Set start MSIX vector for this LF within this PF/VF */
499 rvu_set_msix_offset(rvu, pfvf, block, lf);
500 }
501 }
502
rvu_check_min_msix_vec(struct rvu * rvu,int nvecs,int pf,int vf)503 static void rvu_check_min_msix_vec(struct rvu *rvu, int nvecs, int pf, int vf)
504 {
505 int min_vecs;
506
507 if (!vf)
508 goto check_pf;
509
510 if (!nvecs) {
511 dev_warn(rvu->dev,
512 "PF%d:VF%d is configured with zero msix vectors, %d\n",
513 pf, vf - 1, nvecs);
514 }
515 return;
516
517 check_pf:
518 if (pf == 0)
519 min_vecs = RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT;
520 else
521 min_vecs = RVU_PF_INT_VEC_CNT;
522
523 if (!(nvecs < min_vecs))
524 return;
525 dev_warn(rvu->dev,
526 "PF%d is configured with too few vectors, %d, min is %d\n",
527 pf, nvecs, min_vecs);
528 }
529
rvu_setup_msix_resources(struct rvu * rvu)530 static int rvu_setup_msix_resources(struct rvu *rvu)
531 {
532 struct rvu_hwinfo *hw = rvu->hw;
533 int pf, vf, numvfs, hwvf, err;
534 int nvecs, offset, max_msix;
535 struct rvu_pfvf *pfvf;
536 u64 cfg, phy_addr;
537 dma_addr_t iova;
538
539 for (pf = 0; pf < hw->total_pfs; pf++) {
540 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
541 /* If PF is not enabled, nothing to do */
542 if (!((cfg >> 20) & 0x01))
543 continue;
544
545 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf);
546
547 pfvf = &rvu->pf[pf];
548 /* Get num of MSIX vectors attached to this PF */
549 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_MSIX_CFG(pf));
550 pfvf->msix.max = ((cfg >> 32) & 0xFFF) + 1;
551 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, 0);
552
553 /* Alloc msix bitmap for this PF */
554 err = rvu_alloc_bitmap(&pfvf->msix);
555 if (err)
556 return err;
557
558 /* Allocate memory for MSIX vector to RVU block LF mapping */
559 pfvf->msix_lfmap = devm_kcalloc(rvu->dev, pfvf->msix.max,
560 sizeof(u16), GFP_KERNEL);
561 if (!pfvf->msix_lfmap)
562 return -ENOMEM;
563
564 /* For PF0 (AF) firmware will set msix vector offsets for
565 * AF, block AF and PF0_INT vectors, so jump to VFs.
566 */
567 if (!pf)
568 goto setup_vfmsix;
569
570 /* Set MSIX offset for PF's 'RVU_PF_INT_VEC' vectors.
571 * These are allocated on driver init and never freed,
572 * so no need to set 'msix_lfmap' for these.
573 */
574 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(pf));
575 nvecs = (cfg >> 12) & 0xFF;
576 cfg &= ~0x7FFULL;
577 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs);
578 rvu_write64(rvu, BLKADDR_RVUM,
579 RVU_PRIV_PFX_INT_CFG(pf), cfg | offset);
580 setup_vfmsix:
581 /* Alloc msix bitmap for VFs */
582 for (vf = 0; vf < numvfs; vf++) {
583 pfvf = &rvu->hwvf[hwvf + vf];
584 /* Get num of MSIX vectors attached to this VF */
585 cfg = rvu_read64(rvu, BLKADDR_RVUM,
586 RVU_PRIV_PFX_MSIX_CFG(pf));
587 pfvf->msix.max = (cfg & 0xFFF) + 1;
588 rvu_check_min_msix_vec(rvu, pfvf->msix.max, pf, vf + 1);
589
590 /* Alloc msix bitmap for this VF */
591 err = rvu_alloc_bitmap(&pfvf->msix);
592 if (err)
593 return err;
594
595 pfvf->msix_lfmap =
596 devm_kcalloc(rvu->dev, pfvf->msix.max,
597 sizeof(u16), GFP_KERNEL);
598 if (!pfvf->msix_lfmap)
599 return -ENOMEM;
600
601 /* Set MSIX offset for HWVF's 'RVU_VF_INT_VEC' vectors.
602 * These are allocated on driver init and never freed,
603 * so no need to set 'msix_lfmap' for these.
604 */
605 cfg = rvu_read64(rvu, BLKADDR_RVUM,
606 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf));
607 nvecs = (cfg >> 12) & 0xFF;
608 cfg &= ~0x7FFULL;
609 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs);
610 rvu_write64(rvu, BLKADDR_RVUM,
611 RVU_PRIV_HWVFX_INT_CFG(hwvf + vf),
612 cfg | offset);
613 }
614 }
615
616 /* HW interprets RVU_AF_MSIXTR_BASE address as an IOVA, hence
617 * create a IOMMU mapping for the physcial address configured by
618 * firmware and reconfig RVU_AF_MSIXTR_BASE with IOVA.
619 */
620 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST);
621 max_msix = cfg & 0xFFFFF;
622 if (rvu->fwdata && rvu->fwdata->msixtr_base)
623 phy_addr = rvu->fwdata->msixtr_base;
624 else
625 phy_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE);
626
627 iova = dma_map_resource(rvu->dev, phy_addr,
628 max_msix * PCI_MSIX_ENTRY_SIZE,
629 DMA_BIDIRECTIONAL, 0);
630
631 if (dma_mapping_error(rvu->dev, iova))
632 return -ENOMEM;
633
634 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE, (u64)iova);
635 rvu->msix_base_iova = iova;
636 rvu->msixtr_base_phy = phy_addr;
637
638 return 0;
639 }
640
rvu_reset_msix(struct rvu * rvu)641 static void rvu_reset_msix(struct rvu *rvu)
642 {
643 /* Restore msixtr base register */
644 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_MSIXTR_BASE,
645 rvu->msixtr_base_phy);
646 }
647
rvu_free_hw_resources(struct rvu * rvu)648 static void rvu_free_hw_resources(struct rvu *rvu)
649 {
650 struct rvu_hwinfo *hw = rvu->hw;
651 struct rvu_block *block;
652 struct rvu_pfvf *pfvf;
653 int id, max_msix;
654 u64 cfg;
655
656 rvu_npa_freemem(rvu);
657 rvu_npc_freemem(rvu);
658 rvu_nix_freemem(rvu);
659
660 /* Free block LF bitmaps */
661 for (id = 0; id < BLK_COUNT; id++) {
662 block = &hw->block[id];
663 kfree(block->lf.bmap);
664 }
665
666 /* Free MSIX bitmaps */
667 for (id = 0; id < hw->total_pfs; id++) {
668 pfvf = &rvu->pf[id];
669 kfree(pfvf->msix.bmap);
670 }
671
672 for (id = 0; id < hw->total_vfs; id++) {
673 pfvf = &rvu->hwvf[id];
674 kfree(pfvf->msix.bmap);
675 }
676
677 /* Unmap MSIX vector base IOVA mapping */
678 if (!rvu->msix_base_iova)
679 return;
680 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST);
681 max_msix = cfg & 0xFFFFF;
682 dma_unmap_resource(rvu->dev, rvu->msix_base_iova,
683 max_msix * PCI_MSIX_ENTRY_SIZE,
684 DMA_BIDIRECTIONAL, 0);
685
686 rvu_reset_msix(rvu);
687 mutex_destroy(&rvu->rsrc_lock);
688 }
689
rvu_setup_pfvf_macaddress(struct rvu * rvu)690 static void rvu_setup_pfvf_macaddress(struct rvu *rvu)
691 {
692 struct rvu_hwinfo *hw = rvu->hw;
693 int pf, vf, numvfs, hwvf;
694 struct rvu_pfvf *pfvf;
695 u64 *mac;
696
697 for (pf = 0; pf < hw->total_pfs; pf++) {
698 if (!is_pf_cgxmapped(rvu, pf))
699 continue;
700 /* Assign MAC address to PF */
701 pfvf = &rvu->pf[pf];
702 if (rvu->fwdata && pf < PF_MACNUM_MAX) {
703 mac = &rvu->fwdata->pf_macs[pf];
704 if (*mac)
705 u64_to_ether_addr(*mac, pfvf->mac_addr);
706 else
707 eth_random_addr(pfvf->mac_addr);
708 } else {
709 eth_random_addr(pfvf->mac_addr);
710 }
711
712 /* Assign MAC address to VFs */
713 rvu_get_pf_numvfs(rvu, pf, &numvfs, &hwvf);
714 for (vf = 0; vf < numvfs; vf++, hwvf++) {
715 pfvf = &rvu->hwvf[hwvf];
716 if (rvu->fwdata && hwvf < VF_MACNUM_MAX) {
717 mac = &rvu->fwdata->vf_macs[hwvf];
718 if (*mac)
719 u64_to_ether_addr(*mac, pfvf->mac_addr);
720 else
721 eth_random_addr(pfvf->mac_addr);
722 } else {
723 eth_random_addr(pfvf->mac_addr);
724 }
725 }
726 }
727 }
728
rvu_fwdata_init(struct rvu * rvu)729 static int rvu_fwdata_init(struct rvu *rvu)
730 {
731 u64 fwdbase;
732 int err;
733
734 /* Get firmware data base address */
735 err = cgx_get_fwdata_base(&fwdbase);
736 if (err)
737 goto fail;
738 rvu->fwdata = ioremap_wc(fwdbase, sizeof(struct rvu_fwdata));
739 if (!rvu->fwdata)
740 goto fail;
741 if (!is_rvu_fwdata_valid(rvu)) {
742 dev_err(rvu->dev,
743 "Mismatch in 'fwdata' struct btw kernel and firmware\n");
744 iounmap(rvu->fwdata);
745 rvu->fwdata = NULL;
746 return -EINVAL;
747 }
748 return 0;
749 fail:
750 dev_info(rvu->dev, "Unable to fetch 'fwdata' from firmware\n");
751 return -EIO;
752 }
753
rvu_fwdata_exit(struct rvu * rvu)754 static void rvu_fwdata_exit(struct rvu *rvu)
755 {
756 if (rvu->fwdata)
757 iounmap(rvu->fwdata);
758 }
759
rvu_setup_hw_resources(struct rvu * rvu)760 static int rvu_setup_hw_resources(struct rvu *rvu)
761 {
762 struct rvu_hwinfo *hw = rvu->hw;
763 struct rvu_block *block;
764 int blkid, err;
765 u64 cfg;
766
767 /* Get HW supported max RVU PF & VF count */
768 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_CONST);
769 hw->total_pfs = (cfg >> 32) & 0xFF;
770 hw->total_vfs = (cfg >> 20) & 0xFFF;
771 hw->max_vfs_per_pf = (cfg >> 40) & 0xFF;
772
773 /* Init NPA LF's bitmap */
774 block = &hw->block[BLKADDR_NPA];
775 if (!block->implemented)
776 goto nix;
777 cfg = rvu_read64(rvu, BLKADDR_NPA, NPA_AF_CONST);
778 block->lf.max = (cfg >> 16) & 0xFFF;
779 block->addr = BLKADDR_NPA;
780 block->type = BLKTYPE_NPA;
781 block->lfshift = 8;
782 block->lookup_reg = NPA_AF_RVU_LF_CFG_DEBUG;
783 block->pf_lfcnt_reg = RVU_PRIV_PFX_NPA_CFG;
784 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NPA_CFG;
785 block->lfcfg_reg = NPA_PRIV_LFX_CFG;
786 block->msixcfg_reg = NPA_PRIV_LFX_INT_CFG;
787 block->lfreset_reg = NPA_AF_LF_RST;
788 sprintf(block->name, "NPA");
789 err = rvu_alloc_bitmap(&block->lf);
790 if (err)
791 return err;
792
793 nix:
794 /* Init NIX LF's bitmap */
795 block = &hw->block[BLKADDR_NIX0];
796 if (!block->implemented)
797 goto sso;
798 cfg = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST2);
799 block->lf.max = cfg & 0xFFF;
800 block->addr = BLKADDR_NIX0;
801 block->type = BLKTYPE_NIX;
802 block->lfshift = 8;
803 block->lookup_reg = NIX_AF_RVU_LF_CFG_DEBUG;
804 block->pf_lfcnt_reg = RVU_PRIV_PFX_NIX0_CFG;
805 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_NIX0_CFG;
806 block->lfcfg_reg = NIX_PRIV_LFX_CFG;
807 block->msixcfg_reg = NIX_PRIV_LFX_INT_CFG;
808 block->lfreset_reg = NIX_AF_LF_RST;
809 sprintf(block->name, "NIX");
810 err = rvu_alloc_bitmap(&block->lf);
811 if (err)
812 return err;
813
814 sso:
815 /* Init SSO group's bitmap */
816 block = &hw->block[BLKADDR_SSO];
817 if (!block->implemented)
818 goto ssow;
819 cfg = rvu_read64(rvu, BLKADDR_SSO, SSO_AF_CONST);
820 block->lf.max = cfg & 0xFFFF;
821 block->addr = BLKADDR_SSO;
822 block->type = BLKTYPE_SSO;
823 block->multislot = true;
824 block->lfshift = 3;
825 block->lookup_reg = SSO_AF_RVU_LF_CFG_DEBUG;
826 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSO_CFG;
827 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSO_CFG;
828 block->lfcfg_reg = SSO_PRIV_LFX_HWGRP_CFG;
829 block->msixcfg_reg = SSO_PRIV_LFX_HWGRP_INT_CFG;
830 block->lfreset_reg = SSO_AF_LF_HWGRP_RST;
831 sprintf(block->name, "SSO GROUP");
832 err = rvu_alloc_bitmap(&block->lf);
833 if (err)
834 return err;
835
836 ssow:
837 /* Init SSO workslot's bitmap */
838 block = &hw->block[BLKADDR_SSOW];
839 if (!block->implemented)
840 goto tim;
841 block->lf.max = (cfg >> 56) & 0xFF;
842 block->addr = BLKADDR_SSOW;
843 block->type = BLKTYPE_SSOW;
844 block->multislot = true;
845 block->lfshift = 3;
846 block->lookup_reg = SSOW_AF_RVU_LF_HWS_CFG_DEBUG;
847 block->pf_lfcnt_reg = RVU_PRIV_PFX_SSOW_CFG;
848 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_SSOW_CFG;
849 block->lfcfg_reg = SSOW_PRIV_LFX_HWS_CFG;
850 block->msixcfg_reg = SSOW_PRIV_LFX_HWS_INT_CFG;
851 block->lfreset_reg = SSOW_AF_LF_HWS_RST;
852 sprintf(block->name, "SSOWS");
853 err = rvu_alloc_bitmap(&block->lf);
854 if (err)
855 return err;
856
857 tim:
858 /* Init TIM LF's bitmap */
859 block = &hw->block[BLKADDR_TIM];
860 if (!block->implemented)
861 goto cpt;
862 cfg = rvu_read64(rvu, BLKADDR_TIM, TIM_AF_CONST);
863 block->lf.max = cfg & 0xFFFF;
864 block->addr = BLKADDR_TIM;
865 block->type = BLKTYPE_TIM;
866 block->multislot = true;
867 block->lfshift = 3;
868 block->lookup_reg = TIM_AF_RVU_LF_CFG_DEBUG;
869 block->pf_lfcnt_reg = RVU_PRIV_PFX_TIM_CFG;
870 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_TIM_CFG;
871 block->lfcfg_reg = TIM_PRIV_LFX_CFG;
872 block->msixcfg_reg = TIM_PRIV_LFX_INT_CFG;
873 block->lfreset_reg = TIM_AF_LF_RST;
874 sprintf(block->name, "TIM");
875 err = rvu_alloc_bitmap(&block->lf);
876 if (err)
877 return err;
878
879 cpt:
880 /* Init CPT LF's bitmap */
881 block = &hw->block[BLKADDR_CPT0];
882 if (!block->implemented)
883 goto init;
884 cfg = rvu_read64(rvu, BLKADDR_CPT0, CPT_AF_CONSTANTS0);
885 block->lf.max = cfg & 0xFF;
886 block->addr = BLKADDR_CPT0;
887 block->type = BLKTYPE_CPT;
888 block->multislot = true;
889 block->lfshift = 3;
890 block->lookup_reg = CPT_AF_RVU_LF_CFG_DEBUG;
891 block->pf_lfcnt_reg = RVU_PRIV_PFX_CPT0_CFG;
892 block->vf_lfcnt_reg = RVU_PRIV_HWVFX_CPT0_CFG;
893 block->lfcfg_reg = CPT_PRIV_LFX_CFG;
894 block->msixcfg_reg = CPT_PRIV_LFX_INT_CFG;
895 block->lfreset_reg = CPT_AF_LF_RST;
896 sprintf(block->name, "CPT");
897 err = rvu_alloc_bitmap(&block->lf);
898 if (err)
899 return err;
900
901 init:
902 /* Allocate memory for PFVF data */
903 rvu->pf = devm_kcalloc(rvu->dev, hw->total_pfs,
904 sizeof(struct rvu_pfvf), GFP_KERNEL);
905 if (!rvu->pf)
906 return -ENOMEM;
907
908 rvu->hwvf = devm_kcalloc(rvu->dev, hw->total_vfs,
909 sizeof(struct rvu_pfvf), GFP_KERNEL);
910 if (!rvu->hwvf)
911 return -ENOMEM;
912
913 mutex_init(&rvu->rsrc_lock);
914
915 rvu_fwdata_init(rvu);
916
917 err = rvu_setup_msix_resources(rvu);
918 if (err)
919 return err;
920
921 for (blkid = 0; blkid < BLK_COUNT; blkid++) {
922 block = &hw->block[blkid];
923 if (!block->lf.bmap)
924 continue;
925
926 /* Allocate memory for block LF/slot to pcifunc mapping info */
927 block->fn_map = devm_kcalloc(rvu->dev, block->lf.max,
928 sizeof(u16), GFP_KERNEL);
929 if (!block->fn_map) {
930 err = -ENOMEM;
931 goto msix_err;
932 }
933
934 /* Scan all blocks to check if low level firmware has
935 * already provisioned any of the resources to a PF/VF.
936 */
937 rvu_scan_block(rvu, block);
938 }
939
940 err = rvu_npc_init(rvu);
941 if (err)
942 goto npc_err;
943
944 err = rvu_cgx_init(rvu);
945 if (err)
946 goto cgx_err;
947
948 /* Assign MACs for CGX mapped functions */
949 rvu_setup_pfvf_macaddress(rvu);
950
951 err = rvu_npa_init(rvu);
952 if (err)
953 goto npa_err;
954
955 err = rvu_nix_init(rvu);
956 if (err)
957 goto nix_err;
958
959 return 0;
960
961 nix_err:
962 rvu_nix_freemem(rvu);
963 npa_err:
964 rvu_npa_freemem(rvu);
965 cgx_err:
966 rvu_cgx_exit(rvu);
967 npc_err:
968 rvu_npc_freemem(rvu);
969 rvu_fwdata_exit(rvu);
970 msix_err:
971 rvu_reset_msix(rvu);
972 return err;
973 }
974
975 /* NPA and NIX admin queue APIs */
rvu_aq_free(struct rvu * rvu,struct admin_queue * aq)976 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq)
977 {
978 if (!aq)
979 return;
980
981 qmem_free(rvu->dev, aq->inst);
982 qmem_free(rvu->dev, aq->res);
983 devm_kfree(rvu->dev, aq);
984 }
985
rvu_aq_alloc(struct rvu * rvu,struct admin_queue ** ad_queue,int qsize,int inst_size,int res_size)986 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue,
987 int qsize, int inst_size, int res_size)
988 {
989 struct admin_queue *aq;
990 int err;
991
992 *ad_queue = devm_kzalloc(rvu->dev, sizeof(*aq), GFP_KERNEL);
993 if (!*ad_queue)
994 return -ENOMEM;
995 aq = *ad_queue;
996
997 /* Alloc memory for instructions i.e AQ */
998 err = qmem_alloc(rvu->dev, &aq->inst, qsize, inst_size);
999 if (err) {
1000 devm_kfree(rvu->dev, aq);
1001 return err;
1002 }
1003
1004 /* Alloc memory for results */
1005 err = qmem_alloc(rvu->dev, &aq->res, qsize, res_size);
1006 if (err) {
1007 rvu_aq_free(rvu, aq);
1008 return err;
1009 }
1010
1011 spin_lock_init(&aq->lock);
1012 return 0;
1013 }
1014
rvu_mbox_handler_ready(struct rvu * rvu,struct msg_req * req,struct ready_msg_rsp * rsp)1015 int rvu_mbox_handler_ready(struct rvu *rvu, struct msg_req *req,
1016 struct ready_msg_rsp *rsp)
1017 {
1018 if (rvu->fwdata) {
1019 rsp->rclk_freq = rvu->fwdata->rclk;
1020 rsp->sclk_freq = rvu->fwdata->sclk;
1021 }
1022 return 0;
1023 }
1024
1025 /* Get current count of a RVU block's LF/slots
1026 * provisioned to a given RVU func.
1027 */
rvu_get_rsrc_mapcount(struct rvu_pfvf * pfvf,int blktype)1028 static u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blktype)
1029 {
1030 switch (blktype) {
1031 case BLKTYPE_NPA:
1032 return pfvf->npalf ? 1 : 0;
1033 case BLKTYPE_NIX:
1034 return pfvf->nixlf ? 1 : 0;
1035 case BLKTYPE_SSO:
1036 return pfvf->sso;
1037 case BLKTYPE_SSOW:
1038 return pfvf->ssow;
1039 case BLKTYPE_TIM:
1040 return pfvf->timlfs;
1041 case BLKTYPE_CPT:
1042 return pfvf->cptlfs;
1043 }
1044 return 0;
1045 }
1046
is_pffunc_map_valid(struct rvu * rvu,u16 pcifunc,int blktype)1047 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype)
1048 {
1049 struct rvu_pfvf *pfvf;
1050
1051 if (!is_pf_func_valid(rvu, pcifunc))
1052 return false;
1053
1054 pfvf = rvu_get_pfvf(rvu, pcifunc);
1055
1056 /* Check if this PFFUNC has a LF of type blktype attached */
1057 if (!rvu_get_rsrc_mapcount(pfvf, blktype))
1058 return false;
1059
1060 return true;
1061 }
1062
rvu_lookup_rsrc(struct rvu * rvu,struct rvu_block * block,int pcifunc,int slot)1063 static int rvu_lookup_rsrc(struct rvu *rvu, struct rvu_block *block,
1064 int pcifunc, int slot)
1065 {
1066 u64 val;
1067
1068 val = ((u64)pcifunc << 24) | (slot << 16) | (1ULL << 13);
1069 rvu_write64(rvu, block->addr, block->lookup_reg, val);
1070 /* Wait for the lookup to finish */
1071 /* TODO: put some timeout here */
1072 while (rvu_read64(rvu, block->addr, block->lookup_reg) & (1ULL << 13))
1073 ;
1074
1075 val = rvu_read64(rvu, block->addr, block->lookup_reg);
1076
1077 /* Check LF valid bit */
1078 if (!(val & (1ULL << 12)))
1079 return -1;
1080
1081 return (val & 0xFFF);
1082 }
1083
rvu_detach_block(struct rvu * rvu,int pcifunc,int blktype)1084 static void rvu_detach_block(struct rvu *rvu, int pcifunc, int blktype)
1085 {
1086 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1087 struct rvu_hwinfo *hw = rvu->hw;
1088 struct rvu_block *block;
1089 int slot, lf, num_lfs;
1090 int blkaddr;
1091
1092 blkaddr = rvu_get_blkaddr(rvu, blktype, pcifunc);
1093 if (blkaddr < 0)
1094 return;
1095
1096 block = &hw->block[blkaddr];
1097
1098 num_lfs = rvu_get_rsrc_mapcount(pfvf, block->type);
1099 if (!num_lfs)
1100 return;
1101
1102 for (slot = 0; slot < num_lfs; slot++) {
1103 lf = rvu_lookup_rsrc(rvu, block, pcifunc, slot);
1104 if (lf < 0) /* This should never happen */
1105 continue;
1106
1107 /* Disable the LF */
1108 rvu_write64(rvu, blkaddr, block->lfcfg_reg |
1109 (lf << block->lfshift), 0x00ULL);
1110
1111 /* Update SW maintained mapping info as well */
1112 rvu_update_rsrc_map(rvu, pfvf, block,
1113 pcifunc, lf, false);
1114
1115 /* Free the resource */
1116 rvu_free_rsrc(&block->lf, lf);
1117
1118 /* Clear MSIX vector offset for this LF */
1119 rvu_clear_msix_offset(rvu, pfvf, block, lf);
1120 }
1121 }
1122
rvu_detach_rsrcs(struct rvu * rvu,struct rsrc_detach * detach,u16 pcifunc)1123 static int rvu_detach_rsrcs(struct rvu *rvu, struct rsrc_detach *detach,
1124 u16 pcifunc)
1125 {
1126 struct rvu_hwinfo *hw = rvu->hw;
1127 bool detach_all = true;
1128 struct rvu_block *block;
1129 int blkid;
1130
1131 mutex_lock(&rvu->rsrc_lock);
1132
1133 /* Check for partial resource detach */
1134 if (detach && detach->partial)
1135 detach_all = false;
1136
1137 /* Check for RVU block's LFs attached to this func,
1138 * if so, detach them.
1139 */
1140 for (blkid = 0; blkid < BLK_COUNT; blkid++) {
1141 block = &hw->block[blkid];
1142 if (!block->lf.bmap)
1143 continue;
1144 if (!detach_all && detach) {
1145 if (blkid == BLKADDR_NPA && !detach->npalf)
1146 continue;
1147 else if ((blkid == BLKADDR_NIX0) && !detach->nixlf)
1148 continue;
1149 else if ((blkid == BLKADDR_SSO) && !detach->sso)
1150 continue;
1151 else if ((blkid == BLKADDR_SSOW) && !detach->ssow)
1152 continue;
1153 else if ((blkid == BLKADDR_TIM) && !detach->timlfs)
1154 continue;
1155 else if ((blkid == BLKADDR_CPT0) && !detach->cptlfs)
1156 continue;
1157 }
1158 rvu_detach_block(rvu, pcifunc, block->type);
1159 }
1160
1161 mutex_unlock(&rvu->rsrc_lock);
1162 return 0;
1163 }
1164
rvu_mbox_handler_detach_resources(struct rvu * rvu,struct rsrc_detach * detach,struct msg_rsp * rsp)1165 int rvu_mbox_handler_detach_resources(struct rvu *rvu,
1166 struct rsrc_detach *detach,
1167 struct msg_rsp *rsp)
1168 {
1169 return rvu_detach_rsrcs(rvu, detach, detach->hdr.pcifunc);
1170 }
1171
rvu_attach_block(struct rvu * rvu,int pcifunc,int blktype,int num_lfs)1172 static void rvu_attach_block(struct rvu *rvu, int pcifunc,
1173 int blktype, int num_lfs)
1174 {
1175 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1176 struct rvu_hwinfo *hw = rvu->hw;
1177 struct rvu_block *block;
1178 int slot, lf;
1179 int blkaddr;
1180 u64 cfg;
1181
1182 if (!num_lfs)
1183 return;
1184
1185 blkaddr = rvu_get_blkaddr(rvu, blktype, 0);
1186 if (blkaddr < 0)
1187 return;
1188
1189 block = &hw->block[blkaddr];
1190 if (!block->lf.bmap)
1191 return;
1192
1193 for (slot = 0; slot < num_lfs; slot++) {
1194 /* Allocate the resource */
1195 lf = rvu_alloc_rsrc(&block->lf);
1196 if (lf < 0)
1197 return;
1198
1199 cfg = (1ULL << 63) | (pcifunc << 8) | slot;
1200 rvu_write64(rvu, blkaddr, block->lfcfg_reg |
1201 (lf << block->lfshift), cfg);
1202 rvu_update_rsrc_map(rvu, pfvf, block,
1203 pcifunc, lf, true);
1204
1205 /* Set start MSIX vector for this LF within this PF/VF */
1206 rvu_set_msix_offset(rvu, pfvf, block, lf);
1207 }
1208 }
1209
rvu_check_rsrc_availability(struct rvu * rvu,struct rsrc_attach * req,u16 pcifunc)1210 static int rvu_check_rsrc_availability(struct rvu *rvu,
1211 struct rsrc_attach *req, u16 pcifunc)
1212 {
1213 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
1214 struct rvu_hwinfo *hw = rvu->hw;
1215 struct rvu_block *block;
1216 int free_lfs, mappedlfs;
1217
1218 /* Only one NPA LF can be attached */
1219 if (req->npalf && !rvu_get_rsrc_mapcount(pfvf, BLKTYPE_NPA)) {
1220 block = &hw->block[BLKADDR_NPA];
1221 free_lfs = rvu_rsrc_free_count(&block->lf);
1222 if (!free_lfs)
1223 goto fail;
1224 } else if (req->npalf) {
1225 dev_err(&rvu->pdev->dev,
1226 "Func 0x%x: Invalid req, already has NPA\n",
1227 pcifunc);
1228 return -EINVAL;
1229 }
1230
1231 /* Only one NIX LF can be attached */
1232 if (req->nixlf && !rvu_get_rsrc_mapcount(pfvf, BLKTYPE_NIX)) {
1233 block = &hw->block[BLKADDR_NIX0];
1234 free_lfs = rvu_rsrc_free_count(&block->lf);
1235 if (!free_lfs)
1236 goto fail;
1237 } else if (req->nixlf) {
1238 dev_err(&rvu->pdev->dev,
1239 "Func 0x%x: Invalid req, already has NIX\n",
1240 pcifunc);
1241 return -EINVAL;
1242 }
1243
1244 if (req->sso) {
1245 block = &hw->block[BLKADDR_SSO];
1246 /* Is request within limits ? */
1247 if (req->sso > block->lf.max) {
1248 dev_err(&rvu->pdev->dev,
1249 "Func 0x%x: Invalid SSO req, %d > max %d\n",
1250 pcifunc, req->sso, block->lf.max);
1251 return -EINVAL;
1252 }
1253 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->type);
1254 free_lfs = rvu_rsrc_free_count(&block->lf);
1255 /* Check if additional resources are available */
1256 if (req->sso > mappedlfs &&
1257 ((req->sso - mappedlfs) > free_lfs))
1258 goto fail;
1259 }
1260
1261 if (req->ssow) {
1262 block = &hw->block[BLKADDR_SSOW];
1263 if (req->ssow > block->lf.max) {
1264 dev_err(&rvu->pdev->dev,
1265 "Func 0x%x: Invalid SSOW req, %d > max %d\n",
1266 pcifunc, req->sso, block->lf.max);
1267 return -EINVAL;
1268 }
1269 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->type);
1270 free_lfs = rvu_rsrc_free_count(&block->lf);
1271 if (req->ssow > mappedlfs &&
1272 ((req->ssow - mappedlfs) > free_lfs))
1273 goto fail;
1274 }
1275
1276 if (req->timlfs) {
1277 block = &hw->block[BLKADDR_TIM];
1278 if (req->timlfs > block->lf.max) {
1279 dev_err(&rvu->pdev->dev,
1280 "Func 0x%x: Invalid TIMLF req, %d > max %d\n",
1281 pcifunc, req->timlfs, block->lf.max);
1282 return -EINVAL;
1283 }
1284 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->type);
1285 free_lfs = rvu_rsrc_free_count(&block->lf);
1286 if (req->timlfs > mappedlfs &&
1287 ((req->timlfs - mappedlfs) > free_lfs))
1288 goto fail;
1289 }
1290
1291 if (req->cptlfs) {
1292 block = &hw->block[BLKADDR_CPT0];
1293 if (req->cptlfs > block->lf.max) {
1294 dev_err(&rvu->pdev->dev,
1295 "Func 0x%x: Invalid CPTLF req, %d > max %d\n",
1296 pcifunc, req->cptlfs, block->lf.max);
1297 return -EINVAL;
1298 }
1299 mappedlfs = rvu_get_rsrc_mapcount(pfvf, block->type);
1300 free_lfs = rvu_rsrc_free_count(&block->lf);
1301 if (req->cptlfs > mappedlfs &&
1302 ((req->cptlfs - mappedlfs) > free_lfs))
1303 goto fail;
1304 }
1305
1306 return 0;
1307
1308 fail:
1309 dev_info(rvu->dev, "Request for %s failed\n", block->name);
1310 return -ENOSPC;
1311 }
1312
rvu_mbox_handler_attach_resources(struct rvu * rvu,struct rsrc_attach * attach,struct msg_rsp * rsp)1313 int rvu_mbox_handler_attach_resources(struct rvu *rvu,
1314 struct rsrc_attach *attach,
1315 struct msg_rsp *rsp)
1316 {
1317 u16 pcifunc = attach->hdr.pcifunc;
1318 int err;
1319
1320 /* If first request, detach all existing attached resources */
1321 if (!attach->modify)
1322 rvu_detach_rsrcs(rvu, NULL, pcifunc);
1323
1324 mutex_lock(&rvu->rsrc_lock);
1325
1326 /* Check if the request can be accommodated */
1327 err = rvu_check_rsrc_availability(rvu, attach, pcifunc);
1328 if (err)
1329 goto exit;
1330
1331 /* Now attach the requested resources */
1332 if (attach->npalf)
1333 rvu_attach_block(rvu, pcifunc, BLKTYPE_NPA, 1);
1334
1335 if (attach->nixlf)
1336 rvu_attach_block(rvu, pcifunc, BLKTYPE_NIX, 1);
1337
1338 if (attach->sso) {
1339 /* RVU func doesn't know which exact LF or slot is attached
1340 * to it, it always sees as slot 0,1,2. So for a 'modify'
1341 * request, simply detach all existing attached LFs/slots
1342 * and attach a fresh.
1343 */
1344 if (attach->modify)
1345 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSO);
1346 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSO, attach->sso);
1347 }
1348
1349 if (attach->ssow) {
1350 if (attach->modify)
1351 rvu_detach_block(rvu, pcifunc, BLKTYPE_SSOW);
1352 rvu_attach_block(rvu, pcifunc, BLKTYPE_SSOW, attach->ssow);
1353 }
1354
1355 if (attach->timlfs) {
1356 if (attach->modify)
1357 rvu_detach_block(rvu, pcifunc, BLKTYPE_TIM);
1358 rvu_attach_block(rvu, pcifunc, BLKTYPE_TIM, attach->timlfs);
1359 }
1360
1361 if (attach->cptlfs) {
1362 if (attach->modify)
1363 rvu_detach_block(rvu, pcifunc, BLKTYPE_CPT);
1364 rvu_attach_block(rvu, pcifunc, BLKTYPE_CPT, attach->cptlfs);
1365 }
1366
1367 exit:
1368 mutex_unlock(&rvu->rsrc_lock);
1369 return err;
1370 }
1371
rvu_get_msix_offset(struct rvu * rvu,struct rvu_pfvf * pfvf,int blkaddr,int lf)1372 static u16 rvu_get_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
1373 int blkaddr, int lf)
1374 {
1375 u16 vec;
1376
1377 if (lf < 0)
1378 return MSIX_VECTOR_INVALID;
1379
1380 for (vec = 0; vec < pfvf->msix.max; vec++) {
1381 if (pfvf->msix_lfmap[vec] == MSIX_BLKLF(blkaddr, lf))
1382 return vec;
1383 }
1384 return MSIX_VECTOR_INVALID;
1385 }
1386
rvu_set_msix_offset(struct rvu * rvu,struct rvu_pfvf * pfvf,struct rvu_block * block,int lf)1387 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
1388 struct rvu_block *block, int lf)
1389 {
1390 u16 nvecs, vec, offset;
1391 u64 cfg;
1392
1393 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg |
1394 (lf << block->lfshift));
1395 nvecs = (cfg >> 12) & 0xFF;
1396
1397 /* Check and alloc MSIX vectors, must be contiguous */
1398 if (!rvu_rsrc_check_contig(&pfvf->msix, nvecs))
1399 return;
1400
1401 offset = rvu_alloc_rsrc_contig(&pfvf->msix, nvecs);
1402
1403 /* Config MSIX offset in LF */
1404 rvu_write64(rvu, block->addr, block->msixcfg_reg |
1405 (lf << block->lfshift), (cfg & ~0x7FFULL) | offset);
1406
1407 /* Update the bitmap as well */
1408 for (vec = 0; vec < nvecs; vec++)
1409 pfvf->msix_lfmap[offset + vec] = MSIX_BLKLF(block->addr, lf);
1410 }
1411
rvu_clear_msix_offset(struct rvu * rvu,struct rvu_pfvf * pfvf,struct rvu_block * block,int lf)1412 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
1413 struct rvu_block *block, int lf)
1414 {
1415 u16 nvecs, vec, offset;
1416 u64 cfg;
1417
1418 cfg = rvu_read64(rvu, block->addr, block->msixcfg_reg |
1419 (lf << block->lfshift));
1420 nvecs = (cfg >> 12) & 0xFF;
1421
1422 /* Clear MSIX offset in LF */
1423 rvu_write64(rvu, block->addr, block->msixcfg_reg |
1424 (lf << block->lfshift), cfg & ~0x7FFULL);
1425
1426 offset = rvu_get_msix_offset(rvu, pfvf, block->addr, lf);
1427
1428 /* Update the mapping */
1429 for (vec = 0; vec < nvecs; vec++)
1430 pfvf->msix_lfmap[offset + vec] = 0;
1431
1432 /* Free the same in MSIX bitmap */
1433 rvu_free_rsrc_contig(&pfvf->msix, nvecs, offset);
1434 }
1435
rvu_mbox_handler_msix_offset(struct rvu * rvu,struct msg_req * req,struct msix_offset_rsp * rsp)1436 int rvu_mbox_handler_msix_offset(struct rvu *rvu, struct msg_req *req,
1437 struct msix_offset_rsp *rsp)
1438 {
1439 struct rvu_hwinfo *hw = rvu->hw;
1440 u16 pcifunc = req->hdr.pcifunc;
1441 struct rvu_pfvf *pfvf;
1442 int lf, slot;
1443
1444 pfvf = rvu_get_pfvf(rvu, pcifunc);
1445 if (!pfvf->msix.bmap)
1446 return 0;
1447
1448 /* Set MSIX offsets for each block's LFs attached to this PF/VF */
1449 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NPA], pcifunc, 0);
1450 rsp->npa_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NPA, lf);
1451
1452 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_NIX0], pcifunc, 0);
1453 rsp->nix_msixoff = rvu_get_msix_offset(rvu, pfvf, BLKADDR_NIX0, lf);
1454
1455 rsp->sso = pfvf->sso;
1456 for (slot = 0; slot < rsp->sso; slot++) {
1457 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSO], pcifunc, slot);
1458 rsp->sso_msixoff[slot] =
1459 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSO, lf);
1460 }
1461
1462 rsp->ssow = pfvf->ssow;
1463 for (slot = 0; slot < rsp->ssow; slot++) {
1464 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_SSOW], pcifunc, slot);
1465 rsp->ssow_msixoff[slot] =
1466 rvu_get_msix_offset(rvu, pfvf, BLKADDR_SSOW, lf);
1467 }
1468
1469 rsp->timlfs = pfvf->timlfs;
1470 for (slot = 0; slot < rsp->timlfs; slot++) {
1471 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_TIM], pcifunc, slot);
1472 rsp->timlf_msixoff[slot] =
1473 rvu_get_msix_offset(rvu, pfvf, BLKADDR_TIM, lf);
1474 }
1475
1476 rsp->cptlfs = pfvf->cptlfs;
1477 for (slot = 0; slot < rsp->cptlfs; slot++) {
1478 lf = rvu_get_lf(rvu, &hw->block[BLKADDR_CPT0], pcifunc, slot);
1479 rsp->cptlf_msixoff[slot] =
1480 rvu_get_msix_offset(rvu, pfvf, BLKADDR_CPT0, lf);
1481 }
1482 return 0;
1483 }
1484
rvu_mbox_handler_vf_flr(struct rvu * rvu,struct msg_req * req,struct msg_rsp * rsp)1485 int rvu_mbox_handler_vf_flr(struct rvu *rvu, struct msg_req *req,
1486 struct msg_rsp *rsp)
1487 {
1488 u16 pcifunc = req->hdr.pcifunc;
1489 u16 vf, numvfs;
1490 u64 cfg;
1491
1492 vf = pcifunc & RVU_PFVF_FUNC_MASK;
1493 cfg = rvu_read64(rvu, BLKADDR_RVUM,
1494 RVU_PRIV_PFX_CFG(rvu_get_pf(pcifunc)));
1495 numvfs = (cfg >> 12) & 0xFF;
1496
1497 if (vf && vf <= numvfs)
1498 __rvu_flr_handler(rvu, pcifunc);
1499 else
1500 return RVU_INVALID_VF_ID;
1501
1502 return 0;
1503 }
1504
rvu_mbox_handler_get_hw_cap(struct rvu * rvu,struct msg_req * req,struct get_hw_cap_rsp * rsp)1505 int rvu_mbox_handler_get_hw_cap(struct rvu *rvu, struct msg_req *req,
1506 struct get_hw_cap_rsp *rsp)
1507 {
1508 struct rvu_hwinfo *hw = rvu->hw;
1509
1510 rsp->nix_fixed_txschq_mapping = hw->cap.nix_fixed_txschq_mapping;
1511 rsp->nix_shaping = hw->cap.nix_shaping;
1512
1513 return 0;
1514 }
1515
rvu_process_mbox_msg(struct otx2_mbox * mbox,int devid,struct mbox_msghdr * req)1516 static int rvu_process_mbox_msg(struct otx2_mbox *mbox, int devid,
1517 struct mbox_msghdr *req)
1518 {
1519 struct rvu *rvu = pci_get_drvdata(mbox->pdev);
1520
1521 /* Check if valid, if not reply with a invalid msg */
1522 if (req->sig != OTX2_MBOX_REQ_SIG)
1523 goto bad_message;
1524
1525 switch (req->id) {
1526 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
1527 case _id: { \
1528 struct _rsp_type *rsp; \
1529 int err; \
1530 \
1531 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \
1532 mbox, devid, \
1533 sizeof(struct _rsp_type)); \
1534 /* some handlers should complete even if reply */ \
1535 /* could not be allocated */ \
1536 if (!rsp && \
1537 _id != MBOX_MSG_DETACH_RESOURCES && \
1538 _id != MBOX_MSG_NIX_TXSCH_FREE && \
1539 _id != MBOX_MSG_VF_FLR) \
1540 return -ENOMEM; \
1541 if (rsp) { \
1542 rsp->hdr.id = _id; \
1543 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \
1544 rsp->hdr.pcifunc = req->pcifunc; \
1545 rsp->hdr.rc = 0; \
1546 } \
1547 \
1548 err = rvu_mbox_handler_ ## _fn_name(rvu, \
1549 (struct _req_type *)req, \
1550 rsp); \
1551 if (rsp && err) \
1552 rsp->hdr.rc = err; \
1553 \
1554 trace_otx2_msg_process(mbox->pdev, _id, err); \
1555 return rsp ? err : -ENOMEM; \
1556 }
1557 MBOX_MESSAGES
1558 #undef M
1559
1560 bad_message:
1561 default:
1562 otx2_reply_invalid_msg(mbox, devid, req->pcifunc, req->id);
1563 return -ENODEV;
1564 }
1565 }
1566
__rvu_mbox_handler(struct rvu_work * mwork,int type)1567 static void __rvu_mbox_handler(struct rvu_work *mwork, int type)
1568 {
1569 struct rvu *rvu = mwork->rvu;
1570 int offset, err, id, devid;
1571 struct otx2_mbox_dev *mdev;
1572 struct mbox_hdr *req_hdr;
1573 struct mbox_msghdr *msg;
1574 struct mbox_wq_info *mw;
1575 struct otx2_mbox *mbox;
1576
1577 switch (type) {
1578 case TYPE_AFPF:
1579 mw = &rvu->afpf_wq_info;
1580 break;
1581 case TYPE_AFVF:
1582 mw = &rvu->afvf_wq_info;
1583 break;
1584 default:
1585 return;
1586 }
1587
1588 devid = mwork - mw->mbox_wrk;
1589 mbox = &mw->mbox;
1590 mdev = &mbox->dev[devid];
1591
1592 /* Process received mbox messages */
1593 req_hdr = mdev->mbase + mbox->rx_start;
1594 if (mw->mbox_wrk[devid].num_msgs == 0)
1595 return;
1596
1597 offset = mbox->rx_start + ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
1598
1599 for (id = 0; id < mw->mbox_wrk[devid].num_msgs; id++) {
1600 msg = mdev->mbase + offset;
1601
1602 /* Set which PF/VF sent this message based on mbox IRQ */
1603 switch (type) {
1604 case TYPE_AFPF:
1605 msg->pcifunc &=
1606 ~(RVU_PFVF_PF_MASK << RVU_PFVF_PF_SHIFT);
1607 msg->pcifunc |= (devid << RVU_PFVF_PF_SHIFT);
1608 break;
1609 case TYPE_AFVF:
1610 msg->pcifunc &=
1611 ~(RVU_PFVF_FUNC_MASK << RVU_PFVF_FUNC_SHIFT);
1612 msg->pcifunc |= (devid << RVU_PFVF_FUNC_SHIFT) + 1;
1613 break;
1614 }
1615
1616 err = rvu_process_mbox_msg(mbox, devid, msg);
1617 if (!err) {
1618 offset = mbox->rx_start + msg->next_msgoff;
1619 continue;
1620 }
1621
1622 if (msg->pcifunc & RVU_PFVF_FUNC_MASK)
1623 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d:VF%d\n",
1624 err, otx2_mbox_id2name(msg->id),
1625 msg->id, rvu_get_pf(msg->pcifunc),
1626 (msg->pcifunc & RVU_PFVF_FUNC_MASK) - 1);
1627 else
1628 dev_warn(rvu->dev, "Error %d when processing message %s (0x%x) from PF%d\n",
1629 err, otx2_mbox_id2name(msg->id),
1630 msg->id, devid);
1631 }
1632 mw->mbox_wrk[devid].num_msgs = 0;
1633
1634 /* Send mbox responses to VF/PF */
1635 otx2_mbox_msg_send(mbox, devid);
1636 }
1637
rvu_afpf_mbox_handler(struct work_struct * work)1638 static inline void rvu_afpf_mbox_handler(struct work_struct *work)
1639 {
1640 struct rvu_work *mwork = container_of(work, struct rvu_work, work);
1641
1642 __rvu_mbox_handler(mwork, TYPE_AFPF);
1643 }
1644
rvu_afvf_mbox_handler(struct work_struct * work)1645 static inline void rvu_afvf_mbox_handler(struct work_struct *work)
1646 {
1647 struct rvu_work *mwork = container_of(work, struct rvu_work, work);
1648
1649 __rvu_mbox_handler(mwork, TYPE_AFVF);
1650 }
1651
__rvu_mbox_up_handler(struct rvu_work * mwork,int type)1652 static void __rvu_mbox_up_handler(struct rvu_work *mwork, int type)
1653 {
1654 struct rvu *rvu = mwork->rvu;
1655 struct otx2_mbox_dev *mdev;
1656 struct mbox_hdr *rsp_hdr;
1657 struct mbox_msghdr *msg;
1658 struct mbox_wq_info *mw;
1659 struct otx2_mbox *mbox;
1660 int offset, id, devid;
1661
1662 switch (type) {
1663 case TYPE_AFPF:
1664 mw = &rvu->afpf_wq_info;
1665 break;
1666 case TYPE_AFVF:
1667 mw = &rvu->afvf_wq_info;
1668 break;
1669 default:
1670 return;
1671 }
1672
1673 devid = mwork - mw->mbox_wrk_up;
1674 mbox = &mw->mbox_up;
1675 mdev = &mbox->dev[devid];
1676
1677 rsp_hdr = mdev->mbase + mbox->rx_start;
1678 if (mw->mbox_wrk_up[devid].up_num_msgs == 0) {
1679 dev_warn(rvu->dev, "mbox up handler: num_msgs = 0\n");
1680 return;
1681 }
1682
1683 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN);
1684
1685 for (id = 0; id < mw->mbox_wrk_up[devid].up_num_msgs; id++) {
1686 msg = mdev->mbase + offset;
1687
1688 if (msg->id >= MBOX_MSG_MAX) {
1689 dev_err(rvu->dev,
1690 "Mbox msg with unknown ID 0x%x\n", msg->id);
1691 goto end;
1692 }
1693
1694 if (msg->sig != OTX2_MBOX_RSP_SIG) {
1695 dev_err(rvu->dev,
1696 "Mbox msg with wrong signature %x, ID 0x%x\n",
1697 msg->sig, msg->id);
1698 goto end;
1699 }
1700
1701 switch (msg->id) {
1702 case MBOX_MSG_CGX_LINK_EVENT:
1703 break;
1704 default:
1705 if (msg->rc)
1706 dev_err(rvu->dev,
1707 "Mbox msg response has err %d, ID 0x%x\n",
1708 msg->rc, msg->id);
1709 break;
1710 }
1711 end:
1712 offset = mbox->rx_start + msg->next_msgoff;
1713 mdev->msgs_acked++;
1714 }
1715 mw->mbox_wrk_up[devid].up_num_msgs = 0;
1716
1717 otx2_mbox_reset(mbox, devid);
1718 }
1719
rvu_afpf_mbox_up_handler(struct work_struct * work)1720 static inline void rvu_afpf_mbox_up_handler(struct work_struct *work)
1721 {
1722 struct rvu_work *mwork = container_of(work, struct rvu_work, work);
1723
1724 __rvu_mbox_up_handler(mwork, TYPE_AFPF);
1725 }
1726
rvu_afvf_mbox_up_handler(struct work_struct * work)1727 static inline void rvu_afvf_mbox_up_handler(struct work_struct *work)
1728 {
1729 struct rvu_work *mwork = container_of(work, struct rvu_work, work);
1730
1731 __rvu_mbox_up_handler(mwork, TYPE_AFVF);
1732 }
1733
rvu_mbox_init(struct rvu * rvu,struct mbox_wq_info * mw,int type,int num,void (mbox_handler)(struct work_struct *),void (mbox_up_handler)(struct work_struct *))1734 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw,
1735 int type, int num,
1736 void (mbox_handler)(struct work_struct *),
1737 void (mbox_up_handler)(struct work_struct *))
1738 {
1739 void __iomem *hwbase = NULL, *reg_base;
1740 int err, i, dir, dir_up;
1741 struct rvu_work *mwork;
1742 const char *name;
1743 u64 bar4_addr;
1744
1745 switch (type) {
1746 case TYPE_AFPF:
1747 name = "rvu_afpf_mailbox";
1748 bar4_addr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PF_BAR4_ADDR);
1749 dir = MBOX_DIR_AFPF;
1750 dir_up = MBOX_DIR_AFPF_UP;
1751 reg_base = rvu->afreg_base;
1752 break;
1753 case TYPE_AFVF:
1754 name = "rvu_afvf_mailbox";
1755 bar4_addr = rvupf_read64(rvu, RVU_PF_VF_BAR4_ADDR);
1756 dir = MBOX_DIR_PFVF;
1757 dir_up = MBOX_DIR_PFVF_UP;
1758 reg_base = rvu->pfreg_base;
1759 break;
1760 default:
1761 return -EINVAL;
1762 }
1763
1764 mw->mbox_wq = alloc_workqueue(name,
1765 WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM,
1766 num);
1767 if (!mw->mbox_wq)
1768 return -ENOMEM;
1769
1770 mw->mbox_wrk = devm_kcalloc(rvu->dev, num,
1771 sizeof(struct rvu_work), GFP_KERNEL);
1772 if (!mw->mbox_wrk) {
1773 err = -ENOMEM;
1774 goto exit;
1775 }
1776
1777 mw->mbox_wrk_up = devm_kcalloc(rvu->dev, num,
1778 sizeof(struct rvu_work), GFP_KERNEL);
1779 if (!mw->mbox_wrk_up) {
1780 err = -ENOMEM;
1781 goto exit;
1782 }
1783
1784 /* Mailbox is a reserved memory (in RAM) region shared between
1785 * RVU devices, shouldn't be mapped as device memory to allow
1786 * unaligned accesses.
1787 */
1788 hwbase = ioremap_wc(bar4_addr, MBOX_SIZE * num);
1789 if (!hwbase) {
1790 dev_err(rvu->dev, "Unable to map mailbox region\n");
1791 err = -ENOMEM;
1792 goto exit;
1793 }
1794
1795 err = otx2_mbox_init(&mw->mbox, hwbase, rvu->pdev, reg_base, dir, num);
1796 if (err)
1797 goto exit;
1798
1799 err = otx2_mbox_init(&mw->mbox_up, hwbase, rvu->pdev,
1800 reg_base, dir_up, num);
1801 if (err)
1802 goto exit;
1803
1804 for (i = 0; i < num; i++) {
1805 mwork = &mw->mbox_wrk[i];
1806 mwork->rvu = rvu;
1807 INIT_WORK(&mwork->work, mbox_handler);
1808
1809 mwork = &mw->mbox_wrk_up[i];
1810 mwork->rvu = rvu;
1811 INIT_WORK(&mwork->work, mbox_up_handler);
1812 }
1813
1814 return 0;
1815 exit:
1816 if (hwbase)
1817 iounmap((void __iomem *)hwbase);
1818 destroy_workqueue(mw->mbox_wq);
1819 return err;
1820 }
1821
rvu_mbox_destroy(struct mbox_wq_info * mw)1822 static void rvu_mbox_destroy(struct mbox_wq_info *mw)
1823 {
1824 if (mw->mbox_wq) {
1825 flush_workqueue(mw->mbox_wq);
1826 destroy_workqueue(mw->mbox_wq);
1827 mw->mbox_wq = NULL;
1828 }
1829
1830 if (mw->mbox.hwbase)
1831 iounmap((void __iomem *)mw->mbox.hwbase);
1832
1833 otx2_mbox_destroy(&mw->mbox);
1834 otx2_mbox_destroy(&mw->mbox_up);
1835 }
1836
rvu_queue_work(struct mbox_wq_info * mw,int first,int mdevs,u64 intr)1837 static void rvu_queue_work(struct mbox_wq_info *mw, int first,
1838 int mdevs, u64 intr)
1839 {
1840 struct otx2_mbox_dev *mdev;
1841 struct otx2_mbox *mbox;
1842 struct mbox_hdr *hdr;
1843 int i;
1844
1845 for (i = first; i < mdevs; i++) {
1846 /* start from 0 */
1847 if (!(intr & BIT_ULL(i - first)))
1848 continue;
1849
1850 mbox = &mw->mbox;
1851 mdev = &mbox->dev[i];
1852 hdr = mdev->mbase + mbox->rx_start;
1853
1854 /*The hdr->num_msgs is set to zero immediately in the interrupt
1855 * handler to ensure that it holds a correct value next time
1856 * when the interrupt handler is called.
1857 * pf->mbox.num_msgs holds the data for use in pfaf_mbox_handler
1858 * pf>mbox.up_num_msgs holds the data for use in
1859 * pfaf_mbox_up_handler.
1860 */
1861
1862 if (hdr->num_msgs) {
1863 mw->mbox_wrk[i].num_msgs = hdr->num_msgs;
1864 hdr->num_msgs = 0;
1865 queue_work(mw->mbox_wq, &mw->mbox_wrk[i].work);
1866 }
1867 mbox = &mw->mbox_up;
1868 mdev = &mbox->dev[i];
1869 hdr = mdev->mbase + mbox->rx_start;
1870 if (hdr->num_msgs) {
1871 mw->mbox_wrk_up[i].up_num_msgs = hdr->num_msgs;
1872 hdr->num_msgs = 0;
1873 queue_work(mw->mbox_wq, &mw->mbox_wrk_up[i].work);
1874 }
1875 }
1876 }
1877
rvu_mbox_intr_handler(int irq,void * rvu_irq)1878 static irqreturn_t rvu_mbox_intr_handler(int irq, void *rvu_irq)
1879 {
1880 struct rvu *rvu = (struct rvu *)rvu_irq;
1881 int vfs = rvu->vfs;
1882 u64 intr;
1883
1884 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT);
1885 /* Clear interrupts */
1886 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT, intr);
1887 if (intr)
1888 trace_otx2_msg_interrupt(rvu->pdev, "PF(s) to AF", intr);
1889
1890 /* Sync with mbox memory region */
1891 rmb();
1892
1893 rvu_queue_work(&rvu->afpf_wq_info, 0, rvu->hw->total_pfs, intr);
1894
1895 /* Handle VF interrupts */
1896 if (vfs > 64) {
1897 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(1));
1898 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), intr);
1899
1900 rvu_queue_work(&rvu->afvf_wq_info, 64, vfs, intr);
1901 vfs -= 64;
1902 }
1903
1904 intr = rvupf_read64(rvu, RVU_PF_VFPF_MBOX_INTX(0));
1905 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), intr);
1906 if (intr)
1907 trace_otx2_msg_interrupt(rvu->pdev, "VF(s) to AF", intr);
1908
1909 rvu_queue_work(&rvu->afvf_wq_info, 0, vfs, intr);
1910
1911 return IRQ_HANDLED;
1912 }
1913
rvu_enable_mbox_intr(struct rvu * rvu)1914 static void rvu_enable_mbox_intr(struct rvu *rvu)
1915 {
1916 struct rvu_hwinfo *hw = rvu->hw;
1917
1918 /* Clear spurious irqs, if any */
1919 rvu_write64(rvu, BLKADDR_RVUM,
1920 RVU_AF_PFAF_MBOX_INT, INTR_MASK(hw->total_pfs));
1921
1922 /* Enable mailbox interrupt for all PFs except PF0 i.e AF itself */
1923 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1S,
1924 INTR_MASK(hw->total_pfs) & ~1ULL);
1925 }
1926
rvu_blklf_teardown(struct rvu * rvu,u16 pcifunc,u8 blkaddr)1927 static void rvu_blklf_teardown(struct rvu *rvu, u16 pcifunc, u8 blkaddr)
1928 {
1929 struct rvu_block *block;
1930 int slot, lf, num_lfs;
1931 int err;
1932
1933 block = &rvu->hw->block[blkaddr];
1934 num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc),
1935 block->type);
1936 if (!num_lfs)
1937 return;
1938 for (slot = 0; slot < num_lfs; slot++) {
1939 lf = rvu_get_lf(rvu, block, pcifunc, slot);
1940 if (lf < 0)
1941 continue;
1942
1943 /* Cleanup LF and reset it */
1944 if (block->addr == BLKADDR_NIX0)
1945 rvu_nix_lf_teardown(rvu, pcifunc, block->addr, lf);
1946 else if (block->addr == BLKADDR_NPA)
1947 rvu_npa_lf_teardown(rvu, pcifunc, lf);
1948
1949 err = rvu_lf_reset(rvu, block, lf);
1950 if (err) {
1951 dev_err(rvu->dev, "Failed to reset blkaddr %d LF%d\n",
1952 block->addr, lf);
1953 }
1954 }
1955 }
1956
__rvu_flr_handler(struct rvu * rvu,u16 pcifunc)1957 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc)
1958 {
1959 mutex_lock(&rvu->flr_lock);
1960 /* Reset order should reflect inter-block dependencies:
1961 * 1. Reset any packet/work sources (NIX, CPT, TIM)
1962 * 2. Flush and reset SSO/SSOW
1963 * 3. Cleanup pools (NPA)
1964 */
1965 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NIX0);
1966 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_CPT0);
1967 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_TIM);
1968 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSOW);
1969 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_SSO);
1970 rvu_blklf_teardown(rvu, pcifunc, BLKADDR_NPA);
1971 rvu_detach_rsrcs(rvu, NULL, pcifunc);
1972 mutex_unlock(&rvu->flr_lock);
1973 }
1974
rvu_afvf_flr_handler(struct rvu * rvu,int vf)1975 static void rvu_afvf_flr_handler(struct rvu *rvu, int vf)
1976 {
1977 int reg = 0;
1978
1979 /* pcifunc = 0(PF0) | (vf + 1) */
1980 __rvu_flr_handler(rvu, vf + 1);
1981
1982 if (vf >= 64) {
1983 reg = 1;
1984 vf = vf - 64;
1985 }
1986
1987 /* Signal FLR finish and enable IRQ */
1988 rvupf_write64(rvu, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf));
1989 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf));
1990 }
1991
rvu_flr_handler(struct work_struct * work)1992 static void rvu_flr_handler(struct work_struct *work)
1993 {
1994 struct rvu_work *flrwork = container_of(work, struct rvu_work, work);
1995 struct rvu *rvu = flrwork->rvu;
1996 u16 pcifunc, numvfs, vf;
1997 u64 cfg;
1998 int pf;
1999
2000 pf = flrwork - rvu->flr_wrk;
2001 if (pf >= rvu->hw->total_pfs) {
2002 rvu_afvf_flr_handler(rvu, pf - rvu->hw->total_pfs);
2003 return;
2004 }
2005
2006 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
2007 numvfs = (cfg >> 12) & 0xFF;
2008 pcifunc = pf << RVU_PFVF_PF_SHIFT;
2009
2010 for (vf = 0; vf < numvfs; vf++)
2011 __rvu_flr_handler(rvu, (pcifunc | (vf + 1)));
2012
2013 __rvu_flr_handler(rvu, pcifunc);
2014
2015 /* Signal FLR finish */
2016 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND, BIT_ULL(pf));
2017
2018 /* Enable interrupt */
2019 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S, BIT_ULL(pf));
2020 }
2021
rvu_afvf_queue_flr_work(struct rvu * rvu,int start_vf,int numvfs)2022 static void rvu_afvf_queue_flr_work(struct rvu *rvu, int start_vf, int numvfs)
2023 {
2024 int dev, vf, reg = 0;
2025 u64 intr;
2026
2027 if (start_vf >= 64)
2028 reg = 1;
2029
2030 intr = rvupf_read64(rvu, RVU_PF_VFFLR_INTX(reg));
2031 if (!intr)
2032 return;
2033
2034 for (vf = 0; vf < numvfs; vf++) {
2035 if (!(intr & BIT_ULL(vf)))
2036 continue;
2037 dev = vf + start_vf + rvu->hw->total_pfs;
2038 queue_work(rvu->flr_wq, &rvu->flr_wrk[dev].work);
2039 /* Clear and disable the interrupt */
2040 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf));
2041 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(reg), BIT_ULL(vf));
2042 }
2043 }
2044
rvu_flr_intr_handler(int irq,void * rvu_irq)2045 static irqreturn_t rvu_flr_intr_handler(int irq, void *rvu_irq)
2046 {
2047 struct rvu *rvu = (struct rvu *)rvu_irq;
2048 u64 intr;
2049 u8 pf;
2050
2051 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT);
2052 if (!intr)
2053 goto afvf_flr;
2054
2055 for (pf = 0; pf < rvu->hw->total_pfs; pf++) {
2056 if (intr & (1ULL << pf)) {
2057 /* PF is already dead do only AF related operations */
2058 queue_work(rvu->flr_wq, &rvu->flr_wrk[pf].work);
2059 /* clear interrupt */
2060 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT,
2061 BIT_ULL(pf));
2062 /* Disable the interrupt */
2063 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C,
2064 BIT_ULL(pf));
2065 }
2066 }
2067
2068 afvf_flr:
2069 rvu_afvf_queue_flr_work(rvu, 0, 64);
2070 if (rvu->vfs > 64)
2071 rvu_afvf_queue_flr_work(rvu, 64, rvu->vfs - 64);
2072
2073 return IRQ_HANDLED;
2074 }
2075
rvu_me_handle_vfset(struct rvu * rvu,int idx,u64 intr)2076 static void rvu_me_handle_vfset(struct rvu *rvu, int idx, u64 intr)
2077 {
2078 int vf;
2079
2080 /* Nothing to be done here other than clearing the
2081 * TRPEND bit.
2082 */
2083 for (vf = 0; vf < 64; vf++) {
2084 if (intr & (1ULL << vf)) {
2085 /* clear the trpend due to ME(master enable) */
2086 rvupf_write64(rvu, RVU_PF_VFTRPENDX(idx), BIT_ULL(vf));
2087 /* clear interrupt */
2088 rvupf_write64(rvu, RVU_PF_VFME_INTX(idx), BIT_ULL(vf));
2089 }
2090 }
2091 }
2092
2093 /* Handles ME interrupts from VFs of AF */
rvu_me_vf_intr_handler(int irq,void * rvu_irq)2094 static irqreturn_t rvu_me_vf_intr_handler(int irq, void *rvu_irq)
2095 {
2096 struct rvu *rvu = (struct rvu *)rvu_irq;
2097 int vfset;
2098 u64 intr;
2099
2100 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT);
2101
2102 for (vfset = 0; vfset <= 1; vfset++) {
2103 intr = rvupf_read64(rvu, RVU_PF_VFME_INTX(vfset));
2104 if (intr)
2105 rvu_me_handle_vfset(rvu, vfset, intr);
2106 }
2107
2108 return IRQ_HANDLED;
2109 }
2110
2111 /* Handles ME interrupts from PFs */
rvu_me_pf_intr_handler(int irq,void * rvu_irq)2112 static irqreturn_t rvu_me_pf_intr_handler(int irq, void *rvu_irq)
2113 {
2114 struct rvu *rvu = (struct rvu *)rvu_irq;
2115 u64 intr;
2116 u8 pf;
2117
2118 intr = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT);
2119
2120 /* Nothing to be done here other than clearing the
2121 * TRPEND bit.
2122 */
2123 for (pf = 0; pf < rvu->hw->total_pfs; pf++) {
2124 if (intr & (1ULL << pf)) {
2125 /* clear the trpend due to ME(master enable) */
2126 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFTRPEND,
2127 BIT_ULL(pf));
2128 /* clear interrupt */
2129 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT,
2130 BIT_ULL(pf));
2131 }
2132 }
2133
2134 return IRQ_HANDLED;
2135 }
2136
rvu_unregister_interrupts(struct rvu * rvu)2137 static void rvu_unregister_interrupts(struct rvu *rvu)
2138 {
2139 int irq;
2140
2141 /* Disable the Mbox interrupt */
2142 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFAF_MBOX_INT_ENA_W1C,
2143 INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2144
2145 /* Disable the PF FLR interrupt */
2146 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1C,
2147 INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2148
2149 /* Disable the PF ME interrupt */
2150 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1C,
2151 INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2152
2153 for (irq = 0; irq < rvu->num_vec; irq++) {
2154 if (rvu->irq_allocated[irq])
2155 free_irq(pci_irq_vector(rvu->pdev, irq), rvu);
2156 }
2157
2158 pci_free_irq_vectors(rvu->pdev);
2159 rvu->num_vec = 0;
2160 }
2161
rvu_afvf_msix_vectors_num_ok(struct rvu * rvu)2162 static int rvu_afvf_msix_vectors_num_ok(struct rvu *rvu)
2163 {
2164 struct rvu_pfvf *pfvf = &rvu->pf[0];
2165 int offset;
2166
2167 pfvf = &rvu->pf[0];
2168 offset = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff;
2169
2170 /* Make sure there are enough MSIX vectors configured so that
2171 * VF interrupts can be handled. Offset equal to zero means
2172 * that PF vectors are not configured and overlapping AF vectors.
2173 */
2174 return (pfvf->msix.max >= RVU_AF_INT_VEC_CNT + RVU_PF_INT_VEC_CNT) &&
2175 offset;
2176 }
2177
rvu_register_interrupts(struct rvu * rvu)2178 static int rvu_register_interrupts(struct rvu *rvu)
2179 {
2180 int ret, offset, pf_vec_start;
2181
2182 rvu->num_vec = pci_msix_vec_count(rvu->pdev);
2183
2184 rvu->irq_name = devm_kmalloc_array(rvu->dev, rvu->num_vec,
2185 NAME_SIZE, GFP_KERNEL);
2186 if (!rvu->irq_name)
2187 return -ENOMEM;
2188
2189 rvu->irq_allocated = devm_kcalloc(rvu->dev, rvu->num_vec,
2190 sizeof(bool), GFP_KERNEL);
2191 if (!rvu->irq_allocated)
2192 return -ENOMEM;
2193
2194 /* Enable MSI-X */
2195 ret = pci_alloc_irq_vectors(rvu->pdev, rvu->num_vec,
2196 rvu->num_vec, PCI_IRQ_MSIX);
2197 if (ret < 0) {
2198 dev_err(rvu->dev,
2199 "RVUAF: Request for %d msix vectors failed, ret %d\n",
2200 rvu->num_vec, ret);
2201 return ret;
2202 }
2203
2204 /* Register mailbox interrupt handler */
2205 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], "RVUAF Mbox");
2206 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_MBOX),
2207 rvu_mbox_intr_handler, 0,
2208 &rvu->irq_name[RVU_AF_INT_VEC_MBOX * NAME_SIZE], rvu);
2209 if (ret) {
2210 dev_err(rvu->dev,
2211 "RVUAF: IRQ registration failed for mbox irq\n");
2212 goto fail;
2213 }
2214
2215 rvu->irq_allocated[RVU_AF_INT_VEC_MBOX] = true;
2216
2217 /* Enable mailbox interrupts from all PFs */
2218 rvu_enable_mbox_intr(rvu);
2219
2220 /* Register FLR interrupt handler */
2221 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE],
2222 "RVUAF FLR");
2223 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFFLR),
2224 rvu_flr_intr_handler, 0,
2225 &rvu->irq_name[RVU_AF_INT_VEC_PFFLR * NAME_SIZE],
2226 rvu);
2227 if (ret) {
2228 dev_err(rvu->dev,
2229 "RVUAF: IRQ registration failed for FLR\n");
2230 goto fail;
2231 }
2232 rvu->irq_allocated[RVU_AF_INT_VEC_PFFLR] = true;
2233
2234 /* Enable FLR interrupt for all PFs*/
2235 rvu_write64(rvu, BLKADDR_RVUM,
2236 RVU_AF_PFFLR_INT, INTR_MASK(rvu->hw->total_pfs));
2237
2238 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFFLR_INT_ENA_W1S,
2239 INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2240
2241 /* Register ME interrupt handler */
2242 sprintf(&rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE],
2243 "RVUAF ME");
2244 ret = request_irq(pci_irq_vector(rvu->pdev, RVU_AF_INT_VEC_PFME),
2245 rvu_me_pf_intr_handler, 0,
2246 &rvu->irq_name[RVU_AF_INT_VEC_PFME * NAME_SIZE],
2247 rvu);
2248 if (ret) {
2249 dev_err(rvu->dev,
2250 "RVUAF: IRQ registration failed for ME\n");
2251 }
2252 rvu->irq_allocated[RVU_AF_INT_VEC_PFME] = true;
2253
2254 /* Clear TRPEND bit for all PF */
2255 rvu_write64(rvu, BLKADDR_RVUM,
2256 RVU_AF_PFTRPEND, INTR_MASK(rvu->hw->total_pfs));
2257 /* Enable ME interrupt for all PFs*/
2258 rvu_write64(rvu, BLKADDR_RVUM,
2259 RVU_AF_PFME_INT, INTR_MASK(rvu->hw->total_pfs));
2260
2261 rvu_write64(rvu, BLKADDR_RVUM, RVU_AF_PFME_INT_ENA_W1S,
2262 INTR_MASK(rvu->hw->total_pfs) & ~1ULL);
2263
2264 if (!rvu_afvf_msix_vectors_num_ok(rvu))
2265 return 0;
2266
2267 /* Get PF MSIX vectors offset. */
2268 pf_vec_start = rvu_read64(rvu, BLKADDR_RVUM,
2269 RVU_PRIV_PFX_INT_CFG(0)) & 0x3ff;
2270
2271 /* Register MBOX0 interrupt. */
2272 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX0;
2273 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox0");
2274 ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2275 rvu_mbox_intr_handler, 0,
2276 &rvu->irq_name[offset * NAME_SIZE],
2277 rvu);
2278 if (ret)
2279 dev_err(rvu->dev,
2280 "RVUAF: IRQ registration failed for Mbox0\n");
2281
2282 rvu->irq_allocated[offset] = true;
2283
2284 /* Register MBOX1 interrupt. MBOX1 IRQ number follows MBOX0 so
2285 * simply increment current offset by 1.
2286 */
2287 offset = pf_vec_start + RVU_PF_INT_VEC_VFPF_MBOX1;
2288 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF Mbox1");
2289 ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2290 rvu_mbox_intr_handler, 0,
2291 &rvu->irq_name[offset * NAME_SIZE],
2292 rvu);
2293 if (ret)
2294 dev_err(rvu->dev,
2295 "RVUAF: IRQ registration failed for Mbox1\n");
2296
2297 rvu->irq_allocated[offset] = true;
2298
2299 /* Register FLR interrupt handler for AF's VFs */
2300 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR0;
2301 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR0");
2302 ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2303 rvu_flr_intr_handler, 0,
2304 &rvu->irq_name[offset * NAME_SIZE], rvu);
2305 if (ret) {
2306 dev_err(rvu->dev,
2307 "RVUAF: IRQ registration failed for RVUAFVF FLR0\n");
2308 goto fail;
2309 }
2310 rvu->irq_allocated[offset] = true;
2311
2312 offset = pf_vec_start + RVU_PF_INT_VEC_VFFLR1;
2313 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF FLR1");
2314 ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2315 rvu_flr_intr_handler, 0,
2316 &rvu->irq_name[offset * NAME_SIZE], rvu);
2317 if (ret) {
2318 dev_err(rvu->dev,
2319 "RVUAF: IRQ registration failed for RVUAFVF FLR1\n");
2320 goto fail;
2321 }
2322 rvu->irq_allocated[offset] = true;
2323
2324 /* Register ME interrupt handler for AF's VFs */
2325 offset = pf_vec_start + RVU_PF_INT_VEC_VFME0;
2326 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME0");
2327 ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2328 rvu_me_vf_intr_handler, 0,
2329 &rvu->irq_name[offset * NAME_SIZE], rvu);
2330 if (ret) {
2331 dev_err(rvu->dev,
2332 "RVUAF: IRQ registration failed for RVUAFVF ME0\n");
2333 goto fail;
2334 }
2335 rvu->irq_allocated[offset] = true;
2336
2337 offset = pf_vec_start + RVU_PF_INT_VEC_VFME1;
2338 sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAFVF ME1");
2339 ret = request_irq(pci_irq_vector(rvu->pdev, offset),
2340 rvu_me_vf_intr_handler, 0,
2341 &rvu->irq_name[offset * NAME_SIZE], rvu);
2342 if (ret) {
2343 dev_err(rvu->dev,
2344 "RVUAF: IRQ registration failed for RVUAFVF ME1\n");
2345 goto fail;
2346 }
2347 rvu->irq_allocated[offset] = true;
2348 return 0;
2349
2350 fail:
2351 rvu_unregister_interrupts(rvu);
2352 return ret;
2353 }
2354
rvu_flr_wq_destroy(struct rvu * rvu)2355 static void rvu_flr_wq_destroy(struct rvu *rvu)
2356 {
2357 if (rvu->flr_wq) {
2358 flush_workqueue(rvu->flr_wq);
2359 destroy_workqueue(rvu->flr_wq);
2360 rvu->flr_wq = NULL;
2361 }
2362 }
2363
rvu_flr_init(struct rvu * rvu)2364 static int rvu_flr_init(struct rvu *rvu)
2365 {
2366 int dev, num_devs;
2367 u64 cfg;
2368 int pf;
2369
2370 /* Enable FLR for all PFs*/
2371 for (pf = 0; pf < rvu->hw->total_pfs; pf++) {
2372 cfg = rvu_read64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf));
2373 rvu_write64(rvu, BLKADDR_RVUM, RVU_PRIV_PFX_CFG(pf),
2374 cfg | BIT_ULL(22));
2375 }
2376
2377 rvu->flr_wq = alloc_workqueue("rvu_afpf_flr",
2378 WQ_UNBOUND | WQ_HIGHPRI | WQ_MEM_RECLAIM,
2379 1);
2380 if (!rvu->flr_wq)
2381 return -ENOMEM;
2382
2383 num_devs = rvu->hw->total_pfs + pci_sriov_get_totalvfs(rvu->pdev);
2384 rvu->flr_wrk = devm_kcalloc(rvu->dev, num_devs,
2385 sizeof(struct rvu_work), GFP_KERNEL);
2386 if (!rvu->flr_wrk) {
2387 destroy_workqueue(rvu->flr_wq);
2388 return -ENOMEM;
2389 }
2390
2391 for (dev = 0; dev < num_devs; dev++) {
2392 rvu->flr_wrk[dev].rvu = rvu;
2393 INIT_WORK(&rvu->flr_wrk[dev].work, rvu_flr_handler);
2394 }
2395
2396 mutex_init(&rvu->flr_lock);
2397
2398 return 0;
2399 }
2400
rvu_disable_afvf_intr(struct rvu * rvu)2401 static void rvu_disable_afvf_intr(struct rvu *rvu)
2402 {
2403 int vfs = rvu->vfs;
2404
2405 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), INTR_MASK(vfs));
2406 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs));
2407 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs));
2408 if (vfs <= 64)
2409 return;
2410
2411 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1),
2412 INTR_MASK(vfs - 64));
2413 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
2414 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64));
2415 }
2416
rvu_enable_afvf_intr(struct rvu * rvu)2417 static void rvu_enable_afvf_intr(struct rvu *rvu)
2418 {
2419 int vfs = rvu->vfs;
2420
2421 /* Clear any pending interrupts and enable AF VF interrupts for
2422 * the first 64 VFs.
2423 */
2424 /* Mbox */
2425 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(0), INTR_MASK(vfs));
2426 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(vfs));
2427
2428 /* FLR */
2429 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(0), INTR_MASK(vfs));
2430 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(vfs));
2431 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(vfs));
2432
2433 /* Same for remaining VFs, if any. */
2434 if (vfs <= 64)
2435 return;
2436
2437 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INTX(1), INTR_MASK(vfs - 64));
2438 rvupf_write64(rvu, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1),
2439 INTR_MASK(vfs - 64));
2440
2441 rvupf_write64(rvu, RVU_PF_VFFLR_INTX(1), INTR_MASK(vfs - 64));
2442 rvupf_write64(rvu, RVU_PF_VFFLR_INT_ENA_W1SX(1), INTR_MASK(vfs - 64));
2443 rvupf_write64(rvu, RVU_PF_VFME_INT_ENA_W1SX(1), INTR_MASK(vfs - 64));
2444 }
2445
2446 #define PCI_DEVID_OCTEONTX2_LBK 0xA061
2447
lbk_get_num_chans(void)2448 static int lbk_get_num_chans(void)
2449 {
2450 struct pci_dev *pdev;
2451 void __iomem *base;
2452 int ret = -EIO;
2453
2454 pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_LBK,
2455 NULL);
2456 if (!pdev)
2457 goto err;
2458
2459 base = pci_ioremap_bar(pdev, 0);
2460 if (!base)
2461 goto err_put;
2462
2463 /* Read number of available LBK channels from LBK(0)_CONST register. */
2464 ret = (readq(base + 0x10) >> 32) & 0xffff;
2465 iounmap(base);
2466 err_put:
2467 pci_dev_put(pdev);
2468 err:
2469 return ret;
2470 }
2471
rvu_enable_sriov(struct rvu * rvu)2472 static int rvu_enable_sriov(struct rvu *rvu)
2473 {
2474 struct pci_dev *pdev = rvu->pdev;
2475 int err, chans, vfs;
2476
2477 if (!rvu_afvf_msix_vectors_num_ok(rvu)) {
2478 dev_warn(&pdev->dev,
2479 "Skipping SRIOV enablement since not enough IRQs are available\n");
2480 return 0;
2481 }
2482
2483 chans = lbk_get_num_chans();
2484 if (chans < 0)
2485 return chans;
2486
2487 vfs = pci_sriov_get_totalvfs(pdev);
2488
2489 /* Limit VFs in case we have more VFs than LBK channels available. */
2490 if (vfs > chans)
2491 vfs = chans;
2492
2493 if (!vfs)
2494 return 0;
2495
2496 /* Save VFs number for reference in VF interrupts handlers.
2497 * Since interrupts might start arriving during SRIOV enablement
2498 * ordinary API cannot be used to get number of enabled VFs.
2499 */
2500 rvu->vfs = vfs;
2501
2502 err = rvu_mbox_init(rvu, &rvu->afvf_wq_info, TYPE_AFVF, vfs,
2503 rvu_afvf_mbox_handler, rvu_afvf_mbox_up_handler);
2504 if (err)
2505 return err;
2506
2507 rvu_enable_afvf_intr(rvu);
2508 /* Make sure IRQs are enabled before SRIOV. */
2509 mb();
2510
2511 err = pci_enable_sriov(pdev, vfs);
2512 if (err) {
2513 rvu_disable_afvf_intr(rvu);
2514 rvu_mbox_destroy(&rvu->afvf_wq_info);
2515 return err;
2516 }
2517
2518 return 0;
2519 }
2520
rvu_disable_sriov(struct rvu * rvu)2521 static void rvu_disable_sriov(struct rvu *rvu)
2522 {
2523 rvu_disable_afvf_intr(rvu);
2524 rvu_mbox_destroy(&rvu->afvf_wq_info);
2525 pci_disable_sriov(rvu->pdev);
2526 }
2527
rvu_update_module_params(struct rvu * rvu)2528 static void rvu_update_module_params(struct rvu *rvu)
2529 {
2530 const char *default_pfl_name = "default";
2531
2532 strscpy(rvu->mkex_pfl_name,
2533 mkex_profile ? mkex_profile : default_pfl_name, MKEX_NAME_LEN);
2534 }
2535
rvu_probe(struct pci_dev * pdev,const struct pci_device_id * id)2536 static int rvu_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2537 {
2538 struct device *dev = &pdev->dev;
2539 struct rvu *rvu;
2540 int err;
2541
2542 rvu = devm_kzalloc(dev, sizeof(*rvu), GFP_KERNEL);
2543 if (!rvu)
2544 return -ENOMEM;
2545
2546 rvu->hw = devm_kzalloc(dev, sizeof(struct rvu_hwinfo), GFP_KERNEL);
2547 if (!rvu->hw) {
2548 devm_kfree(dev, rvu);
2549 return -ENOMEM;
2550 }
2551
2552 pci_set_drvdata(pdev, rvu);
2553 rvu->pdev = pdev;
2554 rvu->dev = &pdev->dev;
2555
2556 err = pci_enable_device(pdev);
2557 if (err) {
2558 dev_err(dev, "Failed to enable PCI device\n");
2559 goto err_freemem;
2560 }
2561
2562 err = pci_request_regions(pdev, DRV_NAME);
2563 if (err) {
2564 dev_err(dev, "PCI request regions failed 0x%x\n", err);
2565 goto err_disable_device;
2566 }
2567
2568 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48));
2569 if (err) {
2570 dev_err(dev, "DMA mask config failed, abort\n");
2571 goto err_release_regions;
2572 }
2573
2574 pci_set_master(pdev);
2575
2576 rvu->ptp = ptp_get();
2577 if (IS_ERR(rvu->ptp)) {
2578 err = PTR_ERR(rvu->ptp);
2579 if (err == -EPROBE_DEFER)
2580 goto err_release_regions;
2581 rvu->ptp = NULL;
2582 }
2583
2584 /* Map Admin function CSRs */
2585 rvu->afreg_base = pcim_iomap(pdev, PCI_AF_REG_BAR_NUM, 0);
2586 rvu->pfreg_base = pcim_iomap(pdev, PCI_PF_REG_BAR_NUM, 0);
2587 if (!rvu->afreg_base || !rvu->pfreg_base) {
2588 dev_err(dev, "Unable to map admin function CSRs, aborting\n");
2589 err = -ENOMEM;
2590 goto err_put_ptp;
2591 }
2592
2593 /* Store module params in rvu structure */
2594 rvu_update_module_params(rvu);
2595
2596 /* Check which blocks the HW supports */
2597 rvu_check_block_implemented(rvu);
2598
2599 rvu_reset_all_blocks(rvu);
2600
2601 rvu_setup_hw_capabilities(rvu);
2602
2603 err = rvu_setup_hw_resources(rvu);
2604 if (err)
2605 goto err_put_ptp;
2606
2607 /* Init mailbox btw AF and PFs */
2608 err = rvu_mbox_init(rvu, &rvu->afpf_wq_info, TYPE_AFPF,
2609 rvu->hw->total_pfs, rvu_afpf_mbox_handler,
2610 rvu_afpf_mbox_up_handler);
2611 if (err)
2612 goto err_hwsetup;
2613
2614 err = rvu_flr_init(rvu);
2615 if (err)
2616 goto err_mbox;
2617
2618 err = rvu_register_interrupts(rvu);
2619 if (err)
2620 goto err_flr;
2621
2622 rvu_setup_rvum_blk_revid(rvu);
2623
2624 /* Enable AF's VFs (if any) */
2625 err = rvu_enable_sriov(rvu);
2626 if (err)
2627 goto err_irq;
2628
2629 /* Initialize debugfs */
2630 rvu_dbg_init(rvu);
2631
2632 return 0;
2633 err_irq:
2634 rvu_unregister_interrupts(rvu);
2635 err_flr:
2636 rvu_flr_wq_destroy(rvu);
2637 err_mbox:
2638 rvu_mbox_destroy(&rvu->afpf_wq_info);
2639 err_hwsetup:
2640 rvu_cgx_exit(rvu);
2641 rvu_fwdata_exit(rvu);
2642 rvu_reset_all_blocks(rvu);
2643 rvu_free_hw_resources(rvu);
2644 rvu_clear_rvum_blk_revid(rvu);
2645 err_put_ptp:
2646 ptp_put(rvu->ptp);
2647 err_release_regions:
2648 pci_release_regions(pdev);
2649 err_disable_device:
2650 pci_disable_device(pdev);
2651 err_freemem:
2652 pci_set_drvdata(pdev, NULL);
2653 devm_kfree(&pdev->dev, rvu->hw);
2654 devm_kfree(dev, rvu);
2655 return err;
2656 }
2657
rvu_remove(struct pci_dev * pdev)2658 static void rvu_remove(struct pci_dev *pdev)
2659 {
2660 struct rvu *rvu = pci_get_drvdata(pdev);
2661
2662 rvu_dbg_exit(rvu);
2663 rvu_unregister_interrupts(rvu);
2664 rvu_flr_wq_destroy(rvu);
2665 rvu_cgx_exit(rvu);
2666 rvu_fwdata_exit(rvu);
2667 rvu_mbox_destroy(&rvu->afpf_wq_info);
2668 rvu_disable_sriov(rvu);
2669 rvu_reset_all_blocks(rvu);
2670 rvu_free_hw_resources(rvu);
2671 rvu_clear_rvum_blk_revid(rvu);
2672 ptp_put(rvu->ptp);
2673 pci_release_regions(pdev);
2674 pci_disable_device(pdev);
2675 pci_set_drvdata(pdev, NULL);
2676
2677 devm_kfree(&pdev->dev, rvu->hw);
2678 devm_kfree(&pdev->dev, rvu);
2679 }
2680
2681 static struct pci_driver rvu_driver = {
2682 .name = DRV_NAME,
2683 .id_table = rvu_id_table,
2684 .probe = rvu_probe,
2685 .remove = rvu_remove,
2686 };
2687
rvu_init_module(void)2688 static int __init rvu_init_module(void)
2689 {
2690 int err;
2691
2692 pr_info("%s: %s\n", DRV_NAME, DRV_STRING);
2693
2694 err = pci_register_driver(&cgx_driver);
2695 if (err < 0)
2696 return err;
2697
2698 err = pci_register_driver(&ptp_driver);
2699 if (err < 0)
2700 goto ptp_err;
2701
2702 err = pci_register_driver(&rvu_driver);
2703 if (err < 0)
2704 goto rvu_err;
2705
2706 return 0;
2707 rvu_err:
2708 pci_unregister_driver(&ptp_driver);
2709 ptp_err:
2710 pci_unregister_driver(&cgx_driver);
2711
2712 return err;
2713 }
2714
rvu_cleanup_module(void)2715 static void __exit rvu_cleanup_module(void)
2716 {
2717 pci_unregister_driver(&rvu_driver);
2718 pci_unregister_driver(&ptp_driver);
2719 pci_unregister_driver(&cgx_driver);
2720 }
2721
2722 module_init(rvu_init_module);
2723 module_exit(rvu_cleanup_module);
2724
