1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Renesas R-Car VIN
4 *
5 * Copyright (C) 2016 Renesas Electronics Corp.
6 * Copyright (C) 2011-2013 Renesas Solutions Corp.
7 * Copyright (C) 2013 Cogent Embedded, Inc., <source@cogentembedded.com>
8 * Copyright (C) 2008 Magnus Damm
9 *
10 * Based on the soc-camera rcar_vin driver
11 */
12
13 #include <linux/delay.h>
14 #include <linux/interrupt.h>
15 #include <linux/pm_runtime.h>
16
17 #include <media/videobuf2-dma-contig.h>
18
19 #include "rcar-vin.h"
20
21 /* -----------------------------------------------------------------------------
22 * HW Functions
23 */
24
25 /* Register offsets for R-Car VIN */
26 #define VNMC_REG 0x00 /* Video n Main Control Register */
27 #define VNMS_REG 0x04 /* Video n Module Status Register */
28 #define VNFC_REG 0x08 /* Video n Frame Capture Register */
29 #define VNSLPRC_REG 0x0C /* Video n Start Line Pre-Clip Register */
30 #define VNELPRC_REG 0x10 /* Video n End Line Pre-Clip Register */
31 #define VNSPPRC_REG 0x14 /* Video n Start Pixel Pre-Clip Register */
32 #define VNEPPRC_REG 0x18 /* Video n End Pixel Pre-Clip Register */
33 #define VNIS_REG 0x2C /* Video n Image Stride Register */
34 #define VNMB_REG(m) (0x30 + ((m) << 2)) /* Video n Memory Base m Register */
35 #define VNIE_REG 0x40 /* Video n Interrupt Enable Register */
36 #define VNINTS_REG 0x44 /* Video n Interrupt Status Register */
37 #define VNSI_REG 0x48 /* Video n Scanline Interrupt Register */
38 #define VNMTC_REG 0x4C /* Video n Memory Transfer Control Register */
39 #define VNDMR_REG 0x58 /* Video n Data Mode Register */
40 #define VNDMR2_REG 0x5C /* Video n Data Mode Register 2 */
41 #define VNUVAOF_REG 0x60 /* Video n UV Address Offset Register */
42
43 /* Register offsets specific for Gen2 */
44 #define VNSLPOC_REG 0x1C /* Video n Start Line Post-Clip Register */
45 #define VNELPOC_REG 0x20 /* Video n End Line Post-Clip Register */
46 #define VNSPPOC_REG 0x24 /* Video n Start Pixel Post-Clip Register */
47 #define VNEPPOC_REG 0x28 /* Video n End Pixel Post-Clip Register */
48 #define VNYS_REG 0x50 /* Video n Y Scale Register */
49 #define VNXS_REG 0x54 /* Video n X Scale Register */
50 #define VNC1A_REG 0x80 /* Video n Coefficient Set C1A Register */
51 #define VNC1B_REG 0x84 /* Video n Coefficient Set C1B Register */
52 #define VNC1C_REG 0x88 /* Video n Coefficient Set C1C Register */
53 #define VNC2A_REG 0x90 /* Video n Coefficient Set C2A Register */
54 #define VNC2B_REG 0x94 /* Video n Coefficient Set C2B Register */
55 #define VNC2C_REG 0x98 /* Video n Coefficient Set C2C Register */
56 #define VNC3A_REG 0xA0 /* Video n Coefficient Set C3A Register */
57 #define VNC3B_REG 0xA4 /* Video n Coefficient Set C3B Register */
58 #define VNC3C_REG 0xA8 /* Video n Coefficient Set C3C Register */
59 #define VNC4A_REG 0xB0 /* Video n Coefficient Set C4A Register */
60 #define VNC4B_REG 0xB4 /* Video n Coefficient Set C4B Register */
61 #define VNC4C_REG 0xB8 /* Video n Coefficient Set C4C Register */
62 #define VNC5A_REG 0xC0 /* Video n Coefficient Set C5A Register */
63 #define VNC5B_REG 0xC4 /* Video n Coefficient Set C5B Register */
64 #define VNC5C_REG 0xC8 /* Video n Coefficient Set C5C Register */
65 #define VNC6A_REG 0xD0 /* Video n Coefficient Set C6A Register */
66 #define VNC6B_REG 0xD4 /* Video n Coefficient Set C6B Register */
67 #define VNC6C_REG 0xD8 /* Video n Coefficient Set C6C Register */
68 #define VNC7A_REG 0xE0 /* Video n Coefficient Set C7A Register */
69 #define VNC7B_REG 0xE4 /* Video n Coefficient Set C7B Register */
70 #define VNC7C_REG 0xE8 /* Video n Coefficient Set C7C Register */
71 #define VNC8A_REG 0xF0 /* Video n Coefficient Set C8A Register */
72 #define VNC8B_REG 0xF4 /* Video n Coefficient Set C8B Register */
73 #define VNC8C_REG 0xF8 /* Video n Coefficient Set C8C Register */
74
75 /* Register offsets specific for Gen3 */
76 #define VNCSI_IFMD_REG 0x20 /* Video n CSI2 Interface Mode Register */
77
78 /* Register bit fields for R-Car VIN */
79 /* Video n Main Control Register bits */
80 #define VNMC_DPINE (1 << 27) /* Gen3 specific */
81 #define VNMC_SCLE (1 << 26) /* Gen3 specific */
82 #define VNMC_FOC (1 << 21)
83 #define VNMC_YCAL (1 << 19)
84 #define VNMC_INF_YUV8_BT656 (0 << 16)
85 #define VNMC_INF_YUV8_BT601 (1 << 16)
86 #define VNMC_INF_YUV10_BT656 (2 << 16)
87 #define VNMC_INF_YUV10_BT601 (3 << 16)
88 #define VNMC_INF_YUV16 (5 << 16)
89 #define VNMC_INF_RGB888 (6 << 16)
90 #define VNMC_VUP (1 << 10)
91 #define VNMC_IM_ODD (0 << 3)
92 #define VNMC_IM_ODD_EVEN (1 << 3)
93 #define VNMC_IM_EVEN (2 << 3)
94 #define VNMC_IM_FULL (3 << 3)
95 #define VNMC_BPS (1 << 1)
96 #define VNMC_ME (1 << 0)
97
98 /* Video n Module Status Register bits */
99 #define VNMS_FBS_MASK (3 << 3)
100 #define VNMS_FBS_SHIFT 3
101 #define VNMS_FS (1 << 2)
102 #define VNMS_AV (1 << 1)
103 #define VNMS_CA (1 << 0)
104
105 /* Video n Frame Capture Register bits */
106 #define VNFC_C_FRAME (1 << 1)
107 #define VNFC_S_FRAME (1 << 0)
108
109 /* Video n Interrupt Enable Register bits */
110 #define VNIE_FIE (1 << 4)
111 #define VNIE_EFE (1 << 1)
112
113 /* Video n Data Mode Register bits */
114 #define VNDMR_EXRGB (1 << 8)
115 #define VNDMR_BPSM (1 << 4)
116 #define VNDMR_DTMD_YCSEP (1 << 1)
117 #define VNDMR_DTMD_ARGB1555 (1 << 0)
118
119 /* Video n Data Mode Register 2 bits */
120 #define VNDMR2_VPS (1 << 30)
121 #define VNDMR2_HPS (1 << 29)
122 #define VNDMR2_CES (1 << 28)
123 #define VNDMR2_FTEV (1 << 17)
124 #define VNDMR2_VLV(n) ((n & 0xf) << 12)
125
126 /* Video n CSI2 Interface Mode Register (Gen3) */
127 #define VNCSI_IFMD_DES1 (1 << 26)
128 #define VNCSI_IFMD_DES0 (1 << 25)
129 #define VNCSI_IFMD_CSI_CHSEL(n) (((n) & 0xf) << 0)
130 #define VNCSI_IFMD_CSI_CHSEL_MASK 0xf
131
132 struct rvin_buffer {
133 struct vb2_v4l2_buffer vb;
134 struct list_head list;
135 };
136
137 #define to_buf_list(vb2_buffer) (&container_of(vb2_buffer, \
138 struct rvin_buffer, \
139 vb)->list)
140
rvin_write(struct rvin_dev * vin,u32 value,u32 offset)141 static void rvin_write(struct rvin_dev *vin, u32 value, u32 offset)
142 {
143 iowrite32(value, vin->base + offset);
144 }
145
rvin_read(struct rvin_dev * vin,u32 offset)146 static u32 rvin_read(struct rvin_dev *vin, u32 offset)
147 {
148 return ioread32(vin->base + offset);
149 }
150
151 /* -----------------------------------------------------------------------------
152 * Crop and Scaling Gen2
153 */
154
155 struct vin_coeff {
156 unsigned short xs_value;
157 u32 coeff_set[24];
158 };
159
160 static const struct vin_coeff vin_coeff_set[] = {
161 { 0x0000, {
162 0x00000000, 0x00000000, 0x00000000,
163 0x00000000, 0x00000000, 0x00000000,
164 0x00000000, 0x00000000, 0x00000000,
165 0x00000000, 0x00000000, 0x00000000,
166 0x00000000, 0x00000000, 0x00000000,
167 0x00000000, 0x00000000, 0x00000000,
168 0x00000000, 0x00000000, 0x00000000,
169 0x00000000, 0x00000000, 0x00000000 },
170 },
171 { 0x1000, {
172 0x000fa400, 0x000fa400, 0x09625902,
173 0x000003f8, 0x00000403, 0x3de0d9f0,
174 0x001fffed, 0x00000804, 0x3cc1f9c3,
175 0x001003de, 0x00000c01, 0x3cb34d7f,
176 0x002003d2, 0x00000c00, 0x3d24a92d,
177 0x00200bca, 0x00000bff, 0x3df600d2,
178 0x002013cc, 0x000007ff, 0x3ed70c7e,
179 0x00100fde, 0x00000000, 0x3f87c036 },
180 },
181 { 0x1200, {
182 0x002ffff1, 0x002ffff1, 0x02a0a9c8,
183 0x002003e7, 0x001ffffa, 0x000185bc,
184 0x002007dc, 0x000003ff, 0x3e52859c,
185 0x00200bd4, 0x00000002, 0x3d53996b,
186 0x00100fd0, 0x00000403, 0x3d04ad2d,
187 0x00000bd5, 0x00000403, 0x3d35ace7,
188 0x3ff003e4, 0x00000801, 0x3dc674a1,
189 0x3fffe800, 0x00000800, 0x3e76f461 },
190 },
191 { 0x1400, {
192 0x00100be3, 0x00100be3, 0x04d1359a,
193 0x00000fdb, 0x002003ed, 0x0211fd93,
194 0x00000fd6, 0x002003f4, 0x0002d97b,
195 0x000007d6, 0x002ffffb, 0x3e93b956,
196 0x3ff003da, 0x001003ff, 0x3db49926,
197 0x3fffefe9, 0x00100001, 0x3d655cee,
198 0x3fffd400, 0x00000003, 0x3d65f4b6,
199 0x000fb421, 0x00000402, 0x3dc6547e },
200 },
201 { 0x1600, {
202 0x00000bdd, 0x00000bdd, 0x06519578,
203 0x3ff007da, 0x00000be3, 0x03c24973,
204 0x3ff003d9, 0x00000be9, 0x01b30d5f,
205 0x3ffff7df, 0x001003f1, 0x0003c542,
206 0x000fdfec, 0x001003f7, 0x3ec4711d,
207 0x000fc400, 0x002ffffd, 0x3df504f1,
208 0x001fa81a, 0x002ffc00, 0x3d957cc2,
209 0x002f8c3c, 0x00100000, 0x3db5c891 },
210 },
211 { 0x1800, {
212 0x3ff003dc, 0x3ff003dc, 0x0791e558,
213 0x000ff7dd, 0x3ff007de, 0x05328554,
214 0x000fe7e3, 0x3ff00be2, 0x03232546,
215 0x000fd7ee, 0x000007e9, 0x0143bd30,
216 0x001fb800, 0x000007ee, 0x00044511,
217 0x002fa015, 0x000007f4, 0x3ef4bcee,
218 0x002f8832, 0x001003f9, 0x3e4514c7,
219 0x001f7853, 0x001003fd, 0x3de54c9f },
220 },
221 { 0x1a00, {
222 0x000fefe0, 0x000fefe0, 0x08721d3c,
223 0x001fdbe7, 0x000ffbde, 0x0652a139,
224 0x001fcbf0, 0x000003df, 0x0463292e,
225 0x002fb3ff, 0x3ff007e3, 0x0293a91d,
226 0x002f9c12, 0x3ff00be7, 0x01241905,
227 0x001f8c29, 0x000007ed, 0x3fe470eb,
228 0x000f7c46, 0x000007f2, 0x3f04b8ca,
229 0x3fef7865, 0x000007f6, 0x3e74e4a8 },
230 },
231 { 0x1c00, {
232 0x001fd3e9, 0x001fd3e9, 0x08f23d26,
233 0x002fbff3, 0x001fe3e4, 0x0712ad23,
234 0x002fa800, 0x000ff3e0, 0x05631d1b,
235 0x001f9810, 0x000ffbe1, 0x03b3890d,
236 0x000f8c23, 0x000003e3, 0x0233e8fa,
237 0x3fef843b, 0x000003e7, 0x00f430e4,
238 0x3fbf8456, 0x3ff00bea, 0x00046cc8,
239 0x3f8f8c72, 0x3ff00bef, 0x3f3490ac },
240 },
241 { 0x1e00, {
242 0x001fbbf4, 0x001fbbf4, 0x09425112,
243 0x001fa800, 0x002fc7ed, 0x0792b110,
244 0x000f980e, 0x001fdbe6, 0x0613110a,
245 0x3fff8c20, 0x001fe7e3, 0x04a368fd,
246 0x3fcf8c33, 0x000ff7e2, 0x0343b8ed,
247 0x3f9f8c4a, 0x000fffe3, 0x0203f8da,
248 0x3f5f9c61, 0x000003e6, 0x00e428c5,
249 0x3f1fb07b, 0x000003eb, 0x3fe440af },
250 },
251 { 0x2000, {
252 0x000fa400, 0x000fa400, 0x09625902,
253 0x3fff980c, 0x001fb7f5, 0x0812b0ff,
254 0x3fdf901c, 0x001fc7ed, 0x06b2fcfa,
255 0x3faf902d, 0x001fd3e8, 0x055348f1,
256 0x3f7f983f, 0x001fe3e5, 0x04038ce3,
257 0x3f3fa454, 0x001fefe3, 0x02e3c8d1,
258 0x3f0fb86a, 0x001ff7e4, 0x01c3e8c0,
259 0x3ecfd880, 0x000fffe6, 0x00c404ac },
260 },
261 { 0x2200, {
262 0x3fdf9c0b, 0x3fdf9c0b, 0x09725cf4,
263 0x3fbf9818, 0x3fffa400, 0x0842a8f1,
264 0x3f8f9827, 0x000fb3f7, 0x0702f0ec,
265 0x3f5fa037, 0x000fc3ef, 0x05d330e4,
266 0x3f2fac49, 0x001fcfea, 0x04a364d9,
267 0x3effc05c, 0x001fdbe7, 0x038394ca,
268 0x3ecfdc6f, 0x001fe7e6, 0x0273b0bb,
269 0x3ea00083, 0x001fefe6, 0x0183c0a9 },
270 },
271 { 0x2400, {
272 0x3f9fa014, 0x3f9fa014, 0x098260e6,
273 0x3f7f9c23, 0x3fcf9c0a, 0x08629ce5,
274 0x3f4fa431, 0x3fefa400, 0x0742d8e1,
275 0x3f1fb440, 0x3fffb3f8, 0x062310d9,
276 0x3eefc850, 0x000fbbf2, 0x050340d0,
277 0x3ecfe062, 0x000fcbec, 0x041364c2,
278 0x3ea00073, 0x001fd3ea, 0x03037cb5,
279 0x3e902086, 0x001fdfe8, 0x022388a5 },
280 },
281 { 0x2600, {
282 0x3f5fa81e, 0x3f5fa81e, 0x096258da,
283 0x3f3fac2b, 0x3f8fa412, 0x088290d8,
284 0x3f0fbc38, 0x3fafa408, 0x0772c8d5,
285 0x3eefcc47, 0x3fcfa800, 0x0672f4ce,
286 0x3ecfe456, 0x3fefaffa, 0x05531cc6,
287 0x3eb00066, 0x3fffbbf3, 0x047334bb,
288 0x3ea01c77, 0x000fc7ee, 0x039348ae,
289 0x3ea04486, 0x000fd3eb, 0x02b350a1 },
290 },
291 { 0x2800, {
292 0x3f2fb426, 0x3f2fb426, 0x094250ce,
293 0x3f0fc032, 0x3f4fac1b, 0x086284cd,
294 0x3eefd040, 0x3f7fa811, 0x0782acc9,
295 0x3ecfe84c, 0x3f9fa807, 0x06a2d8c4,
296 0x3eb0005b, 0x3fbfac00, 0x05b2f4bc,
297 0x3eb0186a, 0x3fdfb3fa, 0x04c308b4,
298 0x3eb04077, 0x3fefbbf4, 0x03f31ca8,
299 0x3ec06884, 0x000fbff2, 0x03031c9e },
300 },
301 { 0x2a00, {
302 0x3f0fc42d, 0x3f0fc42d, 0x090240c4,
303 0x3eefd439, 0x3f2fb822, 0x08526cc2,
304 0x3edfe845, 0x3f4fb018, 0x078294bf,
305 0x3ec00051, 0x3f6fac0f, 0x06b2b4bb,
306 0x3ec0185f, 0x3f8fac07, 0x05e2ccb4,
307 0x3ec0386b, 0x3fafac00, 0x0502e8ac,
308 0x3ed05c77, 0x3fcfb3fb, 0x0432f0a3,
309 0x3ef08482, 0x3fdfbbf6, 0x0372f898 },
310 },
311 { 0x2c00, {
312 0x3eefdc31, 0x3eefdc31, 0x08e238b8,
313 0x3edfec3d, 0x3f0fc828, 0x082258b9,
314 0x3ed00049, 0x3f1fc01e, 0x077278b6,
315 0x3ed01455, 0x3f3fb815, 0x06c294b2,
316 0x3ed03460, 0x3f5fb40d, 0x0602acac,
317 0x3ef0506c, 0x3f7fb006, 0x0542c0a4,
318 0x3f107476, 0x3f9fb400, 0x0472c89d,
319 0x3f309c80, 0x3fbfb7fc, 0x03b2cc94 },
320 },
321 { 0x2e00, {
322 0x3eefec37, 0x3eefec37, 0x088220b0,
323 0x3ee00041, 0x3effdc2d, 0x07f244ae,
324 0x3ee0144c, 0x3f0fd023, 0x07625cad,
325 0x3ef02c57, 0x3f1fc81a, 0x06c274a9,
326 0x3f004861, 0x3f3fbc13, 0x060288a6,
327 0x3f20686b, 0x3f5fb80c, 0x05529c9e,
328 0x3f408c74, 0x3f6fb805, 0x04b2ac96,
329 0x3f80ac7e, 0x3f8fb800, 0x0402ac8e },
330 },
331 { 0x3000, {
332 0x3ef0003a, 0x3ef0003a, 0x084210a6,
333 0x3ef01045, 0x3effec32, 0x07b228a7,
334 0x3f00284e, 0x3f0fdc29, 0x073244a4,
335 0x3f104058, 0x3f0fd420, 0x06a258a2,
336 0x3f305c62, 0x3f2fc818, 0x0612689d,
337 0x3f508069, 0x3f3fc011, 0x05728496,
338 0x3f80a072, 0x3f4fc00a, 0x04d28c90,
339 0x3fc0c07b, 0x3f6fbc04, 0x04429088 },
340 },
341 { 0x3200, {
342 0x3f00103e, 0x3f00103e, 0x07f1fc9e,
343 0x3f102447, 0x3f000035, 0x0782149d,
344 0x3f203c4f, 0x3f0ff02c, 0x07122c9c,
345 0x3f405458, 0x3f0fe424, 0x06924099,
346 0x3f607061, 0x3f1fd41d, 0x06024c97,
347 0x3f909068, 0x3f2fcc16, 0x05726490,
348 0x3fc0b070, 0x3f3fc80f, 0x04f26c8a,
349 0x0000d077, 0x3f4fc409, 0x04627484 },
350 },
351 { 0x3400, {
352 0x3f202040, 0x3f202040, 0x07a1e898,
353 0x3f303449, 0x3f100c38, 0x0741fc98,
354 0x3f504c50, 0x3f10002f, 0x06e21495,
355 0x3f706459, 0x3f1ff028, 0x06722492,
356 0x3fa08060, 0x3f1fe421, 0x05f2348f,
357 0x3fd09c67, 0x3f1fdc19, 0x05824c89,
358 0x0000bc6e, 0x3f2fd014, 0x04f25086,
359 0x0040dc74, 0x3f3fcc0d, 0x04825c7f },
360 },
361 { 0x3600, {
362 0x3f403042, 0x3f403042, 0x0761d890,
363 0x3f504848, 0x3f301c3b, 0x0701f090,
364 0x3f805c50, 0x3f200c33, 0x06a2008f,
365 0x3fa07458, 0x3f10002b, 0x06520c8d,
366 0x3fd0905e, 0x3f1ff424, 0x05e22089,
367 0x0000ac65, 0x3f1fe81d, 0x05823483,
368 0x0030cc6a, 0x3f2fdc18, 0x04f23c81,
369 0x0080e871, 0x3f2fd412, 0x0482407c },
370 },
371 { 0x3800, {
372 0x3f604043, 0x3f604043, 0x0721c88a,
373 0x3f80544a, 0x3f502c3c, 0x06d1d88a,
374 0x3fb06851, 0x3f301c35, 0x0681e889,
375 0x3fd08456, 0x3f30082f, 0x0611fc88,
376 0x00009c5d, 0x3f200027, 0x05d20884,
377 0x0030b863, 0x3f2ff421, 0x05621880,
378 0x0070d468, 0x3f2fe81b, 0x0502247c,
379 0x00c0ec6f, 0x3f2fe015, 0x04a22877 },
380 },
381 { 0x3a00, {
382 0x3f904c44, 0x3f904c44, 0x06e1b884,
383 0x3fb0604a, 0x3f70383e, 0x0691c885,
384 0x3fe07451, 0x3f502c36, 0x0661d483,
385 0x00009055, 0x3f401831, 0x0601ec81,
386 0x0030a85b, 0x3f300c2a, 0x05b1f480,
387 0x0070c061, 0x3f300024, 0x0562047a,
388 0x00b0d867, 0x3f3ff41e, 0x05020c77,
389 0x00f0f46b, 0x3f2fec19, 0x04a21474 },
390 },
391 { 0x3c00, {
392 0x3fb05c43, 0x3fb05c43, 0x06c1b07e,
393 0x3fe06c4b, 0x3f902c3f, 0x0681c081,
394 0x0000844f, 0x3f703838, 0x0631cc7d,
395 0x00309855, 0x3f602433, 0x05d1d47e,
396 0x0060b459, 0x3f50142e, 0x0581e47b,
397 0x00a0c85f, 0x3f400828, 0x0531f078,
398 0x00e0e064, 0x3f300021, 0x0501fc73,
399 0x00b0fc6a, 0x3f3ff41d, 0x04a20873 },
400 },
401 { 0x3e00, {
402 0x3fe06444, 0x3fe06444, 0x0681a07a,
403 0x00007849, 0x3fc0503f, 0x0641b07a,
404 0x0020904d, 0x3fa0403a, 0x05f1c07a,
405 0x0060a453, 0x3f803034, 0x05c1c878,
406 0x0090b858, 0x3f70202f, 0x0571d477,
407 0x00d0d05d, 0x3f501829, 0x0531e073,
408 0x0110e462, 0x3f500825, 0x04e1e471,
409 0x01510065, 0x3f40001f, 0x04a1f06d },
410 },
411 { 0x4000, {
412 0x00007044, 0x00007044, 0x06519476,
413 0x00208448, 0x3fe05c3f, 0x0621a476,
414 0x0050984d, 0x3fc04c3a, 0x05e1b075,
415 0x0080ac52, 0x3fa03c35, 0x05a1b875,
416 0x00c0c056, 0x3f803030, 0x0561c473,
417 0x0100d45b, 0x3f70202b, 0x0521d46f,
418 0x0140e860, 0x3f601427, 0x04d1d46e,
419 0x01810064, 0x3f500822, 0x0491dc6b },
420 },
421 { 0x5000, {
422 0x0110a442, 0x0110a442, 0x0551545e,
423 0x0140b045, 0x00e0983f, 0x0531585f,
424 0x0160c047, 0x00c08c3c, 0x0511645e,
425 0x0190cc4a, 0x00908039, 0x04f1685f,
426 0x01c0dc4c, 0x00707436, 0x04d1705e,
427 0x0200e850, 0x00506833, 0x04b1785b,
428 0x0230f453, 0x00305c30, 0x0491805a,
429 0x02710056, 0x0010542d, 0x04718059 },
430 },
431 { 0x6000, {
432 0x01c0bc40, 0x01c0bc40, 0x04c13052,
433 0x01e0c841, 0x01a0b43d, 0x04c13851,
434 0x0210cc44, 0x0180a83c, 0x04a13453,
435 0x0230d845, 0x0160a03a, 0x04913c52,
436 0x0260e047, 0x01409838, 0x04714052,
437 0x0280ec49, 0x01208c37, 0x04514c50,
438 0x02b0f44b, 0x01008435, 0x04414c50,
439 0x02d1004c, 0x00e07c33, 0x0431544f },
440 },
441 { 0x7000, {
442 0x0230c83e, 0x0230c83e, 0x04711c4c,
443 0x0250d03f, 0x0210c43c, 0x0471204b,
444 0x0270d840, 0x0200b83c, 0x0451244b,
445 0x0290dc42, 0x01e0b43a, 0x0441244c,
446 0x02b0e443, 0x01c0b038, 0x0441284b,
447 0x02d0ec44, 0x01b0a438, 0x0421304a,
448 0x02f0f445, 0x0190a036, 0x04213449,
449 0x0310f847, 0x01709c34, 0x04213848 },
450 },
451 { 0x8000, {
452 0x0280d03d, 0x0280d03d, 0x04310c48,
453 0x02a0d43e, 0x0270c83c, 0x04311047,
454 0x02b0dc3e, 0x0250c83a, 0x04311447,
455 0x02d0e040, 0x0240c03a, 0x04211446,
456 0x02e0e840, 0x0220bc39, 0x04111847,
457 0x0300e842, 0x0210b438, 0x04012445,
458 0x0310f043, 0x0200b037, 0x04012045,
459 0x0330f444, 0x01e0ac36, 0x03f12445 },
460 },
461 { 0xefff, {
462 0x0340dc3a, 0x0340dc3a, 0x03b0ec40,
463 0x0340e03a, 0x0330e039, 0x03c0f03e,
464 0x0350e03b, 0x0330dc39, 0x03c0ec3e,
465 0x0350e43a, 0x0320dc38, 0x03c0f43e,
466 0x0360e43b, 0x0320d839, 0x03b0f03e,
467 0x0360e83b, 0x0310d838, 0x03c0fc3b,
468 0x0370e83b, 0x0310d439, 0x03a0f83d,
469 0x0370e83c, 0x0300d438, 0x03b0fc3c },
470 }
471 };
472
rvin_set_coeff(struct rvin_dev * vin,unsigned short xs)473 static void rvin_set_coeff(struct rvin_dev *vin, unsigned short xs)
474 {
475 int i;
476 const struct vin_coeff *p_prev_set = NULL;
477 const struct vin_coeff *p_set = NULL;
478
479 /* Look for suitable coefficient values */
480 for (i = 0; i < ARRAY_SIZE(vin_coeff_set); i++) {
481 p_prev_set = p_set;
482 p_set = &vin_coeff_set[i];
483
484 if (xs < p_set->xs_value)
485 break;
486 }
487
488 /* Use previous value if its XS value is closer */
489 if (p_prev_set && p_set &&
490 xs - p_prev_set->xs_value < p_set->xs_value - xs)
491 p_set = p_prev_set;
492
493 /* Set coefficient registers */
494 rvin_write(vin, p_set->coeff_set[0], VNC1A_REG);
495 rvin_write(vin, p_set->coeff_set[1], VNC1B_REG);
496 rvin_write(vin, p_set->coeff_set[2], VNC1C_REG);
497
498 rvin_write(vin, p_set->coeff_set[3], VNC2A_REG);
499 rvin_write(vin, p_set->coeff_set[4], VNC2B_REG);
500 rvin_write(vin, p_set->coeff_set[5], VNC2C_REG);
501
502 rvin_write(vin, p_set->coeff_set[6], VNC3A_REG);
503 rvin_write(vin, p_set->coeff_set[7], VNC3B_REG);
504 rvin_write(vin, p_set->coeff_set[8], VNC3C_REG);
505
506 rvin_write(vin, p_set->coeff_set[9], VNC4A_REG);
507 rvin_write(vin, p_set->coeff_set[10], VNC4B_REG);
508 rvin_write(vin, p_set->coeff_set[11], VNC4C_REG);
509
510 rvin_write(vin, p_set->coeff_set[12], VNC5A_REG);
511 rvin_write(vin, p_set->coeff_set[13], VNC5B_REG);
512 rvin_write(vin, p_set->coeff_set[14], VNC5C_REG);
513
514 rvin_write(vin, p_set->coeff_set[15], VNC6A_REG);
515 rvin_write(vin, p_set->coeff_set[16], VNC6B_REG);
516 rvin_write(vin, p_set->coeff_set[17], VNC6C_REG);
517
518 rvin_write(vin, p_set->coeff_set[18], VNC7A_REG);
519 rvin_write(vin, p_set->coeff_set[19], VNC7B_REG);
520 rvin_write(vin, p_set->coeff_set[20], VNC7C_REG);
521
522 rvin_write(vin, p_set->coeff_set[21], VNC8A_REG);
523 rvin_write(vin, p_set->coeff_set[22], VNC8B_REG);
524 rvin_write(vin, p_set->coeff_set[23], VNC8C_REG);
525 }
526
rvin_crop_scale_comp_gen2(struct rvin_dev * vin)527 static void rvin_crop_scale_comp_gen2(struct rvin_dev *vin)
528 {
529 u32 xs, ys;
530
531 /* Set scaling coefficient */
532 ys = 0;
533 if (vin->crop.height != vin->compose.height)
534 ys = (4096 * vin->crop.height) / vin->compose.height;
535 rvin_write(vin, ys, VNYS_REG);
536
537 xs = 0;
538 if (vin->crop.width != vin->compose.width)
539 xs = (4096 * vin->crop.width) / vin->compose.width;
540
541 /* Horizontal upscaling is up to double size */
542 if (xs > 0 && xs < 2048)
543 xs = 2048;
544
545 rvin_write(vin, xs, VNXS_REG);
546
547 /* Horizontal upscaling is done out by scaling down from double size */
548 if (xs < 4096)
549 xs *= 2;
550
551 rvin_set_coeff(vin, xs);
552
553 /* Set Start/End Pixel/Line Post-Clip */
554 rvin_write(vin, 0, VNSPPOC_REG);
555 rvin_write(vin, 0, VNSLPOC_REG);
556 rvin_write(vin, vin->format.width - 1, VNEPPOC_REG);
557 switch (vin->format.field) {
558 case V4L2_FIELD_INTERLACED:
559 case V4L2_FIELD_INTERLACED_TB:
560 case V4L2_FIELD_INTERLACED_BT:
561 rvin_write(vin, vin->format.height / 2 - 1, VNELPOC_REG);
562 break;
563 default:
564 rvin_write(vin, vin->format.height - 1, VNELPOC_REG);
565 break;
566 }
567
568 vin_dbg(vin,
569 "Pre-Clip: %ux%u@%u:%u YS: %d XS: %d Post-Clip: %ux%u@%u:%u\n",
570 vin->crop.width, vin->crop.height, vin->crop.left,
571 vin->crop.top, ys, xs, vin->format.width, vin->format.height,
572 0, 0);
573 }
574
rvin_crop_scale_comp(struct rvin_dev * vin)575 void rvin_crop_scale_comp(struct rvin_dev *vin)
576 {
577 /* Set Start/End Pixel/Line Pre-Clip */
578 rvin_write(vin, vin->crop.left, VNSPPRC_REG);
579 rvin_write(vin, vin->crop.left + vin->crop.width - 1, VNEPPRC_REG);
580
581 switch (vin->format.field) {
582 case V4L2_FIELD_INTERLACED:
583 case V4L2_FIELD_INTERLACED_TB:
584 case V4L2_FIELD_INTERLACED_BT:
585 rvin_write(vin, vin->crop.top / 2, VNSLPRC_REG);
586 rvin_write(vin, (vin->crop.top + vin->crop.height) / 2 - 1,
587 VNELPRC_REG);
588 break;
589 default:
590 rvin_write(vin, vin->crop.top, VNSLPRC_REG);
591 rvin_write(vin, vin->crop.top + vin->crop.height - 1,
592 VNELPRC_REG);
593 break;
594 }
595
596 /* TODO: Add support for the UDS scaler. */
597 if (vin->info->model != RCAR_GEN3)
598 rvin_crop_scale_comp_gen2(vin);
599
600 if (vin->format.pixelformat == V4L2_PIX_FMT_NV16)
601 rvin_write(vin, ALIGN(vin->format.width, 0x20), VNIS_REG);
602 else
603 rvin_write(vin, ALIGN(vin->format.width, 0x10), VNIS_REG);
604 }
605
606 /* -----------------------------------------------------------------------------
607 * Hardware setup
608 */
609
rvin_setup(struct rvin_dev * vin)610 static int rvin_setup(struct rvin_dev *vin)
611 {
612 u32 vnmc, dmr, dmr2, interrupts;
613 bool progressive = false, output_is_yuv = false, input_is_yuv = false;
614
615 switch (vin->format.field) {
616 case V4L2_FIELD_TOP:
617 vnmc = VNMC_IM_ODD;
618 break;
619 case V4L2_FIELD_BOTTOM:
620 vnmc = VNMC_IM_EVEN;
621 break;
622 case V4L2_FIELD_INTERLACED:
623 /* Default to TB */
624 vnmc = VNMC_IM_FULL;
625 /* Use BT if video standard can be read and is 60 Hz format */
626 if (!vin->info->use_mc && vin->std & V4L2_STD_525_60)
627 vnmc = VNMC_IM_FULL | VNMC_FOC;
628 break;
629 case V4L2_FIELD_INTERLACED_TB:
630 vnmc = VNMC_IM_FULL;
631 break;
632 case V4L2_FIELD_INTERLACED_BT:
633 vnmc = VNMC_IM_FULL | VNMC_FOC;
634 break;
635 case V4L2_FIELD_NONE:
636 vnmc = VNMC_IM_ODD_EVEN;
637 progressive = true;
638 break;
639 default:
640 vnmc = VNMC_IM_ODD;
641 break;
642 }
643
644 /*
645 * Input interface
646 */
647 switch (vin->mbus_code) {
648 case MEDIA_BUS_FMT_YUYV8_1X16:
649 /* BT.601/BT.1358 16bit YCbCr422 */
650 vnmc |= VNMC_INF_YUV16;
651 input_is_yuv = true;
652 break;
653 case MEDIA_BUS_FMT_UYVY8_1X16:
654 vnmc |= VNMC_INF_YUV16 | VNMC_YCAL;
655 input_is_yuv = true;
656 break;
657 case MEDIA_BUS_FMT_UYVY8_2X8:
658 /* BT.656 8bit YCbCr422 or BT.601 8bit YCbCr422 */
659 if (!vin->is_csi &&
660 vin->parallel->mbus_type == V4L2_MBUS_BT656)
661 vnmc |= VNMC_INF_YUV8_BT656;
662 else
663 vnmc |= VNMC_INF_YUV8_BT601;
664
665 input_is_yuv = true;
666 break;
667 case MEDIA_BUS_FMT_RGB888_1X24:
668 vnmc |= VNMC_INF_RGB888;
669 break;
670 case MEDIA_BUS_FMT_UYVY10_2X10:
671 /* BT.656 10bit YCbCr422 or BT.601 10bit YCbCr422 */
672 if (!vin->is_csi &&
673 vin->parallel->mbus_type == V4L2_MBUS_BT656)
674 vnmc |= VNMC_INF_YUV10_BT656;
675 else
676 vnmc |= VNMC_INF_YUV10_BT601;
677
678 input_is_yuv = true;
679 break;
680 default:
681 break;
682 }
683
684 /* Enable VSYNC Field Toogle mode after one VSYNC input */
685 if (vin->info->model == RCAR_GEN3)
686 dmr2 = VNDMR2_FTEV;
687 else
688 dmr2 = VNDMR2_FTEV | VNDMR2_VLV(1);
689
690 if (!vin->is_csi) {
691 /* Hsync Signal Polarity Select */
692 if (!(vin->parallel->mbus_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW))
693 dmr2 |= VNDMR2_HPS;
694
695 /* Vsync Signal Polarity Select */
696 if (!(vin->parallel->mbus_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW))
697 dmr2 |= VNDMR2_VPS;
698
699 /* Data Enable Polarity Select */
700 if (vin->parallel->mbus_flags & V4L2_MBUS_DATA_ENABLE_LOW)
701 dmr2 |= VNDMR2_CES;
702 }
703
704 /*
705 * Output format
706 */
707 switch (vin->format.pixelformat) {
708 case V4L2_PIX_FMT_NV16:
709 rvin_write(vin,
710 ALIGN(vin->format.width * vin->format.height, 0x80),
711 VNUVAOF_REG);
712 dmr = VNDMR_DTMD_YCSEP;
713 output_is_yuv = true;
714 break;
715 case V4L2_PIX_FMT_YUYV:
716 dmr = VNDMR_BPSM;
717 output_is_yuv = true;
718 break;
719 case V4L2_PIX_FMT_UYVY:
720 dmr = 0;
721 output_is_yuv = true;
722 break;
723 case V4L2_PIX_FMT_XRGB555:
724 dmr = VNDMR_DTMD_ARGB1555;
725 break;
726 case V4L2_PIX_FMT_RGB565:
727 dmr = 0;
728 break;
729 case V4L2_PIX_FMT_XBGR32:
730 /* Note: not supported on M1 */
731 dmr = VNDMR_EXRGB;
732 break;
733 default:
734 vin_err(vin, "Invalid pixelformat (0x%x)\n",
735 vin->format.pixelformat);
736 return -EINVAL;
737 }
738
739 /* Always update on field change */
740 vnmc |= VNMC_VUP;
741
742 /* If input and output use the same colorspace, use bypass mode */
743 if (input_is_yuv == output_is_yuv)
744 vnmc |= VNMC_BPS;
745
746 if (vin->info->model == RCAR_GEN3) {
747 /* Select between CSI-2 and parallel input */
748 if (vin->is_csi)
749 vnmc &= ~VNMC_DPINE;
750 else
751 vnmc |= VNMC_DPINE;
752 }
753
754 /* Progressive or interlaced mode */
755 interrupts = progressive ? VNIE_FIE : VNIE_EFE;
756
757 /* Ack interrupts */
758 rvin_write(vin, interrupts, VNINTS_REG);
759 /* Enable interrupts */
760 rvin_write(vin, interrupts, VNIE_REG);
761 /* Start capturing */
762 rvin_write(vin, dmr, VNDMR_REG);
763 rvin_write(vin, dmr2, VNDMR2_REG);
764
765 /* Enable module */
766 rvin_write(vin, vnmc | VNMC_ME, VNMC_REG);
767
768 return 0;
769 }
770
rvin_disable_interrupts(struct rvin_dev * vin)771 static void rvin_disable_interrupts(struct rvin_dev *vin)
772 {
773 rvin_write(vin, 0, VNIE_REG);
774 }
775
rvin_get_interrupt_status(struct rvin_dev * vin)776 static u32 rvin_get_interrupt_status(struct rvin_dev *vin)
777 {
778 return rvin_read(vin, VNINTS_REG);
779 }
780
rvin_ack_interrupt(struct rvin_dev * vin)781 static void rvin_ack_interrupt(struct rvin_dev *vin)
782 {
783 rvin_write(vin, rvin_read(vin, VNINTS_REG), VNINTS_REG);
784 }
785
rvin_capture_active(struct rvin_dev * vin)786 static bool rvin_capture_active(struct rvin_dev *vin)
787 {
788 return rvin_read(vin, VNMS_REG) & VNMS_CA;
789 }
790
rvin_set_slot_addr(struct rvin_dev * vin,int slot,dma_addr_t addr)791 static void rvin_set_slot_addr(struct rvin_dev *vin, int slot, dma_addr_t addr)
792 {
793 const struct rvin_video_format *fmt;
794 int offsetx, offsety;
795 dma_addr_t offset;
796
797 fmt = rvin_format_from_pixel(vin->format.pixelformat);
798
799 /*
800 * There is no HW support for composition do the beast we can
801 * by modifying the buffer offset
802 */
803 offsetx = vin->compose.left * fmt->bpp;
804 offsety = vin->compose.top * vin->format.bytesperline;
805 offset = addr + offsetx + offsety;
806
807 /*
808 * The address needs to be 128 bytes aligned. Driver should never accept
809 * settings that do not satisfy this in the first place...
810 */
811 if (WARN_ON((offsetx | offsety | offset) & HW_BUFFER_MASK))
812 return;
813
814 rvin_write(vin, offset, VNMB_REG(slot));
815 }
816
817 /*
818 * Moves a buffer from the queue to the HW slot. If no buffer is
819 * available use the scratch buffer. The scratch buffer is never
820 * returned to userspace, its only function is to enable the capture
821 * loop to keep running.
822 */
rvin_fill_hw_slot(struct rvin_dev * vin,int slot)823 static void rvin_fill_hw_slot(struct rvin_dev *vin, int slot)
824 {
825 struct rvin_buffer *buf;
826 struct vb2_v4l2_buffer *vbuf;
827 dma_addr_t phys_addr;
828
829 /* A already populated slot shall never be overwritten. */
830 if (WARN_ON(vin->queue_buf[slot] != NULL))
831 return;
832
833 vin_dbg(vin, "Filling HW slot: %d\n", slot);
834
835 if (list_empty(&vin->buf_list)) {
836 vin->queue_buf[slot] = NULL;
837 phys_addr = vin->scratch_phys;
838 } else {
839 /* Keep track of buffer we give to HW */
840 buf = list_entry(vin->buf_list.next, struct rvin_buffer, list);
841 vbuf = &buf->vb;
842 list_del_init(to_buf_list(vbuf));
843 vin->queue_buf[slot] = vbuf;
844
845 /* Setup DMA */
846 phys_addr = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0);
847 }
848
849 rvin_set_slot_addr(vin, slot, phys_addr);
850 }
851
rvin_capture_start(struct rvin_dev * vin)852 static int rvin_capture_start(struct rvin_dev *vin)
853 {
854 int slot, ret;
855
856 for (slot = 0; slot < HW_BUFFER_NUM; slot++)
857 rvin_fill_hw_slot(vin, slot);
858
859 rvin_crop_scale_comp(vin);
860
861 ret = rvin_setup(vin);
862 if (ret)
863 return ret;
864
865 vin_dbg(vin, "Starting to capture\n");
866
867 /* Continuous Frame Capture Mode */
868 rvin_write(vin, VNFC_C_FRAME, VNFC_REG);
869
870 vin->state = STARTING;
871
872 return 0;
873 }
874
rvin_capture_stop(struct rvin_dev * vin)875 static void rvin_capture_stop(struct rvin_dev *vin)
876 {
877 /* Set continuous & single transfer off */
878 rvin_write(vin, 0, VNFC_REG);
879
880 /* Disable module */
881 rvin_write(vin, rvin_read(vin, VNMC_REG) & ~VNMC_ME, VNMC_REG);
882 }
883
884 /* -----------------------------------------------------------------------------
885 * DMA Functions
886 */
887
888 #define RVIN_TIMEOUT_MS 100
889 #define RVIN_RETRIES 10
890
rvin_irq(int irq,void * data)891 static irqreturn_t rvin_irq(int irq, void *data)
892 {
893 struct rvin_dev *vin = data;
894 u32 int_status, vnms;
895 int slot;
896 unsigned int handled = 0;
897 unsigned long flags;
898
899 spin_lock_irqsave(&vin->qlock, flags);
900
901 int_status = rvin_get_interrupt_status(vin);
902 if (!int_status)
903 goto done;
904
905 rvin_ack_interrupt(vin);
906 handled = 1;
907
908 /* Nothing to do if capture status is 'STOPPED' */
909 if (vin->state == STOPPED) {
910 vin_dbg(vin, "IRQ while state stopped\n");
911 goto done;
912 }
913
914 /* Nothing to do if capture status is 'STOPPING' */
915 if (vin->state == STOPPING) {
916 vin_dbg(vin, "IRQ while state stopping\n");
917 goto done;
918 }
919
920 /* Prepare for capture and update state */
921 vnms = rvin_read(vin, VNMS_REG);
922 slot = (vnms & VNMS_FBS_MASK) >> VNMS_FBS_SHIFT;
923
924 /*
925 * To hand buffers back in a known order to userspace start
926 * to capture first from slot 0.
927 */
928 if (vin->state == STARTING) {
929 if (slot != 0) {
930 vin_dbg(vin, "Starting sync slot: %d\n", slot);
931 goto done;
932 }
933
934 vin_dbg(vin, "Capture start synced!\n");
935 vin->state = RUNNING;
936 }
937
938 /* Capture frame */
939 if (vin->queue_buf[slot]) {
940 vin->queue_buf[slot]->field = vin->format.field;
941 vin->queue_buf[slot]->sequence = vin->sequence;
942 vin->queue_buf[slot]->vb2_buf.timestamp = ktime_get_ns();
943 vb2_buffer_done(&vin->queue_buf[slot]->vb2_buf,
944 VB2_BUF_STATE_DONE);
945 vin->queue_buf[slot] = NULL;
946 } else {
947 /* Scratch buffer was used, dropping frame. */
948 vin_dbg(vin, "Dropping frame %u\n", vin->sequence);
949 }
950
951 vin->sequence++;
952
953 /* Prepare for next frame */
954 rvin_fill_hw_slot(vin, slot);
955 done:
956 spin_unlock_irqrestore(&vin->qlock, flags);
957
958 return IRQ_RETVAL(handled);
959 }
960
961 /* Need to hold qlock before calling */
return_all_buffers(struct rvin_dev * vin,enum vb2_buffer_state state)962 static void return_all_buffers(struct rvin_dev *vin,
963 enum vb2_buffer_state state)
964 {
965 struct rvin_buffer *buf, *node;
966 int i;
967
968 for (i = 0; i < HW_BUFFER_NUM; i++) {
969 if (vin->queue_buf[i]) {
970 vb2_buffer_done(&vin->queue_buf[i]->vb2_buf,
971 state);
972 vin->queue_buf[i] = NULL;
973 }
974 }
975
976 list_for_each_entry_safe(buf, node, &vin->buf_list, list) {
977 vb2_buffer_done(&buf->vb.vb2_buf, state);
978 list_del(&buf->list);
979 }
980 }
981
rvin_queue_setup(struct vb2_queue * vq,unsigned int * nbuffers,unsigned int * nplanes,unsigned int sizes[],struct device * alloc_devs[])982 static int rvin_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers,
983 unsigned int *nplanes, unsigned int sizes[],
984 struct device *alloc_devs[])
985
986 {
987 struct rvin_dev *vin = vb2_get_drv_priv(vq);
988
989 /* Make sure the image size is large enough. */
990 if (*nplanes)
991 return sizes[0] < vin->format.sizeimage ? -EINVAL : 0;
992
993 *nplanes = 1;
994 sizes[0] = vin->format.sizeimage;
995
996 return 0;
997 };
998
rvin_buffer_prepare(struct vb2_buffer * vb)999 static int rvin_buffer_prepare(struct vb2_buffer *vb)
1000 {
1001 struct rvin_dev *vin = vb2_get_drv_priv(vb->vb2_queue);
1002 unsigned long size = vin->format.sizeimage;
1003
1004 if (vb2_plane_size(vb, 0) < size) {
1005 vin_err(vin, "buffer too small (%lu < %lu)\n",
1006 vb2_plane_size(vb, 0), size);
1007 return -EINVAL;
1008 }
1009
1010 vb2_set_plane_payload(vb, 0, size);
1011
1012 return 0;
1013 }
1014
rvin_buffer_queue(struct vb2_buffer * vb)1015 static void rvin_buffer_queue(struct vb2_buffer *vb)
1016 {
1017 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1018 struct rvin_dev *vin = vb2_get_drv_priv(vb->vb2_queue);
1019 unsigned long flags;
1020
1021 spin_lock_irqsave(&vin->qlock, flags);
1022
1023 list_add_tail(to_buf_list(vbuf), &vin->buf_list);
1024
1025 spin_unlock_irqrestore(&vin->qlock, flags);
1026 }
1027
rvin_mc_validate_format(struct rvin_dev * vin,struct v4l2_subdev * sd,struct media_pad * pad)1028 static int rvin_mc_validate_format(struct rvin_dev *vin, struct v4l2_subdev *sd,
1029 struct media_pad *pad)
1030 {
1031 struct v4l2_subdev_format fmt = {
1032 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1033 };
1034
1035 fmt.pad = pad->index;
1036 if (v4l2_subdev_call(sd, pad, get_fmt, NULL, &fmt))
1037 return -EPIPE;
1038
1039 switch (fmt.format.code) {
1040 case MEDIA_BUS_FMT_YUYV8_1X16:
1041 case MEDIA_BUS_FMT_UYVY8_1X16:
1042 case MEDIA_BUS_FMT_UYVY8_2X8:
1043 case MEDIA_BUS_FMT_UYVY10_2X10:
1044 case MEDIA_BUS_FMT_RGB888_1X24:
1045 vin->mbus_code = fmt.format.code;
1046 break;
1047 default:
1048 return -EPIPE;
1049 }
1050
1051 switch (fmt.format.field) {
1052 case V4L2_FIELD_TOP:
1053 case V4L2_FIELD_BOTTOM:
1054 case V4L2_FIELD_NONE:
1055 case V4L2_FIELD_INTERLACED_TB:
1056 case V4L2_FIELD_INTERLACED_BT:
1057 case V4L2_FIELD_INTERLACED:
1058 case V4L2_FIELD_SEQ_TB:
1059 case V4L2_FIELD_SEQ_BT:
1060 /* Supported natively */
1061 break;
1062 case V4L2_FIELD_ALTERNATE:
1063 switch (vin->format.field) {
1064 case V4L2_FIELD_TOP:
1065 case V4L2_FIELD_BOTTOM:
1066 case V4L2_FIELD_NONE:
1067 break;
1068 case V4L2_FIELD_INTERLACED_TB:
1069 case V4L2_FIELD_INTERLACED_BT:
1070 case V4L2_FIELD_INTERLACED:
1071 case V4L2_FIELD_SEQ_TB:
1072 case V4L2_FIELD_SEQ_BT:
1073 /* Use VIN hardware to combine the two fields */
1074 fmt.format.height *= 2;
1075 break;
1076 default:
1077 return -EPIPE;
1078 }
1079 break;
1080 default:
1081 return -EPIPE;
1082 }
1083
1084 if (fmt.format.width != vin->format.width ||
1085 fmt.format.height != vin->format.height ||
1086 fmt.format.code != vin->mbus_code)
1087 return -EPIPE;
1088
1089 return 0;
1090 }
1091
rvin_set_stream(struct rvin_dev * vin,int on)1092 static int rvin_set_stream(struct rvin_dev *vin, int on)
1093 {
1094 struct media_pipeline *pipe;
1095 struct media_device *mdev;
1096 struct v4l2_subdev *sd;
1097 struct media_pad *pad;
1098 int ret;
1099
1100 /* No media controller used, simply pass operation to subdevice. */
1101 if (!vin->info->use_mc) {
1102 ret = v4l2_subdev_call(vin->parallel->subdev, video, s_stream,
1103 on);
1104
1105 return ret == -ENOIOCTLCMD ? 0 : ret;
1106 }
1107
1108 pad = media_entity_remote_pad(&vin->pad);
1109 if (!pad)
1110 return -EPIPE;
1111
1112 sd = media_entity_to_v4l2_subdev(pad->entity);
1113
1114 if (!on) {
1115 media_pipeline_stop(&vin->vdev.entity);
1116 return v4l2_subdev_call(sd, video, s_stream, 0);
1117 }
1118
1119 ret = rvin_mc_validate_format(vin, sd, pad);
1120 if (ret)
1121 return ret;
1122
1123 /*
1124 * The graph lock needs to be taken to protect concurrent
1125 * starts of multiple VIN instances as they might share
1126 * a common subdevice down the line and then should use
1127 * the same pipe.
1128 */
1129 mdev = vin->vdev.entity.graph_obj.mdev;
1130 mutex_lock(&mdev->graph_mutex);
1131 pipe = sd->entity.pipe ? sd->entity.pipe : &vin->vdev.pipe;
1132 ret = __media_pipeline_start(&vin->vdev.entity, pipe);
1133 mutex_unlock(&mdev->graph_mutex);
1134 if (ret)
1135 return ret;
1136
1137 ret = v4l2_subdev_call(sd, video, s_stream, 1);
1138 if (ret == -ENOIOCTLCMD)
1139 ret = 0;
1140 if (ret)
1141 media_pipeline_stop(&vin->vdev.entity);
1142
1143 return ret;
1144 }
1145
rvin_start_streaming(struct vb2_queue * vq,unsigned int count)1146 static int rvin_start_streaming(struct vb2_queue *vq, unsigned int count)
1147 {
1148 struct rvin_dev *vin = vb2_get_drv_priv(vq);
1149 unsigned long flags;
1150 int ret;
1151
1152 /* Allocate scratch buffer. */
1153 vin->scratch = dma_alloc_coherent(vin->dev, vin->format.sizeimage,
1154 &vin->scratch_phys, GFP_KERNEL);
1155 if (!vin->scratch) {
1156 spin_lock_irqsave(&vin->qlock, flags);
1157 return_all_buffers(vin, VB2_BUF_STATE_QUEUED);
1158 spin_unlock_irqrestore(&vin->qlock, flags);
1159 vin_err(vin, "Failed to allocate scratch buffer\n");
1160 return -ENOMEM;
1161 }
1162
1163 ret = rvin_set_stream(vin, 1);
1164 if (ret) {
1165 spin_lock_irqsave(&vin->qlock, flags);
1166 return_all_buffers(vin, VB2_BUF_STATE_QUEUED);
1167 spin_unlock_irqrestore(&vin->qlock, flags);
1168 goto out;
1169 }
1170
1171 spin_lock_irqsave(&vin->qlock, flags);
1172
1173 vin->sequence = 0;
1174
1175 ret = rvin_capture_start(vin);
1176 if (ret) {
1177 return_all_buffers(vin, VB2_BUF_STATE_QUEUED);
1178 rvin_set_stream(vin, 0);
1179 }
1180
1181 spin_unlock_irqrestore(&vin->qlock, flags);
1182 out:
1183 if (ret)
1184 dma_free_coherent(vin->dev, vin->format.sizeimage, vin->scratch,
1185 vin->scratch_phys);
1186
1187 return ret;
1188 }
1189
rvin_stop_streaming(struct vb2_queue * vq)1190 static void rvin_stop_streaming(struct vb2_queue *vq)
1191 {
1192 struct rvin_dev *vin = vb2_get_drv_priv(vq);
1193 unsigned long flags;
1194 int retries = 0;
1195
1196 spin_lock_irqsave(&vin->qlock, flags);
1197
1198 vin->state = STOPPING;
1199
1200 /* Wait for streaming to stop */
1201 while (retries++ < RVIN_RETRIES) {
1202
1203 rvin_capture_stop(vin);
1204
1205 /* Check if HW is stopped */
1206 if (!rvin_capture_active(vin)) {
1207 vin->state = STOPPED;
1208 break;
1209 }
1210
1211 spin_unlock_irqrestore(&vin->qlock, flags);
1212 msleep(RVIN_TIMEOUT_MS);
1213 spin_lock_irqsave(&vin->qlock, flags);
1214 }
1215
1216 if (vin->state != STOPPED) {
1217 /*
1218 * If this happens something have gone horribly wrong.
1219 * Set state to stopped to prevent the interrupt handler
1220 * to make things worse...
1221 */
1222 vin_err(vin, "Failed stop HW, something is seriously broken\n");
1223 vin->state = STOPPED;
1224 }
1225
1226 /* Release all active buffers */
1227 return_all_buffers(vin, VB2_BUF_STATE_ERROR);
1228
1229 spin_unlock_irqrestore(&vin->qlock, flags);
1230
1231 rvin_set_stream(vin, 0);
1232
1233 /* disable interrupts */
1234 rvin_disable_interrupts(vin);
1235
1236 /* Free scratch buffer. */
1237 dma_free_coherent(vin->dev, vin->format.sizeimage, vin->scratch,
1238 vin->scratch_phys);
1239 }
1240
1241 static const struct vb2_ops rvin_qops = {
1242 .queue_setup = rvin_queue_setup,
1243 .buf_prepare = rvin_buffer_prepare,
1244 .buf_queue = rvin_buffer_queue,
1245 .start_streaming = rvin_start_streaming,
1246 .stop_streaming = rvin_stop_streaming,
1247 .wait_prepare = vb2_ops_wait_prepare,
1248 .wait_finish = vb2_ops_wait_finish,
1249 };
1250
rvin_dma_unregister(struct rvin_dev * vin)1251 void rvin_dma_unregister(struct rvin_dev *vin)
1252 {
1253 mutex_destroy(&vin->lock);
1254
1255 v4l2_device_unregister(&vin->v4l2_dev);
1256 }
1257
rvin_dma_register(struct rvin_dev * vin,int irq)1258 int rvin_dma_register(struct rvin_dev *vin, int irq)
1259 {
1260 struct vb2_queue *q = &vin->queue;
1261 int i, ret;
1262
1263 /* Initialize the top-level structure */
1264 ret = v4l2_device_register(vin->dev, &vin->v4l2_dev);
1265 if (ret)
1266 return ret;
1267
1268 mutex_init(&vin->lock);
1269 INIT_LIST_HEAD(&vin->buf_list);
1270
1271 spin_lock_init(&vin->qlock);
1272
1273 vin->state = STOPPED;
1274
1275 for (i = 0; i < HW_BUFFER_NUM; i++)
1276 vin->queue_buf[i] = NULL;
1277
1278 /* buffer queue */
1279 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1280 q->io_modes = VB2_MMAP | VB2_READ | VB2_DMABUF;
1281 q->lock = &vin->lock;
1282 q->drv_priv = vin;
1283 q->buf_struct_size = sizeof(struct rvin_buffer);
1284 q->ops = &rvin_qops;
1285 q->mem_ops = &vb2_dma_contig_memops;
1286 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1287 q->min_buffers_needed = 4;
1288 q->dev = vin->dev;
1289
1290 ret = vb2_queue_init(q);
1291 if (ret < 0) {
1292 vin_err(vin, "failed to initialize VB2 queue\n");
1293 goto error;
1294 }
1295
1296 /* irq */
1297 ret = devm_request_irq(vin->dev, irq, rvin_irq, IRQF_SHARED,
1298 KBUILD_MODNAME, vin);
1299 if (ret) {
1300 vin_err(vin, "failed to request irq\n");
1301 goto error;
1302 }
1303
1304 return 0;
1305 error:
1306 rvin_dma_unregister(vin);
1307
1308 return ret;
1309 }
1310
1311 /* -----------------------------------------------------------------------------
1312 * Gen3 CHSEL manipulation
1313 */
1314
1315 /*
1316 * There is no need to have locking around changing the routing
1317 * as it's only possible to do so when no VIN in the group is
1318 * streaming so nothing can race with the VNMC register.
1319 */
rvin_set_channel_routing(struct rvin_dev * vin,u8 chsel)1320 int rvin_set_channel_routing(struct rvin_dev *vin, u8 chsel)
1321 {
1322 u32 ifmd, vnmc;
1323 int ret;
1324
1325 ret = pm_runtime_get_sync(vin->dev);
1326 if (ret < 0)
1327 return ret;
1328
1329 /* Make register writes take effect immediately. */
1330 vnmc = rvin_read(vin, VNMC_REG);
1331 rvin_write(vin, vnmc & ~VNMC_VUP, VNMC_REG);
1332
1333 ifmd = VNCSI_IFMD_DES1 | VNCSI_IFMD_DES0 | VNCSI_IFMD_CSI_CHSEL(chsel);
1334
1335 rvin_write(vin, ifmd, VNCSI_IFMD_REG);
1336
1337 vin_dbg(vin, "Set IFMD 0x%x\n", ifmd);
1338
1339 /* Restore VNMC. */
1340 rvin_write(vin, vnmc, VNMC_REG);
1341
1342 pm_runtime_put(vin->dev);
1343
1344 return ret;
1345 }
1346
