1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #include "cam.h"
6 #include "chan.h"
7 #include "debug.h"
8 #include "fw.h"
9 #include "mac.h"
10 #include "ps.h"
11 #include "reg.h"
12 #include "util.h"
13
14 const u32 rtw89_mac_mem_base_addrs[RTW89_MAC_MEM_NUM] = {
15 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR,
16 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR,
17 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR,
18 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR,
19 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR,
20 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR,
21 [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR,
22 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR,
23 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR,
24 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR,
25 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR,
26 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR,
27 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR,
28 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR,
29 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR,
30 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR,
31 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR,
32 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR,
33 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR,
34 };
35
rtw89_mac_mem_write(struct rtw89_dev * rtwdev,u32 offset,u32 val,enum rtw89_mac_mem_sel sel)36 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset,
37 u32 val, enum rtw89_mac_mem_sel sel)
38 {
39 u32 addr = rtw89_mac_mem_base_addrs[sel] + offset;
40
41 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr);
42 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, val);
43 }
44
rtw89_mac_mem_read(struct rtw89_dev * rtwdev,u32 offset,enum rtw89_mac_mem_sel sel)45 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset,
46 enum rtw89_mac_mem_sel sel)
47 {
48 u32 addr = rtw89_mac_mem_base_addrs[sel] + offset;
49
50 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, addr);
51 return rtw89_read32(rtwdev, R_AX_INDIR_ACCESS_ENTRY);
52 }
53
rtw89_mac_check_mac_en(struct rtw89_dev * rtwdev,u8 mac_idx,enum rtw89_mac_hwmod_sel sel)54 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 mac_idx,
55 enum rtw89_mac_hwmod_sel sel)
56 {
57 u32 val, r_val;
58
59 if (sel == RTW89_DMAC_SEL) {
60 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN);
61 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN);
62 } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) {
63 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN);
64 val = B_AX_CMAC_EN;
65 } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) {
66 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND);
67 val = B_AX_CMAC1_FEN;
68 } else {
69 return -EINVAL;
70 }
71 if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD ||
72 (val & r_val) != val)
73 return -EFAULT;
74
75 return 0;
76 }
77
rtw89_mac_write_lte(struct rtw89_dev * rtwdev,const u32 offset,u32 val)78 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val)
79 {
80 u8 lte_ctrl;
81 int ret;
82
83 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0,
84 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3);
85 if (ret)
86 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n");
87
88 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val);
89 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset);
90
91 return ret;
92 }
93
rtw89_mac_read_lte(struct rtw89_dev * rtwdev,const u32 offset,u32 * val)94 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val)
95 {
96 u8 lte_ctrl;
97 int ret;
98
99 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0,
100 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3);
101 if (ret)
102 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n");
103
104 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset);
105 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA);
106
107 return ret;
108 }
109
110 static
dle_dfi_ctrl(struct rtw89_dev * rtwdev,struct rtw89_mac_dle_dfi_ctrl * ctrl)111 int dle_dfi_ctrl(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl)
112 {
113 u32 ctrl_reg, data_reg, ctrl_data;
114 u32 val;
115 int ret;
116
117 switch (ctrl->type) {
118 case DLE_CTRL_TYPE_WDE:
119 ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL;
120 data_reg = R_AX_WDE_DBG_FUN_INTF_DATA;
121 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) |
122 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) |
123 B_AX_WDE_DFI_ACTIVE;
124 break;
125 case DLE_CTRL_TYPE_PLE:
126 ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL;
127 data_reg = R_AX_PLE_DBG_FUN_INTF_DATA;
128 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) |
129 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) |
130 B_AX_PLE_DFI_ACTIVE;
131 break;
132 default:
133 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type);
134 return -EINVAL;
135 }
136
137 rtw89_write32(rtwdev, ctrl_reg, ctrl_data);
138
139 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE),
140 1, 1000, false, rtwdev, ctrl_reg);
141 if (ret) {
142 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n",
143 ctrl_reg, ctrl_data);
144 return ret;
145 }
146
147 ctrl->out_data = rtw89_read32(rtwdev, data_reg);
148 return 0;
149 }
150
dle_dfi_quota(struct rtw89_dev * rtwdev,struct rtw89_mac_dle_dfi_quota * quota)151 static int dle_dfi_quota(struct rtw89_dev *rtwdev,
152 struct rtw89_mac_dle_dfi_quota *quota)
153 {
154 struct rtw89_mac_dle_dfi_ctrl ctrl;
155 int ret;
156
157 ctrl.type = quota->dle_type;
158 ctrl.target = DLE_DFI_TYPE_QUOTA;
159 ctrl.addr = quota->qtaid;
160 ret = dle_dfi_ctrl(rtwdev, &ctrl);
161 if (ret) {
162 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret);
163 return ret;
164 }
165
166 quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data);
167 quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data);
168 return 0;
169 }
170
dle_dfi_qempty(struct rtw89_dev * rtwdev,struct rtw89_mac_dle_dfi_qempty * qempty)171 static int dle_dfi_qempty(struct rtw89_dev *rtwdev,
172 struct rtw89_mac_dle_dfi_qempty *qempty)
173 {
174 struct rtw89_mac_dle_dfi_ctrl ctrl;
175 u32 ret;
176
177 ctrl.type = qempty->dle_type;
178 ctrl.target = DLE_DFI_TYPE_QEMPTY;
179 ctrl.addr = qempty->grpsel;
180 ret = dle_dfi_ctrl(rtwdev, &ctrl);
181 if (ret) {
182 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret);
183 return ret;
184 }
185
186 qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data);
187 return 0;
188 }
189
dump_err_status_dispatcher(struct rtw89_dev * rtwdev)190 static void dump_err_status_dispatcher(struct rtw89_dev *rtwdev)
191 {
192 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ",
193 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR));
194 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n",
195 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR));
196 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ",
197 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR));
198 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n",
199 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR));
200 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ",
201 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR));
202 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n",
203 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR));
204 }
205
rtw89_mac_dump_qta_lost(struct rtw89_dev * rtwdev)206 static void rtw89_mac_dump_qta_lost(struct rtw89_dev *rtwdev)
207 {
208 struct rtw89_mac_dle_dfi_qempty qempty;
209 struct rtw89_mac_dle_dfi_quota quota;
210 struct rtw89_mac_dle_dfi_ctrl ctrl;
211 u32 val, not_empty, i;
212 int ret;
213
214 qempty.dle_type = DLE_CTRL_TYPE_PLE;
215 qempty.grpsel = 0;
216 qempty.qempty = ~(u32)0;
217 ret = dle_dfi_qempty(rtwdev, &qempty);
218 if (ret)
219 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
220 else
221 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty);
222
223 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) {
224 if (!(not_empty & BIT(0)))
225 continue;
226 ctrl.type = DLE_CTRL_TYPE_PLE;
227 ctrl.target = DLE_DFI_TYPE_QLNKTBL;
228 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) |
229 FIELD_PREP(QLNKTBL_ADDR_TBL_IDX_MASK, i);
230 ret = dle_dfi_ctrl(rtwdev, &ctrl);
231 if (ret)
232 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
233 else
234 rtw89_info(rtwdev, "qidx%d pktcnt = %ld\n", i,
235 FIELD_GET(QLNKTBL_DATA_SEL1_PKT_CNT_MASK,
236 ctrl.out_data));
237 }
238
239 quota.dle_type = DLE_CTRL_TYPE_PLE;
240 quota.qtaid = 6;
241 ret = dle_dfi_quota(rtwdev, "a);
242 if (ret)
243 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
244 else
245 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n",
246 quota.rsv_pgnum, quota.use_pgnum);
247
248 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG);
249 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%lx\n",
250 FIELD_GET(B_AX_PLE_Q6_MIN_SIZE_MASK, val));
251 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%lx\n",
252 FIELD_GET(B_AX_PLE_Q6_MAX_SIZE_MASK, val));
253
254 dump_err_status_dispatcher(rtwdev);
255 }
256
rtw89_mac_dump_l0_to_l1(struct rtw89_dev * rtwdev,enum mac_ax_err_info err)257 static void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev,
258 enum mac_ax_err_info err)
259 {
260 u32 dbg, event;
261
262 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO);
263 event = FIELD_GET(B_AX_L0_TO_L1_EVENT_MASK, dbg);
264
265 switch (event) {
266 case MAC_AX_L0_TO_L1_RX_QTA_LOST:
267 rtw89_info(rtwdev, "quota lost!\n");
268 rtw89_mac_dump_qta_lost(rtwdev);
269 break;
270 default:
271 break;
272 }
273 }
274
rtw89_mac_dump_err_status(struct rtw89_dev * rtwdev,enum mac_ax_err_info err)275 static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev,
276 enum mac_ax_err_info err)
277 {
278 u32 dmac_err, cmac_err;
279
280 if (err != MAC_AX_ERR_L1_ERR_DMAC &&
281 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 &&
282 err != MAC_AX_ERR_L0_ERR_CMAC0 &&
283 err != MAC_AX_ERR_L0_ERR_CMAC1)
284 return;
285
286 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err);
287 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n",
288 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO));
289
290 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR);
291 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR =0x%08x\n", cmac_err);
292 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR);
293 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR =0x%08x\n", dmac_err);
294
295 if (dmac_err) {
296 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG =0x%08x ",
297 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG));
298 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG =0x%08x\n",
299 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG));
300 }
301
302 if (dmac_err & B_AX_WDRLS_ERR_FLAG) {
303 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR =0x%08x ",
304 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR));
305 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR =0x%08x\n",
306 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR));
307 }
308
309 if (dmac_err & B_AX_WSEC_ERR_FLAG) {
310 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR =0x%08x\n",
311 rtw89_read32(rtwdev, R_AX_SEC_DEBUG));
312 rtw89_info(rtwdev, "SEC_local_Register 0x9D00 =0x%08x\n",
313 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL));
314 rtw89_info(rtwdev, "SEC_local_Register 0x9D04 =0x%08x\n",
315 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC));
316 rtw89_info(rtwdev, "SEC_local_Register 0x9D10 =0x%08x\n",
317 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS));
318 rtw89_info(rtwdev, "SEC_local_Register 0x9D14 =0x%08x\n",
319 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA));
320 rtw89_info(rtwdev, "SEC_local_Register 0x9D18 =0x%08x\n",
321 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA));
322 rtw89_info(rtwdev, "SEC_local_Register 0x9D20 =0x%08x\n",
323 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG));
324 rtw89_info(rtwdev, "SEC_local_Register 0x9D24 =0x%08x\n",
325 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG));
326 rtw89_info(rtwdev, "SEC_local_Register 0x9D28 =0x%08x\n",
327 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT));
328 rtw89_info(rtwdev, "SEC_local_Register 0x9D2C =0x%08x\n",
329 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT));
330 }
331
332 if (dmac_err & B_AX_MPDU_ERR_FLAG) {
333 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR =0x%08x ",
334 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR));
335 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR =0x%08x\n",
336 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR));
337 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR =0x%08x ",
338 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR));
339 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR =0x%08x\n",
340 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR));
341 }
342
343 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) {
344 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR =0x%08x ",
345 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR));
346 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR= 0x%08x\n",
347 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR));
348 }
349
350 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) {
351 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x ",
352 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));
353 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n",
354 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
355 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x ",
356 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));
357 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
358 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
359 dump_err_status_dispatcher(rtwdev);
360 }
361
362 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) {
363 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n",
364 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR));
365 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n",
366 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1));
367 }
368
369 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) {
370 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x ",
371 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));
372 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n",
373 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
374 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x ",
375 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));
376 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
377 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
378 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n",
379 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0));
380 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n",
381 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1));
382 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n",
383 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2));
384 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n",
385 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS));
386 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n",
387 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0));
388 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n",
389 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1));
390 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n",
391 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2));
392 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n",
393 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS));
394 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n",
395 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0));
396 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n",
397 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1));
398 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n",
399 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2));
400 dump_err_status_dispatcher(rtwdev);
401 }
402
403 if (dmac_err & B_AX_PKTIN_ERR_FLAG) {
404 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR =0x%08x ",
405 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR));
406 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR =0x%08x\n",
407 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR));
408 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR =0x%08x ",
409 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR));
410 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR =0x%08x\n",
411 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR));
412 }
413
414 if (dmac_err & B_AX_DISPATCH_ERR_FLAG)
415 dump_err_status_dispatcher(rtwdev);
416
417 if (dmac_err & B_AX_DLE_CPUIO_ERR_FLAG) {
418 rtw89_info(rtwdev, "R_AX_CPUIO_ERR_IMR=0x%08x ",
419 rtw89_read32(rtwdev, R_AX_CPUIO_ERR_IMR));
420 rtw89_info(rtwdev, "R_AX_CPUIO_ERR_ISR=0x%08x\n",
421 rtw89_read32(rtwdev, R_AX_CPUIO_ERR_ISR));
422 }
423
424 if (dmac_err & BIT(11)) {
425 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n",
426 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR));
427 }
428
429 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) {
430 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR=0x%08x ",
431 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR));
432 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR=0x%04x\n",
433 rtw89_read16(rtwdev, R_AX_SCHEDULE_ERR_ISR));
434 }
435
436 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) {
437 rtw89_info(rtwdev, "R_AX_PTCL_IMR0=0x%08x ",
438 rtw89_read32(rtwdev, R_AX_PTCL_IMR0));
439 rtw89_info(rtwdev, "R_AX_PTCL_ISR0=0x%08x\n",
440 rtw89_read32(rtwdev, R_AX_PTCL_ISR0));
441 }
442
443 if (cmac_err & B_AX_DMA_TOP_ERR_IND) {
444 rtw89_info(rtwdev, "R_AX_DLE_CTRL=0x%08x\n",
445 rtw89_read32(rtwdev, R_AX_DLE_CTRL));
446 }
447
448 if (cmac_err & B_AX_PHYINTF_ERR_IND) {
449 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR=0x%08x\n",
450 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR));
451 }
452
453 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) {
454 rtw89_info(rtwdev, "R_AX_TXPWR_IMR=0x%08x ",
455 rtw89_read32(rtwdev, R_AX_TXPWR_IMR));
456 rtw89_info(rtwdev, "R_AX_TXPWR_ISR=0x%08x\n",
457 rtw89_read32(rtwdev, R_AX_TXPWR_ISR));
458 }
459
460 if (cmac_err & B_AX_WMAC_RX_ERR_IND) {
461 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL=0x%08x ",
462 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL));
463 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR=0x%08x\n",
464 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR));
465 }
466
467 if (cmac_err & B_AX_WMAC_TX_ERR_IND) {
468 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR=0x%08x ",
469 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR));
470 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL=0x%08x\n",
471 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL));
472 }
473
474 rtwdev->hci.ops->dump_err_status(rtwdev);
475
476 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1)
477 rtw89_mac_dump_l0_to_l1(rtwdev, err);
478
479 rtw89_info(rtwdev, "<---\n");
480 }
481
rtw89_mac_get_err_status(struct rtw89_dev * rtwdev)482 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev)
483 {
484 u32 err, err_scnr;
485 int ret;
486
487 ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000,
488 false, rtwdev, R_AX_HALT_C2H_CTRL);
489 if (ret) {
490 rtw89_warn(rtwdev, "Polling FW err status fail\n");
491 return ret;
492 }
493
494 err = rtw89_read32(rtwdev, R_AX_HALT_C2H);
495 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0);
496
497 err_scnr = RTW89_ERROR_SCENARIO(err);
498 if (err_scnr == RTW89_WCPU_CPU_EXCEPTION)
499 err = MAC_AX_ERR_CPU_EXCEPTION;
500 else if (err_scnr == RTW89_WCPU_ASSERTION)
501 err = MAC_AX_ERR_ASSERTION;
502
503 rtw89_fw_st_dbg_dump(rtwdev);
504 rtw89_mac_dump_err_status(rtwdev, err);
505
506 return err;
507 }
508 EXPORT_SYMBOL(rtw89_mac_get_err_status);
509
rtw89_mac_set_err_status(struct rtw89_dev * rtwdev,u32 err)510 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err)
511 {
512 u32 halt;
513 int ret = 0;
514
515 if (err > MAC_AX_SET_ERR_MAX) {
516 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err);
517 return -EINVAL;
518 }
519
520 ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000,
521 100000, false, rtwdev, R_AX_HALT_H2C_CTRL);
522 if (ret) {
523 rtw89_err(rtwdev, "FW doesn't receive previous msg\n");
524 return -EFAULT;
525 }
526
527 rtw89_write32(rtwdev, R_AX_HALT_H2C, err);
528 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER);
529
530 return 0;
531 }
532 EXPORT_SYMBOL(rtw89_mac_set_err_status);
533
hfc_reset_param(struct rtw89_dev * rtwdev)534 static int hfc_reset_param(struct rtw89_dev *rtwdev)
535 {
536 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
537 struct rtw89_hfc_param_ini param_ini = {NULL};
538 u8 qta_mode = rtwdev->mac.dle_info.qta_mode;
539
540 switch (rtwdev->hci.type) {
541 case RTW89_HCI_TYPE_PCIE:
542 param_ini = rtwdev->chip->hfc_param_ini[qta_mode];
543 param->en = 0;
544 break;
545 default:
546 return -EINVAL;
547 }
548
549 if (param_ini.pub_cfg)
550 param->pub_cfg = *param_ini.pub_cfg;
551
552 if (param_ini.prec_cfg) {
553 param->prec_cfg = *param_ini.prec_cfg;
554 rtwdev->hal.sw_amsdu_max_size =
555 param->prec_cfg.wp_ch07_prec * HFC_PAGE_UNIT;
556 }
557
558 if (param_ini.ch_cfg)
559 param->ch_cfg = param_ini.ch_cfg;
560
561 memset(¶m->ch_info, 0, sizeof(param->ch_info));
562 memset(¶m->pub_info, 0, sizeof(param->pub_info));
563 param->mode = param_ini.mode;
564
565 return 0;
566 }
567
hfc_ch_cfg_chk(struct rtw89_dev * rtwdev,u8 ch)568 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch)
569 {
570 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
571 const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg;
572 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
573 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
574
575 if (ch >= RTW89_DMA_CH_NUM)
576 return -EINVAL;
577
578 if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) ||
579 ch_cfg[ch].max > pub_cfg->pub_max)
580 return -EINVAL;
581 if (ch_cfg[ch].grp >= grp_num)
582 return -EINVAL;
583
584 return 0;
585 }
586
hfc_pub_info_chk(struct rtw89_dev * rtwdev)587 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev)
588 {
589 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
590 const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg;
591 struct rtw89_hfc_pub_info *info = ¶m->pub_info;
592
593 if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) {
594 if (rtwdev->chip->chip_id == RTL8852A)
595 return 0;
596 else
597 return -EFAULT;
598 }
599
600 return 0;
601 }
602
hfc_pub_cfg_chk(struct rtw89_dev * rtwdev)603 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev)
604 {
605 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
606 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
607
608 if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max)
609 return -EFAULT;
610
611 return 0;
612 }
613
hfc_ch_ctrl(struct rtw89_dev * rtwdev,u8 ch)614 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch)
615 {
616 const struct rtw89_chip_info *chip = rtwdev->chip;
617 const struct rtw89_page_regs *regs = chip->page_regs;
618 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
619 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg;
620 int ret = 0;
621 u32 val = 0;
622
623 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
624 if (ret)
625 return ret;
626
627 ret = hfc_ch_cfg_chk(rtwdev, ch);
628 if (ret)
629 return ret;
630
631 if (ch > RTW89_DMA_B1HI)
632 return -EINVAL;
633
634 val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) |
635 u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) |
636 (cfg[ch].grp ? B_AX_GRP : 0);
637 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val);
638
639 return 0;
640 }
641
hfc_upd_ch_info(struct rtw89_dev * rtwdev,u8 ch)642 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch)
643 {
644 const struct rtw89_chip_info *chip = rtwdev->chip;
645 const struct rtw89_page_regs *regs = chip->page_regs;
646 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
647 struct rtw89_hfc_ch_info *info = param->ch_info;
648 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg;
649 u32 val;
650 u32 ret;
651
652 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
653 if (ret)
654 return ret;
655
656 if (ch > RTW89_DMA_H2C)
657 return -EINVAL;
658
659 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4);
660 info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK);
661 if (ch < RTW89_DMA_H2C)
662 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK);
663 else
664 info[ch].used = cfg[ch].min - info[ch].aval;
665
666 return 0;
667 }
668
hfc_pub_ctrl(struct rtw89_dev * rtwdev)669 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev)
670 {
671 const struct rtw89_chip_info *chip = rtwdev->chip;
672 const struct rtw89_page_regs *regs = chip->page_regs;
673 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg;
674 u32 val;
675 int ret;
676
677 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
678 if (ret)
679 return ret;
680
681 ret = hfc_pub_cfg_chk(rtwdev);
682 if (ret)
683 return ret;
684
685 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) |
686 u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK);
687 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val);
688
689 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK);
690 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val);
691
692 return 0;
693 }
694
hfc_upd_mix_info(struct rtw89_dev * rtwdev)695 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev)
696 {
697 const struct rtw89_chip_info *chip = rtwdev->chip;
698 const struct rtw89_page_regs *regs = chip->page_regs;
699 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
700 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
701 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
702 struct rtw89_hfc_pub_info *info = ¶m->pub_info;
703 u32 val;
704 int ret;
705
706 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
707 if (ret)
708 return ret;
709
710 val = rtw89_read32(rtwdev, regs->pub_page_info1);
711 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK);
712 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK);
713 val = rtw89_read32(rtwdev, regs->pub_page_info3);
714 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK);
715 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK);
716 info->pub_aval =
717 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2),
718 B_AX_PUB_AVAL_PG_MASK);
719 info->wp_aval =
720 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1),
721 B_AX_WP_AVAL_PG_MASK);
722
723 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl);
724 param->en = val & B_AX_HCI_FC_EN ? 1 : 0;
725 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0;
726 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK);
727 prec_cfg->ch011_full_cond =
728 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK);
729 prec_cfg->h2c_full_cond =
730 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK);
731 prec_cfg->wp_ch07_full_cond =
732 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK);
733 prec_cfg->wp_ch811_full_cond =
734 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK);
735
736 val = rtw89_read32(rtwdev, regs->ch_page_ctrl);
737 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK);
738 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK);
739
740 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2);
741 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK);
742
743 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1);
744 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK);
745 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK);
746
747 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2);
748 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK);
749
750 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1);
751 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK);
752 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK);
753
754 ret = hfc_pub_info_chk(rtwdev);
755 if (param->en && ret)
756 return ret;
757
758 return 0;
759 }
760
hfc_h2c_cfg(struct rtw89_dev * rtwdev)761 static void hfc_h2c_cfg(struct rtw89_dev *rtwdev)
762 {
763 const struct rtw89_chip_info *chip = rtwdev->chip;
764 const struct rtw89_page_regs *regs = chip->page_regs;
765 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
766 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
767 u32 val;
768
769 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK);
770 rtw89_write32(rtwdev, regs->ch_page_ctrl, val);
771
772 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl,
773 B_AX_HCI_FC_CH12_FULL_COND_MASK,
774 prec_cfg->h2c_full_cond);
775 }
776
hfc_mix_cfg(struct rtw89_dev * rtwdev)777 static void hfc_mix_cfg(struct rtw89_dev *rtwdev)
778 {
779 const struct rtw89_chip_info *chip = rtwdev->chip;
780 const struct rtw89_page_regs *regs = chip->page_regs;
781 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
782 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg;
783 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg;
784 u32 val;
785
786 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) |
787 u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK);
788 rtw89_write32(rtwdev, regs->ch_page_ctrl, val);
789
790 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK);
791 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val);
792
793 val = u32_encode_bits(prec_cfg->wp_ch07_prec,
794 B_AX_PREC_PAGE_WP_CH07_MASK) |
795 u32_encode_bits(prec_cfg->wp_ch811_prec,
796 B_AX_PREC_PAGE_WP_CH811_MASK);
797 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val);
798
799 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl),
800 param->mode, B_AX_HCI_FC_MODE_MASK);
801 val = u32_replace_bits(val, prec_cfg->ch011_full_cond,
802 B_AX_HCI_FC_WD_FULL_COND_MASK);
803 val = u32_replace_bits(val, prec_cfg->h2c_full_cond,
804 B_AX_HCI_FC_CH12_FULL_COND_MASK);
805 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond,
806 B_AX_HCI_FC_WP_CH07_FULL_COND_MASK);
807 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond,
808 B_AX_HCI_FC_WP_CH811_FULL_COND_MASK);
809 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val);
810 }
811
hfc_func_en(struct rtw89_dev * rtwdev,bool en,bool h2c_en)812 static void hfc_func_en(struct rtw89_dev *rtwdev, bool en, bool h2c_en)
813 {
814 const struct rtw89_chip_info *chip = rtwdev->chip;
815 const struct rtw89_page_regs *regs = chip->page_regs;
816 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
817 u32 val;
818
819 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl);
820 param->en = en;
821 param->h2c_en = h2c_en;
822 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN);
823 val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) :
824 (val & ~B_AX_HCI_FC_CH12_EN);
825 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val);
826 }
827
hfc_init(struct rtw89_dev * rtwdev,bool reset,bool en,bool h2c_en)828 static int hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en)
829 {
830 const struct rtw89_chip_info *chip = rtwdev->chip;
831 u32 dma_ch_mask = chip->dma_ch_mask;
832 u8 ch;
833 u32 ret = 0;
834
835 if (reset)
836 ret = hfc_reset_param(rtwdev);
837 if (ret)
838 return ret;
839
840 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
841 if (ret)
842 return ret;
843
844 hfc_func_en(rtwdev, false, false);
845
846 if (!en && h2c_en) {
847 hfc_h2c_cfg(rtwdev);
848 hfc_func_en(rtwdev, en, h2c_en);
849 return ret;
850 }
851
852 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) {
853 if (dma_ch_mask & BIT(ch))
854 continue;
855 ret = hfc_ch_ctrl(rtwdev, ch);
856 if (ret)
857 return ret;
858 }
859
860 ret = hfc_pub_ctrl(rtwdev);
861 if (ret)
862 return ret;
863
864 hfc_mix_cfg(rtwdev);
865 if (en || h2c_en) {
866 hfc_func_en(rtwdev, en, h2c_en);
867 udelay(10);
868 }
869 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) {
870 if (dma_ch_mask & BIT(ch))
871 continue;
872 ret = hfc_upd_ch_info(rtwdev, ch);
873 if (ret)
874 return ret;
875 }
876 ret = hfc_upd_mix_info(rtwdev);
877
878 return ret;
879 }
880
881 #define PWR_POLL_CNT 2000
pwr_cmd_poll(struct rtw89_dev * rtwdev,const struct rtw89_pwr_cfg * cfg)882 static int pwr_cmd_poll(struct rtw89_dev *rtwdev,
883 const struct rtw89_pwr_cfg *cfg)
884 {
885 u8 val = 0;
886 int ret;
887 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ?
888 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr;
889
890 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk),
891 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr);
892
893 if (!ret)
894 return 0;
895
896 rtw89_warn(rtwdev, "[ERR] Polling timeout\n");
897 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr);
898 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val);
899
900 return -EBUSY;
901 }
902
rtw89_mac_sub_pwr_seq(struct rtw89_dev * rtwdev,u8 cv_msk,u8 intf_msk,const struct rtw89_pwr_cfg * cfg)903 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk,
904 u8 intf_msk, const struct rtw89_pwr_cfg *cfg)
905 {
906 const struct rtw89_pwr_cfg *cur_cfg;
907 u32 addr;
908 u8 val;
909
910 for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) {
911 if (!(cur_cfg->intf_msk & intf_msk) ||
912 !(cur_cfg->cv_msk & cv_msk))
913 continue;
914
915 switch (cur_cfg->cmd) {
916 case PWR_CMD_WRITE:
917 addr = cur_cfg->addr;
918
919 if (cur_cfg->base == PWR_BASE_SDIO)
920 addr |= SDIO_LOCAL_BASE_ADDR;
921
922 val = rtw89_read8(rtwdev, addr);
923 val &= ~(cur_cfg->msk);
924 val |= (cur_cfg->val & cur_cfg->msk);
925
926 rtw89_write8(rtwdev, addr, val);
927 break;
928 case PWR_CMD_POLL:
929 if (pwr_cmd_poll(rtwdev, cur_cfg))
930 return -EBUSY;
931 break;
932 case PWR_CMD_DELAY:
933 if (cur_cfg->val == PWR_DELAY_US)
934 udelay(cur_cfg->addr);
935 else
936 fsleep(cur_cfg->addr * 1000);
937 break;
938 default:
939 return -EINVAL;
940 }
941 }
942
943 return 0;
944 }
945
rtw89_mac_pwr_seq(struct rtw89_dev * rtwdev,const struct rtw89_pwr_cfg * const * cfg_seq)946 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev,
947 const struct rtw89_pwr_cfg * const *cfg_seq)
948 {
949 int ret;
950
951 for (; *cfg_seq; cfg_seq++) {
952 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv),
953 PWR_INTF_MSK_PCIE, *cfg_seq);
954 if (ret)
955 return -EBUSY;
956 }
957
958 return 0;
959 }
960
961 static enum rtw89_rpwm_req_pwr_state
rtw89_mac_get_req_pwr_state(struct rtw89_dev * rtwdev)962 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev)
963 {
964 enum rtw89_rpwm_req_pwr_state state;
965
966 switch (rtwdev->ps_mode) {
967 case RTW89_PS_MODE_RFOFF:
968 state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF;
969 break;
970 case RTW89_PS_MODE_CLK_GATED:
971 state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED;
972 break;
973 case RTW89_PS_MODE_PWR_GATED:
974 state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED;
975 break;
976 default:
977 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE;
978 break;
979 }
980 return state;
981 }
982
rtw89_mac_send_rpwm(struct rtw89_dev * rtwdev,enum rtw89_rpwm_req_pwr_state req_pwr_state,bool notify_wake)983 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev,
984 enum rtw89_rpwm_req_pwr_state req_pwr_state,
985 bool notify_wake)
986 {
987 u16 request;
988
989 spin_lock_bh(&rtwdev->rpwm_lock);
990
991 request = rtw89_read16(rtwdev, R_AX_RPWM);
992 request ^= request | PS_RPWM_TOGGLE;
993 request |= req_pwr_state;
994
995 if (notify_wake) {
996 request |= PS_RPWM_NOTIFY_WAKE;
997 } else {
998 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) &
999 RPWM_SEQ_NUM_MAX;
1000 request |= FIELD_PREP(PS_RPWM_SEQ_NUM,
1001 rtwdev->mac.rpwm_seq_num);
1002
1003 if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED)
1004 request |= PS_RPWM_ACK;
1005 }
1006 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request);
1007
1008 spin_unlock_bh(&rtwdev->rpwm_lock);
1009 }
1010
rtw89_mac_check_cpwm_state(struct rtw89_dev * rtwdev,enum rtw89_rpwm_req_pwr_state req_pwr_state)1011 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev,
1012 enum rtw89_rpwm_req_pwr_state req_pwr_state)
1013 {
1014 bool request_deep_mode;
1015 bool in_deep_mode;
1016 u8 rpwm_req_num;
1017 u8 cpwm_rsp_seq;
1018 u8 cpwm_seq;
1019 u8 cpwm_status;
1020
1021 if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED)
1022 request_deep_mode = true;
1023 else
1024 request_deep_mode = false;
1025
1026 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K))
1027 in_deep_mode = true;
1028 else
1029 in_deep_mode = false;
1030
1031 if (request_deep_mode != in_deep_mode)
1032 return -EPERM;
1033
1034 if (request_deep_mode)
1035 return 0;
1036
1037 rpwm_req_num = rtwdev->mac.rpwm_seq_num;
1038 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr,
1039 PS_CPWM_RSP_SEQ_NUM);
1040
1041 if (rpwm_req_num != cpwm_rsp_seq)
1042 return -EPERM;
1043
1044 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) &
1045 CPWM_SEQ_NUM_MAX;
1046
1047 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM);
1048 if (cpwm_seq != rtwdev->mac.cpwm_seq_num)
1049 return -EPERM;
1050
1051 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE);
1052 if (cpwm_status != req_pwr_state)
1053 return -EPERM;
1054
1055 return 0;
1056 }
1057
rtw89_mac_power_mode_change(struct rtw89_dev * rtwdev,bool enter)1058 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter)
1059 {
1060 enum rtw89_rpwm_req_pwr_state state;
1061 unsigned long delay = enter ? 10 : 150;
1062 int ret;
1063 int i;
1064
1065 if (enter)
1066 state = rtw89_mac_get_req_pwr_state(rtwdev);
1067 else
1068 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE;
1069
1070 for (i = 0; i < RPWM_TRY_CNT; i++) {
1071 rtw89_mac_send_rpwm(rtwdev, state, false);
1072 ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret,
1073 !ret, delay, 15000, false,
1074 rtwdev, state);
1075 if (!ret)
1076 break;
1077
1078 if (i == RPWM_TRY_CNT - 1)
1079 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n",
1080 enter ? "entering" : "leaving");
1081 else
1082 rtw89_debug(rtwdev, RTW89_DBG_UNEXP,
1083 "%d time firmware failed to ack for %s ps mode\n",
1084 i + 1, enter ? "entering" : "leaving");
1085 }
1086 }
1087
rtw89_mac_notify_wake(struct rtw89_dev * rtwdev)1088 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev)
1089 {
1090 enum rtw89_rpwm_req_pwr_state state;
1091
1092 state = rtw89_mac_get_req_pwr_state(rtwdev);
1093 rtw89_mac_send_rpwm(rtwdev, state, true);
1094 }
1095
rtw89_mac_power_switch(struct rtw89_dev * rtwdev,bool on)1096 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on)
1097 {
1098 #define PWR_ACT 1
1099 const struct rtw89_chip_info *chip = rtwdev->chip;
1100 const struct rtw89_pwr_cfg * const *cfg_seq;
1101 int (*cfg_func)(struct rtw89_dev *rtwdev);
1102 int ret;
1103 u8 val;
1104
1105 if (on) {
1106 cfg_seq = chip->pwr_on_seq;
1107 cfg_func = chip->ops->pwr_on_func;
1108 } else {
1109 cfg_seq = chip->pwr_off_seq;
1110 cfg_func = chip->ops->pwr_off_func;
1111 }
1112
1113 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
1114 __rtw89_leave_ps_mode(rtwdev);
1115
1116 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK);
1117 if (on && val == PWR_ACT) {
1118 rtw89_err(rtwdev, "MAC has already powered on\n");
1119 return -EBUSY;
1120 }
1121
1122 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq);
1123 if (ret)
1124 return ret;
1125
1126 if (on) {
1127 set_bit(RTW89_FLAG_POWERON, rtwdev->flags);
1128 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR);
1129 } else {
1130 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags);
1131 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);
1132 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR);
1133 rtw89_set_entity_state(rtwdev, false);
1134 }
1135
1136 return 0;
1137 #undef PWR_ACT
1138 }
1139
rtw89_mac_pwr_off(struct rtw89_dev * rtwdev)1140 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev)
1141 {
1142 rtw89_mac_power_switch(rtwdev, false);
1143 }
1144
cmac_func_en(struct rtw89_dev * rtwdev,u8 mac_idx,bool en)1145 static int cmac_func_en(struct rtw89_dev *rtwdev, u8 mac_idx, bool en)
1146 {
1147 u32 func_en = 0;
1148 u32 ck_en = 0;
1149 u32 c1pc_en = 0;
1150 u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1};
1151 u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1};
1152
1153 func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN |
1154 B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN |
1155 B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN |
1156 B_AX_CMAC_CRPRT;
1157 ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN |
1158 B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN |
1159 B_AX_RMAC_CKEN;
1160 c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN |
1161 B_AX_R_SYM_WLCMAC1_P1_PC_EN |
1162 B_AX_R_SYM_WLCMAC1_P2_PC_EN |
1163 B_AX_R_SYM_WLCMAC1_P3_PC_EN |
1164 B_AX_R_SYM_WLCMAC1_P4_PC_EN;
1165
1166 if (en) {
1167 if (mac_idx == RTW89_MAC_1) {
1168 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en);
1169 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
1170 B_AX_R_SYM_ISO_CMAC12PP);
1171 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
1172 B_AX_CMAC1_FEN);
1173 }
1174 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en);
1175 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en);
1176 } else {
1177 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en);
1178 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en);
1179 if (mac_idx == RTW89_MAC_1) {
1180 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
1181 B_AX_CMAC1_FEN);
1182 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
1183 B_AX_R_SYM_ISO_CMAC12PP);
1184 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en);
1185 }
1186 }
1187
1188 return 0;
1189 }
1190
dmac_func_en(struct rtw89_dev * rtwdev)1191 static int dmac_func_en(struct rtw89_dev *rtwdev)
1192 {
1193 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
1194 u32 val32;
1195
1196 if (chip_id == RTL8852C)
1197 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN |
1198 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN |
1199 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN |
1200 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN |
1201 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN |
1202 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN |
1203 B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN);
1204 else
1205 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN |
1206 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN |
1207 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN |
1208 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN |
1209 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN |
1210 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN |
1211 B_AX_DMAC_CRPRT);
1212 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32);
1213
1214 val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN |
1215 B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN |
1216 B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN |
1217 B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN);
1218 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32);
1219
1220 return 0;
1221 }
1222
chip_func_en(struct rtw89_dev * rtwdev)1223 static int chip_func_en(struct rtw89_dev *rtwdev)
1224 {
1225 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
1226
1227 if (chip_id == RTL8852A || chip_id == RTL8852B)
1228 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0,
1229 B_AX_OCP_L1_MASK);
1230
1231 return 0;
1232 }
1233
rtw89_mac_sys_init(struct rtw89_dev * rtwdev)1234 static int rtw89_mac_sys_init(struct rtw89_dev *rtwdev)
1235 {
1236 int ret;
1237
1238 ret = dmac_func_en(rtwdev);
1239 if (ret)
1240 return ret;
1241
1242 ret = cmac_func_en(rtwdev, 0, true);
1243 if (ret)
1244 return ret;
1245
1246 ret = chip_func_en(rtwdev);
1247 if (ret)
1248 return ret;
1249
1250 return ret;
1251 }
1252
1253 const struct rtw89_mac_size_set rtw89_mac_size = {
1254 .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0},
1255 /* PCIE 64 */
1256 .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,},
1257 /* DLFW */
1258 .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,},
1259 /* PCIE 64 */
1260 .wde_size6 = {RTW89_WDE_PG_64, 512, 0,},
1261 /* DLFW */
1262 .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,},
1263 /* 8852C DLFW */
1264 .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,},
1265 /* 8852C PCIE SCC */
1266 .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,},
1267 /* PCIE */
1268 .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,},
1269 /* DLFW */
1270 .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,},
1271 /* PCIE 64 */
1272 .ple_size6 = {RTW89_PLE_PG_128, 496, 16,},
1273 /* DLFW */
1274 .ple_size8 = {RTW89_PLE_PG_128, 64, 960,},
1275 /* 8852C DLFW */
1276 .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,},
1277 /* 8852C PCIE SCC */
1278 .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,},
1279 /* PCIE 64 */
1280 .wde_qt0 = {3792, 196, 0, 107,},
1281 /* DLFW */
1282 .wde_qt4 = {0, 0, 0, 0,},
1283 /* PCIE 64 */
1284 .wde_qt6 = {448, 48, 0, 16,},
1285 /* 8852C DLFW */
1286 .wde_qt17 = {0, 0, 0, 0,},
1287 /* 8852C PCIE SCC */
1288 .wde_qt18 = {3228, 60, 0, 40,},
1289 /* PCIE SCC */
1290 .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,},
1291 /* PCIE SCC */
1292 .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,},
1293 /* DLFW */
1294 .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,},
1295 /* PCIE 64 */
1296 .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,},
1297 /* DLFW 52C */
1298 .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,},
1299 /* DLFW 52C */
1300 .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,},
1301 /* 8852C PCIE SCC */
1302 .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,},
1303 /* 8852C PCIE SCC */
1304 .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,},
1305 /* PCIE 64 */
1306 .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,},
1307 };
1308 EXPORT_SYMBOL(rtw89_mac_size);
1309
get_dle_mem_cfg(struct rtw89_dev * rtwdev,enum rtw89_qta_mode mode)1310 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev,
1311 enum rtw89_qta_mode mode)
1312 {
1313 struct rtw89_mac_info *mac = &rtwdev->mac;
1314 const struct rtw89_dle_mem *cfg;
1315
1316 cfg = &rtwdev->chip->dle_mem[mode];
1317 if (!cfg)
1318 return NULL;
1319
1320 if (cfg->mode != mode) {
1321 rtw89_warn(rtwdev, "qta mode unmatch!\n");
1322 return NULL;
1323 }
1324
1325 mac->dle_info.wde_pg_size = cfg->wde_size->pge_size;
1326 mac->dle_info.ple_pg_size = cfg->ple_size->pge_size;
1327 mac->dle_info.qta_mode = mode;
1328 mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma;
1329 mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma;
1330
1331 return cfg;
1332 }
1333
dle_used_size(const struct rtw89_dle_size * wde,const struct rtw89_dle_size * ple)1334 static inline u32 dle_used_size(const struct rtw89_dle_size *wde,
1335 const struct rtw89_dle_size *ple)
1336 {
1337 return wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) +
1338 ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num);
1339 }
1340
dle_expected_used_size(struct rtw89_dev * rtwdev,enum rtw89_qta_mode mode)1341 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev,
1342 enum rtw89_qta_mode mode)
1343 {
1344 u32 size = rtwdev->chip->fifo_size;
1345
1346 if (mode == RTW89_QTA_SCC)
1347 size -= rtwdev->chip->dle_scc_rsvd_size;
1348
1349 return size;
1350 }
1351
dle_func_en(struct rtw89_dev * rtwdev,bool enable)1352 static void dle_func_en(struct rtw89_dev *rtwdev, bool enable)
1353 {
1354 if (enable)
1355 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
1356 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN);
1357 else
1358 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN,
1359 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN);
1360 }
1361
dle_clk_en(struct rtw89_dev * rtwdev,bool enable)1362 static void dle_clk_en(struct rtw89_dev *rtwdev, bool enable)
1363 {
1364 if (enable)
1365 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN,
1366 B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN);
1367 else
1368 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN,
1369 B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN);
1370 }
1371
dle_mix_cfg(struct rtw89_dev * rtwdev,const struct rtw89_dle_mem * cfg)1372 static int dle_mix_cfg(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg)
1373 {
1374 const struct rtw89_dle_size *size_cfg;
1375 u32 val;
1376 u8 bound = 0;
1377
1378 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG);
1379 size_cfg = cfg->wde_size;
1380
1381 switch (size_cfg->pge_size) {
1382 default:
1383 case RTW89_WDE_PG_64:
1384 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64,
1385 B_AX_WDE_PAGE_SEL_MASK);
1386 break;
1387 case RTW89_WDE_PG_128:
1388 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128,
1389 B_AX_WDE_PAGE_SEL_MASK);
1390 break;
1391 case RTW89_WDE_PG_256:
1392 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n");
1393 return -EINVAL;
1394 }
1395
1396 val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK);
1397 val = u32_replace_bits(val, size_cfg->lnk_pge_num,
1398 B_AX_WDE_FREE_PAGE_NUM_MASK);
1399 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val);
1400
1401 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG);
1402 bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num)
1403 * size_cfg->pge_size / DLE_BOUND_UNIT;
1404 size_cfg = cfg->ple_size;
1405
1406 switch (size_cfg->pge_size) {
1407 default:
1408 case RTW89_PLE_PG_64:
1409 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n");
1410 return -EINVAL;
1411 case RTW89_PLE_PG_128:
1412 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128,
1413 B_AX_PLE_PAGE_SEL_MASK);
1414 break;
1415 case RTW89_PLE_PG_256:
1416 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256,
1417 B_AX_PLE_PAGE_SEL_MASK);
1418 break;
1419 }
1420
1421 val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK);
1422 val = u32_replace_bits(val, size_cfg->lnk_pge_num,
1423 B_AX_PLE_FREE_PAGE_NUM_MASK);
1424 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val);
1425
1426 return 0;
1427 }
1428
1429 #define INVALID_QT_WCPU U16_MAX
1430 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \
1431 do { \
1432 val = ((_min_x) & \
1433 B_AX_ ## _module ## _MIN_SIZE_MASK) | \
1434 (((_max_x) << 16) & \
1435 B_AX_ ## _module ## _MAX_SIZE_MASK); \
1436 rtw89_write32(rtwdev, \
1437 R_AX_ ## _module ## _QTA ## _idx ## _CFG, \
1438 val); \
1439 } while (0)
1440 #define SET_QUOTA(_x, _module, _idx) \
1441 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx)
1442
wde_quota_cfg(struct rtw89_dev * rtwdev,const struct rtw89_wde_quota * min_cfg,const struct rtw89_wde_quota * max_cfg,u16 ext_wde_min_qt_wcpu)1443 static void wde_quota_cfg(struct rtw89_dev *rtwdev,
1444 const struct rtw89_wde_quota *min_cfg,
1445 const struct rtw89_wde_quota *max_cfg,
1446 u16 ext_wde_min_qt_wcpu)
1447 {
1448 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ?
1449 ext_wde_min_qt_wcpu : min_cfg->wcpu;
1450 u32 val;
1451
1452 SET_QUOTA(hif, WDE, 0);
1453 SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1);
1454 SET_QUOTA(pkt_in, WDE, 3);
1455 SET_QUOTA(cpu_io, WDE, 4);
1456 }
1457
ple_quota_cfg(struct rtw89_dev * rtwdev,const struct rtw89_ple_quota * min_cfg,const struct rtw89_ple_quota * max_cfg)1458 static void ple_quota_cfg(struct rtw89_dev *rtwdev,
1459 const struct rtw89_ple_quota *min_cfg,
1460 const struct rtw89_ple_quota *max_cfg)
1461 {
1462 u32 val;
1463
1464 SET_QUOTA(cma0_tx, PLE, 0);
1465 SET_QUOTA(cma1_tx, PLE, 1);
1466 SET_QUOTA(c2h, PLE, 2);
1467 SET_QUOTA(h2c, PLE, 3);
1468 SET_QUOTA(wcpu, PLE, 4);
1469 SET_QUOTA(mpdu_proc, PLE, 5);
1470 SET_QUOTA(cma0_dma, PLE, 6);
1471 SET_QUOTA(cma1_dma, PLE, 7);
1472 SET_QUOTA(bb_rpt, PLE, 8);
1473 SET_QUOTA(wd_rel, PLE, 9);
1474 SET_QUOTA(cpu_io, PLE, 10);
1475 if (rtwdev->chip->chip_id == RTL8852C)
1476 SET_QUOTA(tx_rpt, PLE, 11);
1477 }
1478
1479 #undef SET_QUOTA
1480
dle_quota_cfg(struct rtw89_dev * rtwdev,const struct rtw89_dle_mem * cfg,u16 ext_wde_min_qt_wcpu)1481 static void dle_quota_cfg(struct rtw89_dev *rtwdev,
1482 const struct rtw89_dle_mem *cfg,
1483 u16 ext_wde_min_qt_wcpu)
1484 {
1485 wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu);
1486 ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt);
1487 }
1488
dle_init(struct rtw89_dev * rtwdev,enum rtw89_qta_mode mode,enum rtw89_qta_mode ext_mode)1489 static int dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode,
1490 enum rtw89_qta_mode ext_mode)
1491 {
1492 const struct rtw89_dle_mem *cfg, *ext_cfg;
1493 u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU;
1494 int ret = 0;
1495 u32 ini;
1496
1497 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
1498 if (ret)
1499 return ret;
1500
1501 cfg = get_dle_mem_cfg(rtwdev, mode);
1502 if (!cfg) {
1503 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n");
1504 ret = -EINVAL;
1505 goto error;
1506 }
1507
1508 if (mode == RTW89_QTA_DLFW) {
1509 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode);
1510 if (!ext_cfg) {
1511 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n",
1512 ext_mode);
1513 ret = -EINVAL;
1514 goto error;
1515 }
1516 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu;
1517 }
1518
1519 if (dle_used_size(cfg->wde_size, cfg->ple_size) !=
1520 dle_expected_used_size(rtwdev, mode)) {
1521 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n");
1522 ret = -EINVAL;
1523 goto error;
1524 }
1525
1526 dle_func_en(rtwdev, false);
1527 dle_clk_en(rtwdev, true);
1528
1529 ret = dle_mix_cfg(rtwdev, cfg);
1530 if (ret) {
1531 rtw89_err(rtwdev, "[ERR] dle mix cfg\n");
1532 goto error;
1533 }
1534 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu);
1535
1536 dle_func_en(rtwdev, true);
1537
1538 ret = read_poll_timeout(rtw89_read32, ini,
1539 (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1,
1540 2000, false, rtwdev, R_AX_WDE_INI_STATUS);
1541 if (ret) {
1542 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n");
1543 return ret;
1544 }
1545
1546 ret = read_poll_timeout(rtw89_read32, ini,
1547 (ini & WDE_MGN_INI_RDY) == WDE_MGN_INI_RDY, 1,
1548 2000, false, rtwdev, R_AX_PLE_INI_STATUS);
1549 if (ret) {
1550 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n");
1551 return ret;
1552 }
1553
1554 return 0;
1555 error:
1556 dle_func_en(rtwdev, false);
1557 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n",
1558 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS));
1559 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n",
1560 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS));
1561
1562 return ret;
1563 }
1564
preload_init_set(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx,enum rtw89_qta_mode mode)1565 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx,
1566 enum rtw89_qta_mode mode)
1567 {
1568 u32 reg, max_preld_size, min_rsvd_size;
1569
1570 max_preld_size = (mac_idx == RTW89_MAC_0 ?
1571 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE;
1572 reg = mac_idx == RTW89_MAC_0 ?
1573 R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0;
1574 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size);
1575 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN);
1576
1577 min_rsvd_size = PRELD_AMSDU_SIZE;
1578 reg = mac_idx == RTW89_MAC_0 ?
1579 R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1;
1580 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND);
1581 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size);
1582
1583 return 0;
1584 }
1585
is_qta_poh(struct rtw89_dev * rtwdev)1586 static bool is_qta_poh(struct rtw89_dev *rtwdev)
1587 {
1588 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE;
1589 }
1590
preload_init(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx,enum rtw89_qta_mode mode)1591 static int preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx,
1592 enum rtw89_qta_mode mode)
1593 {
1594 const struct rtw89_chip_info *chip = rtwdev->chip;
1595
1596 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || !is_qta_poh(rtwdev))
1597 return 0;
1598
1599 return preload_init_set(rtwdev, mac_idx, mode);
1600 }
1601
dle_is_txq_empty(struct rtw89_dev * rtwdev)1602 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev)
1603 {
1604 u32 msk32;
1605 u32 val32;
1606
1607 msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH |
1608 B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 |
1609 B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS |
1610 B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C |
1611 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN |
1612 B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU |
1613 B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO |
1614 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL |
1615 B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL |
1616 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX |
1617 B_AX_PLE_EMPTY_QTA_DMAC_CPUIO |
1618 B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU |
1619 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU;
1620 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0);
1621
1622 if ((val32 & msk32) == msk32)
1623 return true;
1624
1625 return false;
1626 }
1627
_patch_ss2f_path(struct rtw89_dev * rtwdev)1628 static void _patch_ss2f_path(struct rtw89_dev *rtwdev)
1629 {
1630 const struct rtw89_chip_info *chip = rtwdev->chip;
1631
1632 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B)
1633 return;
1634
1635 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK,
1636 SS2F_PATH_WLCPU);
1637 }
1638
sta_sch_init(struct rtw89_dev * rtwdev)1639 static int sta_sch_init(struct rtw89_dev *rtwdev)
1640 {
1641 u32 p_val;
1642 u8 val;
1643 int ret;
1644
1645 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
1646 if (ret)
1647 return ret;
1648
1649 val = rtw89_read8(rtwdev, R_AX_SS_CTRL);
1650 val |= B_AX_SS_EN;
1651 rtw89_write8(rtwdev, R_AX_SS_CTRL, val);
1652
1653 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1,
1654 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL);
1655 if (ret) {
1656 rtw89_err(rtwdev, "[ERR]STA scheduler init\n");
1657 return ret;
1658 }
1659
1660 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG);
1661 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN);
1662
1663 _patch_ss2f_path(rtwdev);
1664
1665 return 0;
1666 }
1667
mpdu_proc_init(struct rtw89_dev * rtwdev)1668 static int mpdu_proc_init(struct rtw89_dev *rtwdev)
1669 {
1670 int ret;
1671
1672 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
1673 if (ret)
1674 return ret;
1675
1676 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD);
1677 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD);
1678 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC,
1679 B_AX_APPEND_FCS | B_AX_A_ICV_ERR);
1680 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL);
1681
1682 return 0;
1683 }
1684
sec_eng_init(struct rtw89_dev * rtwdev)1685 static int sec_eng_init(struct rtw89_dev *rtwdev)
1686 {
1687 const struct rtw89_chip_info *chip = rtwdev->chip;
1688 u32 val = 0;
1689 int ret;
1690
1691 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
1692 if (ret)
1693 return ret;
1694
1695 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL);
1696 /* init clock */
1697 val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP);
1698 /* init TX encryption */
1699 val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC);
1700 val |= (B_AX_MC_DEC | B_AX_BC_DEC);
1701 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B)
1702 val &= ~B_AX_TX_PARTIAL_MODE;
1703 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val);
1704
1705 /* init MIC ICV append */
1706 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC);
1707 val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC);
1708
1709 /* option init */
1710 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val);
1711
1712 if (chip->chip_id == RTL8852C)
1713 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1,
1714 B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL);
1715
1716 return 0;
1717 }
1718
dmac_init(struct rtw89_dev * rtwdev,u8 mac_idx)1719 static int dmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)
1720 {
1721 int ret;
1722
1723 ret = dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID);
1724 if (ret) {
1725 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret);
1726 return ret;
1727 }
1728
1729 ret = preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode);
1730 if (ret) {
1731 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret);
1732 return ret;
1733 }
1734
1735 ret = hfc_init(rtwdev, true, true, true);
1736 if (ret) {
1737 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret);
1738 return ret;
1739 }
1740
1741 ret = sta_sch_init(rtwdev);
1742 if (ret) {
1743 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret);
1744 return ret;
1745 }
1746
1747 ret = mpdu_proc_init(rtwdev);
1748 if (ret) {
1749 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret);
1750 return ret;
1751 }
1752
1753 ret = sec_eng_init(rtwdev);
1754 if (ret) {
1755 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret);
1756 return ret;
1757 }
1758
1759 return ret;
1760 }
1761
addr_cam_init(struct rtw89_dev * rtwdev,u8 mac_idx)1762 static int addr_cam_init(struct rtw89_dev *rtwdev, u8 mac_idx)
1763 {
1764 u32 val, reg;
1765 u16 p_val;
1766 int ret;
1767
1768 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1769 if (ret)
1770 return ret;
1771
1772 reg = rtw89_mac_reg_by_idx(R_AX_ADDR_CAM_CTRL, mac_idx);
1773
1774 val = rtw89_read32(rtwdev, reg);
1775 val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) |
1776 B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN;
1777 rtw89_write32(rtwdev, reg, val);
1778
1779 ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR),
1780 1, TRXCFG_WAIT_CNT, false, rtwdev, reg);
1781 if (ret) {
1782 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n");
1783 return ret;
1784 }
1785
1786 return 0;
1787 }
1788
scheduler_init(struct rtw89_dev * rtwdev,u8 mac_idx)1789 static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx)
1790 {
1791 u32 ret;
1792 u32 reg;
1793 u32 val;
1794
1795 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1796 if (ret)
1797 return ret;
1798
1799 reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_1, mac_idx);
1800 if (rtwdev->chip->chip_id == RTL8852C)
1801 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK,
1802 SIFS_MACTXEN_T1_V1);
1803 else
1804 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK,
1805 SIFS_MACTXEN_T1);
1806
1807 if (rtwdev->chip->chip_id == RTL8852B) {
1808 reg = rtw89_mac_reg_by_idx(R_AX_SCH_EXT_CTRL, mac_idx);
1809 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV);
1810 }
1811
1812 reg = rtw89_mac_reg_by_idx(R_AX_CCA_CFG_0, mac_idx);
1813 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN);
1814
1815 reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_0, mac_idx);
1816 if (rtwdev->chip->chip_id == RTL8852C) {
1817 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL,
1818 B_AX_TX_PARTIAL_MODE);
1819 if (!val)
1820 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK,
1821 SCH_PREBKF_24US);
1822 } else {
1823 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK,
1824 SCH_PREBKF_24US);
1825 }
1826
1827 return 0;
1828 }
1829
rtw89_mac_typ_fltr_opt(struct rtw89_dev * rtwdev,enum rtw89_machdr_frame_type type,enum rtw89_mac_fwd_target fwd_target,u8 mac_idx)1830 static int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev,
1831 enum rtw89_machdr_frame_type type,
1832 enum rtw89_mac_fwd_target fwd_target,
1833 u8 mac_idx)
1834 {
1835 u32 reg;
1836 u32 val;
1837
1838 switch (fwd_target) {
1839 case RTW89_FWD_DONT_CARE:
1840 val = RX_FLTR_FRAME_DROP;
1841 break;
1842 case RTW89_FWD_TO_HOST:
1843 val = RX_FLTR_FRAME_TO_HOST;
1844 break;
1845 case RTW89_FWD_TO_WLAN_CPU:
1846 val = RX_FLTR_FRAME_TO_WLCPU;
1847 break;
1848 default:
1849 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n");
1850 return -EINVAL;
1851 }
1852
1853 switch (type) {
1854 case RTW89_MGNT:
1855 reg = rtw89_mac_reg_by_idx(R_AX_MGNT_FLTR, mac_idx);
1856 break;
1857 case RTW89_CTRL:
1858 reg = rtw89_mac_reg_by_idx(R_AX_CTRL_FLTR, mac_idx);
1859 break;
1860 case RTW89_DATA:
1861 reg = rtw89_mac_reg_by_idx(R_AX_DATA_FLTR, mac_idx);
1862 break;
1863 default:
1864 rtw89_err(rtwdev, "[ERR]set rx filter type err\n");
1865 return -EINVAL;
1866 }
1867 rtw89_write32(rtwdev, reg, val);
1868
1869 return 0;
1870 }
1871
rx_fltr_init(struct rtw89_dev * rtwdev,u8 mac_idx)1872 static int rx_fltr_init(struct rtw89_dev *rtwdev, u8 mac_idx)
1873 {
1874 int ret, i;
1875 u32 mac_ftlr, plcp_ftlr;
1876
1877 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1878 if (ret)
1879 return ret;
1880
1881 for (i = RTW89_MGNT; i <= RTW89_DATA; i++) {
1882 ret = rtw89_mac_typ_fltr_opt(rtwdev, i, RTW89_FWD_TO_HOST,
1883 mac_idx);
1884 if (ret)
1885 return ret;
1886 }
1887 mac_ftlr = rtwdev->hal.rx_fltr;
1888 plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK |
1889 B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK |
1890 B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK |
1891 B_AX_HE_SIGB_CRC_CHK;
1892 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx),
1893 mac_ftlr);
1894 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx),
1895 plcp_ftlr);
1896
1897 return 0;
1898 }
1899
_patch_dis_resp_chk(struct rtw89_dev * rtwdev,u8 mac_idx)1900 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx)
1901 {
1902 u32 reg, val32;
1903 u32 b_rsp_chk_nav, b_rsp_chk_cca;
1904
1905 b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV |
1906 B_AX_RSP_CHK_BASIC_NAV;
1907 b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 |
1908 B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA |
1909 B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA;
1910
1911 switch (rtwdev->chip->chip_id) {
1912 case RTL8852A:
1913 case RTL8852B:
1914 reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx);
1915 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav;
1916 rtw89_write32(rtwdev, reg, val32);
1917
1918 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx);
1919 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca;
1920 rtw89_write32(rtwdev, reg, val32);
1921 break;
1922 default:
1923 reg = rtw89_mac_reg_by_idx(R_AX_RSP_CHK_SIG, mac_idx);
1924 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav;
1925 rtw89_write32(rtwdev, reg, val32);
1926
1927 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx);
1928 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca;
1929 rtw89_write32(rtwdev, reg, val32);
1930 break;
1931 }
1932 }
1933
cca_ctrl_init(struct rtw89_dev * rtwdev,u8 mac_idx)1934 static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx)
1935 {
1936 u32 val, reg;
1937 int ret;
1938
1939 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1940 if (ret)
1941 return ret;
1942
1943 reg = rtw89_mac_reg_by_idx(R_AX_CCA_CONTROL, mac_idx);
1944 val = rtw89_read32(rtwdev, reg);
1945 val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA |
1946 B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 |
1947 B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 |
1948 B_AX_CTN_CHK_INTRA_NAV |
1949 B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA |
1950 B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 |
1951 B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 |
1952 B_AX_CTN_CHK_CCA_P20);
1953 val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 |
1954 B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 |
1955 B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 |
1956 B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV |
1957 B_AX_SIFS_CHK_EDCCA);
1958
1959 rtw89_write32(rtwdev, reg, val);
1960
1961 _patch_dis_resp_chk(rtwdev, mac_idx);
1962
1963 return 0;
1964 }
1965
nav_ctrl_init(struct rtw89_dev * rtwdev)1966 static int nav_ctrl_init(struct rtw89_dev *rtwdev)
1967 {
1968 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN |
1969 B_AX_WMAC_TF_UP_NAV_EN |
1970 B_AX_WMAC_NAV_UPPER_EN);
1971 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS);
1972
1973 return 0;
1974 }
1975
spatial_reuse_init(struct rtw89_dev * rtwdev,u8 mac_idx)1976 static int spatial_reuse_init(struct rtw89_dev *rtwdev, u8 mac_idx)
1977 {
1978 u32 reg;
1979 int ret;
1980
1981 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1982 if (ret)
1983 return ret;
1984 reg = rtw89_mac_reg_by_idx(R_AX_RX_SR_CTRL, mac_idx);
1985 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN);
1986
1987 return 0;
1988 }
1989
tmac_init(struct rtw89_dev * rtwdev,u8 mac_idx)1990 static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)
1991 {
1992 u32 reg;
1993 int ret;
1994
1995 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
1996 if (ret)
1997 return ret;
1998
1999 reg = rtw89_mac_reg_by_idx(R_AX_MAC_LOOPBACK, mac_idx);
2000 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN);
2001
2002 reg = rtw89_mac_reg_by_idx(R_AX_TCR0, mac_idx);
2003 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD);
2004
2005 reg = rtw89_mac_reg_by_idx(R_AX_TXD_FIFO_CTRL, mac_idx);
2006 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE);
2007 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE);
2008
2009 return 0;
2010 }
2011
trxptcl_init(struct rtw89_dev * rtwdev,u8 mac_idx)2012 static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2013 {
2014 const struct rtw89_chip_info *chip = rtwdev->chip;
2015 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs;
2016 u32 reg, val, sifs;
2017 int ret;
2018
2019 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2020 if (ret)
2021 return ret;
2022
2023 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_0, mac_idx);
2024 val = rtw89_read32(rtwdev, reg);
2025 val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK;
2026 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK);
2027
2028 switch (rtwdev->chip->chip_id) {
2029 case RTL8852A:
2030 sifs = WMAC_SPEC_SIFS_OFDM_52A;
2031 break;
2032 case RTL8852B:
2033 sifs = WMAC_SPEC_SIFS_OFDM_52B;
2034 break;
2035 default:
2036 sifs = WMAC_SPEC_SIFS_OFDM_52C;
2037 break;
2038 }
2039 val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK;
2040 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs);
2041 rtw89_write32(rtwdev, reg, val);
2042
2043 reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, mac_idx);
2044 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN);
2045
2046 reg = rtw89_mac_reg_by_idx(rrsr->ref_rate.addr, mac_idx);
2047 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data);
2048 reg = rtw89_mac_reg_by_idx(rrsr->rsc.addr, mac_idx);
2049 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data);
2050
2051 return 0;
2052 }
2053
rst_bacam(struct rtw89_dev * rtwdev)2054 static void rst_bacam(struct rtw89_dev *rtwdev)
2055 {
2056 u32 val32;
2057 int ret;
2058
2059 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK,
2060 S_AX_BACAM_RST_ALL);
2061
2062 ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0,
2063 1, 1000, false,
2064 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK);
2065 if (ret)
2066 rtw89_warn(rtwdev, "failed to reset BA CAM\n");
2067 }
2068
rmac_init(struct rtw89_dev * rtwdev,u8 mac_idx)2069 static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2070 {
2071 #define TRXCFG_RMAC_CCA_TO 32
2072 #define TRXCFG_RMAC_DATA_TO 15
2073 #define RX_MAX_LEN_UNIT 512
2074 #define PLD_RLS_MAX_PG 127
2075 #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT)
2076 int ret;
2077 u32 reg, rx_max_len, rx_qta;
2078 u16 val;
2079
2080 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2081 if (ret)
2082 return ret;
2083
2084 if (mac_idx == RTW89_MAC_0)
2085 rst_bacam(rtwdev);
2086
2087 reg = rtw89_mac_reg_by_idx(R_AX_RESPBA_CAM_CTRL, mac_idx);
2088 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL);
2089
2090 reg = rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx);
2091 val = rtw89_read16(rtwdev, reg);
2092 val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO,
2093 B_AX_RX_DLK_DATA_TIME_MASK);
2094 val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO,
2095 B_AX_RX_DLK_CCA_TIME_MASK);
2096 rtw89_write16(rtwdev, reg, val);
2097
2098 reg = rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx);
2099 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1);
2100
2101 reg = rtw89_mac_reg_by_idx(R_AX_RX_FLTR_OPT, mac_idx);
2102 if (mac_idx == RTW89_MAC_0)
2103 rx_qta = rtwdev->mac.dle_info.c0_rx_qta;
2104 else
2105 rx_qta = rtwdev->mac.dle_info.c1_rx_qta;
2106 rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG);
2107 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size;
2108 rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN);
2109 rx_max_len /= RX_MAX_LEN_UNIT;
2110 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len);
2111
2112 if (rtwdev->chip->chip_id == RTL8852A &&
2113 rtwdev->hal.cv == CHIP_CBV) {
2114 rtw89_write16_mask(rtwdev,
2115 rtw89_mac_reg_by_idx(R_AX_DLK_PROTECT_CTL, mac_idx),
2116 B_AX_RX_DLK_CCA_TIME_MASK, 0);
2117 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(R_AX_RCR, mac_idx),
2118 BIT(12));
2119 }
2120
2121 reg = rtw89_mac_reg_by_idx(R_AX_PLCP_HDR_FLTR, mac_idx);
2122 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK);
2123
2124 return ret;
2125 }
2126
cmac_com_init(struct rtw89_dev * rtwdev,u8 mac_idx)2127 static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2128 {
2129 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2130 u32 val, reg;
2131 int ret;
2132
2133 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2134 if (ret)
2135 return ret;
2136
2137 reg = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, mac_idx);
2138 val = rtw89_read32(rtwdev, reg);
2139 val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK);
2140 val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK);
2141 val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK);
2142 rtw89_write32(rtwdev, reg, val);
2143
2144 if (chip_id == RTL8852A || chip_id == RTL8852B) {
2145 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_RRSR1, mac_idx);
2146 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN);
2147 }
2148
2149 return 0;
2150 }
2151
is_qta_dbcc(struct rtw89_dev * rtwdev,enum rtw89_qta_mode mode)2152 static bool is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode)
2153 {
2154 const struct rtw89_dle_mem *cfg;
2155
2156 cfg = get_dle_mem_cfg(rtwdev, mode);
2157 if (!cfg) {
2158 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n");
2159 return false;
2160 }
2161
2162 return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma);
2163 }
2164
ptcl_init(struct rtw89_dev * rtwdev,u8 mac_idx)2165 static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2166 {
2167 u32 val, reg;
2168 int ret;
2169
2170 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2171 if (ret)
2172 return ret;
2173
2174 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) {
2175 reg = rtw89_mac_reg_by_idx(R_AX_SIFS_SETTING, mac_idx);
2176 val = rtw89_read32(rtwdev, reg);
2177 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K,
2178 B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK);
2179 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B,
2180 B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK);
2181 val |= B_AX_HW_CTS2SELF_EN;
2182 rtw89_write32(rtwdev, reg, val);
2183
2184 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_FSM_MON, mac_idx);
2185 val = rtw89_read32(rtwdev, reg);
2186 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK);
2187 val &= ~B_AX_PTCL_TX_ARB_TO_MODE;
2188 rtw89_write32(rtwdev, reg, val);
2189 }
2190
2191 if (mac_idx == RTW89_MAC_0) {
2192 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0,
2193 B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1);
2194 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0,
2195 B_AX_PTCL_TRIGGER_SS_EN_0 |
2196 B_AX_PTCL_TRIGGER_SS_EN_1 |
2197 B_AX_PTCL_TRIGGER_SS_EN_UL);
2198 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL,
2199 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU);
2200 } else if (mac_idx == RTW89_MAC_1) {
2201 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1,
2202 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU);
2203 }
2204
2205 return 0;
2206 }
2207
cmac_dma_init(struct rtw89_dev * rtwdev,u8 mac_idx)2208 static int cmac_dma_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2209 {
2210 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2211 u32 reg;
2212 int ret;
2213
2214 if (chip_id != RTL8852A && chip_id != RTL8852B)
2215 return 0;
2216
2217 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2218 if (ret)
2219 return ret;
2220
2221 reg = rtw89_mac_reg_by_idx(R_AX_RXDMA_CTRL_0, mac_idx);
2222 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE);
2223
2224 return 0;
2225 }
2226
cmac_init(struct rtw89_dev * rtwdev,u8 mac_idx)2227 static int cmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2228 {
2229 int ret;
2230
2231 ret = scheduler_init(rtwdev, mac_idx);
2232 if (ret) {
2233 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret);
2234 return ret;
2235 }
2236
2237 ret = addr_cam_init(rtwdev, mac_idx);
2238 if (ret) {
2239 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx,
2240 ret);
2241 return ret;
2242 }
2243
2244 ret = rx_fltr_init(rtwdev, mac_idx);
2245 if (ret) {
2246 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx,
2247 ret);
2248 return ret;
2249 }
2250
2251 ret = cca_ctrl_init(rtwdev, mac_idx);
2252 if (ret) {
2253 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx,
2254 ret);
2255 return ret;
2256 }
2257
2258 ret = nav_ctrl_init(rtwdev);
2259 if (ret) {
2260 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx,
2261 ret);
2262 return ret;
2263 }
2264
2265 ret = spatial_reuse_init(rtwdev, mac_idx);
2266 if (ret) {
2267 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n",
2268 mac_idx, ret);
2269 return ret;
2270 }
2271
2272 ret = tmac_init(rtwdev, mac_idx);
2273 if (ret) {
2274 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret);
2275 return ret;
2276 }
2277
2278 ret = trxptcl_init(rtwdev, mac_idx);
2279 if (ret) {
2280 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret);
2281 return ret;
2282 }
2283
2284 ret = rmac_init(rtwdev, mac_idx);
2285 if (ret) {
2286 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret);
2287 return ret;
2288 }
2289
2290 ret = cmac_com_init(rtwdev, mac_idx);
2291 if (ret) {
2292 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret);
2293 return ret;
2294 }
2295
2296 ret = ptcl_init(rtwdev, mac_idx);
2297 if (ret) {
2298 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret);
2299 return ret;
2300 }
2301
2302 ret = cmac_dma_init(rtwdev, mac_idx);
2303 if (ret) {
2304 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret);
2305 return ret;
2306 }
2307
2308 return ret;
2309 }
2310
rtw89_mac_read_phycap(struct rtw89_dev * rtwdev,struct rtw89_mac_c2h_info * c2h_info)2311 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev,
2312 struct rtw89_mac_c2h_info *c2h_info)
2313 {
2314 struct rtw89_mac_h2c_info h2c_info = {0};
2315 u32 ret;
2316
2317 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE;
2318 h2c_info.content_len = 0;
2319
2320 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info);
2321 if (ret)
2322 return ret;
2323
2324 if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP)
2325 return -EINVAL;
2326
2327 return 0;
2328 }
2329
rtw89_mac_setup_phycap(struct rtw89_dev * rtwdev)2330 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev)
2331 {
2332 struct rtw89_hal *hal = &rtwdev->hal;
2333 const struct rtw89_chip_info *chip = rtwdev->chip;
2334 struct rtw89_mac_c2h_info c2h_info = {0};
2335 u8 tx_nss;
2336 u8 rx_nss;
2337 u8 tx_ant;
2338 u8 rx_ant;
2339 u32 ret;
2340
2341 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info);
2342 if (ret)
2343 return ret;
2344
2345 tx_nss = RTW89_GET_C2H_PHYCAP_TX_NSS(c2h_info.c2hreg);
2346 rx_nss = RTW89_GET_C2H_PHYCAP_RX_NSS(c2h_info.c2hreg);
2347 tx_ant = RTW89_GET_C2H_PHYCAP_ANT_TX_NUM(c2h_info.c2hreg);
2348 rx_ant = RTW89_GET_C2H_PHYCAP_ANT_RX_NUM(c2h_info.c2hreg);
2349
2350 hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss;
2351 hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss;
2352
2353 if (tx_ant == 1)
2354 hal->antenna_tx = RF_B;
2355 if (rx_ant == 1)
2356 hal->antenna_rx = RF_B;
2357
2358 if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) {
2359 hal->antenna_tx = RF_B;
2360 hal->tx_path_diversity = true;
2361 }
2362
2363 rtw89_debug(rtwdev, RTW89_DBG_FW,
2364 "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n",
2365 hal->tx_nss, tx_nss, chip->tx_nss,
2366 hal->rx_nss, rx_nss, chip->rx_nss);
2367 rtw89_debug(rtwdev, RTW89_DBG_FW,
2368 "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n",
2369 tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx);
2370 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity);
2371
2372 return 0;
2373 }
2374
rtw89_hw_sch_tx_en_h2c(struct rtw89_dev * rtwdev,u8 band,u16 tx_en_u16,u16 mask_u16)2375 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band,
2376 u16 tx_en_u16, u16 mask_u16)
2377 {
2378 u32 ret;
2379 struct rtw89_mac_c2h_info c2h_info = {0};
2380 struct rtw89_mac_h2c_info h2c_info = {0};
2381 struct rtw89_h2creg_sch_tx_en *h2creg =
2382 (struct rtw89_h2creg_sch_tx_en *)h2c_info.h2creg;
2383
2384 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN;
2385 h2c_info.content_len = sizeof(*h2creg) - RTW89_H2CREG_HDR_LEN;
2386 h2creg->tx_en = tx_en_u16;
2387 h2creg->mask = mask_u16;
2388 h2creg->band = band;
2389
2390 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info);
2391 if (ret)
2392 return ret;
2393
2394 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT)
2395 return -EINVAL;
2396
2397 return 0;
2398 }
2399
rtw89_set_hw_sch_tx_en(struct rtw89_dev * rtwdev,u8 mac_idx,u16 tx_en,u16 tx_en_mask)2400 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx,
2401 u16 tx_en, u16 tx_en_mask)
2402 {
2403 u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx);
2404 u16 val;
2405 int ret;
2406
2407 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2408 if (ret)
2409 return ret;
2410
2411 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
2412 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx,
2413 tx_en, tx_en_mask);
2414
2415 val = rtw89_read16(rtwdev, reg);
2416 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask);
2417 rtw89_write16(rtwdev, reg, val);
2418
2419 return 0;
2420 }
2421
rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev * rtwdev,u8 mac_idx,u32 tx_en,u32 tx_en_mask)2422 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx,
2423 u32 tx_en, u32 tx_en_mask)
2424 {
2425 u32 reg = rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx);
2426 u32 val;
2427 int ret;
2428
2429 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2430 if (ret)
2431 return ret;
2432
2433 val = rtw89_read32(rtwdev, reg);
2434 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask);
2435 rtw89_write32(rtwdev, reg, val);
2436
2437 return 0;
2438 }
2439
rtw89_mac_stop_sch_tx(struct rtw89_dev * rtwdev,u8 mac_idx,u32 * tx_en,enum rtw89_sch_tx_sel sel)2440 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
2441 u32 *tx_en, enum rtw89_sch_tx_sel sel)
2442 {
2443 int ret;
2444
2445 *tx_en = rtw89_read16(rtwdev,
2446 rtw89_mac_reg_by_idx(R_AX_CTN_TXEN, mac_idx));
2447
2448 switch (sel) {
2449 case RTW89_SCH_TX_SEL_ALL:
2450 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0,
2451 B_AX_CTN_TXEN_ALL_MASK);
2452 if (ret)
2453 return ret;
2454 break;
2455 case RTW89_SCH_TX_SEL_HIQ:
2456 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx,
2457 0, B_AX_CTN_TXEN_HGQ);
2458 if (ret)
2459 return ret;
2460 break;
2461 case RTW89_SCH_TX_SEL_MG0:
2462 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx,
2463 0, B_AX_CTN_TXEN_MGQ);
2464 if (ret)
2465 return ret;
2466 break;
2467 case RTW89_SCH_TX_SEL_MACID:
2468 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0,
2469 B_AX_CTN_TXEN_ALL_MASK);
2470 if (ret)
2471 return ret;
2472 break;
2473 default:
2474 return 0;
2475 }
2476
2477 return 0;
2478 }
2479 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx);
2480
rtw89_mac_stop_sch_tx_v1(struct rtw89_dev * rtwdev,u8 mac_idx,u32 * tx_en,enum rtw89_sch_tx_sel sel)2481 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx,
2482 u32 *tx_en, enum rtw89_sch_tx_sel sel)
2483 {
2484 int ret;
2485
2486 *tx_en = rtw89_read32(rtwdev,
2487 rtw89_mac_reg_by_idx(R_AX_CTN_DRV_TXEN, mac_idx));
2488
2489 switch (sel) {
2490 case RTW89_SCH_TX_SEL_ALL:
2491 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0,
2492 B_AX_CTN_TXEN_ALL_MASK_V1);
2493 if (ret)
2494 return ret;
2495 break;
2496 case RTW89_SCH_TX_SEL_HIQ:
2497 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx,
2498 0, B_AX_CTN_TXEN_HGQ);
2499 if (ret)
2500 return ret;
2501 break;
2502 case RTW89_SCH_TX_SEL_MG0:
2503 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx,
2504 0, B_AX_CTN_TXEN_MGQ);
2505 if (ret)
2506 return ret;
2507 break;
2508 case RTW89_SCH_TX_SEL_MACID:
2509 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0,
2510 B_AX_CTN_TXEN_ALL_MASK_V1);
2511 if (ret)
2512 return ret;
2513 break;
2514 default:
2515 return 0;
2516 }
2517
2518 return 0;
2519 }
2520 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1);
2521
rtw89_mac_resume_sch_tx(struct rtw89_dev * rtwdev,u8 mac_idx,u32 tx_en)2522 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
2523 {
2524 int ret;
2525
2526 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK);
2527 if (ret)
2528 return ret;
2529
2530 return 0;
2531 }
2532 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx);
2533
rtw89_mac_resume_sch_tx_v1(struct rtw89_dev * rtwdev,u8 mac_idx,u32 tx_en)2534 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
2535 {
2536 int ret;
2537
2538 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en,
2539 B_AX_CTN_TXEN_ALL_MASK_V1);
2540 if (ret)
2541 return ret;
2542
2543 return 0;
2544 }
2545 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1);
2546
rtw89_mac_dle_buf_req(struct rtw89_dev * rtwdev,u16 buf_len,bool wd)2547 u16 rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, bool wd)
2548 {
2549 u32 val, reg;
2550 int ret;
2551
2552 reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ;
2553 val = buf_len;
2554 val |= B_AX_WD_BUF_REQ_EXEC;
2555 rtw89_write32(rtwdev, reg, val);
2556
2557 reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS;
2558
2559 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE,
2560 1, 2000, false, rtwdev, reg);
2561 if (ret)
2562 return 0xffff;
2563
2564 return FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val);
2565 }
2566
rtw89_mac_set_cpuio(struct rtw89_dev * rtwdev,struct rtw89_cpuio_ctrl * ctrl_para,bool wd)2567 int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev,
2568 struct rtw89_cpuio_ctrl *ctrl_para, bool wd)
2569 {
2570 u32 val, cmd_type, reg;
2571 int ret;
2572
2573 cmd_type = ctrl_para->cmd_type;
2574
2575 reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2;
2576 val = 0;
2577 val = u32_replace_bits(val, ctrl_para->start_pktid,
2578 B_AX_WD_CPUQ_OP_STRT_PKTID_MASK);
2579 val = u32_replace_bits(val, ctrl_para->end_pktid,
2580 B_AX_WD_CPUQ_OP_END_PKTID_MASK);
2581 rtw89_write32(rtwdev, reg, val);
2582
2583 reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1;
2584 val = 0;
2585 val = u32_replace_bits(val, ctrl_para->src_pid,
2586 B_AX_CPUQ_OP_SRC_PID_MASK);
2587 val = u32_replace_bits(val, ctrl_para->src_qid,
2588 B_AX_CPUQ_OP_SRC_QID_MASK);
2589 val = u32_replace_bits(val, ctrl_para->dst_pid,
2590 B_AX_CPUQ_OP_DST_PID_MASK);
2591 val = u32_replace_bits(val, ctrl_para->dst_qid,
2592 B_AX_CPUQ_OP_DST_QID_MASK);
2593 rtw89_write32(rtwdev, reg, val);
2594
2595 reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0;
2596 val = 0;
2597 val = u32_replace_bits(val, cmd_type,
2598 B_AX_CPUQ_OP_CMD_TYPE_MASK);
2599 val = u32_replace_bits(val, ctrl_para->macid,
2600 B_AX_CPUQ_OP_MACID_MASK);
2601 val = u32_replace_bits(val, ctrl_para->pkt_num,
2602 B_AX_CPUQ_OP_PKTNUM_MASK);
2603 val |= B_AX_WD_CPUQ_OP_EXEC;
2604 rtw89_write32(rtwdev, reg, val);
2605
2606 reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS;
2607
2608 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE,
2609 1, 2000, false, rtwdev, reg);
2610 if (ret)
2611 return ret;
2612
2613 if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID ||
2614 cmd_type == CPUIO_OP_CMD_GET_NEXT_PID)
2615 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val);
2616
2617 return 0;
2618 }
2619
dle_quota_change(struct rtw89_dev * rtwdev,enum rtw89_qta_mode mode)2620 static int dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode)
2621 {
2622 const struct rtw89_dle_mem *cfg;
2623 struct rtw89_cpuio_ctrl ctrl_para = {0};
2624 u16 pkt_id;
2625 int ret;
2626
2627 cfg = get_dle_mem_cfg(rtwdev, mode);
2628 if (!cfg) {
2629 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n");
2630 return -EINVAL;
2631 }
2632
2633 if (dle_used_size(cfg->wde_size, cfg->ple_size) !=
2634 dle_expected_used_size(rtwdev, mode)) {
2635 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n");
2636 return -EINVAL;
2637 }
2638
2639 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU);
2640
2641 pkt_id = rtw89_mac_dle_buf_req(rtwdev, 0x20, true);
2642 if (pkt_id == 0xffff) {
2643 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n");
2644 return -ENOMEM;
2645 }
2646
2647 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD;
2648 ctrl_para.start_pktid = pkt_id;
2649 ctrl_para.end_pktid = pkt_id;
2650 ctrl_para.pkt_num = 0;
2651 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS;
2652 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT;
2653 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true);
2654 if (ret) {
2655 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n");
2656 return -EFAULT;
2657 }
2658
2659 pkt_id = rtw89_mac_dle_buf_req(rtwdev, 0x20, false);
2660 if (pkt_id == 0xffff) {
2661 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n");
2662 return -ENOMEM;
2663 }
2664
2665 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD;
2666 ctrl_para.start_pktid = pkt_id;
2667 ctrl_para.end_pktid = pkt_id;
2668 ctrl_para.pkt_num = 0;
2669 ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS;
2670 ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT;
2671 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, false);
2672 if (ret) {
2673 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n");
2674 return -EFAULT;
2675 }
2676
2677 return 0;
2678 }
2679
band_idle_ck_b(struct rtw89_dev * rtwdev,u8 mac_idx)2680 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx)
2681 {
2682 int ret;
2683 u32 reg;
2684 u8 val;
2685
2686 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2687 if (ret)
2688 return ret;
2689
2690 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_TX_CTN_SEL, mac_idx);
2691
2692 ret = read_poll_timeout(rtw89_read8, val,
2693 (val & B_AX_PTCL_TX_ON_STAT) == 0,
2694 SW_CVR_DUR_US,
2695 SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT,
2696 false, rtwdev, reg);
2697 if (ret)
2698 return ret;
2699
2700 return 0;
2701 }
2702
band1_enable(struct rtw89_dev * rtwdev)2703 static int band1_enable(struct rtw89_dev *rtwdev)
2704 {
2705 int ret, i;
2706 u32 sleep_bak[4] = {0};
2707 u32 pause_bak[4] = {0};
2708 u32 tx_en;
2709
2710 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL);
2711 if (ret) {
2712 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret);
2713 return ret;
2714 }
2715
2716 for (i = 0; i < 4; i++) {
2717 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4);
2718 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4);
2719 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX);
2720 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX);
2721 }
2722
2723 ret = band_idle_ck_b(rtwdev, 0);
2724 if (ret) {
2725 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret);
2726 return ret;
2727 }
2728
2729 ret = dle_quota_change(rtwdev, rtwdev->mac.qta_mode);
2730 if (ret) {
2731 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret);
2732 return ret;
2733 }
2734
2735 for (i = 0; i < 4; i++) {
2736 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]);
2737 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]);
2738 }
2739
2740 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en);
2741 if (ret) {
2742 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret);
2743 return ret;
2744 }
2745
2746 ret = cmac_func_en(rtwdev, 1, true);
2747 if (ret) {
2748 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret);
2749 return ret;
2750 }
2751
2752 ret = cmac_init(rtwdev, 1);
2753 if (ret) {
2754 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret);
2755 return ret;
2756 }
2757
2758 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
2759 B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1);
2760
2761 return 0;
2762 }
2763
rtw89_wdrls_imr_enable(struct rtw89_dev * rtwdev)2764 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev)
2765 {
2766 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
2767
2768 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR);
2769 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set);
2770 }
2771
rtw89_wsec_imr_enable(struct rtw89_dev * rtwdev)2772 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev)
2773 {
2774 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
2775
2776 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set);
2777 }
2778
rtw89_mpdu_trx_imr_enable(struct rtw89_dev * rtwdev)2779 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev)
2780 {
2781 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2782 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
2783
2784 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR,
2785 B_AX_TX_GET_ERRPKTID_INT_EN |
2786 B_AX_TX_NXT_ERRPKTID_INT_EN |
2787 B_AX_TX_MPDU_SIZE_ZERO_INT_EN |
2788 B_AX_TX_OFFSET_ERR_INT_EN |
2789 B_AX_TX_HDR3_SIZE_ERR_INT_EN);
2790 if (chip_id == RTL8852C)
2791 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR,
2792 B_AX_TX_ETH_TYPE_ERR_EN |
2793 B_AX_TX_LLC_PRE_ERR_EN |
2794 B_AX_TX_NW_TYPE_ERR_EN |
2795 B_AX_TX_KSRCH_ERR_EN);
2796 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR,
2797 imr->mpdu_tx_imr_set);
2798
2799 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR,
2800 B_AX_GETPKTID_ERR_INT_EN |
2801 B_AX_MHDRLEN_ERR_INT_EN |
2802 B_AX_RPT_ERR_INT_EN);
2803 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR,
2804 imr->mpdu_rx_imr_set);
2805 }
2806
rtw89_sta_sch_imr_enable(struct rtw89_dev * rtwdev)2807 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev)
2808 {
2809 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
2810
2811 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR,
2812 B_AX_SEARCH_HANG_TIMEOUT_INT_EN |
2813 B_AX_RPT_HANG_TIMEOUT_INT_EN |
2814 B_AX_PLE_B_PKTID_ERR_INT_EN);
2815 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR,
2816 imr->sta_sch_imr_set);
2817 }
2818
rtw89_txpktctl_imr_enable(struct rtw89_dev * rtwdev)2819 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev)
2820 {
2821 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
2822
2823 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg,
2824 imr->txpktctl_imr_b0_clr);
2825 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg,
2826 imr->txpktctl_imr_b0_set);
2827 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg,
2828 imr->txpktctl_imr_b1_clr);
2829 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg,
2830 imr->txpktctl_imr_b1_set);
2831 }
2832
rtw89_wde_imr_enable(struct rtw89_dev * rtwdev)2833 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev)
2834 {
2835 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
2836
2837 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr);
2838 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set);
2839 }
2840
rtw89_ple_imr_enable(struct rtw89_dev * rtwdev)2841 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev)
2842 {
2843 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
2844
2845 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr);
2846 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set);
2847 }
2848
rtw89_pktin_imr_enable(struct rtw89_dev * rtwdev)2849 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev)
2850 {
2851 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR,
2852 B_AX_PKTIN_GETPKTID_ERR_INT_EN);
2853 }
2854
rtw89_dispatcher_imr_enable(struct rtw89_dev * rtwdev)2855 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev)
2856 {
2857 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
2858
2859 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR,
2860 imr->host_disp_imr_clr);
2861 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR,
2862 imr->host_disp_imr_set);
2863 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR,
2864 imr->cpu_disp_imr_clr);
2865 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR,
2866 imr->cpu_disp_imr_set);
2867 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR,
2868 imr->other_disp_imr_clr);
2869 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR,
2870 imr->other_disp_imr_set);
2871 }
2872
rtw89_cpuio_imr_enable(struct rtw89_dev * rtwdev)2873 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev)
2874 {
2875 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR);
2876 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET);
2877 }
2878
rtw89_bbrpt_imr_enable(struct rtw89_dev * rtwdev)2879 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev)
2880 {
2881 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
2882
2883 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg,
2884 B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN);
2885 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg,
2886 B_AX_BBRPT_CHINFO_IMR_CLR);
2887 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg,
2888 imr->bbrpt_err_imr_set);
2889 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg,
2890 B_AX_BBRPT_DFS_TO_ERR_INT_EN);
2891 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR);
2892 }
2893
rtw89_scheduler_imr_enable(struct rtw89_dev * rtwdev,u8 mac_idx)2894 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
2895 {
2896 u32 reg;
2897
2898 reg = rtw89_mac_reg_by_idx(R_AX_SCHEDULE_ERR_IMR, mac_idx);
2899 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN |
2900 B_AX_FSM_TIMEOUT_ERR_INT_EN);
2901 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN);
2902 }
2903
rtw89_ptcl_imr_enable(struct rtw89_dev * rtwdev,u8 mac_idx)2904 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
2905 {
2906 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
2907 u32 reg;
2908
2909 reg = rtw89_mac_reg_by_idx(R_AX_PTCL_IMR0, mac_idx);
2910 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr);
2911 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set);
2912 }
2913
rtw89_cdma_imr_enable(struct rtw89_dev * rtwdev,u8 mac_idx)2914 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
2915 {
2916 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
2917 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2918 u32 reg;
2919
2920 reg = rtw89_mac_reg_by_idx(imr->cdma_imr_0_reg, mac_idx);
2921 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr);
2922 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set);
2923
2924 if (chip_id == RTL8852C) {
2925 reg = rtw89_mac_reg_by_idx(imr->cdma_imr_1_reg, mac_idx);
2926 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr);
2927 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set);
2928 }
2929 }
2930
rtw89_phy_intf_imr_enable(struct rtw89_dev * rtwdev,u8 mac_idx)2931 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
2932 {
2933 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
2934 u32 reg;
2935
2936 reg = rtw89_mac_reg_by_idx(imr->phy_intf_imr_reg, mac_idx);
2937 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr);
2938 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set);
2939 }
2940
rtw89_rmac_imr_enable(struct rtw89_dev * rtwdev,u8 mac_idx)2941 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
2942 {
2943 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
2944 u32 reg;
2945
2946 reg = rtw89_mac_reg_by_idx(imr->rmac_imr_reg, mac_idx);
2947 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr);
2948 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set);
2949 }
2950
rtw89_tmac_imr_enable(struct rtw89_dev * rtwdev,u8 mac_idx)2951 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
2952 {
2953 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
2954 u32 reg;
2955
2956 reg = rtw89_mac_reg_by_idx(imr->tmac_imr_reg, mac_idx);
2957 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr);
2958 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set);
2959 }
2960
rtw89_mac_enable_imr(struct rtw89_dev * rtwdev,u8 mac_idx,enum rtw89_mac_hwmod_sel sel)2961 static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx,
2962 enum rtw89_mac_hwmod_sel sel)
2963 {
2964 int ret;
2965
2966 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel);
2967 if (ret) {
2968 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n",
2969 sel, mac_idx);
2970 return ret;
2971 }
2972
2973 if (sel == RTW89_DMAC_SEL) {
2974 rtw89_wdrls_imr_enable(rtwdev);
2975 rtw89_wsec_imr_enable(rtwdev);
2976 rtw89_mpdu_trx_imr_enable(rtwdev);
2977 rtw89_sta_sch_imr_enable(rtwdev);
2978 rtw89_txpktctl_imr_enable(rtwdev);
2979 rtw89_wde_imr_enable(rtwdev);
2980 rtw89_ple_imr_enable(rtwdev);
2981 rtw89_pktin_imr_enable(rtwdev);
2982 rtw89_dispatcher_imr_enable(rtwdev);
2983 rtw89_cpuio_imr_enable(rtwdev);
2984 rtw89_bbrpt_imr_enable(rtwdev);
2985 } else if (sel == RTW89_CMAC_SEL) {
2986 rtw89_scheduler_imr_enable(rtwdev, mac_idx);
2987 rtw89_ptcl_imr_enable(rtwdev, mac_idx);
2988 rtw89_cdma_imr_enable(rtwdev, mac_idx);
2989 rtw89_phy_intf_imr_enable(rtwdev, mac_idx);
2990 rtw89_rmac_imr_enable(rtwdev, mac_idx);
2991 rtw89_tmac_imr_enable(rtwdev, mac_idx);
2992 } else {
2993 return -EINVAL;
2994 }
2995
2996 return 0;
2997 }
2998
rtw89_mac_err_imr_ctrl(struct rtw89_dev * rtwdev,bool en)2999 static void rtw89_mac_err_imr_ctrl(struct rtw89_dev *rtwdev, bool en)
3000 {
3001 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3002
3003 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR,
3004 en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS);
3005 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR,
3006 en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS);
3007 if (chip_id != RTL8852B && rtwdev->mac.dle_info.c1_rx_qta)
3008 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1,
3009 en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS);
3010 }
3011
rtw89_mac_dbcc_enable(struct rtw89_dev * rtwdev,bool enable)3012 static int rtw89_mac_dbcc_enable(struct rtw89_dev *rtwdev, bool enable)
3013 {
3014 int ret = 0;
3015
3016 if (enable) {
3017 ret = band1_enable(rtwdev);
3018 if (ret) {
3019 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret);
3020 return ret;
3021 }
3022
3023 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL);
3024 if (ret) {
3025 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret);
3026 return ret;
3027 }
3028 } else {
3029 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n");
3030 return -EINVAL;
3031 }
3032
3033 return 0;
3034 }
3035
set_host_rpr(struct rtw89_dev * rtwdev)3036 static int set_host_rpr(struct rtw89_dev *rtwdev)
3037 {
3038 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) {
3039 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG,
3040 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH);
3041 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0,
3042 B_AX_RLSRPT0_FLTR_MAP_MASK);
3043 } else {
3044 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG,
3045 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF);
3046 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0,
3047 B_AX_RLSRPT0_FLTR_MAP_MASK);
3048 }
3049
3050 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30);
3051 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255);
3052
3053 return 0;
3054 }
3055
rtw89_mac_trx_init(struct rtw89_dev * rtwdev)3056 static int rtw89_mac_trx_init(struct rtw89_dev *rtwdev)
3057 {
3058 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode;
3059 int ret;
3060
3061 ret = dmac_init(rtwdev, 0);
3062 if (ret) {
3063 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret);
3064 return ret;
3065 }
3066
3067 ret = cmac_init(rtwdev, 0);
3068 if (ret) {
3069 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret);
3070 return ret;
3071 }
3072
3073 if (is_qta_dbcc(rtwdev, qta_mode)) {
3074 ret = rtw89_mac_dbcc_enable(rtwdev, true);
3075 if (ret) {
3076 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret);
3077 return ret;
3078 }
3079 }
3080
3081 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
3082 if (ret) {
3083 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret);
3084 return ret;
3085 }
3086
3087 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL);
3088 if (ret) {
3089 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret);
3090 return ret;
3091 }
3092
3093 rtw89_mac_err_imr_ctrl(rtwdev, true);
3094
3095 ret = set_host_rpr(rtwdev);
3096 if (ret) {
3097 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret);
3098 return ret;
3099 }
3100
3101 return 0;
3102 }
3103
rtw89_disable_fw_watchdog(struct rtw89_dev * rtwdev)3104 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev)
3105 {
3106 u32 val32;
3107
3108 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL,
3109 WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL);
3110
3111 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL);
3112 val32 |= B_AX_FS_WDT_INT;
3113 val32 &= ~B_AX_FS_WDT_INT_MSK;
3114 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL);
3115 }
3116
rtw89_mac_disable_cpu(struct rtw89_dev * rtwdev)3117 static void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev)
3118 {
3119 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);
3120
3121 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN);
3122 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN |
3123 B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY);
3124 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN);
3125
3126 rtw89_disable_fw_watchdog(rtwdev);
3127
3128 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
3129 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
3130 }
3131
rtw89_mac_enable_cpu(struct rtw89_dev * rtwdev,u8 boot_reason,bool dlfw)3132 static int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason,
3133 bool dlfw)
3134 {
3135 u32 val;
3136 int ret;
3137
3138 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN)
3139 return -EFAULT;
3140
3141 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0);
3142 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0);
3143 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0);
3144 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0);
3145
3146 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN);
3147
3148 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL);
3149 val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY);
3150 val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE,
3151 B_AX_WCPU_FWDL_STS_MASK);
3152
3153 if (dlfw)
3154 val |= B_AX_WCPU_FWDL_EN;
3155
3156 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val);
3157 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK,
3158 boot_reason);
3159 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN);
3160
3161 if (!dlfw) {
3162 mdelay(5);
3163
3164 ret = rtw89_fw_check_rdy(rtwdev);
3165 if (ret)
3166 return ret;
3167 }
3168
3169 return 0;
3170 }
3171
rtw89_mac_dmac_pre_init(struct rtw89_dev * rtwdev)3172 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev)
3173 {
3174 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3175 u32 val;
3176 int ret;
3177
3178 if (chip_id == RTL8852C)
3179 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN |
3180 B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN;
3181 else
3182 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN |
3183 B_AX_PKT_BUF_EN;
3184 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val);
3185
3186 val = B_AX_DISPATCHER_CLK_EN;
3187 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val);
3188
3189 if (chip_id != RTL8852C)
3190 goto dle;
3191
3192 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1);
3193 val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST);
3194 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) |
3195 B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1;
3196 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val);
3197
3198 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1,
3199 B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 |
3200 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 |
3201 B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 |
3202 B_AX_STOP_CH12 | B_AX_STOP_ACH2);
3203 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11);
3204 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN);
3205
3206 dle:
3207 ret = dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode);
3208 if (ret) {
3209 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret);
3210 return ret;
3211 }
3212
3213 ret = hfc_init(rtwdev, true, false, true);
3214 if (ret) {
3215 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret);
3216 return ret;
3217 }
3218
3219 return ret;
3220 }
3221
rtw89_mac_enable_bb_rf(struct rtw89_dev * rtwdev)3222 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
3223 {
3224 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN,
3225 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
3226 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL,
3227 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 |
3228 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1);
3229 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE);
3230
3231 return 0;
3232 }
3233 EXPORT_SYMBOL(rtw89_mac_enable_bb_rf);
3234
rtw89_mac_disable_bb_rf(struct rtw89_dev * rtwdev)3235 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
3236 {
3237 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,
3238 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
3239 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL,
3240 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 |
3241 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1);
3242 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE);
3243
3244 return 0;
3245 }
3246 EXPORT_SYMBOL(rtw89_mac_disable_bb_rf);
3247
rtw89_mac_partial_init(struct rtw89_dev * rtwdev)3248 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev)
3249 {
3250 int ret;
3251
3252 ret = rtw89_mac_power_switch(rtwdev, true);
3253 if (ret) {
3254 rtw89_mac_power_switch(rtwdev, false);
3255 ret = rtw89_mac_power_switch(rtwdev, true);
3256 if (ret)
3257 return ret;
3258 }
3259
3260 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true);
3261
3262 ret = rtw89_mac_dmac_pre_init(rtwdev);
3263 if (ret)
3264 return ret;
3265
3266 if (rtwdev->hci.ops->mac_pre_init) {
3267 ret = rtwdev->hci.ops->mac_pre_init(rtwdev);
3268 if (ret)
3269 return ret;
3270 }
3271
3272 rtw89_mac_disable_cpu(rtwdev);
3273 ret = rtw89_mac_enable_cpu(rtwdev, 0, true);
3274 if (ret)
3275 return ret;
3276
3277 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL);
3278 if (ret)
3279 return ret;
3280
3281 return 0;
3282 }
3283
rtw89_mac_init(struct rtw89_dev * rtwdev)3284 int rtw89_mac_init(struct rtw89_dev *rtwdev)
3285 {
3286 int ret;
3287
3288 ret = rtw89_mac_partial_init(rtwdev);
3289 if (ret)
3290 goto fail;
3291
3292 ret = rtw89_chip_enable_bb_rf(rtwdev);
3293 if (ret)
3294 goto fail;
3295
3296 ret = rtw89_mac_sys_init(rtwdev);
3297 if (ret)
3298 goto fail;
3299
3300 ret = rtw89_mac_trx_init(rtwdev);
3301 if (ret)
3302 goto fail;
3303
3304 if (rtwdev->hci.ops->mac_post_init) {
3305 ret = rtwdev->hci.ops->mac_post_init(rtwdev);
3306 if (ret)
3307 goto fail;
3308 }
3309
3310 rtw89_fw_send_all_early_h2c(rtwdev);
3311 rtw89_fw_h2c_set_ofld_cfg(rtwdev);
3312
3313 return ret;
3314 fail:
3315 rtw89_mac_power_switch(rtwdev, false);
3316
3317 return ret;
3318 }
3319
rtw89_mac_dmac_tbl_init(struct rtw89_dev * rtwdev,u8 macid)3320 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid)
3321 {
3322 u8 i;
3323
3324 for (i = 0; i < 4; i++) {
3325 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR,
3326 DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2));
3327 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0);
3328 }
3329 }
3330
rtw89_mac_cmac_tbl_init(struct rtw89_dev * rtwdev,u8 macid)3331 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid)
3332 {
3333 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR,
3334 CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE);
3335 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4);
3336 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004);
3337 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0);
3338 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0);
3339 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0);
3340 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B);
3341 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0);
3342 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109);
3343 }
3344
rtw89_mac_set_macid_pause(struct rtw89_dev * rtwdev,u8 macid,bool pause)3345 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause)
3346 {
3347 u8 sh = FIELD_GET(GENMASK(4, 0), macid);
3348 u8 grp = macid >> 5;
3349 int ret;
3350
3351 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL);
3352 if (ret)
3353 return ret;
3354
3355 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause);
3356
3357 return 0;
3358 }
3359
3360 static const struct rtw89_port_reg rtw_port_base = {
3361 .port_cfg = R_AX_PORT_CFG_P0,
3362 .tbtt_prohib = R_AX_TBTT_PROHIB_P0,
3363 .bcn_area = R_AX_BCN_AREA_P0,
3364 .bcn_early = R_AX_BCNERLYINT_CFG_P0,
3365 .tbtt_early = R_AX_TBTTERLYINT_CFG_P0,
3366 .tbtt_agg = R_AX_TBTT_AGG_P0,
3367 .bcn_space = R_AX_BCN_SPACE_CFG_P0,
3368 .bcn_forcetx = R_AX_BCN_FORCETX_P0,
3369 .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0,
3370 .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0,
3371 .dtim_ctrl = R_AX_DTIM_CTRL_P0,
3372 .tbtt_shift = R_AX_TBTT_SHIFT_P0,
3373 .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0,
3374 .tsftr_l = R_AX_TSFTR_LOW_P0,
3375 .tsftr_h = R_AX_TSFTR_HIGH_P0
3376 };
3377
3378 #define BCN_INTERVAL 100
3379 #define BCN_ERLY_DEF 160
3380 #define BCN_SETUP_DEF 2
3381 #define BCN_HOLD_DEF 200
3382 #define BCN_MASK_DEF 0
3383 #define TBTT_ERLY_DEF 5
3384 #define BCN_SET_UNIT 32
3385 #define BCN_ERLY_SET_DLY (10 * 2)
3386
rtw89_mac_port_cfg_func_sw(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3387 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev,
3388 struct rtw89_vif *rtwvif)
3389 {
3390 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
3391 const struct rtw89_port_reg *p = &rtw_port_base;
3392
3393 if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN))
3394 return;
3395
3396 rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK);
3397 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1);
3398 rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK);
3399 rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK);
3400
3401 msleep(vif->bss_conf.beacon_int + 1);
3402
3403 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN |
3404 B_AX_BRK_SETUP);
3405 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST);
3406 rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0);
3407 }
3408
rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,bool en)3409 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev,
3410 struct rtw89_vif *rtwvif, bool en)
3411 {
3412 const struct rtw89_port_reg *p = &rtw_port_base;
3413
3414 if (en)
3415 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN);
3416 else
3417 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN);
3418 }
3419
rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,bool en)3420 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev,
3421 struct rtw89_vif *rtwvif, bool en)
3422 {
3423 const struct rtw89_port_reg *p = &rtw_port_base;
3424
3425 if (en)
3426 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN);
3427 else
3428 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN);
3429 }
3430
rtw89_mac_port_cfg_net_type(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3431 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev,
3432 struct rtw89_vif *rtwvif)
3433 {
3434 const struct rtw89_port_reg *p = &rtw_port_base;
3435
3436 rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK,
3437 rtwvif->net_type);
3438 }
3439
rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3440 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev,
3441 struct rtw89_vif *rtwvif)
3442 {
3443 const struct rtw89_port_reg *p = &rtw_port_base;
3444 bool en = rtwvif->net_type != RTW89_NET_TYPE_NO_LINK;
3445 u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP;
3446
3447 if (en)
3448 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits);
3449 else
3450 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits);
3451 }
3452
rtw89_mac_port_cfg_rx_sw(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3453 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev,
3454 struct rtw89_vif *rtwvif)
3455 {
3456 const struct rtw89_port_reg *p = &rtw_port_base;
3457 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA ||
3458 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC;
3459 u32 bit = B_AX_RX_BSSID_FIT_EN;
3460
3461 if (en)
3462 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit);
3463 else
3464 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit);
3465 }
3466
rtw89_mac_port_cfg_rx_sync(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3467 static void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev,
3468 struct rtw89_vif *rtwvif)
3469 {
3470 const struct rtw89_port_reg *p = &rtw_port_base;
3471 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA ||
3472 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC;
3473
3474 if (en)
3475 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN);
3476 else
3477 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN);
3478 }
3479
rtw89_mac_port_cfg_tx_sw(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3480 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev,
3481 struct rtw89_vif *rtwvif)
3482 {
3483 const struct rtw89_port_reg *p = &rtw_port_base;
3484 bool en = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ||
3485 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC;
3486
3487 if (en)
3488 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN);
3489 else
3490 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN);
3491 }
3492
rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3493 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev,
3494 struct rtw89_vif *rtwvif)
3495 {
3496 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
3497 const struct rtw89_port_reg *p = &rtw_port_base;
3498 u16 bcn_int = vif->bss_conf.beacon_int ? vif->bss_conf.beacon_int : BCN_INTERVAL;
3499
3500 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK,
3501 bcn_int);
3502 }
3503
rtw89_mac_port_cfg_hiq_win(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3504 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev,
3505 struct rtw89_vif *rtwvif)
3506 {
3507 static const u32 hiq_win_addr[RTW89_PORT_NUM] = {
3508 R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG,
3509 R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2,
3510 R_AX_PORT_HGQ_WINDOW_CFG + 3,
3511 };
3512 u8 win = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0;
3513 u8 port = rtwvif->port;
3514 u32 reg;
3515
3516 reg = rtw89_mac_reg_by_idx(hiq_win_addr[port], rtwvif->mac_idx);
3517 rtw89_write8(rtwdev, reg, win);
3518 }
3519
rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3520 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev,
3521 struct rtw89_vif *rtwvif)
3522 {
3523 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
3524 const struct rtw89_port_reg *p = &rtw_port_base;
3525 u32 addr;
3526
3527 addr = rtw89_mac_reg_by_idx(R_AX_MD_TSFT_STMP_CTL, rtwvif->mac_idx);
3528 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE);
3529
3530 rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK,
3531 vif->bss_conf.dtim_period);
3532 }
3533
rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3534 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev,
3535 struct rtw89_vif *rtwvif)
3536 {
3537 const struct rtw89_port_reg *p = &rtw_port_base;
3538
3539 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib,
3540 B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF);
3541 }
3542
rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3543 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev,
3544 struct rtw89_vif *rtwvif)
3545 {
3546 const struct rtw89_port_reg *p = &rtw_port_base;
3547
3548 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib,
3549 B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF);
3550 }
3551
rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3552 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev,
3553 struct rtw89_vif *rtwvif)
3554 {
3555 const struct rtw89_port_reg *p = &rtw_port_base;
3556
3557 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area,
3558 B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF);
3559 }
3560
rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3561 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev,
3562 struct rtw89_vif *rtwvif)
3563 {
3564 const struct rtw89_port_reg *p = &rtw_port_base;
3565
3566 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early,
3567 B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF);
3568 }
3569
rtw89_mac_port_cfg_bss_color(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3570 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev,
3571 struct rtw89_vif *rtwvif)
3572 {
3573 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
3574 static const u32 masks[RTW89_PORT_NUM] = {
3575 B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK,
3576 B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK,
3577 B_AX_BSS_COLOB_AX_PORT_4_MASK,
3578 };
3579 u8 port = rtwvif->port;
3580 u32 reg_base;
3581 u32 reg;
3582 u8 bss_color;
3583
3584 bss_color = vif->bss_conf.he_bss_color.color;
3585 reg_base = port >= 4 ? R_AX_PTCL_BSS_COLOR_1 : R_AX_PTCL_BSS_COLOR_0;
3586 reg = rtw89_mac_reg_by_idx(reg_base, rtwvif->mac_idx);
3587 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color);
3588 }
3589
rtw89_mac_port_cfg_mbssid(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3590 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev,
3591 struct rtw89_vif *rtwvif)
3592 {
3593 u8 port = rtwvif->port;
3594 u32 reg;
3595
3596 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE)
3597 return;
3598
3599 if (port == 0) {
3600 reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_CTRL, rtwvif->mac_idx);
3601 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK);
3602 }
3603 }
3604
rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3605 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev,
3606 struct rtw89_vif *rtwvif)
3607 {
3608 u8 port = rtwvif->port;
3609 u32 reg;
3610 u32 val;
3611
3612 reg = rtw89_mac_reg_by_idx(R_AX_MBSSID_DROP_0, rtwvif->mac_idx);
3613 val = rtw89_read32(rtwdev, reg);
3614 val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port));
3615 if (port == 0)
3616 val &= ~BIT(0);
3617 rtw89_write32(rtwdev, reg, val);
3618 }
3619
rtw89_mac_port_cfg_func_en(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3620 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev,
3621 struct rtw89_vif *rtwvif)
3622 {
3623 const struct rtw89_port_reg *p = &rtw_port_base;
3624
3625 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN);
3626 }
3627
rtw89_mac_port_cfg_bcn_early(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3628 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev,
3629 struct rtw89_vif *rtwvif)
3630 {
3631 const struct rtw89_port_reg *p = &rtw_port_base;
3632
3633 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK,
3634 BCN_ERLY_DEF);
3635 }
3636
rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3637 static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev,
3638 struct rtw89_vif *rtwvif)
3639 {
3640 const struct rtw89_port_reg *p = &rtw_port_base;
3641 u16 val;
3642
3643 if (rtwdev->chip->chip_id != RTL8852C)
3644 return;
3645
3646 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT &&
3647 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION)
3648 return;
3649
3650 val = FIELD_PREP(B_AX_TBTT_SHIFT_OFST_MAG, 1) |
3651 B_AX_TBTT_SHIFT_OFST_SIGN;
3652
3653 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_shift,
3654 B_AX_TBTT_SHIFT_OFST_MASK, val);
3655 }
3656
rtw89_mac_vif_init(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3657 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
3658 {
3659 int ret;
3660
3661 ret = rtw89_mac_port_update(rtwdev, rtwvif);
3662 if (ret)
3663 return ret;
3664
3665 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id);
3666 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id);
3667
3668 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false);
3669 if (ret)
3670 return ret;
3671
3672 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE);
3673 if (ret)
3674 return ret;
3675
3676 ret = rtw89_cam_init(rtwdev, rtwvif);
3677 if (ret)
3678 return ret;
3679
3680 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL);
3681 if (ret)
3682 return ret;
3683
3684 ret = rtw89_fw_h2c_default_cmac_tbl(rtwdev, rtwvif);
3685 if (ret)
3686 return ret;
3687
3688 return 0;
3689 }
3690
rtw89_mac_vif_deinit(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3691 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
3692 {
3693 int ret;
3694
3695 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE);
3696 if (ret)
3697 return ret;
3698
3699 rtw89_cam_deinit(rtwdev, rtwvif);
3700
3701 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL);
3702 if (ret)
3703 return ret;
3704
3705 return 0;
3706 }
3707
rtw89_mac_port_update(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3708 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
3709 {
3710 u8 port = rtwvif->port;
3711
3712 if (port >= RTW89_PORT_NUM)
3713 return -EINVAL;
3714
3715 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif);
3716 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false);
3717 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false);
3718 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif);
3719 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif);
3720 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif);
3721 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif);
3722 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif);
3723 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif);
3724 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif);
3725 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif);
3726 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif);
3727 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif);
3728 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif);
3729 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif);
3730 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif);
3731 rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif);
3732 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif);
3733 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif);
3734 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif);
3735 fsleep(BCN_ERLY_SET_DLY);
3736 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif);
3737
3738 return 0;
3739 }
3740
rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy * wiphy,struct cfg80211_bss * bss,void * data)3741 static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy,
3742 struct cfg80211_bss *bss,
3743 void *data)
3744 {
3745 const struct cfg80211_bss_ies *ies;
3746 const struct element *elem;
3747 bool *tolerated = data;
3748
3749 rcu_read_lock();
3750 ies = rcu_dereference(bss->ies);
3751 elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data,
3752 ies->len);
3753
3754 if (!elem || elem->datalen < 10 ||
3755 !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT))
3756 *tolerated = false;
3757 rcu_read_unlock();
3758 }
3759
rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif)3760 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev,
3761 struct ieee80211_vif *vif)
3762 {
3763 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
3764 struct ieee80211_hw *hw = rtwdev->hw;
3765 bool tolerated = true;
3766 u32 reg;
3767
3768 if (!vif->bss_conf.he_support || vif->type != NL80211_IFTYPE_STATION)
3769 return;
3770
3771 if (!(vif->bss_conf.chandef.chan->flags & IEEE80211_CHAN_RADAR))
3772 return;
3773
3774 cfg80211_bss_iter(hw->wiphy, &vif->bss_conf.chandef,
3775 rtw89_mac_check_he_obss_narrow_bw_ru_iter,
3776 &tolerated);
3777
3778 reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, rtwvif->mac_idx);
3779 if (tolerated)
3780 rtw89_write32_clr(rtwdev, reg, B_AX_RXTRIG_RU26_DIS);
3781 else
3782 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_RU26_DIS);
3783 }
3784
rtw89_mac_add_vif(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3785 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
3786 {
3787 int ret;
3788
3789 rtwvif->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map,
3790 RTW89_MAX_MAC_ID_NUM);
3791 if (rtwvif->mac_id == RTW89_MAX_MAC_ID_NUM)
3792 return -ENOSPC;
3793
3794 ret = rtw89_mac_vif_init(rtwdev, rtwvif);
3795 if (ret)
3796 goto release_mac_id;
3797
3798 return 0;
3799
3800 release_mac_id:
3801 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id);
3802
3803 return ret;
3804 }
3805
rtw89_mac_remove_vif(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)3806 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
3807 {
3808 int ret;
3809
3810 ret = rtw89_mac_vif_deinit(rtwdev, rtwvif);
3811 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id);
3812
3813 return ret;
3814 }
3815
3816 static void
rtw89_mac_c2h_macid_pause(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3817 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3818 {
3819 }
3820
rtw89_is_op_chan(struct rtw89_dev * rtwdev,u8 band,u8 channel)3821 static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel)
3822 {
3823 struct rtw89_hw_scan_info *scan_info = &rtwdev->scan_info;
3824
3825 return band == scan_info->op_band && channel == scan_info->op_pri_ch;
3826 }
3827
3828 static void
rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3829 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
3830 u32 len)
3831 {
3832 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif;
3833 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif);
3834 struct rtw89_chan new;
3835 u8 reason, status, tx_fail, band, actual_period;
3836 u32 last_chan = rtwdev->scan_info.last_chan_idx;
3837 u16 chan;
3838 int ret;
3839
3840 tx_fail = RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h->data);
3841 status = RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h->data);
3842 chan = RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h->data);
3843 reason = RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h->data);
3844 band = RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h->data);
3845 actual_period = RTW89_GET_MAC_C2H_ACTUAL_PERIOD(c2h->data);
3846
3847 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ)))
3848 band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G;
3849
3850 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN,
3851 "band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n",
3852 band, chan, reason, status, tx_fail, actual_period);
3853
3854 switch (reason) {
3855 case RTW89_SCAN_LEAVE_CH_NOTIFY:
3856 if (rtw89_is_op_chan(rtwdev, band, chan))
3857 ieee80211_stop_queues(rtwdev->hw);
3858 return;
3859 case RTW89_SCAN_END_SCAN_NOTIFY:
3860 if (rtwvif && rtwvif->scan_req &&
3861 last_chan < rtwvif->scan_req->n_channels) {
3862 ret = rtw89_hw_scan_offload(rtwdev, vif, true);
3863 if (ret) {
3864 rtw89_hw_scan_abort(rtwdev, vif);
3865 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret);
3866 }
3867 } else {
3868 rtw89_hw_scan_complete(rtwdev, vif, false);
3869 }
3870 break;
3871 case RTW89_SCAN_ENTER_CH_NOTIFY:
3872 rtw89_chan_create(&new, chan, chan, band, RTW89_CHANNEL_WIDTH_20);
3873 rtw89_assign_entity_chan(rtwdev, RTW89_SUB_ENTITY_0, &new);
3874 if (rtw89_is_op_chan(rtwdev, band, chan)) {
3875 rtw89_store_op_chan(rtwdev, false);
3876 ieee80211_wake_queues(rtwdev->hw);
3877 }
3878 break;
3879 default:
3880 return;
3881 }
3882 }
3883
3884 static void
rtw89_mac_c2h_rec_ack(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3885 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3886 {
3887 rtw89_debug(rtwdev, RTW89_DBG_FW,
3888 "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n",
3889 RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data),
3890 RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data),
3891 RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data),
3892 RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data));
3893 }
3894
3895 static void
rtw89_mac_c2h_done_ack(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3896 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3897 {
3898 rtw89_debug(rtwdev, RTW89_DBG_FW,
3899 "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n",
3900 RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h->data),
3901 RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h->data),
3902 RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h->data),
3903 RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h->data),
3904 RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h->data));
3905 }
3906
3907 static void
rtw89_mac_c2h_log(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3908 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3909 {
3910 rtw89_info(rtwdev, "%*s", RTW89_GET_C2H_LOG_LEN(len),
3911 RTW89_GET_C2H_LOG_SRT_PRT(c2h->data));
3912 }
3913
3914 static void
rtw89_mac_c2h_bcn_cnt(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3915 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3916 {
3917 }
3918
3919 static void
rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3920 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
3921 u32 len)
3922 {
3923 }
3924
3925 static void
rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3926 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
3927 u32 len)
3928 {
3929 }
3930
3931 static
3932 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev,
3933 struct sk_buff *c2h, u32 len) = {
3934 [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL,
3935 [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL,
3936 [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp,
3937 [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL,
3938 [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause,
3939 [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp,
3940 [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt,
3941 };
3942
3943 static
3944 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev,
3945 struct sk_buff *c2h, u32 len) = {
3946 [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack,
3947 [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack,
3948 [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log,
3949 [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt,
3950 };
3951
rtw89_mac_c2h_handle(struct rtw89_dev * rtwdev,struct sk_buff * skb,u32 len,u8 class,u8 func)3952 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
3953 u32 len, u8 class, u8 func)
3954 {
3955 void (*handler)(struct rtw89_dev *rtwdev,
3956 struct sk_buff *c2h, u32 len) = NULL;
3957
3958 switch (class) {
3959 case RTW89_MAC_C2H_CLASS_INFO:
3960 if (func < RTW89_MAC_C2H_FUNC_INFO_MAX)
3961 handler = rtw89_mac_c2h_info_handler[func];
3962 break;
3963 case RTW89_MAC_C2H_CLASS_OFLD:
3964 if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX)
3965 handler = rtw89_mac_c2h_ofld_handler[func];
3966 break;
3967 case RTW89_MAC_C2H_CLASS_FWDBG:
3968 return;
3969 default:
3970 rtw89_info(rtwdev, "c2h class %d not support\n", class);
3971 return;
3972 }
3973 if (!handler) {
3974 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class,
3975 func);
3976 return;
3977 }
3978 handler(rtwdev, skb, len);
3979 }
3980
rtw89_mac_get_txpwr_cr(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 * cr)3981 bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev,
3982 enum rtw89_phy_idx phy_idx,
3983 u32 reg_base, u32 *cr)
3984 {
3985 const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem;
3986 enum rtw89_qta_mode mode = dle_mem->mode;
3987 u32 addr = rtw89_mac_reg_by_idx(reg_base, phy_idx);
3988
3989 if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR) {
3990 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n",
3991 addr);
3992 goto error;
3993 }
3994
3995 if (addr >= CMAC1_START_ADDR && addr <= CMAC1_END_ADDR)
3996 if (mode == RTW89_QTA_SCC) {
3997 rtw89_err(rtwdev,
3998 "[TXPWR] addr=0x%x but hw not enable\n",
3999 addr);
4000 goto error;
4001 }
4002
4003 *cr = addr;
4004 return true;
4005
4006 error:
4007 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n",
4008 addr, phy_idx);
4009
4010 return false;
4011 }
4012 EXPORT_SYMBOL(rtw89_mac_get_txpwr_cr);
4013
rtw89_mac_cfg_ppdu_status(struct rtw89_dev * rtwdev,u8 mac_idx,bool enable)4014 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)
4015 {
4016 u32 reg = rtw89_mac_reg_by_idx(R_AX_PPDU_STAT, mac_idx);
4017 int ret = 0;
4018
4019 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
4020 if (ret)
4021 return ret;
4022
4023 if (!enable) {
4024 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN);
4025 return ret;
4026 }
4027
4028 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN |
4029 B_AX_APP_MAC_INFO_RPT |
4030 B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT |
4031 B_AX_PPDU_STAT_RPT_CRC32);
4032 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK,
4033 RTW89_PRPT_DEST_HOST);
4034
4035 return ret;
4036 }
4037 EXPORT_SYMBOL(rtw89_mac_cfg_ppdu_status);
4038
rtw89_mac_update_rts_threshold(struct rtw89_dev * rtwdev,u8 mac_idx)4039 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx)
4040 {
4041 #define MAC_AX_TIME_TH_SH 5
4042 #define MAC_AX_LEN_TH_SH 4
4043 #define MAC_AX_TIME_TH_MAX 255
4044 #define MAC_AX_LEN_TH_MAX 255
4045 #define MAC_AX_TIME_TH_DEF 88
4046 #define MAC_AX_LEN_TH_DEF 4080
4047 struct ieee80211_hw *hw = rtwdev->hw;
4048 u32 rts_threshold = hw->wiphy->rts_threshold;
4049 u32 time_th, len_th;
4050 u32 reg;
4051
4052 if (rts_threshold == (u32)-1) {
4053 time_th = MAC_AX_TIME_TH_DEF;
4054 len_th = MAC_AX_LEN_TH_DEF;
4055 } else {
4056 time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH;
4057 len_th = rts_threshold;
4058 }
4059
4060 time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX);
4061 len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX);
4062
4063 reg = rtw89_mac_reg_by_idx(R_AX_AGG_LEN_HT_0, mac_idx);
4064 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th);
4065 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th);
4066 }
4067
rtw89_mac_flush_txq(struct rtw89_dev * rtwdev,u32 queues,bool drop)4068 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop)
4069 {
4070 bool empty;
4071 int ret;
4072
4073 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
4074 return;
4075
4076 ret = read_poll_timeout(dle_is_txq_empty, empty, empty,
4077 10000, 200000, false, rtwdev);
4078 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning))
4079 rtw89_info(rtwdev, "timed out to flush queues\n");
4080 }
4081
rtw89_mac_coex_init(struct rtw89_dev * rtwdev,const struct rtw89_mac_ax_coex * coex)4082 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex)
4083 {
4084 u8 val;
4085 u16 val16;
4086 u32 val32;
4087 int ret;
4088
4089 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT);
4090 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN);
4091 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8);
4092 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK);
4093 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16);
4094 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24);
4095
4096 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0);
4097 val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN;
4098 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16);
4099
4100 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32);
4101 if (ret) {
4102 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n");
4103 return ret;
4104 }
4105 val32 = val32 & B_AX_WL_RX_CTRL;
4106 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32);
4107 if (ret) {
4108 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n");
4109 return ret;
4110 }
4111
4112 switch (coex->pta_mode) {
4113 case RTW89_MAC_AX_COEX_RTK_MODE:
4114 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG);
4115 val &= ~B_AX_BTMODE_MASK;
4116 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3);
4117 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val);
4118
4119 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE);
4120 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE);
4121
4122 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5);
4123 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK;
4124 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE);
4125 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val);
4126 break;
4127 case RTW89_MAC_AX_COEX_CSR_MODE:
4128 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG);
4129 val &= ~B_AX_BTMODE_MASK;
4130 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2);
4131 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val);
4132
4133 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE);
4134 val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK;
4135 val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO);
4136 val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK;
4137 val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO);
4138 val16 &= ~B_AX_BT_STAT_DELAY_MASK;
4139 val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY);
4140 val16 |= B_AX_ENHANCED_BT;
4141 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16);
4142
4143 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE);
4144 break;
4145 default:
4146 return -EINVAL;
4147 }
4148
4149 switch (coex->direction) {
4150 case RTW89_MAC_AX_COEX_INNER:
4151 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);
4152 val = (val & ~BIT(2)) | BIT(1);
4153 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);
4154 break;
4155 case RTW89_MAC_AX_COEX_OUTPUT:
4156 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);
4157 val = val | BIT(1) | BIT(0);
4158 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);
4159 break;
4160 case RTW89_MAC_AX_COEX_INPUT:
4161 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);
4162 val = val & ~(BIT(2) | BIT(1));
4163 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);
4164 break;
4165 default:
4166 return -EINVAL;
4167 }
4168
4169 return 0;
4170 }
4171 EXPORT_SYMBOL(rtw89_mac_coex_init);
4172
rtw89_mac_coex_init_v1(struct rtw89_dev * rtwdev,const struct rtw89_mac_ax_coex * coex)4173 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev,
4174 const struct rtw89_mac_ax_coex *coex)
4175 {
4176 rtw89_write32_set(rtwdev, R_AX_BTC_CFG,
4177 B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL);
4178 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN);
4179 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN);
4180 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN);
4181
4182 switch (coex->pta_mode) {
4183 case RTW89_MAC_AX_COEX_RTK_MODE:
4184 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK,
4185 MAC_AX_RTK_MODE);
4186 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1,
4187 B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE);
4188 break;
4189 case RTW89_MAC_AX_COEX_CSR_MODE:
4190 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK,
4191 MAC_AX_CSR_MODE);
4192 break;
4193 default:
4194 return -EINVAL;
4195 }
4196
4197 return 0;
4198 }
4199 EXPORT_SYMBOL(rtw89_mac_coex_init_v1);
4200
rtw89_mac_cfg_gnt(struct rtw89_dev * rtwdev,const struct rtw89_mac_ax_coex_gnt * gnt_cfg)4201 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev,
4202 const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
4203 {
4204 u32 val = 0, ret;
4205
4206 if (gnt_cfg->band[0].gnt_bt)
4207 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL;
4208
4209 if (gnt_cfg->band[0].gnt_bt_sw_en)
4210 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL;
4211
4212 if (gnt_cfg->band[0].gnt_wl)
4213 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL;
4214
4215 if (gnt_cfg->band[0].gnt_wl_sw_en)
4216 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL;
4217
4218 if (gnt_cfg->band[1].gnt_bt)
4219 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL;
4220
4221 if (gnt_cfg->band[1].gnt_bt_sw_en)
4222 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL;
4223
4224 if (gnt_cfg->band[1].gnt_wl)
4225 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL;
4226
4227 if (gnt_cfg->band[1].gnt_wl_sw_en)
4228 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL;
4229
4230 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val);
4231 if (ret) {
4232 rtw89_err(rtwdev, "Write LTE fail!\n");
4233 return ret;
4234 }
4235
4236 return 0;
4237 }
4238 EXPORT_SYMBOL(rtw89_mac_cfg_gnt);
4239
rtw89_mac_cfg_gnt_v1(struct rtw89_dev * rtwdev,const struct rtw89_mac_ax_coex_gnt * gnt_cfg)4240 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev,
4241 const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
4242 {
4243 u32 val = 0;
4244
4245 if (gnt_cfg->band[0].gnt_bt)
4246 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL |
4247 B_AX_GNT_BT_TX_VAL;
4248 else
4249 val |= B_AX_WL_ACT_VAL;
4250
4251 if (gnt_cfg->band[0].gnt_bt_sw_en)
4252 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL |
4253 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL;
4254
4255 if (gnt_cfg->band[0].gnt_wl)
4256 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL |
4257 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL;
4258
4259 if (gnt_cfg->band[0].gnt_wl_sw_en)
4260 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL |
4261 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL;
4262
4263 if (gnt_cfg->band[1].gnt_bt)
4264 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL |
4265 B_AX_GNT_BT_TX_VAL;
4266 else
4267 val |= B_AX_WL_ACT_VAL;
4268
4269 if (gnt_cfg->band[1].gnt_bt_sw_en)
4270 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL |
4271 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL;
4272
4273 if (gnt_cfg->band[1].gnt_wl)
4274 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL |
4275 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL;
4276
4277 if (gnt_cfg->band[1].gnt_wl_sw_en)
4278 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL |
4279 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL;
4280
4281 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val);
4282
4283 return 0;
4284 }
4285 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1);
4286
rtw89_mac_cfg_plt(struct rtw89_dev * rtwdev,struct rtw89_mac_ax_plt * plt)4287 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt)
4288 {
4289 u32 reg;
4290 u16 val;
4291 int ret;
4292
4293 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL);
4294 if (ret)
4295 return ret;
4296
4297 reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, plt->band);
4298 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) |
4299 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) |
4300 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) |
4301 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) |
4302 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) |
4303 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) |
4304 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) |
4305 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) |
4306 B_AX_PLT_EN;
4307 rtw89_write16(rtwdev, reg, val);
4308
4309 return 0;
4310 }
4311
rtw89_mac_cfg_sb(struct rtw89_dev * rtwdev,u32 val)4312 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val)
4313 {
4314 u32 fw_sb;
4315
4316 fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD);
4317 fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb);
4318 fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY;
4319 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
4320 fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR;
4321 else
4322 fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR;
4323 val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val);
4324 val = B_AX_TOGGLE |
4325 FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) |
4326 FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb);
4327 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val);
4328 fsleep(1000); /* avoid BT FW loss information */
4329 }
4330
rtw89_mac_get_sb(struct rtw89_dev * rtwdev)4331 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev)
4332 {
4333 return rtw89_read32(rtwdev, R_AX_SCOREBOARD);
4334 }
4335
rtw89_mac_cfg_ctrl_path(struct rtw89_dev * rtwdev,bool wl)4336 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl)
4337 {
4338 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3);
4339
4340 val = wl ? val | BIT(2) : val & ~BIT(2);
4341 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val);
4342
4343 return 0;
4344 }
4345 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path);
4346
rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev * rtwdev,bool wl)4347 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl)
4348 {
4349 struct rtw89_btc *btc = &rtwdev->btc;
4350 struct rtw89_btc_dm *dm = &btc->dm;
4351 struct rtw89_mac_ax_gnt *g = dm->gnt.band;
4352 int i;
4353
4354 if (wl)
4355 return 0;
4356
4357 for (i = 0; i < RTW89_PHY_MAX; i++) {
4358 g[i].gnt_bt_sw_en = 1;
4359 g[i].gnt_bt = 1;
4360 g[i].gnt_wl_sw_en = 1;
4361 g[i].gnt_wl = 0;
4362 }
4363
4364 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt);
4365 }
4366 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1);
4367
rtw89_mac_get_ctrl_path(struct rtw89_dev * rtwdev)4368 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev)
4369 {
4370 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3);
4371
4372 return FIELD_GET(B_AX_LTE_MUX_CTRL_PATH >> 24, val);
4373 }
4374
rtw89_mac_get_plt_cnt(struct rtw89_dev * rtwdev,u8 band)4375 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band)
4376 {
4377 u32 reg;
4378 u16 cnt;
4379
4380 reg = rtw89_mac_reg_by_idx(R_AX_BT_PLT, band);
4381 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK);
4382 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST);
4383
4384 return cnt;
4385 }
4386
rtw89_mac_bfee_ctrl(struct rtw89_dev * rtwdev,u8 mac_idx,bool en)4387 static void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en)
4388 {
4389 u32 reg;
4390 u32 mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN |
4391 B_AX_BFMEE_HE_NDPA_EN;
4392
4393 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en);
4394 reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx);
4395 if (en) {
4396 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);
4397 rtw89_write32_set(rtwdev, reg, mask);
4398 } else {
4399 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);
4400 rtw89_write32_clr(rtwdev, reg, mask);
4401 }
4402 }
4403
rtw89_mac_init_bfee(struct rtw89_dev * rtwdev,u8 mac_idx)4404 static int rtw89_mac_init_bfee(struct rtw89_dev *rtwdev, u8 mac_idx)
4405 {
4406 u32 reg;
4407 u32 val32;
4408 int ret;
4409
4410 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
4411 if (ret)
4412 return ret;
4413
4414 /* AP mode set tx gid to 63 */
4415 /* STA mode set tx gid to 0(default) */
4416 reg = rtw89_mac_reg_by_idx(R_AX_BFMER_CTRL_0, mac_idx);
4417 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN);
4418
4419 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx);
4420 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP);
4421
4422 reg = rtw89_mac_reg_by_idx(R_AX_BFMEE_RESP_OPTION, mac_idx);
4423 val32 = FIELD_PREP(B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, BFRP_RX_STANDBY_TIMER);
4424 val32 |= FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER);
4425 rtw89_write32(rtwdev, reg, val32);
4426 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true);
4427
4428 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
4429 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL |
4430 B_AX_BFMEE_USE_NSTS |
4431 B_AX_BFMEE_CSI_GID_SEL |
4432 B_AX_BFMEE_CSI_FORCE_RETE_EN);
4433 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx);
4434 rtw89_write32(rtwdev, reg,
4435 u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) |
4436 u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) |
4437 u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK));
4438
4439 reg = rtw89_mac_reg_by_idx(R_AX_CSIRPT_OPTION, mac_idx);
4440 rtw89_write32_set(rtwdev, reg,
4441 B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN);
4442
4443 return 0;
4444 }
4445
rtw89_mac_set_csi_para_reg(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)4446 static int rtw89_mac_set_csi_para_reg(struct rtw89_dev *rtwdev,
4447 struct ieee80211_vif *vif,
4448 struct ieee80211_sta *sta)
4449 {
4450 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
4451 u8 mac_idx = rtwvif->mac_idx;
4452 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1;
4453 u8 port_sel = rtwvif->port;
4454 u8 sound_dim = 3, t;
4455 u8 *phy_cap = sta->deflink.he_cap.he_cap_elem.phy_cap_info;
4456 u32 reg;
4457 u16 val;
4458 int ret;
4459
4460 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
4461 if (ret)
4462 return ret;
4463
4464 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) ||
4465 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) {
4466 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD);
4467 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ);
4468 t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK,
4469 phy_cap[5]);
4470 sound_dim = min(sound_dim, t);
4471 }
4472 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) ||
4473 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) {
4474 ldpc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC);
4475 stbc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK);
4476 t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK,
4477 sta->deflink.vht_cap.cap);
4478 sound_dim = min(sound_dim, t);
4479 }
4480 nc = min(nc, sound_dim);
4481 nr = min(nr, sound_dim);
4482
4483 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
4484 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL);
4485
4486 val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) |
4487 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) |
4488 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) |
4489 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) |
4490 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) |
4491 FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) |
4492 FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en);
4493
4494 if (port_sel == 0)
4495 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
4496 else
4497 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx);
4498
4499 rtw89_write16(rtwdev, reg, val);
4500
4501 return 0;
4502 }
4503
rtw89_mac_csi_rrsc(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)4504 static int rtw89_mac_csi_rrsc(struct rtw89_dev *rtwdev,
4505 struct ieee80211_vif *vif,
4506 struct ieee80211_sta *sta)
4507 {
4508 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
4509 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M);
4510 u32 reg;
4511 u8 mac_idx = rtwvif->mac_idx;
4512 int ret;
4513
4514 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
4515 if (ret)
4516 return ret;
4517
4518 if (sta->deflink.he_cap.has_he) {
4519 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) |
4520 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) |
4521 BIT(RTW89_MAC_BF_RRSC_HE_MSC5));
4522 }
4523 if (sta->deflink.vht_cap.vht_supported) {
4524 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) |
4525 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) |
4526 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5));
4527 }
4528 if (sta->deflink.ht_cap.ht_supported) {
4529 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) |
4530 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) |
4531 BIT(RTW89_MAC_BF_RRSC_HT_MSC5));
4532 }
4533 reg = rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
4534 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL);
4535 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN);
4536 rtw89_write32(rtwdev,
4537 rtw89_mac_reg_by_idx(R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx),
4538 rrsc);
4539
4540 return 0;
4541 }
4542
rtw89_mac_bf_assoc(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)4543 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
4544 struct ieee80211_sta *sta)
4545 {
4546 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
4547
4548 if (rtw89_sta_has_beamformer_cap(sta)) {
4549 rtw89_debug(rtwdev, RTW89_DBG_BF,
4550 "initialize bfee for new association\n");
4551 rtw89_mac_init_bfee(rtwdev, rtwvif->mac_idx);
4552 rtw89_mac_set_csi_para_reg(rtwdev, vif, sta);
4553 rtw89_mac_csi_rrsc(rtwdev, vif, sta);
4554 }
4555 }
4556
rtw89_mac_bf_disassoc(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)4557 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
4558 struct ieee80211_sta *sta)
4559 {
4560 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
4561
4562 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false);
4563 }
4564
rtw89_mac_bf_set_gid_table(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_bss_conf * conf)4565 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
4566 struct ieee80211_bss_conf *conf)
4567 {
4568 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
4569 u8 mac_idx = rtwvif->mac_idx;
4570 __le32 *p;
4571
4572 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n");
4573
4574 p = (__le32 *)conf->mu_group.membership;
4575 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN0, mac_idx),
4576 le32_to_cpu(p[0]));
4577 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION_EN1, mac_idx),
4578 le32_to_cpu(p[1]));
4579
4580 p = (__le32 *)conf->mu_group.position;
4581 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION0, mac_idx),
4582 le32_to_cpu(p[0]));
4583 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION1, mac_idx),
4584 le32_to_cpu(p[1]));
4585 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION2, mac_idx),
4586 le32_to_cpu(p[2]));
4587 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(R_AX_GID_POSITION3, mac_idx),
4588 le32_to_cpu(p[3]));
4589 }
4590
4591 struct rtw89_mac_bf_monitor_iter_data {
4592 struct rtw89_dev *rtwdev;
4593 struct ieee80211_sta *down_sta;
4594 int count;
4595 };
4596
4597 static
rtw89_mac_bf_monitor_calc_iter(void * data,struct ieee80211_sta * sta)4598 void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta)
4599 {
4600 struct rtw89_mac_bf_monitor_iter_data *iter_data =
4601 (struct rtw89_mac_bf_monitor_iter_data *)data;
4602 struct ieee80211_sta *down_sta = iter_data->down_sta;
4603 int *count = &iter_data->count;
4604
4605 if (down_sta == sta)
4606 return;
4607
4608 if (rtw89_sta_has_beamformer_cap(sta))
4609 (*count)++;
4610 }
4611
rtw89_mac_bf_monitor_calc(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,bool disconnect)4612 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev,
4613 struct ieee80211_sta *sta, bool disconnect)
4614 {
4615 struct rtw89_mac_bf_monitor_iter_data data;
4616
4617 data.rtwdev = rtwdev;
4618 data.down_sta = disconnect ? sta : NULL;
4619 data.count = 0;
4620 ieee80211_iterate_stations_atomic(rtwdev->hw,
4621 rtw89_mac_bf_monitor_calc_iter,
4622 &data);
4623
4624 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count);
4625 if (data.count)
4626 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags);
4627 else
4628 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags);
4629 }
4630
_rtw89_mac_bf_monitor_track(struct rtw89_dev * rtwdev)4631 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev)
4632 {
4633 struct rtw89_traffic_stats *stats = &rtwdev->stats;
4634 struct rtw89_vif *rtwvif;
4635 bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv;
4636 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);
4637
4638 if (en == old)
4639 return;
4640
4641 rtw89_for_each_rtwvif(rtwdev, rtwvif)
4642 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en);
4643 }
4644
4645 static int
__rtw89_mac_set_tx_time(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,u32 tx_time)4646 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
4647 u32 tx_time)
4648 {
4649 #define MAC_AX_DFLT_TX_TIME 5280
4650 u8 mac_idx = rtwsta->rtwvif->mac_idx;
4651 u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time;
4652 u32 reg;
4653 int ret = 0;
4654
4655 if (rtwsta->cctl_tx_time) {
4656 rtwsta->ampdu_max_time = (max_tx_time - 512) >> 9;
4657 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta);
4658 } else {
4659 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
4660 if (ret) {
4661 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n");
4662 return ret;
4663 }
4664
4665 reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx);
4666 rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK,
4667 max_tx_time >> 5);
4668 }
4669
4670 return ret;
4671 }
4672
rtw89_mac_set_tx_time(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,bool resume,u32 tx_time)4673 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
4674 bool resume, u32 tx_time)
4675 {
4676 int ret = 0;
4677
4678 if (!resume) {
4679 rtwsta->cctl_tx_time = true;
4680 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time);
4681 } else {
4682 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time);
4683 rtwsta->cctl_tx_time = false;
4684 }
4685
4686 return ret;
4687 }
4688
rtw89_mac_get_tx_time(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,u32 * tx_time)4689 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
4690 u32 *tx_time)
4691 {
4692 u8 mac_idx = rtwsta->rtwvif->mac_idx;
4693 u32 reg;
4694 int ret = 0;
4695
4696 if (rtwsta->cctl_tx_time) {
4697 *tx_time = (rtwsta->ampdu_max_time + 1) << 9;
4698 } else {
4699 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
4700 if (ret) {
4701 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n");
4702 return ret;
4703 }
4704
4705 reg = rtw89_mac_reg_by_idx(R_AX_AMPDU_AGG_LIMIT, mac_idx);
4706 *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5;
4707 }
4708
4709 return ret;
4710 }
4711
rtw89_mac_set_tx_retry_limit(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,bool resume,u8 tx_retry)4712 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev,
4713 struct rtw89_sta *rtwsta,
4714 bool resume, u8 tx_retry)
4715 {
4716 int ret = 0;
4717
4718 rtwsta->data_tx_cnt_lmt = tx_retry;
4719
4720 if (!resume) {
4721 rtwsta->cctl_tx_retry_limit = true;
4722 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta);
4723 } else {
4724 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta);
4725 rtwsta->cctl_tx_retry_limit = false;
4726 }
4727
4728 return ret;
4729 }
4730
rtw89_mac_get_tx_retry_limit(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,u8 * tx_retry)4731 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev,
4732 struct rtw89_sta *rtwsta, u8 *tx_retry)
4733 {
4734 u8 mac_idx = rtwsta->rtwvif->mac_idx;
4735 u32 reg;
4736 int ret = 0;
4737
4738 if (rtwsta->cctl_tx_retry_limit) {
4739 *tx_retry = rtwsta->data_tx_cnt_lmt;
4740 } else {
4741 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
4742 if (ret) {
4743 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n");
4744 return ret;
4745 }
4746
4747 reg = rtw89_mac_reg_by_idx(R_AX_TXCNT, mac_idx);
4748 *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK);
4749 }
4750
4751 return ret;
4752 }
4753
rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,bool en)4754 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev,
4755 struct rtw89_vif *rtwvif, bool en)
4756 {
4757 u8 mac_idx = rtwvif->mac_idx;
4758 u16 set = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0;
4759 u32 reg;
4760 u32 ret;
4761
4762 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
4763 if (ret)
4764 return ret;
4765
4766 reg = rtw89_mac_reg_by_idx(R_AX_MUEDCA_EN, mac_idx);
4767 if (en)
4768 rtw89_write16_set(rtwdev, reg, set);
4769 else
4770 rtw89_write16_clr(rtwdev, reg, set);
4771
4772 return 0;
4773 }
4774
rtw89_mac_write_xtal_si(struct rtw89_dev * rtwdev,u8 offset,u8 val,u8 mask)4775 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask)
4776 {
4777 u32 val32;
4778 int ret;
4779
4780 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) |
4781 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) |
4782 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) |
4783 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) |
4784 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1);
4785 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32);
4786
4787 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL),
4788 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL);
4789 if (ret) {
4790 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n",
4791 offset, val, mask);
4792 return ret;
4793 }
4794
4795 return 0;
4796 }
4797 EXPORT_SYMBOL(rtw89_mac_write_xtal_si);
4798
rtw89_mac_read_xtal_si(struct rtw89_dev * rtwdev,u8 offset,u8 * val)4799 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val)
4800 {
4801 u32 val32;
4802 int ret;
4803
4804 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) |
4805 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) |
4806 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) |
4807 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) |
4808 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1);
4809 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32);
4810
4811 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL),
4812 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL);
4813 if (ret) {
4814 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset);
4815 return ret;
4816 }
4817
4818 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1);
4819
4820 return 0;
4821 }
4822
4823 static
rtw89_mac_pkt_drop_sta(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta)4824 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta)
4825 {
4826 static const enum rtw89_pkt_drop_sel sels[] = {
4827 RTW89_PKT_DROP_SEL_MACID_BE_ONCE,
4828 RTW89_PKT_DROP_SEL_MACID_BK_ONCE,
4829 RTW89_PKT_DROP_SEL_MACID_VI_ONCE,
4830 RTW89_PKT_DROP_SEL_MACID_VO_ONCE,
4831 };
4832 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
4833 struct rtw89_pkt_drop_params params = {0};
4834 int i;
4835
4836 params.mac_band = RTW89_MAC_0;
4837 params.macid = rtwsta->mac_id;
4838 params.port = rtwvif->port;
4839 params.mbssid = 0;
4840 params.tf_trs = rtwvif->trigger;
4841
4842 for (i = 0; i < ARRAY_SIZE(sels); i++) {
4843 params.sel = sels[i];
4844 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms);
4845 }
4846 }
4847
rtw89_mac_pkt_drop_vif_iter(void * data,struct ieee80211_sta * sta)4848 static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta)
4849 {
4850 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
4851 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
4852 struct rtw89_dev *rtwdev = rtwvif->rtwdev;
4853 struct rtw89_vif *target = data;
4854
4855 if (rtwvif != target)
4856 return;
4857
4858 rtw89_mac_pkt_drop_sta(rtwdev, rtwsta);
4859 }
4860
rtw89_mac_pkt_drop_vif(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4861 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
4862 {
4863 ieee80211_iterate_stations_atomic(rtwdev->hw,
4864 rtw89_mac_pkt_drop_vif_iter,
4865 rtwvif);
4866 }
4867
