1 /* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG (wei_wang@realsil.com.cn)
20 * Micky Ching (micky_ching@realsil.com.cn)
21 */
22
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
26 #include <linux/workqueue.h>
27 #include <linux/vmalloc.h>
28
29 #include "rtsx.h"
30 #include "sd.h"
31 #include "xd.h"
32 #include "ms.h"
33
rtsx_calibration(struct rtsx_chip * chip)34 static void rtsx_calibration(struct rtsx_chip *chip)
35 {
36 rtsx_write_phy_register(chip, 0x1B, 0x135E);
37 wait_timeout(10);
38 rtsx_write_phy_register(chip, 0x00, 0x0280);
39 rtsx_write_phy_register(chip, 0x01, 0x7112);
40 rtsx_write_phy_register(chip, 0x01, 0x7110);
41 rtsx_write_phy_register(chip, 0x01, 0x7112);
42 rtsx_write_phy_register(chip, 0x01, 0x7113);
43 rtsx_write_phy_register(chip, 0x00, 0x0288);
44 }
45
rtsx_enable_card_int(struct rtsx_chip * chip)46 void rtsx_enable_card_int(struct rtsx_chip *chip)
47 {
48 u32 reg = rtsx_readl(chip, RTSX_BIER);
49 int i;
50
51 for (i = 0; i <= chip->max_lun; i++) {
52 if (chip->lun2card[i] & XD_CARD)
53 reg |= XD_INT_EN;
54 if (chip->lun2card[i] & SD_CARD)
55 reg |= SD_INT_EN;
56 if (chip->lun2card[i] & MS_CARD)
57 reg |= MS_INT_EN;
58 }
59 if (chip->hw_bypass_sd)
60 reg &= ~((u32)SD_INT_EN);
61
62 rtsx_writel(chip, RTSX_BIER, reg);
63 }
64
rtsx_enable_bus_int(struct rtsx_chip * chip)65 void rtsx_enable_bus_int(struct rtsx_chip *chip)
66 {
67 u32 reg = 0;
68 #ifndef DISABLE_CARD_INT
69 int i;
70 #endif
71
72 reg = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN;
73
74 #ifndef DISABLE_CARD_INT
75 for (i = 0; i <= chip->max_lun; i++) {
76 dev_dbg(rtsx_dev(chip), "lun2card[%d] = 0x%02x\n",
77 i, chip->lun2card[i]);
78
79 if (chip->lun2card[i] & XD_CARD)
80 reg |= XD_INT_EN;
81 if (chip->lun2card[i] & SD_CARD)
82 reg |= SD_INT_EN;
83 if (chip->lun2card[i] & MS_CARD)
84 reg |= MS_INT_EN;
85 }
86 if (chip->hw_bypass_sd)
87 reg &= ~((u32)SD_INT_EN);
88 #endif
89
90 if (chip->ic_version >= IC_VER_C)
91 reg |= DELINK_INT_EN;
92 #ifdef SUPPORT_OCP
93 reg |= OC_INT_EN;
94 #endif
95 if (!chip->adma_mode)
96 reg |= DATA_DONE_INT_EN;
97
98 /* Enable Bus Interrupt */
99 rtsx_writel(chip, RTSX_BIER, reg);
100
101 dev_dbg(rtsx_dev(chip), "RTSX_BIER: 0x%08x\n", reg);
102 }
103
rtsx_disable_bus_int(struct rtsx_chip * chip)104 void rtsx_disable_bus_int(struct rtsx_chip *chip)
105 {
106 rtsx_writel(chip, RTSX_BIER, 0);
107 }
108
rtsx_pre_handle_sdio_old(struct rtsx_chip * chip)109 static int rtsx_pre_handle_sdio_old(struct rtsx_chip *chip)
110 {
111 int retval;
112
113 if (chip->ignore_sd && CHK_SDIO_EXIST(chip)) {
114 if (chip->asic_code) {
115 retval = rtsx_write_register(chip, CARD_PULL_CTL5,
116 0xFF,
117 MS_INS_PU | SD_WP_PU |
118 SD_CD_PU | SD_CMD_PU);
119 if (retval) {
120 return retval;
121 }
122 } else {
123 retval = rtsx_write_register(chip, FPGA_PULL_CTL,
124 0xFF,
125 FPGA_SD_PULL_CTL_EN);
126 if (retval) {
127 return retval;
128 }
129 }
130 retval = rtsx_write_register(chip, CARD_SHARE_MODE, 0xFF,
131 CARD_SHARE_48_SD);
132 if (retval) {
133 return retval;
134 }
135
136 /* Enable SDIO internal clock */
137 retval = rtsx_write_register(chip, 0xFF2C, 0x01, 0x01);
138 if (retval) {
139 return retval;
140 }
141
142 retval = rtsx_write_register(chip, SDIO_CTRL, 0xFF,
143 SDIO_BUS_CTRL | SDIO_CD_CTRL);
144 if (retval) {
145 return retval;
146 }
147
148 chip->sd_int = 1;
149 chip->sd_io = 1;
150 } else {
151 chip->need_reset |= SD_CARD;
152 }
153
154 return STATUS_SUCCESS;
155 }
156
157 #ifdef HW_AUTO_SWITCH_SD_BUS
rtsx_pre_handle_sdio_new(struct rtsx_chip * chip)158 static int rtsx_pre_handle_sdio_new(struct rtsx_chip *chip)
159 {
160 u8 tmp;
161 bool sw_bypass_sd = false;
162 int retval;
163
164 if (chip->driver_first_load) {
165 if (CHECK_PID(chip, 0x5288)) {
166 retval = rtsx_read_register(chip, 0xFE5A, &tmp);
167 if (retval) {
168 return retval;
169 }
170 if (tmp & 0x08)
171 sw_bypass_sd = true;
172 } else if (CHECK_PID(chip, 0x5208)) {
173 retval = rtsx_read_register(chip, 0xFE70, &tmp);
174 if (retval) {
175 return retval;
176 }
177 if (tmp & 0x80)
178 sw_bypass_sd = true;
179 }
180 } else {
181 if (chip->sdio_in_charge)
182 sw_bypass_sd = true;
183 }
184 dev_dbg(rtsx_dev(chip), "chip->sdio_in_charge = %d\n",
185 chip->sdio_in_charge);
186 dev_dbg(rtsx_dev(chip), "chip->driver_first_load = %d\n",
187 chip->driver_first_load);
188 dev_dbg(rtsx_dev(chip), "sw_bypass_sd = %d\n",
189 sw_bypass_sd);
190
191 if (sw_bypass_sd) {
192 u8 cd_toggle_mask = 0;
193
194 retval = rtsx_read_register(chip, TLPTISTAT, &tmp);
195 if (retval) {
196 return retval;
197 }
198 cd_toggle_mask = 0x08;
199
200 if (tmp & cd_toggle_mask) {
201 /* Disable sdio_bus_auto_switch */
202 if (CHECK_PID(chip, 0x5288)) {
203 retval = rtsx_write_register(chip, 0xFE5A,
204 0x08, 0x00);
205 if (retval) {
206 return retval;
207 }
208 } else if (CHECK_PID(chip, 0x5208)) {
209 retval = rtsx_write_register(chip, 0xFE70,
210 0x80, 0x00);
211 if (retval) {
212 return retval;
213 }
214 }
215
216 retval = rtsx_write_register(chip, TLPTISTAT, 0xFF,
217 tmp);
218 if (retval) {
219 return retval;
220 }
221
222 chip->need_reset |= SD_CARD;
223 } else {
224 dev_dbg(rtsx_dev(chip), "Chip inserted with SDIO!\n");
225
226 if (chip->asic_code) {
227 retval = sd_pull_ctl_enable(chip);
228 if (retval != STATUS_SUCCESS) {
229 return STATUS_FAIL;
230 }
231 } else {
232 retval = rtsx_write_register
233 (chip, FPGA_PULL_CTL,
234 FPGA_SD_PULL_CTL_BIT | 0x20,
235 0);
236 if (retval) {
237 return retval;
238 }
239 }
240 retval = card_share_mode(chip, SD_CARD);
241 if (retval != STATUS_SUCCESS) {
242 return STATUS_FAIL;
243 }
244
245 /* Enable sdio_bus_auto_switch */
246 if (CHECK_PID(chip, 0x5288)) {
247 retval = rtsx_write_register(chip, 0xFE5A,
248 0x08, 0x08);
249 if (retval) {
250 return retval;
251 }
252 } else if (CHECK_PID(chip, 0x5208)) {
253 retval = rtsx_write_register(chip, 0xFE70,
254 0x80, 0x80);
255 if (retval) {
256 return retval;
257 }
258 }
259
260 chip->chip_insert_with_sdio = 1;
261 chip->sd_io = 1;
262 }
263 } else {
264 retval = rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
265 if (retval) {
266 return retval;
267 }
268
269 chip->need_reset |= SD_CARD;
270 }
271
272 return STATUS_SUCCESS;
273 }
274 #endif
275
rtsx_reset_aspm(struct rtsx_chip * chip)276 static int rtsx_reset_aspm(struct rtsx_chip *chip)
277 {
278 int ret;
279
280 if (chip->dynamic_aspm) {
281 if (!CHK_SDIO_EXIST(chip) || !CHECK_PID(chip, 0x5288))
282 return STATUS_SUCCESS;
283
284 ret = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF,
285 chip->aspm_l0s_l1_en);
286 if (ret != STATUS_SUCCESS) {
287 return STATUS_FAIL;
288 }
289
290 return STATUS_SUCCESS;
291 }
292
293 if (CHECK_PID(chip, 0x5208)) {
294 ret = rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF, 0x3F);
295 if (ret) {
296 return ret;
297 }
298 }
299 ret = rtsx_write_config_byte(chip, LCTLR, chip->aspm_l0s_l1_en);
300 if (ret != STATUS_SUCCESS) {
301 return STATUS_FAIL;
302 }
303
304 chip->aspm_level[0] = chip->aspm_l0s_l1_en;
305 if (CHK_SDIO_EXIST(chip)) {
306 chip->aspm_level[1] = chip->aspm_l0s_l1_en;
307 ret = rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1,
308 0xC0, 0xFF, chip->aspm_l0s_l1_en);
309 if (ret != STATUS_SUCCESS) {
310 return STATUS_FAIL;
311 }
312 }
313
314 chip->aspm_enabled = 1;
315
316 return STATUS_SUCCESS;
317 }
318
rtsx_enable_pcie_intr(struct rtsx_chip * chip)319 static int rtsx_enable_pcie_intr(struct rtsx_chip *chip)
320 {
321 int ret;
322
323 if (!chip->asic_code || !CHECK_PID(chip, 0x5208)) {
324 rtsx_enable_bus_int(chip);
325 return STATUS_SUCCESS;
326 }
327
328 if (chip->phy_debug_mode) {
329 ret = rtsx_write_register(chip, CDRESUMECTL, 0x77, 0);
330 if (ret) {
331 return ret;
332 }
333 rtsx_disable_bus_int(chip);
334 } else {
335 rtsx_enable_bus_int(chip);
336 }
337
338 if (chip->ic_version >= IC_VER_D) {
339 u16 reg;
340
341 ret = rtsx_read_phy_register(chip, 0x00, ®);
342 if (ret != STATUS_SUCCESS) {
343 return STATUS_FAIL;
344 }
345
346 reg &= 0xFE7F;
347 reg |= 0x80;
348 ret = rtsx_write_phy_register(chip, 0x00, reg);
349 if (ret != STATUS_SUCCESS) {
350 return STATUS_FAIL;
351 }
352
353 ret = rtsx_read_phy_register(chip, 0x1C, ®);
354 if (ret != STATUS_SUCCESS) {
355 return STATUS_FAIL;
356 }
357
358 reg &= 0xFFF7;
359 ret = rtsx_write_phy_register(chip, 0x1C, reg);
360 if (ret != STATUS_SUCCESS) {
361 return STATUS_FAIL;
362 }
363 }
364
365 if (chip->driver_first_load && (chip->ic_version < IC_VER_C))
366 rtsx_calibration(chip);
367
368 return STATUS_SUCCESS;
369 }
370
rtsx_reset_chip(struct rtsx_chip * chip)371 int rtsx_reset_chip(struct rtsx_chip *chip)
372 {
373 int retval;
374
375 rtsx_writel(chip, RTSX_HCBAR, chip->host_cmds_addr);
376
377 rtsx_disable_aspm(chip);
378
379 retval = rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 0x00);
380 if (retval) {
381 return retval;
382 }
383
384 /* Disable card clock */
385 retval = rtsx_write_register(chip, CARD_CLK_EN, 0x1E, 0);
386 if (retval) {
387 return retval;
388 }
389
390 #ifdef SUPPORT_OCP
391 /* SSC power on, OCD power on */
392 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
393 retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN, 0);
394 if (retval) {
395 return retval;
396 }
397 } else {
398 retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN,
399 MS_OC_POWER_DOWN);
400 if (retval) {
401 return retval;
402 }
403 }
404
405 retval = rtsx_write_register(chip, OCPPARA1, OCP_TIME_MASK,
406 OCP_TIME_800);
407 if (retval) {
408 return retval;
409 }
410 retval = rtsx_write_register(chip, OCPPARA2, OCP_THD_MASK,
411 OCP_THD_244_946);
412 if (retval) {
413 return retval;
414 }
415 retval = rtsx_write_register(chip, OCPCTL, 0xFF,
416 CARD_OC_INT_EN | CARD_DETECT_EN);
417 if (retval) {
418 return retval;
419 }
420 #else
421 /* OC power down */
422 retval = rtsx_write_register(chip, FPDCTL, OC_POWER_DOWN,
423 OC_POWER_DOWN);
424 if (retval) {
425 return retval;
426 }
427 #endif
428
429 if (!CHECK_PID(chip, 0x5288)) {
430 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0xFF, 0x03);
431 if (retval) {
432 return retval;
433 }
434 }
435
436 /* Turn off LED */
437 retval = rtsx_write_register(chip, CARD_GPIO, 0xFF, 0x03);
438 if (retval) {
439 return retval;
440 }
441
442 /* Reset delink mode */
443 retval = rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0);
444 if (retval) {
445 return retval;
446 }
447
448 /* Card driving select */
449 retval = rtsx_write_register(chip, CARD_DRIVE_SEL, 0xFF,
450 chip->card_drive_sel);
451 if (retval) {
452 return retval;
453 }
454
455 #ifdef LED_AUTO_BLINK
456 retval = rtsx_write_register(chip, CARD_AUTO_BLINK, 0xFF,
457 LED_BLINK_SPEED | BLINK_EN | LED_GPIO0);
458 if (retval) {
459 return retval;
460 }
461 #endif
462
463 if (chip->asic_code) {
464 /* Enable SSC Clock */
465 retval = rtsx_write_register(chip, SSC_CTL1, 0xFF,
466 SSC_8X_EN | SSC_SEL_4M);
467 if (retval) {
468 return retval;
469 }
470 retval = rtsx_write_register(chip, SSC_CTL2, 0xFF, 0x12);
471 if (retval) {
472 return retval;
473 }
474 }
475
476 /*
477 * Disable cd_pwr_save (u_force_rst_core_en=0, u_cd_rst_core_en=0)
478 * 0xFE5B
479 * bit[1] u_cd_rst_core_en rst_value = 0
480 * bit[2] u_force_rst_core_en rst_value = 0
481 * bit[5] u_mac_phy_rst_n_dbg rst_value = 1
482 * bit[4] u_non_sticky_rst_n_dbg rst_value = 0
483 */
484 retval = rtsx_write_register(chip, CHANGE_LINK_STATE, 0x16, 0x10);
485 if (retval) {
486 return retval;
487 }
488
489 /* Enable ASPM */
490 if (chip->aspm_l0s_l1_en) {
491 retval = rtsx_reset_aspm(chip);
492 if (retval != STATUS_SUCCESS) {
493 return STATUS_FAIL;
494 }
495 } else {
496 if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
497 retval = rtsx_write_phy_register(chip, 0x07, 0x0129);
498 if (retval != STATUS_SUCCESS) {
499 return STATUS_FAIL;
500 }
501 }
502 retval = rtsx_write_config_byte(chip, LCTLR,
503 chip->aspm_l0s_l1_en);
504 if (retval != STATUS_SUCCESS) {
505 return STATUS_FAIL;
506 }
507 }
508
509 retval = rtsx_write_config_byte(chip, 0x81, 1);
510 if (retval != STATUS_SUCCESS) {
511 return STATUS_FAIL;
512 }
513
514 if (CHK_SDIO_EXIST(chip)) {
515 retval = rtsx_write_cfg_dw(chip,
516 CHECK_PID(chip, 0x5288) ? 2 : 1,
517 0xC0, 0xFF00, 0x0100);
518
519 if (retval != STATUS_SUCCESS) {
520 return STATUS_FAIL;
521 }
522 }
523
524 if (CHECK_PID(chip, 0x5288) && !CHK_SDIO_EXIST(chip)) {
525 retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFFFF, 0x0103);
526 if (retval != STATUS_SUCCESS) {
527 return STATUS_FAIL;
528 }
529
530 retval = rtsx_write_cfg_dw(chip, 2, 0x84, 0xFF, 0x03);
531 if (retval != STATUS_SUCCESS) {
532 return STATUS_FAIL;
533 }
534 }
535
536 retval = rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT,
537 LINK_RDY_INT);
538 if (retval) {
539 return retval;
540 }
541
542 retval = rtsx_write_register(chip, PERST_GLITCH_WIDTH, 0xFF, 0x80);
543 if (retval) {
544 return retval;
545 }
546
547 retval = rtsx_enable_pcie_intr(chip);
548 if (retval != STATUS_SUCCESS) {
549 return STATUS_FAIL;
550 }
551
552 chip->need_reset = 0;
553
554 chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
555
556 if (chip->hw_bypass_sd)
557 goto nextcard;
558 dev_dbg(rtsx_dev(chip), "In %s, chip->int_reg = 0x%x\n", __func__,
559 chip->int_reg);
560 if (chip->int_reg & SD_EXIST) {
561 #ifdef HW_AUTO_SWITCH_SD_BUS
562 if (CHECK_PID(chip, 0x5208) && (chip->ic_version < IC_VER_C))
563 retval = rtsx_pre_handle_sdio_old(chip);
564 else
565 retval = rtsx_pre_handle_sdio_new(chip);
566
567 dev_dbg(rtsx_dev(chip), "chip->need_reset = 0x%x (%s)\n",
568 (unsigned int)(chip->need_reset), __func__);
569 #else /* HW_AUTO_SWITCH_SD_BUS */
570 retval = rtsx_pre_handle_sdio_old(chip);
571 #endif /* HW_AUTO_SWITCH_SD_BUS */
572 if (retval != STATUS_SUCCESS) {
573 return STATUS_FAIL;
574 }
575
576 } else {
577 chip->sd_io = 0;
578 retval = rtsx_write_register(chip, SDIO_CTRL,
579 SDIO_BUS_CTRL | SDIO_CD_CTRL, 0);
580 if (retval) {
581 return retval;
582 }
583 }
584
585 nextcard:
586 if (chip->int_reg & XD_EXIST)
587 chip->need_reset |= XD_CARD;
588 if (chip->int_reg & MS_EXIST)
589 chip->need_reset |= MS_CARD;
590 if (chip->int_reg & CARD_EXIST) {
591 retval = rtsx_write_register(chip, SSC_CTL1, SSC_RSTB,
592 SSC_RSTB);
593 if (retval) {
594 return retval;
595 }
596 }
597
598 dev_dbg(rtsx_dev(chip), "In %s, chip->need_reset = 0x%x\n", __func__,
599 (unsigned int)(chip->need_reset));
600
601 retval = rtsx_write_register(chip, RCCTL, 0x01, 0x00);
602 if (retval) {
603 return retval;
604 }
605
606 if (CHECK_PID(chip, 0x5208) || CHECK_PID(chip, 0x5288)) {
607 /* Turn off main power when entering S3/S4 state */
608 retval = rtsx_write_register(chip, MAIN_PWR_OFF_CTL, 0x03,
609 0x03);
610 if (retval) {
611 return retval;
612 }
613 }
614
615 if (chip->remote_wakeup_en && !chip->auto_delink_en) {
616 retval = rtsx_write_register(chip, WAKE_SEL_CTL, 0x07, 0x07);
617 if (retval) {
618 return retval;
619 }
620 if (chip->aux_pwr_exist) {
621 retval = rtsx_write_register(chip, PME_FORCE_CTL,
622 0xFF, 0x33);
623 if (retval) {
624 return retval;
625 }
626 }
627 } else {
628 retval = rtsx_write_register(chip, WAKE_SEL_CTL, 0x07, 0x04);
629 if (retval) {
630 return retval;
631 }
632 retval = rtsx_write_register(chip, PME_FORCE_CTL, 0xFF, 0x30);
633 if (retval) {
634 return retval;
635 }
636 }
637
638 if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) {
639 retval = rtsx_write_register(chip, PETXCFG, 0x1C, 0x14);
640 if (retval) {
641 return retval;
642 }
643 }
644
645 if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
646 retval = rtsx_clr_phy_reg_bit(chip, 0x1C, 2);
647 if (retval != STATUS_SUCCESS) {
648 return STATUS_FAIL;
649 }
650 }
651
652 if (chip->ft2_fast_mode) {
653 retval = rtsx_write_register(chip, CARD_PWR_CTL, 0xFF,
654 MS_PARTIAL_POWER_ON |
655 SD_PARTIAL_POWER_ON);
656 if (retval) {
657 return retval;
658 }
659 udelay(chip->pmos_pwr_on_interval);
660 retval = rtsx_write_register(chip, CARD_PWR_CTL, 0xFF,
661 MS_POWER_ON | SD_POWER_ON);
662 if (retval) {
663 return retval;
664 }
665
666 wait_timeout(200);
667 }
668
669 /* Reset card */
670 rtsx_reset_detected_cards(chip, 0);
671
672 chip->driver_first_load = 0;
673
674 return STATUS_SUCCESS;
675 }
676
check_sd_speed_prior(u32 sd_speed_prior)677 static inline int check_sd_speed_prior(u32 sd_speed_prior)
678 {
679 bool fake_para = false;
680 int i;
681
682 for (i = 0; i < 4; i++) {
683 u8 tmp = (u8)(sd_speed_prior >> (i * 8));
684
685 if ((tmp < 0x01) || (tmp > 0x04)) {
686 fake_para = true;
687 break;
688 }
689 }
690
691 return !fake_para;
692 }
693
check_sd_current_prior(u32 sd_current_prior)694 static inline int check_sd_current_prior(u32 sd_current_prior)
695 {
696 bool fake_para = false;
697 int i;
698
699 for (i = 0; i < 4; i++) {
700 u8 tmp = (u8)(sd_current_prior >> (i * 8));
701
702 if (tmp > 0x03) {
703 fake_para = true;
704 break;
705 }
706 }
707
708 return !fake_para;
709 }
710
rts5208_init(struct rtsx_chip * chip)711 static int rts5208_init(struct rtsx_chip *chip)
712 {
713 int retval;
714 u16 reg = 0;
715 u8 val = 0;
716
717 retval = rtsx_write_register(chip, CLK_SEL, 0x03, 0x03);
718 if (retval) {
719 return retval;
720 }
721 retval = rtsx_read_register(chip, CLK_SEL, &val);
722 if (retval) {
723 return retval;
724 }
725 chip->asic_code = val == 0 ? 1 : 0;
726
727 if (chip->asic_code) {
728 retval = rtsx_read_phy_register(chip, 0x1C, ®);
729 if (retval != STATUS_SUCCESS) {
730 return STATUS_FAIL;
731 }
732
733 dev_dbg(rtsx_dev(chip), "Value of phy register 0x1C is 0x%x\n",
734 reg);
735 chip->ic_version = (reg >> 4) & 0x07;
736 chip->phy_debug_mode = reg & PHY_DEBUG_MODE ? 1 : 0;
737
738 } else {
739 retval = rtsx_read_register(chip, 0xFE80, &val);
740 if (retval) {
741 return retval;
742 }
743 chip->ic_version = val;
744 chip->phy_debug_mode = 0;
745 }
746
747 retval = rtsx_read_register(chip, PDINFO, &val);
748 if (retval) {
749 return retval;
750 }
751 dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val);
752 chip->aux_pwr_exist = val & AUX_PWR_DETECTED ? 1 : 0;
753
754 retval = rtsx_read_register(chip, 0xFE50, &val);
755 if (retval) {
756 return retval;
757 }
758 chip->hw_bypass_sd = val & 0x01 ? 1 : 0;
759
760 rtsx_read_config_byte(chip, 0x0E, &val);
761 if (val & 0x80)
762 SET_SDIO_EXIST(chip);
763 else
764 CLR_SDIO_EXIST(chip);
765
766 if (chip->use_hw_setting) {
767 retval = rtsx_read_register(chip, CHANGE_LINK_STATE, &val);
768 if (retval) {
769 return retval;
770 }
771 chip->auto_delink_en = val & 0x80 ? 1 : 0;
772 }
773
774 return STATUS_SUCCESS;
775 }
776
rts5288_init(struct rtsx_chip * chip)777 static int rts5288_init(struct rtsx_chip *chip)
778 {
779 int retval;
780 u8 val = 0, max_func;
781 u32 lval = 0;
782
783 retval = rtsx_write_register(chip, CLK_SEL, 0x03, 0x03);
784 if (retval) {
785 return retval;
786 }
787 retval = rtsx_read_register(chip, CLK_SEL, &val);
788 if (retval) {
789 return retval;
790 }
791 chip->asic_code = val == 0 ? 1 : 0;
792
793 chip->ic_version = 0;
794 chip->phy_debug_mode = 0;
795
796 retval = rtsx_read_register(chip, PDINFO, &val);
797 if (retval) {
798 return retval;
799 }
800 dev_dbg(rtsx_dev(chip), "PDINFO: 0x%x\n", val);
801 chip->aux_pwr_exist = val & AUX_PWR_DETECTED ? 1 : 0;
802
803 retval = rtsx_read_register(chip, CARD_SHARE_MODE, &val);
804 if (retval) {
805 return retval;
806 }
807 dev_dbg(rtsx_dev(chip), "CARD_SHARE_MODE: 0x%x\n", val);
808 chip->baro_pkg = val & 0x04 ? QFN : LQFP;
809
810 retval = rtsx_read_register(chip, 0xFE5A, &val);
811 if (retval) {
812 return retval;
813 }
814 chip->hw_bypass_sd = val & 0x10 ? 1 : 0;
815
816 retval = rtsx_read_cfg_dw(chip, 0, 0x718, &lval);
817 if (retval != STATUS_SUCCESS) {
818 return STATUS_FAIL;
819 }
820
821 max_func = (u8)((lval >> 29) & 0x07);
822 dev_dbg(rtsx_dev(chip), "Max function number: %d\n", max_func);
823 if (max_func == 0x02)
824 SET_SDIO_EXIST(chip);
825 else
826 CLR_SDIO_EXIST(chip);
827
828 if (chip->use_hw_setting) {
829 retval = rtsx_read_register(chip, CHANGE_LINK_STATE, &val);
830 if (retval) {
831 return retval;
832 }
833 chip->auto_delink_en = val & 0x80 ? 1 : 0;
834
835 if (CHECK_BARO_PKG(chip, LQFP))
836 chip->lun_mode = SD_MS_1LUN;
837 else
838 chip->lun_mode = DEFAULT_SINGLE;
839 }
840
841 return STATUS_SUCCESS;
842 }
843
rtsx_init_chip(struct rtsx_chip * chip)844 int rtsx_init_chip(struct rtsx_chip *chip)
845 {
846 struct sd_info *sd_card = &chip->sd_card;
847 struct xd_info *xd_card = &chip->xd_card;
848 struct ms_info *ms_card = &chip->ms_card;
849 int retval;
850 unsigned int i;
851
852 dev_dbg(rtsx_dev(chip), "Vendor ID: 0x%04x, Product ID: 0x%04x\n",
853 chip->vendor_id, chip->product_id);
854
855 chip->ic_version = 0;
856
857 memset(xd_card, 0, sizeof(struct xd_info));
858 memset(sd_card, 0, sizeof(struct sd_info));
859 memset(ms_card, 0, sizeof(struct ms_info));
860
861 chip->xd_reset_counter = 0;
862 chip->sd_reset_counter = 0;
863 chip->ms_reset_counter = 0;
864
865 chip->xd_show_cnt = MAX_SHOW_CNT;
866 chip->sd_show_cnt = MAX_SHOW_CNT;
867 chip->ms_show_cnt = MAX_SHOW_CNT;
868
869 chip->sd_io = 0;
870 chip->auto_delink_cnt = 0;
871 chip->auto_delink_allowed = 1;
872 rtsx_set_stat(chip, RTSX_STAT_INIT);
873
874 chip->aspm_enabled = 0;
875 chip->chip_insert_with_sdio = 0;
876 chip->sdio_aspm = 0;
877 chip->sdio_idle = 0;
878 chip->sdio_counter = 0;
879 chip->cur_card = 0;
880 chip->phy_debug_mode = 0;
881 chip->sdio_func_exist = 0;
882 memset(chip->sdio_raw_data, 0, 12);
883
884 for (i = 0; i < MAX_ALLOWED_LUN_CNT; i++) {
885 set_sense_type(chip, i, SENSE_TYPE_NO_SENSE);
886 chip->rw_fail_cnt[i] = 0;
887 }
888
889 if (!check_sd_speed_prior(chip->sd_speed_prior))
890 chip->sd_speed_prior = 0x01040203;
891
892 dev_dbg(rtsx_dev(chip), "sd_speed_prior = 0x%08x\n",
893 chip->sd_speed_prior);
894
895 if (!check_sd_current_prior(chip->sd_current_prior))
896 chip->sd_current_prior = 0x00010203;
897
898 dev_dbg(rtsx_dev(chip), "sd_current_prior = 0x%08x\n",
899 chip->sd_current_prior);
900
901 if ((chip->sd_ddr_tx_phase > 31) || (chip->sd_ddr_tx_phase < 0))
902 chip->sd_ddr_tx_phase = 0;
903
904 if ((chip->mmc_ddr_tx_phase > 31) || (chip->mmc_ddr_tx_phase < 0))
905 chip->mmc_ddr_tx_phase = 0;
906
907 retval = rtsx_write_register(chip, FPDCTL, SSC_POWER_DOWN, 0);
908 if (retval) {
909 return retval;
910 }
911 wait_timeout(200);
912 retval = rtsx_write_register(chip, CLK_DIV, 0x07, 0x07);
913 if (retval) {
914 return retval;
915 }
916 dev_dbg(rtsx_dev(chip), "chip->use_hw_setting = %d\n",
917 chip->use_hw_setting);
918
919 if (CHECK_PID(chip, 0x5208)) {
920 retval = rts5208_init(chip);
921 if (retval != STATUS_SUCCESS) {
922 return STATUS_FAIL;
923 }
924
925 } else if (CHECK_PID(chip, 0x5288)) {
926 retval = rts5288_init(chip);
927 if (retval != STATUS_SUCCESS) {
928 return STATUS_FAIL;
929 }
930 }
931
932 if (chip->ss_en == 2)
933 chip->ss_en = 0;
934
935 dev_dbg(rtsx_dev(chip), "chip->asic_code = %d\n", chip->asic_code);
936 dev_dbg(rtsx_dev(chip), "chip->ic_version = 0x%x\n", chip->ic_version);
937 dev_dbg(rtsx_dev(chip), "chip->phy_debug_mode = %d\n",
938 chip->phy_debug_mode);
939 dev_dbg(rtsx_dev(chip), "chip->aux_pwr_exist = %d\n",
940 chip->aux_pwr_exist);
941 dev_dbg(rtsx_dev(chip), "chip->sdio_func_exist = %d\n",
942 chip->sdio_func_exist);
943 dev_dbg(rtsx_dev(chip), "chip->hw_bypass_sd = %d\n",
944 chip->hw_bypass_sd);
945 dev_dbg(rtsx_dev(chip), "chip->aspm_l0s_l1_en = %d\n",
946 chip->aspm_l0s_l1_en);
947 dev_dbg(rtsx_dev(chip), "chip->lun_mode = %d\n", chip->lun_mode);
948 dev_dbg(rtsx_dev(chip), "chip->auto_delink_en = %d\n",
949 chip->auto_delink_en);
950 dev_dbg(rtsx_dev(chip), "chip->ss_en = %d\n", chip->ss_en);
951 dev_dbg(rtsx_dev(chip), "chip->baro_pkg = %d\n", chip->baro_pkg);
952
953 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
954 chip->card2lun[SD_CARD] = 0;
955 chip->card2lun[MS_CARD] = 1;
956 chip->card2lun[XD_CARD] = 0xFF;
957 chip->lun2card[0] = SD_CARD;
958 chip->lun2card[1] = MS_CARD;
959 chip->max_lun = 1;
960 SET_SDIO_IGNORED(chip);
961 } else if (CHECK_LUN_MODE(chip, SD_MS_1LUN)) {
962 chip->card2lun[SD_CARD] = 0;
963 chip->card2lun[MS_CARD] = 0;
964 chip->card2lun[XD_CARD] = 0xFF;
965 chip->lun2card[0] = SD_CARD | MS_CARD;
966 chip->max_lun = 0;
967 } else {
968 chip->card2lun[XD_CARD] = 0;
969 chip->card2lun[SD_CARD] = 0;
970 chip->card2lun[MS_CARD] = 0;
971 chip->lun2card[0] = XD_CARD | SD_CARD | MS_CARD;
972 chip->max_lun = 0;
973 }
974
975 retval = rtsx_reset_chip(chip);
976 if (retval != STATUS_SUCCESS) {
977 return STATUS_FAIL;
978 }
979
980 return STATUS_SUCCESS;
981 }
982
rtsx_release_chip(struct rtsx_chip * chip)983 void rtsx_release_chip(struct rtsx_chip *chip)
984 {
985 xd_free_l2p_tbl(chip);
986 ms_free_l2p_tbl(chip);
987 chip->card_exist = 0;
988 chip->card_ready = 0;
989 }
990
991 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
rtsx_blink_led(struct rtsx_chip * chip)992 static inline void rtsx_blink_led(struct rtsx_chip *chip)
993 {
994 if (chip->card_exist && chip->blink_led) {
995 if (chip->led_toggle_counter < LED_TOGGLE_INTERVAL) {
996 chip->led_toggle_counter++;
997 } else {
998 chip->led_toggle_counter = 0;
999 toggle_gpio(chip, LED_GPIO);
1000 }
1001 }
1002 }
1003 #endif
1004
rtsx_monitor_aspm_config(struct rtsx_chip * chip)1005 static void rtsx_monitor_aspm_config(struct rtsx_chip *chip)
1006 {
1007 bool reg_changed, maybe_support_aspm;
1008 u32 tmp = 0;
1009 u8 reg0 = 0, reg1 = 0;
1010
1011 maybe_support_aspm = false;
1012 reg_changed = false;
1013 rtsx_read_config_byte(chip, LCTLR, ®0);
1014 if (chip->aspm_level[0] != reg0) {
1015 reg_changed = true;
1016 chip->aspm_level[0] = reg0;
1017 }
1018 if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
1019 rtsx_read_cfg_dw(chip, 1, 0xC0, &tmp);
1020 reg1 = (u8)tmp;
1021 if (chip->aspm_level[1] != reg1) {
1022 reg_changed = true;
1023 chip->aspm_level[1] = reg1;
1024 }
1025
1026 if ((reg0 & 0x03) && (reg1 & 0x03))
1027 maybe_support_aspm = true;
1028
1029 } else {
1030 if (reg0 & 0x03)
1031 maybe_support_aspm = true;
1032 }
1033
1034 if (reg_changed) {
1035 if (maybe_support_aspm)
1036 chip->aspm_l0s_l1_en = 0x03;
1037
1038 dev_dbg(rtsx_dev(chip), "aspm_level[0] = 0x%02x, aspm_level[1] = 0x%02x\n",
1039 chip->aspm_level[0], chip->aspm_level[1]);
1040
1041 if (chip->aspm_l0s_l1_en) {
1042 chip->aspm_enabled = 1;
1043 } else {
1044 chip->aspm_enabled = 0;
1045 chip->sdio_aspm = 0;
1046 }
1047 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF,
1048 0x30 | chip->aspm_level[0] |
1049 (chip->aspm_level[1] << 2));
1050 }
1051 }
1052
rtsx_manage_ocp(struct rtsx_chip * chip)1053 static void rtsx_manage_ocp(struct rtsx_chip *chip)
1054 {
1055 #ifdef SUPPORT_OCP
1056 if (!chip->ocp_int)
1057 return;
1058
1059 rtsx_read_register(chip, OCPSTAT, &chip->ocp_stat);
1060
1061 if (chip->card_exist & SD_CARD)
1062 sd_power_off_card3v3(chip);
1063 else if (chip->card_exist & MS_CARD)
1064 ms_power_off_card3v3(chip);
1065 else if (chip->card_exist & XD_CARD)
1066 xd_power_off_card3v3(chip);
1067
1068 chip->ocp_int = 0;
1069 #endif
1070 }
1071
rtsx_manage_sd_lock(struct rtsx_chip * chip)1072 static void rtsx_manage_sd_lock(struct rtsx_chip *chip)
1073 {
1074 #ifdef SUPPORT_SD_LOCK
1075 struct sd_info *sd_card = &chip->sd_card;
1076 u8 val;
1077
1078 if (!sd_card->sd_erase_status)
1079 return;
1080
1081 if (chip->card_exist & SD_CARD) {
1082 rtsx_read_register(chip, 0xFD30, &val);
1083 if (val & 0x02) {
1084 sd_card->sd_erase_status = SD_NOT_ERASE;
1085 sd_card->sd_lock_notify = 1;
1086 chip->need_reinit |= SD_CARD;
1087 }
1088 } else {
1089 sd_card->sd_erase_status = SD_NOT_ERASE;
1090 }
1091 #endif
1092 }
1093
rtsx_is_ss_allowed(struct rtsx_chip * chip)1094 static bool rtsx_is_ss_allowed(struct rtsx_chip *chip)
1095 {
1096 u32 val;
1097
1098 if (!chip->ss_en || CHECK_PID(chip, 0x5288))
1099 return false;
1100
1101 if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
1102 rtsx_read_cfg_dw(chip, 1, 0x04, &val);
1103 if (val & 0x07)
1104 return false;
1105 }
1106
1107 return true;
1108 }
1109
rtsx_manage_ss(struct rtsx_chip * chip)1110 static void rtsx_manage_ss(struct rtsx_chip *chip)
1111 {
1112 if (!rtsx_is_ss_allowed(chip) || chip->sd_io)
1113 return;
1114
1115 if (rtsx_get_stat(chip) != RTSX_STAT_IDLE) {
1116 chip->ss_counter = 0;
1117 return;
1118 }
1119
1120 if (chip->ss_counter < (chip->ss_idle_period / POLLING_INTERVAL))
1121 chip->ss_counter++;
1122 else
1123 rtsx_exclusive_enter_ss(chip);
1124 }
1125
rtsx_manage_aspm(struct rtsx_chip * chip)1126 static void rtsx_manage_aspm(struct rtsx_chip *chip)
1127 {
1128 u8 data;
1129
1130 if (!CHECK_PID(chip, 0x5208))
1131 return;
1132
1133 rtsx_monitor_aspm_config(chip);
1134
1135 #ifdef SUPPORT_SDIO_ASPM
1136 if (!CHK_SDIO_EXIST(chip) || CHK_SDIO_IGNORED(chip) ||
1137 !chip->aspm_l0s_l1_en || !chip->dynamic_aspm)
1138 return;
1139
1140 if (chip->sd_io) {
1141 dynamic_configure_sdio_aspm(chip);
1142 return;
1143 }
1144
1145 if (chip->sdio_aspm)
1146 return;
1147
1148 dev_dbg(rtsx_dev(chip), "SDIO enter ASPM!\n");
1149 data = 0x30 | (chip->aspm_level[1] << 2);
1150 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFC, data);
1151 chip->sdio_aspm = 1;
1152 #endif
1153 }
1154
rtsx_manage_idle(struct rtsx_chip * chip)1155 static void rtsx_manage_idle(struct rtsx_chip *chip)
1156 {
1157 if (chip->idle_counter < IDLE_MAX_COUNT) {
1158 chip->idle_counter++;
1159 return;
1160 }
1161
1162 if (rtsx_get_stat(chip) == RTSX_STAT_IDLE)
1163 return;
1164
1165 dev_dbg(rtsx_dev(chip), "Idle state!\n");
1166 rtsx_set_stat(chip, RTSX_STAT_IDLE);
1167
1168 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1169 chip->led_toggle_counter = 0;
1170 #endif
1171 rtsx_force_power_on(chip, SSC_PDCTL);
1172
1173 turn_off_led(chip, LED_GPIO);
1174
1175 if (chip->auto_power_down && !chip->card_ready && !chip->sd_io)
1176 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
1177 }
1178
rtsx_manage_2lun_mode(struct rtsx_chip * chip)1179 static void rtsx_manage_2lun_mode(struct rtsx_chip *chip)
1180 {
1181 #ifdef SUPPORT_OCP
1182 u8 sd_oc, ms_oc;
1183
1184 sd_oc = chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER);
1185 ms_oc = chip->ocp_stat & (MS_OC_NOW | MS_OC_EVER);
1186
1187 if (sd_oc || ms_oc)
1188 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
1189 chip->ocp_stat);
1190
1191 if (sd_oc && (chip->card_exist & SD_CARD)) {
1192 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
1193 card_power_off(chip, SD_CARD);
1194 chip->card_fail |= SD_CARD;
1195 }
1196
1197 if (ms_oc && (chip->card_exist & MS_CARD)) {
1198 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0);
1199 card_power_off(chip, MS_CARD);
1200 chip->card_fail |= MS_CARD;
1201 }
1202 #endif
1203 }
1204
rtsx_manage_1lun_mode(struct rtsx_chip * chip)1205 static void rtsx_manage_1lun_mode(struct rtsx_chip *chip)
1206 {
1207 #ifdef SUPPORT_OCP
1208 if (!(chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)))
1209 return;
1210
1211 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
1212 chip->ocp_stat);
1213
1214 if (chip->card_exist & SD_CARD) {
1215 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
1216 chip->card_fail |= SD_CARD;
1217 } else if (chip->card_exist & MS_CARD) {
1218 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0);
1219 chip->card_fail |= MS_CARD;
1220 } else if (chip->card_exist & XD_CARD) {
1221 rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0);
1222 chip->card_fail |= XD_CARD;
1223 }
1224 card_power_off(chip, SD_CARD);
1225 #endif
1226 }
1227
rtsx_delink_stage1(struct rtsx_chip * chip,int enter_L1,int stage3_cnt)1228 static void rtsx_delink_stage1(struct rtsx_chip *chip, int enter_L1,
1229 int stage3_cnt)
1230 {
1231 u8 val;
1232
1233 rtsx_set_stat(chip, RTSX_STAT_DELINK);
1234
1235 if (chip->asic_code && CHECK_PID(chip, 0x5208))
1236 rtsx_set_phy_reg_bit(chip, 0x1C, 2);
1237
1238 if (chip->card_exist)
1239 dev_dbg(rtsx_dev(chip), "False card inserted, do force delink\n");
1240 else
1241 dev_dbg(rtsx_dev(chip), "No card inserted, do delink\n");
1242
1243 if (enter_L1)
1244 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 1);
1245
1246 if (chip->card_exist)
1247 val = 0x02;
1248 else
1249 val = 0x0A;
1250
1251 rtsx_write_register(chip, CHANGE_LINK_STATE, val, val);
1252
1253 if (enter_L1)
1254 rtsx_enter_L1(chip);
1255
1256 if (chip->card_exist)
1257 chip->auto_delink_cnt = stage3_cnt + 1;
1258 }
1259
rtsx_delink_stage(struct rtsx_chip * chip)1260 static void rtsx_delink_stage(struct rtsx_chip *chip)
1261 {
1262 int delink_stage1_cnt, delink_stage2_cnt, delink_stage3_cnt;
1263 int enter_L1;
1264
1265 if (!chip->auto_delink_en || !chip->auto_delink_allowed ||
1266 chip->card_ready || chip->card_ejected || chip->sd_io) {
1267 chip->auto_delink_cnt = 0;
1268 return;
1269 }
1270
1271 enter_L1 = chip->auto_delink_in_L1 &&
1272 (chip->aspm_l0s_l1_en || chip->ss_en);
1273
1274 delink_stage1_cnt = chip->delink_stage1_step;
1275 delink_stage2_cnt = delink_stage1_cnt + chip->delink_stage2_step;
1276 delink_stage3_cnt = delink_stage2_cnt + chip->delink_stage3_step;
1277
1278 if (chip->auto_delink_cnt > delink_stage3_cnt)
1279 return;
1280
1281 if (chip->auto_delink_cnt == delink_stage1_cnt)
1282 rtsx_delink_stage1(chip, enter_L1, delink_stage3_cnt);
1283
1284 if (chip->auto_delink_cnt == delink_stage2_cnt) {
1285 dev_dbg(rtsx_dev(chip), "Try to do force delink\n");
1286
1287 if (enter_L1)
1288 rtsx_exit_L1(chip);
1289
1290 if (chip->asic_code && CHECK_PID(chip, 0x5208))
1291 rtsx_set_phy_reg_bit(chip, 0x1C, 2);
1292
1293 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x0A);
1294 }
1295
1296 chip->auto_delink_cnt++;
1297 }
1298
rtsx_polling_func(struct rtsx_chip * chip)1299 void rtsx_polling_func(struct rtsx_chip *chip)
1300 {
1301 if (rtsx_chk_stat(chip, RTSX_STAT_SUSPEND))
1302 return;
1303
1304 if (rtsx_chk_stat(chip, RTSX_STAT_DELINK))
1305 goto delink_stage;
1306
1307 if (chip->polling_config) {
1308 u8 val;
1309
1310 rtsx_read_config_byte(chip, 0, &val);
1311 }
1312
1313 if (rtsx_chk_stat(chip, RTSX_STAT_SS))
1314 return;
1315
1316 rtsx_manage_ocp(chip);
1317
1318 rtsx_manage_sd_lock(chip);
1319
1320 rtsx_init_cards(chip);
1321
1322 rtsx_manage_ss(chip);
1323
1324 rtsx_manage_aspm(chip);
1325
1326 rtsx_manage_idle(chip);
1327
1328 switch (rtsx_get_stat(chip)) {
1329 case RTSX_STAT_RUN:
1330 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1331 rtsx_blink_led(chip);
1332 #endif
1333 do_remaining_work(chip);
1334 break;
1335
1336 case RTSX_STAT_IDLE:
1337 if (chip->sd_io && !chip->sd_int)
1338 try_to_switch_sdio_ctrl(chip);
1339
1340 rtsx_enable_aspm(chip);
1341 break;
1342
1343 default:
1344 break;
1345 }
1346
1347 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
1348 rtsx_manage_2lun_mode(chip);
1349 else
1350 rtsx_manage_1lun_mode(chip);
1351
1352 delink_stage:
1353 rtsx_delink_stage(chip);
1354 }
1355
1356 /**
1357 * rtsx_stop_cmd - stop command transfer and DMA transfer
1358 * @chip: Realtek's card reader chip
1359 * @card: flash card type
1360 *
1361 * Stop command transfer and DMA transfer.
1362 * This function is called in error handler.
1363 */
rtsx_stop_cmd(struct rtsx_chip * chip,int card)1364 void rtsx_stop_cmd(struct rtsx_chip *chip, int card)
1365 {
1366 int i;
1367
1368 for (i = 0; i <= 8; i++) {
1369 int addr = RTSX_HCBAR + i * 4;
1370 u32 reg;
1371
1372 reg = rtsx_readl(chip, addr);
1373 dev_dbg(rtsx_dev(chip), "BAR (0x%02x): 0x%08x\n", addr, reg);
1374 }
1375 rtsx_writel(chip, RTSX_HCBCTLR, STOP_CMD);
1376 rtsx_writel(chip, RTSX_HDBCTLR, STOP_DMA);
1377
1378 for (i = 0; i < 16; i++) {
1379 u16 addr = 0xFE20 + (u16)i;
1380 u8 val;
1381
1382 rtsx_read_register(chip, addr, &val);
1383 dev_dbg(rtsx_dev(chip), "0x%04X: 0x%02x\n", addr, val);
1384 }
1385
1386 rtsx_write_register(chip, DMACTL, 0x80, 0x80);
1387 rtsx_write_register(chip, RBCTL, 0x80, 0x80);
1388 }
1389
1390 #define MAX_RW_REG_CNT 1024
1391
rtsx_write_register(struct rtsx_chip * chip,u16 addr,u8 mask,u8 data)1392 int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data)
1393 {
1394 int i;
1395 u32 val = 3 << 30;
1396
1397 val |= (u32)(addr & 0x3FFF) << 16;
1398 val |= (u32)mask << 8;
1399 val |= (u32)data;
1400
1401 rtsx_writel(chip, RTSX_HAIMR, val);
1402
1403 for (i = 0; i < MAX_RW_REG_CNT; i++) {
1404 val = rtsx_readl(chip, RTSX_HAIMR);
1405 if ((val & BIT(31)) == 0) {
1406 if (data != (u8)val) {
1407 return STATUS_FAIL;
1408 }
1409
1410 return STATUS_SUCCESS;
1411 }
1412 }
1413
1414 return STATUS_TIMEDOUT;
1415 }
1416
rtsx_read_register(struct rtsx_chip * chip,u16 addr,u8 * data)1417 int rtsx_read_register(struct rtsx_chip *chip, u16 addr, u8 *data)
1418 {
1419 u32 val = 2 << 30;
1420 int i;
1421
1422 if (data)
1423 *data = 0;
1424
1425 val |= (u32)(addr & 0x3FFF) << 16;
1426
1427 rtsx_writel(chip, RTSX_HAIMR, val);
1428
1429 for (i = 0; i < MAX_RW_REG_CNT; i++) {
1430 val = rtsx_readl(chip, RTSX_HAIMR);
1431 if ((val & BIT(31)) == 0)
1432 break;
1433 }
1434
1435 if (i >= MAX_RW_REG_CNT) {
1436 return STATUS_TIMEDOUT;
1437 }
1438
1439 if (data)
1440 *data = (u8)(val & 0xFF);
1441
1442 return STATUS_SUCCESS;
1443 }
1444
rtsx_write_cfg_dw(struct rtsx_chip * chip,u8 func_no,u16 addr,u32 mask,u32 val)1445 int rtsx_write_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 mask,
1446 u32 val)
1447 {
1448 int retval;
1449 u8 mode = 0, tmp;
1450 int i;
1451
1452 for (i = 0; i < 4; i++) {
1453 if (mask & 0xFF) {
1454 retval = rtsx_write_register(chip, CFGDATA0 + i,
1455 0xFF,
1456 (u8)(val & mask & 0xFF));
1457 if (retval) {
1458 return retval;
1459 }
1460 mode |= (1 << i);
1461 }
1462 mask >>= 8;
1463 val >>= 8;
1464 }
1465
1466 if (mode) {
1467 retval = rtsx_write_register(chip, CFGADDR0, 0xFF, (u8)addr);
1468 if (retval) {
1469 return retval;
1470 }
1471 retval = rtsx_write_register(chip, CFGADDR1, 0xFF,
1472 (u8)(addr >> 8));
1473 if (retval) {
1474 return retval;
1475 }
1476
1477 retval = rtsx_write_register(chip, CFGRWCTL, 0xFF,
1478 0x80 | mode |
1479 ((func_no & 0x03) << 4));
1480 if (retval) {
1481 return retval;
1482 }
1483
1484 for (i = 0; i < MAX_RW_REG_CNT; i++) {
1485 retval = rtsx_read_register(chip, CFGRWCTL, &tmp);
1486 if (retval) {
1487 return retval;
1488 }
1489 if ((tmp & 0x80) == 0)
1490 break;
1491 }
1492 }
1493
1494 return STATUS_SUCCESS;
1495 }
1496
rtsx_read_cfg_dw(struct rtsx_chip * chip,u8 func_no,u16 addr,u32 * val)1497 int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val)
1498 {
1499 int retval;
1500 int i;
1501 u8 tmp;
1502 u32 data = 0;
1503
1504 retval = rtsx_write_register(chip, CFGADDR0, 0xFF, (u8)addr);
1505 if (retval) {
1506 return retval;
1507 }
1508 retval = rtsx_write_register(chip, CFGADDR1, 0xFF, (u8)(addr >> 8));
1509 if (retval) {
1510 return retval;
1511 }
1512 retval = rtsx_write_register(chip, CFGRWCTL, 0xFF,
1513 0x80 | ((func_no & 0x03) << 4));
1514 if (retval) {
1515 return retval;
1516 }
1517
1518 for (i = 0; i < MAX_RW_REG_CNT; i++) {
1519 retval = rtsx_read_register(chip, CFGRWCTL, &tmp);
1520 if (retval) {
1521 return retval;
1522 }
1523 if ((tmp & 0x80) == 0)
1524 break;
1525 }
1526
1527 for (i = 0; i < 4; i++) {
1528 retval = rtsx_read_register(chip, CFGDATA0 + i, &tmp);
1529 if (retval) {
1530 return retval;
1531 }
1532 data |= (u32)tmp << (i * 8);
1533 }
1534
1535 if (val)
1536 *val = data;
1537
1538 return STATUS_SUCCESS;
1539 }
1540
rtsx_write_cfg_seq(struct rtsx_chip * chip,u8 func,u16 addr,u8 * buf,int len)1541 int rtsx_write_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf,
1542 int len)
1543 {
1544 u32 *data, *mask;
1545 u16 offset = addr % 4;
1546 u16 aligned_addr = addr - offset;
1547 int dw_len, i, j;
1548 int retval;
1549
1550 if (!buf) {
1551 return STATUS_NOMEM;
1552 }
1553
1554 if ((len + offset) % 4)
1555 dw_len = (len + offset) / 4 + 1;
1556 else
1557 dw_len = (len + offset) / 4;
1558
1559 dev_dbg(rtsx_dev(chip), "dw_len = %d\n", dw_len);
1560
1561 data = vzalloc(array_size(dw_len, 4));
1562 if (!data) {
1563 return STATUS_NOMEM;
1564 }
1565
1566 mask = vzalloc(array_size(dw_len, 4));
1567 if (!mask) {
1568 vfree(data);
1569 return STATUS_NOMEM;
1570 }
1571
1572 j = 0;
1573 for (i = 0; i < len; i++) {
1574 mask[j] |= 0xFF << (offset * 8);
1575 data[j] |= buf[i] << (offset * 8);
1576 if (++offset == 4) {
1577 j++;
1578 offset = 0;
1579 }
1580 }
1581
1582 print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, mask,
1583 dw_len * 4);
1584 print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, data,
1585 dw_len * 4);
1586
1587 for (i = 0; i < dw_len; i++) {
1588 retval = rtsx_write_cfg_dw(chip, func, aligned_addr + i * 4,
1589 mask[i], data[i]);
1590 if (retval != STATUS_SUCCESS) {
1591 vfree(data);
1592 vfree(mask);
1593 return STATUS_FAIL;
1594 }
1595 }
1596
1597 vfree(data);
1598 vfree(mask);
1599
1600 return STATUS_SUCCESS;
1601 }
1602
rtsx_read_cfg_seq(struct rtsx_chip * chip,u8 func,u16 addr,u8 * buf,int len)1603 int rtsx_read_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf,
1604 int len)
1605 {
1606 u32 *data;
1607 u16 offset = addr % 4;
1608 u16 aligned_addr = addr - offset;
1609 int dw_len, i, j;
1610 int retval;
1611
1612 if ((len + offset) % 4)
1613 dw_len = (len + offset) / 4 + 1;
1614 else
1615 dw_len = (len + offset) / 4;
1616
1617 dev_dbg(rtsx_dev(chip), "dw_len = %d\n", dw_len);
1618
1619 data = vmalloc(array_size(dw_len, 4));
1620 if (!data) {
1621 return STATUS_NOMEM;
1622 }
1623
1624 for (i = 0; i < dw_len; i++) {
1625 retval = rtsx_read_cfg_dw(chip, func, aligned_addr + i * 4,
1626 data + i);
1627 if (retval != STATUS_SUCCESS) {
1628 vfree(data);
1629 return STATUS_FAIL;
1630 }
1631 }
1632
1633 if (buf) {
1634 j = 0;
1635
1636 for (i = 0; i < len; i++) {
1637 buf[i] = (u8)(data[j] >> (offset * 8));
1638 if (++offset == 4) {
1639 j++;
1640 offset = 0;
1641 }
1642 }
1643 }
1644
1645 vfree(data);
1646
1647 return STATUS_SUCCESS;
1648 }
1649
rtsx_write_phy_register(struct rtsx_chip * chip,u8 addr,u16 val)1650 int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val)
1651 {
1652 int retval;
1653 bool finished = false;
1654 int i;
1655 u8 tmp;
1656
1657 retval = rtsx_write_register(chip, PHYDATA0, 0xFF, (u8)val);
1658 if (retval) {
1659 return retval;
1660 }
1661 retval = rtsx_write_register(chip, PHYDATA1, 0xFF, (u8)(val >> 8));
1662 if (retval) {
1663 return retval;
1664 }
1665 retval = rtsx_write_register(chip, PHYADDR, 0xFF, addr);
1666 if (retval) {
1667 return retval;
1668 }
1669 retval = rtsx_write_register(chip, PHYRWCTL, 0xFF, 0x81);
1670 if (retval) {
1671 return retval;
1672 }
1673
1674 for (i = 0; i < 100000; i++) {
1675 retval = rtsx_read_register(chip, PHYRWCTL, &tmp);
1676 if (retval) {
1677 return retval;
1678 }
1679 if (!(tmp & 0x80)) {
1680 finished = true;
1681 break;
1682 }
1683 }
1684
1685 if (!finished) {
1686 return STATUS_FAIL;
1687 }
1688
1689 return STATUS_SUCCESS;
1690 }
1691
rtsx_read_phy_register(struct rtsx_chip * chip,u8 addr,u16 * val)1692 int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val)
1693 {
1694 int retval;
1695 bool finished = false;
1696 int i;
1697 u16 data = 0;
1698 u8 tmp;
1699
1700 retval = rtsx_write_register(chip, PHYADDR, 0xFF, addr);
1701 if (retval) {
1702 return retval;
1703 }
1704 retval = rtsx_write_register(chip, PHYRWCTL, 0xFF, 0x80);
1705 if (retval) {
1706 return retval;
1707 }
1708
1709 for (i = 0; i < 100000; i++) {
1710 retval = rtsx_read_register(chip, PHYRWCTL, &tmp);
1711 if (retval) {
1712 return retval;
1713 }
1714 if (!(tmp & 0x80)) {
1715 finished = true;
1716 break;
1717 }
1718 }
1719
1720 if (!finished) {
1721 return STATUS_FAIL;
1722 }
1723
1724 retval = rtsx_read_register(chip, PHYDATA0, &tmp);
1725 if (retval) {
1726 return retval;
1727 }
1728 data = tmp;
1729 retval = rtsx_read_register(chip, PHYDATA1, &tmp);
1730 if (retval) {
1731 return retval;
1732 }
1733 data |= (u16)tmp << 8;
1734
1735 if (val)
1736 *val = data;
1737
1738 return STATUS_SUCCESS;
1739 }
1740
rtsx_read_efuse(struct rtsx_chip * chip,u8 addr,u8 * val)1741 int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val)
1742 {
1743 int retval;
1744 int i;
1745 u8 data = 0;
1746
1747 retval = rtsx_write_register(chip, EFUSE_CTRL, 0xFF, 0x80 | addr);
1748 if (retval) {
1749 return retval;
1750 }
1751
1752 for (i = 0; i < 100; i++) {
1753 retval = rtsx_read_register(chip, EFUSE_CTRL, &data);
1754 if (retval) {
1755 return retval;
1756 }
1757 if (!(data & 0x80))
1758 break;
1759 udelay(1);
1760 }
1761
1762 if (data & 0x80) {
1763 return STATUS_TIMEDOUT;
1764 }
1765
1766 retval = rtsx_read_register(chip, EFUSE_DATA, &data);
1767 if (retval) {
1768 return retval;
1769 }
1770 if (val)
1771 *val = data;
1772
1773 return STATUS_SUCCESS;
1774 }
1775
rtsx_write_efuse(struct rtsx_chip * chip,u8 addr,u8 val)1776 int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val)
1777 {
1778 int retval;
1779 int i, j;
1780 u8 data = 0, tmp = 0xFF;
1781
1782 for (i = 0; i < 8; i++) {
1783 if (val & (u8)(1 << i))
1784 continue;
1785
1786 tmp &= (~(u8)(1 << i));
1787 dev_dbg(rtsx_dev(chip), "Write 0x%x to 0x%x\n", tmp, addr);
1788
1789 retval = rtsx_write_register(chip, EFUSE_DATA, 0xFF, tmp);
1790 if (retval) {
1791 return retval;
1792 }
1793 retval = rtsx_write_register(chip, EFUSE_CTRL, 0xFF,
1794 0xA0 | addr);
1795 if (retval) {
1796 return retval;
1797 }
1798
1799 for (j = 0; j < 100; j++) {
1800 retval = rtsx_read_register(chip, EFUSE_CTRL, &data);
1801 if (retval) {
1802 return retval;
1803 }
1804 if (!(data & 0x80))
1805 break;
1806 wait_timeout(3);
1807 }
1808
1809 if (data & 0x80) {
1810 return STATUS_TIMEDOUT;
1811 }
1812
1813 wait_timeout(5);
1814 }
1815
1816 return STATUS_SUCCESS;
1817 }
1818
rtsx_clr_phy_reg_bit(struct rtsx_chip * chip,u8 reg,u8 bit)1819 int rtsx_clr_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit)
1820 {
1821 int retval;
1822 u16 value;
1823
1824 retval = rtsx_read_phy_register(chip, reg, &value);
1825 if (retval != STATUS_SUCCESS) {
1826 return STATUS_FAIL;
1827 }
1828
1829 if (value & (1 << bit)) {
1830 value &= ~(1 << bit);
1831 retval = rtsx_write_phy_register(chip, reg, value);
1832 if (retval != STATUS_SUCCESS) {
1833 return STATUS_FAIL;
1834 }
1835 }
1836
1837 return STATUS_SUCCESS;
1838 }
1839
rtsx_set_phy_reg_bit(struct rtsx_chip * chip,u8 reg,u8 bit)1840 int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit)
1841 {
1842 int retval;
1843 u16 value;
1844
1845 retval = rtsx_read_phy_register(chip, reg, &value);
1846 if (retval != STATUS_SUCCESS) {
1847 return STATUS_FAIL;
1848 }
1849
1850 if ((value & (1 << bit)) == 0) {
1851 value |= (1 << bit);
1852 retval = rtsx_write_phy_register(chip, reg, value);
1853 if (retval != STATUS_SUCCESS) {
1854 return STATUS_FAIL;
1855 }
1856 }
1857
1858 return STATUS_SUCCESS;
1859 }
1860
rtsx_handle_pm_dstate(struct rtsx_chip * chip,u8 dstate)1861 static void rtsx_handle_pm_dstate(struct rtsx_chip *chip, u8 dstate)
1862 {
1863 u32 ultmp;
1864
1865 dev_dbg(rtsx_dev(chip), "%04x set pm_dstate to %d\n",
1866 chip->product_id, dstate);
1867
1868 if (CHK_SDIO_EXIST(chip)) {
1869 u8 func_no;
1870
1871 if (CHECK_PID(chip, 0x5288))
1872 func_no = 2;
1873 else
1874 func_no = 1;
1875
1876 rtsx_read_cfg_dw(chip, func_no, 0x84, &ultmp);
1877 dev_dbg(rtsx_dev(chip), "pm_dstate of function %d: 0x%x\n",
1878 (int)func_no, ultmp);
1879 rtsx_write_cfg_dw(chip, func_no, 0x84, 0xFF, dstate);
1880 }
1881
1882 rtsx_write_config_byte(chip, 0x44, dstate);
1883 rtsx_write_config_byte(chip, 0x45, 0);
1884 }
1885
rtsx_enter_L1(struct rtsx_chip * chip)1886 void rtsx_enter_L1(struct rtsx_chip *chip)
1887 {
1888 rtsx_handle_pm_dstate(chip, 2);
1889 }
1890
rtsx_exit_L1(struct rtsx_chip * chip)1891 void rtsx_exit_L1(struct rtsx_chip *chip)
1892 {
1893 rtsx_write_config_byte(chip, 0x44, 0);
1894 rtsx_write_config_byte(chip, 0x45, 0);
1895 }
1896
rtsx_enter_ss(struct rtsx_chip * chip)1897 void rtsx_enter_ss(struct rtsx_chip *chip)
1898 {
1899 dev_dbg(rtsx_dev(chip), "Enter Selective Suspend State!\n");
1900
1901 rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT);
1902
1903 if (chip->power_down_in_ss) {
1904 rtsx_power_off_card(chip);
1905 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
1906 }
1907
1908 if (CHK_SDIO_EXIST(chip))
1909 rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1,
1910 0xC0, 0xFF00, 0x0100);
1911
1912 if (chip->auto_delink_en) {
1913 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x01, 0x01);
1914 } else {
1915 if (!chip->phy_debug_mode) {
1916 u32 tmp;
1917
1918 tmp = rtsx_readl(chip, RTSX_BIER);
1919 tmp |= CARD_INT;
1920 rtsx_writel(chip, RTSX_BIER, tmp);
1921 }
1922
1923 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 0);
1924 }
1925
1926 rtsx_enter_L1(chip);
1927
1928 RTSX_CLR_DELINK(chip);
1929 rtsx_set_stat(chip, RTSX_STAT_SS);
1930 }
1931
rtsx_exit_ss(struct rtsx_chip * chip)1932 void rtsx_exit_ss(struct rtsx_chip *chip)
1933 {
1934 dev_dbg(rtsx_dev(chip), "Exit Selective Suspend State!\n");
1935
1936 rtsx_exit_L1(chip);
1937
1938 if (chip->power_down_in_ss) {
1939 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL);
1940 udelay(1000);
1941 }
1942
1943 if (RTSX_TST_DELINK(chip)) {
1944 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
1945 rtsx_reinit_cards(chip, 1);
1946 RTSX_CLR_DELINK(chip);
1947 } else if (chip->power_down_in_ss) {
1948 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
1949 rtsx_reinit_cards(chip, 0);
1950 }
1951 }
1952
rtsx_pre_handle_interrupt(struct rtsx_chip * chip)1953 int rtsx_pre_handle_interrupt(struct rtsx_chip *chip)
1954 {
1955 u32 status, int_enable;
1956 bool exit_ss = false;
1957 #ifdef SUPPORT_OCP
1958 u32 ocp_int = 0;
1959
1960 ocp_int = OC_INT;
1961 #endif
1962
1963 if (chip->ss_en) {
1964 chip->ss_counter = 0;
1965 if (rtsx_get_stat(chip) == RTSX_STAT_SS) {
1966 exit_ss = true;
1967 rtsx_exit_L1(chip);
1968 rtsx_set_stat(chip, RTSX_STAT_RUN);
1969 }
1970 }
1971
1972 int_enable = rtsx_readl(chip, RTSX_BIER);
1973 chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
1974
1975 if (((chip->int_reg & int_enable) == 0) ||
1976 (chip->int_reg == 0xFFFFFFFF))
1977 return STATUS_FAIL;
1978
1979 status = chip->int_reg &= (int_enable | 0x7FFFFF);
1980
1981 if (status & CARD_INT) {
1982 chip->auto_delink_cnt = 0;
1983
1984 if (status & SD_INT) {
1985 if (status & SD_EXIST) {
1986 set_bit(SD_NR, &chip->need_reset);
1987 } else {
1988 set_bit(SD_NR, &chip->need_release);
1989 chip->sd_reset_counter = 0;
1990 chip->sd_show_cnt = 0;
1991 clear_bit(SD_NR, &chip->need_reset);
1992 }
1993 } else {
1994 /*
1995 * If multi-luns, it's possible that
1996 * when plugging/unplugging one card
1997 * there is another card which still
1998 * exists in the slot. In this case,
1999 * all existed cards should be reset.
2000 */
2001 if (exit_ss && (status & SD_EXIST))
2002 set_bit(SD_NR, &chip->need_reinit);
2003 }
2004 if (!CHECK_PID(chip, 0x5288) || CHECK_BARO_PKG(chip, QFN)) {
2005 if (status & XD_INT) {
2006 if (status & XD_EXIST) {
2007 set_bit(XD_NR, &chip->need_reset);
2008 } else {
2009 set_bit(XD_NR, &chip->need_release);
2010 chip->xd_reset_counter = 0;
2011 chip->xd_show_cnt = 0;
2012 clear_bit(XD_NR, &chip->need_reset);
2013 }
2014 } else {
2015 if (exit_ss && (status & XD_EXIST))
2016 set_bit(XD_NR, &chip->need_reinit);
2017 }
2018 }
2019 if (status & MS_INT) {
2020 if (status & MS_EXIST) {
2021 set_bit(MS_NR, &chip->need_reset);
2022 } else {
2023 set_bit(MS_NR, &chip->need_release);
2024 chip->ms_reset_counter = 0;
2025 chip->ms_show_cnt = 0;
2026 clear_bit(MS_NR, &chip->need_reset);
2027 }
2028 } else {
2029 if (exit_ss && (status & MS_EXIST))
2030 set_bit(MS_NR, &chip->need_reinit);
2031 }
2032 }
2033
2034 #ifdef SUPPORT_OCP
2035 chip->ocp_int = ocp_int & status;
2036 #endif
2037
2038 if (chip->sd_io && (chip->int_reg & DATA_DONE_INT))
2039 chip->int_reg &= ~(u32)DATA_DONE_INT;
2040
2041 return STATUS_SUCCESS;
2042 }
2043
rtsx_do_before_power_down(struct rtsx_chip * chip,int pm_stat)2044 void rtsx_do_before_power_down(struct rtsx_chip *chip, int pm_stat)
2045 {
2046 int retval;
2047
2048 dev_dbg(rtsx_dev(chip), "%s, pm_stat = %d\n", __func__, pm_stat);
2049
2050 rtsx_set_stat(chip, RTSX_STAT_SUSPEND);
2051
2052 retval = rtsx_force_power_on(chip, SSC_PDCTL);
2053 if (retval != STATUS_SUCCESS)
2054 return;
2055
2056 rtsx_release_cards(chip);
2057 rtsx_disable_bus_int(chip);
2058 turn_off_led(chip, LED_GPIO);
2059
2060 #ifdef HW_AUTO_SWITCH_SD_BUS
2061 if (chip->sd_io) {
2062 chip->sdio_in_charge = 1;
2063 if (CHECK_PID(chip, 0x5208)) {
2064 rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
2065 /* Enable sdio_bus_auto_switch */
2066 rtsx_write_register(chip, 0xFE70, 0x80, 0x80);
2067 } else if (CHECK_PID(chip, 0x5288)) {
2068 rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
2069 /* Enable sdio_bus_auto_switch */
2070 rtsx_write_register(chip, 0xFE5A, 0x08, 0x08);
2071 }
2072 }
2073 #endif
2074
2075 if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) {
2076 /* u_force_clkreq_0 */
2077 rtsx_write_register(chip, PETXCFG, 0x08, 0x08);
2078 }
2079
2080 if (pm_stat == PM_S1) {
2081 dev_dbg(rtsx_dev(chip), "Host enter S1\n");
2082 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03,
2083 HOST_ENTER_S1);
2084 } else if (pm_stat == PM_S3) {
2085 if (chip->s3_pwr_off_delay > 0)
2086 wait_timeout(chip->s3_pwr_off_delay);
2087
2088 dev_dbg(rtsx_dev(chip), "Host enter S3\n");
2089 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03,
2090 HOST_ENTER_S3);
2091 }
2092
2093 if (chip->do_delink_before_power_down && chip->auto_delink_en)
2094 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 2);
2095
2096 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
2097
2098 chip->cur_clk = 0;
2099 chip->cur_card = 0;
2100 chip->card_exist = 0;
2101 }
2102
rtsx_enable_aspm(struct rtsx_chip * chip)2103 void rtsx_enable_aspm(struct rtsx_chip *chip)
2104 {
2105 if (chip->aspm_l0s_l1_en && chip->dynamic_aspm && !chip->aspm_enabled) {
2106 dev_dbg(rtsx_dev(chip), "Try to enable ASPM\n");
2107 chip->aspm_enabled = 1;
2108
2109 if (chip->asic_code && CHECK_PID(chip, 0x5208))
2110 rtsx_write_phy_register(chip, 0x07, 0);
2111 if (CHECK_PID(chip, 0x5208)) {
2112 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xF3,
2113 0x30 | chip->aspm_level[0]);
2114 } else {
2115 rtsx_write_config_byte(chip, LCTLR,
2116 chip->aspm_l0s_l1_en);
2117 }
2118
2119 if (CHK_SDIO_EXIST(chip)) {
2120 u16 val = chip->aspm_l0s_l1_en | 0x0100;
2121
2122 rtsx_write_cfg_dw(chip, CHECK_PID(chip, 0x5288) ? 2 : 1,
2123 0xC0, 0xFFF, val);
2124 }
2125 }
2126 }
2127
rtsx_disable_aspm(struct rtsx_chip * chip)2128 void rtsx_disable_aspm(struct rtsx_chip *chip)
2129 {
2130 if (CHECK_PID(chip, 0x5208))
2131 rtsx_monitor_aspm_config(chip);
2132
2133 if (chip->aspm_l0s_l1_en && chip->dynamic_aspm && chip->aspm_enabled) {
2134 dev_dbg(rtsx_dev(chip), "Try to disable ASPM\n");
2135 chip->aspm_enabled = 0;
2136
2137 if (chip->asic_code && CHECK_PID(chip, 0x5208))
2138 rtsx_write_phy_register(chip, 0x07, 0x0129);
2139 if (CHECK_PID(chip, 0x5208))
2140 rtsx_write_register(chip, ASPM_FORCE_CTL,
2141 0xF3, 0x30);
2142 else
2143 rtsx_write_config_byte(chip, LCTLR, 0x00);
2144
2145 wait_timeout(1);
2146 }
2147 }
2148
rtsx_read_ppbuf(struct rtsx_chip * chip,u8 * buf,int buf_len)2149 int rtsx_read_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len)
2150 {
2151 int retval;
2152 int i, j;
2153 u16 reg_addr;
2154 u8 *ptr;
2155
2156 if (!buf) {
2157 return STATUS_ERROR;
2158 }
2159
2160 ptr = buf;
2161 reg_addr = PPBUF_BASE2;
2162 for (i = 0; i < buf_len / 256; i++) {
2163 rtsx_init_cmd(chip);
2164
2165 for (j = 0; j < 256; j++)
2166 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0);
2167
2168 retval = rtsx_send_cmd(chip, 0, 250);
2169 if (retval < 0) {
2170 return STATUS_FAIL;
2171 }
2172
2173 memcpy(ptr, rtsx_get_cmd_data(chip), 256);
2174 ptr += 256;
2175 }
2176
2177 if (buf_len % 256) {
2178 rtsx_init_cmd(chip);
2179
2180 for (j = 0; j < buf_len % 256; j++)
2181 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0);
2182
2183 retval = rtsx_send_cmd(chip, 0, 250);
2184 if (retval < 0) {
2185 return STATUS_FAIL;
2186 }
2187 }
2188
2189 memcpy(ptr, rtsx_get_cmd_data(chip), buf_len % 256);
2190
2191 return STATUS_SUCCESS;
2192 }
2193
rtsx_write_ppbuf(struct rtsx_chip * chip,u8 * buf,int buf_len)2194 int rtsx_write_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len)
2195 {
2196 int retval;
2197 int i, j;
2198 u16 reg_addr;
2199 u8 *ptr;
2200
2201 if (!buf) {
2202 return STATUS_ERROR;
2203 }
2204
2205 ptr = buf;
2206 reg_addr = PPBUF_BASE2;
2207 for (i = 0; i < buf_len / 256; i++) {
2208 rtsx_init_cmd(chip);
2209
2210 for (j = 0; j < 256; j++) {
2211 rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF,
2212 *ptr);
2213 ptr++;
2214 }
2215
2216 retval = rtsx_send_cmd(chip, 0, 250);
2217 if (retval < 0) {
2218 return STATUS_FAIL;
2219 }
2220 }
2221
2222 if (buf_len % 256) {
2223 rtsx_init_cmd(chip);
2224
2225 for (j = 0; j < buf_len % 256; j++) {
2226 rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF,
2227 *ptr);
2228 ptr++;
2229 }
2230
2231 retval = rtsx_send_cmd(chip, 0, 250);
2232 if (retval < 0) {
2233 return STATUS_FAIL;
2234 }
2235 }
2236
2237 return STATUS_SUCCESS;
2238 }
2239
rtsx_check_chip_exist(struct rtsx_chip * chip)2240 int rtsx_check_chip_exist(struct rtsx_chip *chip)
2241 {
2242 if (rtsx_readl(chip, 0) == 0xFFFFFFFF) {
2243 return STATUS_FAIL;
2244 }
2245
2246 return STATUS_SUCCESS;
2247 }
2248
rtsx_force_power_on(struct rtsx_chip * chip,u8 ctl)2249 int rtsx_force_power_on(struct rtsx_chip *chip, u8 ctl)
2250 {
2251 int retval;
2252 u8 mask = 0;
2253
2254 if (ctl & SSC_PDCTL)
2255 mask |= SSC_POWER_DOWN;
2256
2257 #ifdef SUPPORT_OCP
2258 if (ctl & OC_PDCTL) {
2259 mask |= SD_OC_POWER_DOWN;
2260 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
2261 mask |= MS_OC_POWER_DOWN;
2262 }
2263 #endif
2264
2265 if (mask) {
2266 retval = rtsx_write_register(chip, FPDCTL, mask, 0);
2267 if (retval != STATUS_SUCCESS) {
2268 return STATUS_FAIL;
2269 }
2270
2271 if (CHECK_PID(chip, 0x5288))
2272 wait_timeout(200);
2273 }
2274
2275 return STATUS_SUCCESS;
2276 }
2277
rtsx_force_power_down(struct rtsx_chip * chip,u8 ctl)2278 int rtsx_force_power_down(struct rtsx_chip *chip, u8 ctl)
2279 {
2280 int retval;
2281 u8 mask = 0, val = 0;
2282
2283 if (ctl & SSC_PDCTL)
2284 mask |= SSC_POWER_DOWN;
2285
2286 #ifdef SUPPORT_OCP
2287 if (ctl & OC_PDCTL) {
2288 mask |= SD_OC_POWER_DOWN;
2289 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
2290 mask |= MS_OC_POWER_DOWN;
2291 }
2292 #endif
2293
2294 if (mask) {
2295 val = mask;
2296 retval = rtsx_write_register(chip, FPDCTL, mask, val);
2297 if (retval != STATUS_SUCCESS) {
2298 return STATUS_FAIL;
2299 }
2300 }
2301
2302 return STATUS_SUCCESS;
2303 }
2304
