1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
3
4 #include "wifi.h"
5 #include "core.h"
6 #include "pci.h"
7 #include "base.h"
8 #include "ps.h"
9 #include "efuse.h"
10 #include <linux/interrupt.h>
11 #include <linux/export.h>
12 #include <linux/module.h>
13
14 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
15 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
16 MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>");
17 MODULE_LICENSE("GPL");
18 MODULE_DESCRIPTION("PCI basic driver for rtlwifi");
19
20 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
21 INTEL_VENDOR_ID,
22 ATI_VENDOR_ID,
23 AMD_VENDOR_ID,
24 SIS_VENDOR_ID
25 };
26
27 static const u8 ac_to_hwq[] = {
28 VO_QUEUE,
29 VI_QUEUE,
30 BE_QUEUE,
31 BK_QUEUE
32 };
33
_rtl_mac_to_hwqueue(struct ieee80211_hw * hw,struct sk_buff * skb)34 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, struct sk_buff *skb)
35 {
36 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
37 __le16 fc = rtl_get_fc(skb);
38 u8 queue_index = skb_get_queue_mapping(skb);
39 struct ieee80211_hdr *hdr;
40
41 if (unlikely(ieee80211_is_beacon(fc)))
42 return BEACON_QUEUE;
43 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
44 return MGNT_QUEUE;
45 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
46 if (ieee80211_is_nullfunc(fc))
47 return HIGH_QUEUE;
48 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
49 hdr = rtl_get_hdr(skb);
50
51 if (is_multicast_ether_addr(hdr->addr1) ||
52 is_broadcast_ether_addr(hdr->addr1))
53 return HIGH_QUEUE;
54 }
55
56 return ac_to_hwq[queue_index];
57 }
58
59 /* Update PCI dependent default settings*/
_rtl_pci_update_default_setting(struct ieee80211_hw * hw)60 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
61 {
62 struct rtl_priv *rtlpriv = rtl_priv(hw);
63 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
64 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
65 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
66 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
67 u8 init_aspm;
68
69 ppsc->reg_rfps_level = 0;
70 ppsc->support_aspm = false;
71
72 /*Update PCI ASPM setting */
73 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
74 switch (rtlpci->const_pci_aspm) {
75 case 0:
76 /*No ASPM */
77 break;
78
79 case 1:
80 /*ASPM dynamically enabled/disable. */
81 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
82 break;
83
84 case 2:
85 /*ASPM with Clock Req dynamically enabled/disable. */
86 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
87 RT_RF_OFF_LEVL_CLK_REQ);
88 break;
89
90 case 3:
91 /* Always enable ASPM and Clock Req
92 * from initialization to halt.
93 */
94 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
95 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
96 RT_RF_OFF_LEVL_CLK_REQ);
97 break;
98
99 case 4:
100 /* Always enable ASPM without Clock Req
101 * from initialization to halt.
102 */
103 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
104 RT_RF_OFF_LEVL_CLK_REQ);
105 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
106 break;
107 }
108
109 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
110
111 /*Update Radio OFF setting */
112 switch (rtlpci->const_hwsw_rfoff_d3) {
113 case 1:
114 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
115 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
116 break;
117
118 case 2:
119 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
120 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
121 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
122 break;
123
124 case 3:
125 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
126 break;
127 }
128
129 /*Set HW definition to determine if it supports ASPM. */
130 switch (rtlpci->const_support_pciaspm) {
131 case 0:
132 /*Not support ASPM. */
133 ppsc->support_aspm = false;
134 break;
135 case 1:
136 /*Support ASPM. */
137 ppsc->support_aspm = true;
138 ppsc->support_backdoor = true;
139 break;
140 case 2:
141 /*ASPM value set by chipset. */
142 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
143 ppsc->support_aspm = true;
144 break;
145 default:
146 pr_err("switch case %#x not processed\n",
147 rtlpci->const_support_pciaspm);
148 break;
149 }
150
151 /* toshiba aspm issue, toshiba will set aspm selfly
152 * so we should not set aspm in driver
153 */
154 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
155 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
156 init_aspm == 0x43)
157 ppsc->support_aspm = false;
158 }
159
_rtl_pci_platform_switch_device_pci_aspm(struct ieee80211_hw * hw,u8 value)160 static bool _rtl_pci_platform_switch_device_pci_aspm(
161 struct ieee80211_hw *hw,
162 u8 value)
163 {
164 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
165 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
166
167 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
168 value |= 0x40;
169
170 pci_write_config_byte(rtlpci->pdev, 0x80, value);
171
172 return false;
173 }
174
175 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
_rtl_pci_switch_clk_req(struct ieee80211_hw * hw,u8 value)176 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
177 {
178 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
179 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
180
181 pci_write_config_byte(rtlpci->pdev, 0x81, value);
182
183 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
184 udelay(100);
185 }
186
187 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
rtl_pci_disable_aspm(struct ieee80211_hw * hw)188 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
189 {
190 struct rtl_priv *rtlpriv = rtl_priv(hw);
191 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
192 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
193 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
194 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
195 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
196 /*Retrieve original configuration settings. */
197 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
198 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
199 pcibridge_linkctrlreg;
200 u16 aspmlevel = 0;
201 u8 tmp_u1b = 0;
202
203 if (!ppsc->support_aspm)
204 return;
205
206 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
207 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
208 "PCI(Bridge) UNKNOWN\n");
209
210 return;
211 }
212
213 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
214 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
215 _rtl_pci_switch_clk_req(hw, 0x0);
216 }
217
218 /*for promising device will in L0 state after an I/O. */
219 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
220
221 /*Set corresponding value. */
222 aspmlevel |= BIT(0) | BIT(1);
223 linkctrl_reg &= ~aspmlevel;
224 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
225
226 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
227 udelay(50);
228
229 /*4 Disable Pci Bridge ASPM */
230 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
231 pcibridge_linkctrlreg);
232
233 udelay(50);
234 }
235
236 /*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
237 *power saving We should follow the sequence to enable
238 *RTL8192SE first then enable Pci Bridge ASPM
239 *or the system will show bluescreen.
240 */
rtl_pci_enable_aspm(struct ieee80211_hw * hw)241 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
242 {
243 struct rtl_priv *rtlpriv = rtl_priv(hw);
244 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
245 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
246 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
247 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
248 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
249 u16 aspmlevel;
250 u8 u_pcibridge_aspmsetting;
251 u8 u_device_aspmsetting;
252
253 if (!ppsc->support_aspm)
254 return;
255
256 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
257 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
258 "PCI(Bridge) UNKNOWN\n");
259 return;
260 }
261
262 /*4 Enable Pci Bridge ASPM */
263
264 u_pcibridge_aspmsetting =
265 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
266 rtlpci->const_hostpci_aspm_setting;
267
268 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
269 u_pcibridge_aspmsetting &= ~BIT(0);
270
271 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
272 u_pcibridge_aspmsetting);
273
274 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
275 "PlatformEnableASPM(): Write reg[%x] = %x\n",
276 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
277 u_pcibridge_aspmsetting);
278
279 udelay(50);
280
281 /*Get ASPM level (with/without Clock Req) */
282 aspmlevel = rtlpci->const_devicepci_aspm_setting;
283 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
284
285 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
286 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
287
288 u_device_aspmsetting |= aspmlevel;
289
290 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
291
292 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
293 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
294 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
295 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
296 }
297 udelay(100);
298 }
299
rtl_pci_get_amd_l1_patch(struct ieee80211_hw * hw)300 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
301 {
302 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
303
304 bool status = false;
305 u8 offset_e0;
306 unsigned int offset_e4;
307
308 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
309
310 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
311
312 if (offset_e0 == 0xA0) {
313 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
314 if (offset_e4 & BIT(23))
315 status = true;
316 }
317
318 return status;
319 }
320
rtl_pci_check_buddy_priv(struct ieee80211_hw * hw,struct rtl_priv ** buddy_priv)321 static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw,
322 struct rtl_priv **buddy_priv)
323 {
324 struct rtl_priv *rtlpriv = rtl_priv(hw);
325 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
326 bool find_buddy_priv = false;
327 struct rtl_priv *tpriv;
328 struct rtl_pci_priv *tpcipriv = NULL;
329
330 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) {
331 list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list,
332 list) {
333 tpcipriv = (struct rtl_pci_priv *)tpriv->priv;
334 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
335 "pcipriv->ndis_adapter.funcnumber %x\n",
336 pcipriv->ndis_adapter.funcnumber);
337 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
338 "tpcipriv->ndis_adapter.funcnumber %x\n",
339 tpcipriv->ndis_adapter.funcnumber);
340
341 if (pcipriv->ndis_adapter.busnumber ==
342 tpcipriv->ndis_adapter.busnumber &&
343 pcipriv->ndis_adapter.devnumber ==
344 tpcipriv->ndis_adapter.devnumber &&
345 pcipriv->ndis_adapter.funcnumber !=
346 tpcipriv->ndis_adapter.funcnumber) {
347 find_buddy_priv = true;
348 break;
349 }
350 }
351 }
352
353 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
354 "find_buddy_priv %d\n", find_buddy_priv);
355
356 if (find_buddy_priv)
357 *buddy_priv = tpriv;
358
359 return find_buddy_priv;
360 }
361
rtl_pci_get_linkcontrol_field(struct ieee80211_hw * hw)362 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
363 {
364 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
365 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
366 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
367 u8 linkctrl_reg;
368 u8 num4bbytes;
369
370 num4bbytes = (capabilityoffset + 0x10) / 4;
371
372 /*Read Link Control Register */
373 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
374
375 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
376 }
377
rtl_pci_parse_configuration(struct pci_dev * pdev,struct ieee80211_hw * hw)378 static void rtl_pci_parse_configuration(struct pci_dev *pdev,
379 struct ieee80211_hw *hw)
380 {
381 struct rtl_priv *rtlpriv = rtl_priv(hw);
382 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
383
384 u8 tmp;
385 u16 linkctrl_reg;
386
387 /*Link Control Register */
388 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
389 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
390
391 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
392 pcipriv->ndis_adapter.linkctrl_reg);
393
394 pci_read_config_byte(pdev, 0x98, &tmp);
395 tmp |= BIT(4);
396 pci_write_config_byte(pdev, 0x98, tmp);
397
398 tmp = 0x17;
399 pci_write_config_byte(pdev, 0x70f, tmp);
400 }
401
rtl_pci_init_aspm(struct ieee80211_hw * hw)402 static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
403 {
404 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
405
406 _rtl_pci_update_default_setting(hw);
407
408 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
409 /*Always enable ASPM & Clock Req. */
410 rtl_pci_enable_aspm(hw);
411 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
412 }
413 }
414
_rtl_pci_io_handler_init(struct device * dev,struct ieee80211_hw * hw)415 static void _rtl_pci_io_handler_init(struct device *dev,
416 struct ieee80211_hw *hw)
417 {
418 struct rtl_priv *rtlpriv = rtl_priv(hw);
419
420 rtlpriv->io.dev = dev;
421
422 rtlpriv->io.write8_async = pci_write8_async;
423 rtlpriv->io.write16_async = pci_write16_async;
424 rtlpriv->io.write32_async = pci_write32_async;
425
426 rtlpriv->io.read8_sync = pci_read8_sync;
427 rtlpriv->io.read16_sync = pci_read16_sync;
428 rtlpriv->io.read32_sync = pci_read32_sync;
429 }
430
_rtl_update_earlymode_info(struct ieee80211_hw * hw,struct sk_buff * skb,struct rtl_tcb_desc * tcb_desc,u8 tid)431 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
432 struct sk_buff *skb,
433 struct rtl_tcb_desc *tcb_desc, u8 tid)
434 {
435 struct rtl_priv *rtlpriv = rtl_priv(hw);
436 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
437 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
438 struct sk_buff *next_skb;
439 u8 additionlen = FCS_LEN;
440
441 /* here open is 4, wep/tkip is 8, aes is 12*/
442 if (info->control.hw_key)
443 additionlen += info->control.hw_key->icv_len;
444
445 /* The most skb num is 6 */
446 tcb_desc->empkt_num = 0;
447 spin_lock_bh(&rtlpriv->locks.waitq_lock);
448 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
449 struct ieee80211_tx_info *next_info;
450
451 next_info = IEEE80211_SKB_CB(next_skb);
452 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
453 tcb_desc->empkt_len[tcb_desc->empkt_num] =
454 next_skb->len + additionlen;
455 tcb_desc->empkt_num++;
456 } else {
457 break;
458 }
459
460 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
461 next_skb))
462 break;
463
464 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num)
465 break;
466 }
467 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
468
469 return true;
470 }
471
472 /* just for early mode now */
_rtl_pci_tx_chk_waitq(struct ieee80211_hw * hw)473 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
474 {
475 struct rtl_priv *rtlpriv = rtl_priv(hw);
476 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
477 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
478 struct sk_buff *skb = NULL;
479 struct ieee80211_tx_info *info = NULL;
480 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
481 int tid;
482
483 if (!rtlpriv->rtlhal.earlymode_enable)
484 return;
485
486 if (rtlpriv->dm.supp_phymode_switch &&
487 (rtlpriv->easy_concurrent_ctl.switch_in_process ||
488 (rtlpriv->buddy_priv &&
489 rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process)))
490 return;
491 /* we just use em for BE/BK/VI/VO */
492 for (tid = 7; tid >= 0; tid--) {
493 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)];
494 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
495
496 while (!mac->act_scanning &&
497 rtlpriv->psc.rfpwr_state == ERFON) {
498 struct rtl_tcb_desc tcb_desc;
499
500 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
501
502 spin_lock(&rtlpriv->locks.waitq_lock);
503 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
504 (ring->entries - skb_queue_len(&ring->queue) >
505 rtlhal->max_earlymode_num)) {
506 skb = skb_dequeue(&mac->skb_waitq[tid]);
507 } else {
508 spin_unlock(&rtlpriv->locks.waitq_lock);
509 break;
510 }
511 spin_unlock(&rtlpriv->locks.waitq_lock);
512
513 /* Some macaddr can't do early mode. like
514 * multicast/broadcast/no_qos data
515 */
516 info = IEEE80211_SKB_CB(skb);
517 if (info->flags & IEEE80211_TX_CTL_AMPDU)
518 _rtl_update_earlymode_info(hw, skb,
519 &tcb_desc, tid);
520
521 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
522 }
523 }
524 }
525
_rtl_pci_tx_isr(struct ieee80211_hw * hw,int prio)526 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
527 {
528 struct rtl_priv *rtlpriv = rtl_priv(hw);
529 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
530
531 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
532
533 while (skb_queue_len(&ring->queue)) {
534 struct sk_buff *skb;
535 struct ieee80211_tx_info *info;
536 __le16 fc;
537 u8 tid;
538 u8 *entry;
539
540 if (rtlpriv->use_new_trx_flow)
541 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
542 else
543 entry = (u8 *)(&ring->desc[ring->idx]);
544
545 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx))
546 return;
547 ring->idx = (ring->idx + 1) % ring->entries;
548
549 skb = __skb_dequeue(&ring->queue);
550 pci_unmap_single(rtlpci->pdev,
551 rtlpriv->cfg->ops->
552 get_desc(hw, (u8 *)entry, true,
553 HW_DESC_TXBUFF_ADDR),
554 skb->len, PCI_DMA_TODEVICE);
555
556 /* remove early mode header */
557 if (rtlpriv->rtlhal.earlymode_enable)
558 skb_pull(skb, EM_HDR_LEN);
559
560 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
561 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
562 ring->idx,
563 skb_queue_len(&ring->queue),
564 *(u16 *)(skb->data + 22));
565
566 if (prio == TXCMD_QUEUE) {
567 dev_kfree_skb(skb);
568 goto tx_status_ok;
569 }
570
571 /* for sw LPS, just after NULL skb send out, we can
572 * sure AP knows we are sleeping, we should not let
573 * rf sleep
574 */
575 fc = rtl_get_fc(skb);
576 if (ieee80211_is_nullfunc(fc)) {
577 if (ieee80211_has_pm(fc)) {
578 rtlpriv->mac80211.offchan_delay = true;
579 rtlpriv->psc.state_inap = true;
580 } else {
581 rtlpriv->psc.state_inap = false;
582 }
583 }
584 if (ieee80211_is_action(fc)) {
585 struct ieee80211_mgmt *action_frame =
586 (struct ieee80211_mgmt *)skb->data;
587 if (action_frame->u.action.u.ht_smps.action ==
588 WLAN_HT_ACTION_SMPS) {
589 dev_kfree_skb(skb);
590 goto tx_status_ok;
591 }
592 }
593
594 /* update tid tx pkt num */
595 tid = rtl_get_tid(skb);
596 if (tid <= 7)
597 rtlpriv->link_info.tidtx_inperiod[tid]++;
598
599 info = IEEE80211_SKB_CB(skb);
600
601 if (likely(!ieee80211_is_nullfunc(fc))) {
602 ieee80211_tx_info_clear_status(info);
603 info->flags |= IEEE80211_TX_STAT_ACK;
604 /*info->status.rates[0].count = 1; */
605 ieee80211_tx_status_irqsafe(hw, skb);
606 } else {
607 rtl_tx_ackqueue(hw, skb);
608 }
609
610 if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) {
611 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
612 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n",
613 prio, ring->idx,
614 skb_queue_len(&ring->queue));
615
616 ieee80211_wake_queue(hw, skb_get_queue_mapping(skb));
617 }
618 tx_status_ok:
619 skb = NULL;
620 }
621
622 if (((rtlpriv->link_info.num_rx_inperiod +
623 rtlpriv->link_info.num_tx_inperiod) > 8) ||
624 rtlpriv->link_info.num_rx_inperiod > 2)
625 rtl_lps_leave(hw);
626 }
627
_rtl_pci_init_one_rxdesc(struct ieee80211_hw * hw,struct sk_buff * new_skb,u8 * entry,int rxring_idx,int desc_idx)628 static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw,
629 struct sk_buff *new_skb, u8 *entry,
630 int rxring_idx, int desc_idx)
631 {
632 struct rtl_priv *rtlpriv = rtl_priv(hw);
633 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
634 u32 bufferaddress;
635 u8 tmp_one = 1;
636 struct sk_buff *skb;
637
638 if (likely(new_skb)) {
639 skb = new_skb;
640 goto remap;
641 }
642 skb = dev_alloc_skb(rtlpci->rxbuffersize);
643 if (!skb)
644 return 0;
645
646 remap:
647 /* just set skb->cb to mapping addr for pci_unmap_single use */
648 *((dma_addr_t *)skb->cb) =
649 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
650 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
651 bufferaddress = *((dma_addr_t *)skb->cb);
652 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress))
653 return 0;
654 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb;
655 if (rtlpriv->use_new_trx_flow) {
656 /* skb->cb may be 64 bit address */
657 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
658 HW_DESC_RX_PREPARE,
659 (u8 *)(dma_addr_t *)skb->cb);
660 } else {
661 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
662 HW_DESC_RXBUFF_ADDR,
663 (u8 *)&bufferaddress);
664 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
665 HW_DESC_RXPKT_LEN,
666 (u8 *)&rtlpci->rxbuffersize);
667 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
668 HW_DESC_RXOWN,
669 (u8 *)&tmp_one);
670 }
671 return 1;
672 }
673
674 /* inorder to receive 8K AMSDU we have set skb to
675 * 9100bytes in init rx ring, but if this packet is
676 * not a AMSDU, this large packet will be sent to
677 * TCP/IP directly, this cause big packet ping fail
678 * like: "ping -s 65507", so here we will realloc skb
679 * based on the true size of packet, Mac80211
680 * Probably will do it better, but does not yet.
681 *
682 * Some platform will fail when alloc skb sometimes.
683 * in this condition, we will send the old skb to
684 * mac80211 directly, this will not cause any other
685 * issues, but only this packet will be lost by TCP/IP
686 */
_rtl_pci_rx_to_mac80211(struct ieee80211_hw * hw,struct sk_buff * skb,struct ieee80211_rx_status rx_status)687 static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw,
688 struct sk_buff *skb,
689 struct ieee80211_rx_status rx_status)
690 {
691 if (unlikely(!rtl_action_proc(hw, skb, false))) {
692 dev_kfree_skb_any(skb);
693 } else {
694 struct sk_buff *uskb = NULL;
695
696 uskb = dev_alloc_skb(skb->len + 128);
697 if (likely(uskb)) {
698 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status,
699 sizeof(rx_status));
700 skb_put_data(uskb, skb->data, skb->len);
701 dev_kfree_skb_any(skb);
702 ieee80211_rx_irqsafe(hw, uskb);
703 } else {
704 ieee80211_rx_irqsafe(hw, skb);
705 }
706 }
707 }
708
709 /*hsisr interrupt handler*/
_rtl_pci_hs_interrupt(struct ieee80211_hw * hw)710 static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw)
711 {
712 struct rtl_priv *rtlpriv = rtl_priv(hw);
713 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
714
715 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR],
716 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) |
717 rtlpci->sys_irq_mask);
718 }
719
_rtl_pci_rx_interrupt(struct ieee80211_hw * hw)720 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
721 {
722 struct rtl_priv *rtlpriv = rtl_priv(hw);
723 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
724 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE;
725 struct ieee80211_rx_status rx_status = { 0 };
726 unsigned int count = rtlpci->rxringcount;
727 u8 own;
728 u8 tmp_one;
729 bool unicast = false;
730 u8 hw_queue = 0;
731 unsigned int rx_remained_cnt = 0;
732 struct rtl_stats stats = {
733 .signal = 0,
734 .rate = 0,
735 };
736
737 /*RX NORMAL PKT */
738 while (count--) {
739 struct ieee80211_hdr *hdr;
740 __le16 fc;
741 u16 len;
742 /*rx buffer descriptor */
743 struct rtl_rx_buffer_desc *buffer_desc = NULL;
744 /*if use new trx flow, it means wifi info */
745 struct rtl_rx_desc *pdesc = NULL;
746 /*rx pkt */
747 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[
748 rtlpci->rx_ring[rxring_idx].idx];
749 struct sk_buff *new_skb;
750
751 if (rtlpriv->use_new_trx_flow) {
752 if (rx_remained_cnt == 0)
753 rx_remained_cnt =
754 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw,
755 hw_queue);
756 if (rx_remained_cnt == 0)
757 return;
758 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[
759 rtlpci->rx_ring[rxring_idx].idx];
760 pdesc = (struct rtl_rx_desc *)skb->data;
761 } else { /* rx descriptor */
762 pdesc = &rtlpci->rx_ring[rxring_idx].desc[
763 rtlpci->rx_ring[rxring_idx].idx];
764
765 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
766 false,
767 HW_DESC_OWN);
768 if (own) /* wait data to be filled by hardware */
769 return;
770 }
771
772 /* Reaching this point means: data is filled already
773 * AAAAAAttention !!!
774 * We can NOT access 'skb' before 'pci_unmap_single'
775 */
776 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb),
777 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
778
779 /* get a new skb - if fail, old one will be reused */
780 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
781 if (unlikely(!new_skb))
782 goto no_new;
783 memset(&rx_status, 0, sizeof(rx_status));
784 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
785 &rx_status, (u8 *)pdesc, skb);
786
787 if (rtlpriv->use_new_trx_flow)
788 rtlpriv->cfg->ops->rx_check_dma_ok(hw,
789 (u8 *)buffer_desc,
790 hw_queue);
791
792 len = rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, false,
793 HW_DESC_RXPKT_LEN);
794
795 if (skb->end - skb->tail > len) {
796 skb_put(skb, len);
797 if (rtlpriv->use_new_trx_flow)
798 skb_reserve(skb, stats.rx_drvinfo_size +
799 stats.rx_bufshift + 24);
800 else
801 skb_reserve(skb, stats.rx_drvinfo_size +
802 stats.rx_bufshift);
803 } else {
804 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
805 "skb->end - skb->tail = %d, len is %d\n",
806 skb->end - skb->tail, len);
807 dev_kfree_skb_any(skb);
808 goto new_trx_end;
809 }
810 /* handle command packet here */
811 if (stats.packet_report_type == C2H_PACKET) {
812 rtl_c2hcmd_enqueue(hw, skb);
813 goto new_trx_end;
814 }
815
816 /* NOTICE This can not be use for mac80211,
817 * this is done in mac80211 code,
818 * if done here sec DHCP will fail
819 * skb_trim(skb, skb->len - 4);
820 */
821
822 hdr = rtl_get_hdr(skb);
823 fc = rtl_get_fc(skb);
824
825 if (!stats.crc && !stats.hwerror && (skb->len > FCS_LEN)) {
826 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
827 sizeof(rx_status));
828
829 if (is_broadcast_ether_addr(hdr->addr1)) {
830 ;/*TODO*/
831 } else if (is_multicast_ether_addr(hdr->addr1)) {
832 ;/*TODO*/
833 } else {
834 unicast = true;
835 rtlpriv->stats.rxbytesunicast += skb->len;
836 }
837 rtl_is_special_data(hw, skb, false, true);
838
839 if (ieee80211_is_data(fc)) {
840 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
841 if (unicast)
842 rtlpriv->link_info.num_rx_inperiod++;
843 }
844
845 rtl_collect_scan_list(hw, skb);
846
847 /* static bcn for roaming */
848 rtl_beacon_statistic(hw, skb);
849 rtl_p2p_info(hw, (void *)skb->data, skb->len);
850 /* for sw lps */
851 rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
852 rtl_recognize_peer(hw, (void *)skb->data, skb->len);
853 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP &&
854 rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G &&
855 (ieee80211_is_beacon(fc) ||
856 ieee80211_is_probe_resp(fc))) {
857 dev_kfree_skb_any(skb);
858 } else {
859 _rtl_pci_rx_to_mac80211(hw, skb, rx_status);
860 }
861 } else {
862 /* drop packets with errors or those too short */
863 dev_kfree_skb_any(skb);
864 }
865 new_trx_end:
866 if (rtlpriv->use_new_trx_flow) {
867 rtlpci->rx_ring[hw_queue].next_rx_rp += 1;
868 rtlpci->rx_ring[hw_queue].next_rx_rp %=
869 RTL_PCI_MAX_RX_COUNT;
870
871 rx_remained_cnt--;
872 rtl_write_word(rtlpriv, 0x3B4,
873 rtlpci->rx_ring[hw_queue].next_rx_rp);
874 }
875 if (((rtlpriv->link_info.num_rx_inperiod +
876 rtlpriv->link_info.num_tx_inperiod) > 8) ||
877 rtlpriv->link_info.num_rx_inperiod > 2)
878 rtl_lps_leave(hw);
879 skb = new_skb;
880 no_new:
881 if (rtlpriv->use_new_trx_flow) {
882 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc,
883 rxring_idx,
884 rtlpci->rx_ring[rxring_idx].idx);
885 } else {
886 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc,
887 rxring_idx,
888 rtlpci->rx_ring[rxring_idx].idx);
889 if (rtlpci->rx_ring[rxring_idx].idx ==
890 rtlpci->rxringcount - 1)
891 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc,
892 false,
893 HW_DESC_RXERO,
894 (u8 *)&tmp_one);
895 }
896 rtlpci->rx_ring[rxring_idx].idx =
897 (rtlpci->rx_ring[rxring_idx].idx + 1) %
898 rtlpci->rxringcount;
899 }
900 }
901
_rtl_pci_interrupt(int irq,void * dev_id)902 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
903 {
904 struct ieee80211_hw *hw = dev_id;
905 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
906 struct rtl_priv *rtlpriv = rtl_priv(hw);
907 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
908 unsigned long flags;
909 struct rtl_int intvec = {0};
910
911 irqreturn_t ret = IRQ_HANDLED;
912
913 if (rtlpci->irq_enabled == 0)
914 return ret;
915
916 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
917 rtlpriv->cfg->ops->disable_interrupt(hw);
918
919 /*read ISR: 4/8bytes */
920 rtlpriv->cfg->ops->interrupt_recognized(hw, &intvec);
921
922 /*Shared IRQ or HW disappeared */
923 if (!intvec.inta || intvec.inta == 0xffff)
924 goto done;
925
926 /*<1> beacon related */
927 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK])
928 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
929 "beacon ok interrupt!\n");
930
931 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDER]))
932 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
933 "beacon err interrupt!\n");
934
935 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BDOK])
936 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
937
938 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) {
939 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
940 "prepare beacon for interrupt!\n");
941 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
942 }
943
944 /*<2> Tx related */
945 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
946 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
947
948 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
949 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
950 "Manage ok interrupt!\n");
951 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
952 }
953
954 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
955 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
956 "HIGH_QUEUE ok interrupt!\n");
957 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
958 }
959
960 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
961 rtlpriv->link_info.num_tx_inperiod++;
962
963 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
964 "BK Tx OK interrupt!\n");
965 _rtl_pci_tx_isr(hw, BK_QUEUE);
966 }
967
968 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
969 rtlpriv->link_info.num_tx_inperiod++;
970
971 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
972 "BE TX OK interrupt!\n");
973 _rtl_pci_tx_isr(hw, BE_QUEUE);
974 }
975
976 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
977 rtlpriv->link_info.num_tx_inperiod++;
978
979 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
980 "VI TX OK interrupt!\n");
981 _rtl_pci_tx_isr(hw, VI_QUEUE);
982 }
983
984 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
985 rtlpriv->link_info.num_tx_inperiod++;
986
987 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
988 "Vo TX OK interrupt!\n");
989 _rtl_pci_tx_isr(hw, VO_QUEUE);
990 }
991
992 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
993 if (intvec.intd & rtlpriv->cfg->maps[RTL_IMR_H2CDOK]) {
994 rtlpriv->link_info.num_tx_inperiod++;
995
996 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
997 "H2C TX OK interrupt!\n");
998 _rtl_pci_tx_isr(hw, H2C_QUEUE);
999 }
1000 }
1001
1002 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
1003 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
1004 rtlpriv->link_info.num_tx_inperiod++;
1005
1006 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1007 "CMD TX OK interrupt!\n");
1008 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
1009 }
1010 }
1011
1012 /*<3> Rx related */
1013 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
1014 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
1015 _rtl_pci_rx_interrupt(hw);
1016 }
1017
1018 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
1019 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1020 "rx descriptor unavailable!\n");
1021 _rtl_pci_rx_interrupt(hw);
1022 }
1023
1024 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
1025 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
1026 _rtl_pci_rx_interrupt(hw);
1027 }
1028
1029 /*<4> fw related*/
1030 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
1031 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) {
1032 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1033 "firmware interrupt!\n");
1034 queue_delayed_work(rtlpriv->works.rtl_wq,
1035 &rtlpriv->works.fwevt_wq, 0);
1036 }
1037 }
1038
1039 /*<5> hsisr related*/
1040 /* Only 8188EE & 8723BE Supported.
1041 * If Other ICs Come in, System will corrupt,
1042 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR]
1043 * are not initialized
1044 */
1045 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE ||
1046 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
1047 if (unlikely(intvec.inta &
1048 rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) {
1049 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1050 "hsisr interrupt!\n");
1051 _rtl_pci_hs_interrupt(hw);
1052 }
1053 }
1054
1055 if (rtlpriv->rtlhal.earlymode_enable)
1056 tasklet_schedule(&rtlpriv->works.irq_tasklet);
1057
1058 done:
1059 rtlpriv->cfg->ops->enable_interrupt(hw);
1060 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1061 return ret;
1062 }
1063
_rtl_pci_irq_tasklet(struct ieee80211_hw * hw)1064 static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
1065 {
1066 _rtl_pci_tx_chk_waitq(hw);
1067 }
1068
_rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw * hw)1069 static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
1070 {
1071 struct rtl_priv *rtlpriv = rtl_priv(hw);
1072 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1073 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1074 struct rtl8192_tx_ring *ring = NULL;
1075 struct ieee80211_hdr *hdr = NULL;
1076 struct ieee80211_tx_info *info = NULL;
1077 struct sk_buff *pskb = NULL;
1078 struct rtl_tx_desc *pdesc = NULL;
1079 struct rtl_tcb_desc tcb_desc;
1080 /*This is for new trx flow*/
1081 struct rtl_tx_buffer_desc *pbuffer_desc = NULL;
1082 u8 temp_one = 1;
1083 u8 *entry;
1084
1085 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
1086 ring = &rtlpci->tx_ring[BEACON_QUEUE];
1087 pskb = __skb_dequeue(&ring->queue);
1088 if (rtlpriv->use_new_trx_flow)
1089 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1090 else
1091 entry = (u8 *)(&ring->desc[ring->idx]);
1092 if (pskb) {
1093 pci_unmap_single(rtlpci->pdev,
1094 rtlpriv->cfg->ops->get_desc(
1095 hw, (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
1096 pskb->len, PCI_DMA_TODEVICE);
1097 kfree_skb(pskb);
1098 }
1099
1100 /*NB: the beacon data buffer must be 32-bit aligned. */
1101 pskb = ieee80211_beacon_get(hw, mac->vif);
1102 if (!pskb)
1103 return;
1104 hdr = rtl_get_hdr(pskb);
1105 info = IEEE80211_SKB_CB(pskb);
1106 pdesc = &ring->desc[0];
1107 if (rtlpriv->use_new_trx_flow)
1108 pbuffer_desc = &ring->buffer_desc[0];
1109
1110 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1111 (u8 *)pbuffer_desc, info, NULL, pskb,
1112 BEACON_QUEUE, &tcb_desc);
1113
1114 __skb_queue_tail(&ring->queue, pskb);
1115
1116 if (rtlpriv->use_new_trx_flow) {
1117 temp_one = 4;
1118 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true,
1119 HW_DESC_OWN, (u8 *)&temp_one);
1120 } else {
1121 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN,
1122 &temp_one);
1123 }
1124 }
1125
_rtl_pci_init_trx_var(struct ieee80211_hw * hw)1126 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
1127 {
1128 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1129 struct rtl_priv *rtlpriv = rtl_priv(hw);
1130 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1131 u8 i;
1132 u16 desc_num;
1133
1134 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
1135 desc_num = TX_DESC_NUM_92E;
1136 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE)
1137 desc_num = TX_DESC_NUM_8822B;
1138 else
1139 desc_num = RT_TXDESC_NUM;
1140
1141 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1142 rtlpci->txringcount[i] = desc_num;
1143
1144 /*we just alloc 2 desc for beacon queue,
1145 *because we just need first desc in hw beacon.
1146 */
1147 rtlpci->txringcount[BEACON_QUEUE] = 2;
1148
1149 /*BE queue need more descriptor for performance
1150 *consideration or, No more tx desc will happen,
1151 *and may cause mac80211 mem leakage.
1152 */
1153 if (!rtl_priv(hw)->use_new_trx_flow)
1154 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
1155
1156 rtlpci->rxbuffersize = 9100; /*2048/1024; */
1157 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
1158 }
1159
_rtl_pci_init_struct(struct ieee80211_hw * hw,struct pci_dev * pdev)1160 static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1161 struct pci_dev *pdev)
1162 {
1163 struct rtl_priv *rtlpriv = rtl_priv(hw);
1164 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1165 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1166 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1167
1168 rtlpci->up_first_time = true;
1169 rtlpci->being_init_adapter = false;
1170
1171 rtlhal->hw = hw;
1172 rtlpci->pdev = pdev;
1173
1174 /*Tx/Rx related var */
1175 _rtl_pci_init_trx_var(hw);
1176
1177 /*IBSS*/
1178 mac->beacon_interval = 100;
1179
1180 /*AMPDU*/
1181 mac->min_space_cfg = 0;
1182 mac->max_mss_density = 0;
1183 /*set sane AMPDU defaults */
1184 mac->current_ampdu_density = 7;
1185 mac->current_ampdu_factor = 3;
1186
1187 /*Retry Limit*/
1188 mac->retry_short = 7;
1189 mac->retry_long = 7;
1190
1191 /*QOS*/
1192 rtlpci->acm_method = EACMWAY2_SW;
1193
1194 /*task */
1195 tasklet_init(&rtlpriv->works.irq_tasklet,
1196 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1197 (unsigned long)hw);
1198 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1199 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1200 (unsigned long)hw);
1201 INIT_WORK(&rtlpriv->works.lps_change_work,
1202 rtl_lps_change_work_callback);
1203 }
1204
_rtl_pci_init_tx_ring(struct ieee80211_hw * hw,unsigned int prio,unsigned int entries)1205 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1206 unsigned int prio, unsigned int entries)
1207 {
1208 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1209 struct rtl_priv *rtlpriv = rtl_priv(hw);
1210 struct rtl_tx_buffer_desc *buffer_desc;
1211 struct rtl_tx_desc *desc;
1212 dma_addr_t buffer_desc_dma, desc_dma;
1213 u32 nextdescaddress;
1214 int i;
1215
1216 /* alloc tx buffer desc for new trx flow*/
1217 if (rtlpriv->use_new_trx_flow) {
1218 buffer_desc =
1219 pci_zalloc_consistent(rtlpci->pdev,
1220 sizeof(*buffer_desc) * entries,
1221 &buffer_desc_dma);
1222
1223 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) {
1224 pr_err("Cannot allocate TX ring (prio = %d)\n",
1225 prio);
1226 return -ENOMEM;
1227 }
1228
1229 rtlpci->tx_ring[prio].buffer_desc = buffer_desc;
1230 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma;
1231
1232 rtlpci->tx_ring[prio].cur_tx_rp = 0;
1233 rtlpci->tx_ring[prio].cur_tx_wp = 0;
1234 }
1235
1236 /* alloc dma for this ring */
1237 desc = pci_zalloc_consistent(rtlpci->pdev,
1238 sizeof(*desc) * entries, &desc_dma);
1239
1240 if (!desc || (unsigned long)desc & 0xFF) {
1241 pr_err("Cannot allocate TX ring (prio = %d)\n", prio);
1242 return -ENOMEM;
1243 }
1244
1245 rtlpci->tx_ring[prio].desc = desc;
1246 rtlpci->tx_ring[prio].dma = desc_dma;
1247
1248 rtlpci->tx_ring[prio].idx = 0;
1249 rtlpci->tx_ring[prio].entries = entries;
1250 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1251
1252 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1253 prio, desc);
1254
1255 /* init every desc in this ring */
1256 if (!rtlpriv->use_new_trx_flow) {
1257 for (i = 0; i < entries; i++) {
1258 nextdescaddress = (u32)desc_dma +
1259 ((i + 1) % entries) *
1260 sizeof(*desc);
1261
1262 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i],
1263 true,
1264 HW_DESC_TX_NEXTDESC_ADDR,
1265 (u8 *)&nextdescaddress);
1266 }
1267 }
1268 return 0;
1269 }
1270
_rtl_pci_init_rx_ring(struct ieee80211_hw * hw,int rxring_idx)1271 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1272 {
1273 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1274 struct rtl_priv *rtlpriv = rtl_priv(hw);
1275 int i;
1276
1277 if (rtlpriv->use_new_trx_flow) {
1278 struct rtl_rx_buffer_desc *entry = NULL;
1279 /* alloc dma for this ring */
1280 rtlpci->rx_ring[rxring_idx].buffer_desc =
1281 pci_zalloc_consistent(rtlpci->pdev,
1282 sizeof(*rtlpci->rx_ring[rxring_idx].
1283 buffer_desc) *
1284 rtlpci->rxringcount,
1285 &rtlpci->rx_ring[rxring_idx].dma);
1286 if (!rtlpci->rx_ring[rxring_idx].buffer_desc ||
1287 (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) {
1288 pr_err("Cannot allocate RX ring\n");
1289 return -ENOMEM;
1290 }
1291
1292 /* init every desc in this ring */
1293 rtlpci->rx_ring[rxring_idx].idx = 0;
1294 for (i = 0; i < rtlpci->rxringcount; i++) {
1295 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i];
1296 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1297 rxring_idx, i))
1298 return -ENOMEM;
1299 }
1300 } else {
1301 struct rtl_rx_desc *entry = NULL;
1302 u8 tmp_one = 1;
1303 /* alloc dma for this ring */
1304 rtlpci->rx_ring[rxring_idx].desc =
1305 pci_zalloc_consistent(rtlpci->pdev,
1306 sizeof(*rtlpci->rx_ring[rxring_idx].
1307 desc) * rtlpci->rxringcount,
1308 &rtlpci->rx_ring[rxring_idx].dma);
1309 if (!rtlpci->rx_ring[rxring_idx].desc ||
1310 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) {
1311 pr_err("Cannot allocate RX ring\n");
1312 return -ENOMEM;
1313 }
1314
1315 /* init every desc in this ring */
1316 rtlpci->rx_ring[rxring_idx].idx = 0;
1317
1318 for (i = 0; i < rtlpci->rxringcount; i++) {
1319 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1320 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1321 rxring_idx, i))
1322 return -ENOMEM;
1323 }
1324
1325 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1326 HW_DESC_RXERO, &tmp_one);
1327 }
1328 return 0;
1329 }
1330
_rtl_pci_free_tx_ring(struct ieee80211_hw * hw,unsigned int prio)1331 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1332 unsigned int prio)
1333 {
1334 struct rtl_priv *rtlpriv = rtl_priv(hw);
1335 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1336 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1337
1338 /* free every desc in this ring */
1339 while (skb_queue_len(&ring->queue)) {
1340 u8 *entry;
1341 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1342
1343 if (rtlpriv->use_new_trx_flow)
1344 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1345 else
1346 entry = (u8 *)(&ring->desc[ring->idx]);
1347
1348 pci_unmap_single(rtlpci->pdev,
1349 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1350 true,
1351 HW_DESC_TXBUFF_ADDR),
1352 skb->len, PCI_DMA_TODEVICE);
1353 kfree_skb(skb);
1354 ring->idx = (ring->idx + 1) % ring->entries;
1355 }
1356
1357 /* free dma of this ring */
1358 pci_free_consistent(rtlpci->pdev,
1359 sizeof(*ring->desc) * ring->entries,
1360 ring->desc, ring->dma);
1361 ring->desc = NULL;
1362 if (rtlpriv->use_new_trx_flow) {
1363 pci_free_consistent(rtlpci->pdev,
1364 sizeof(*ring->buffer_desc) * ring->entries,
1365 ring->buffer_desc, ring->buffer_desc_dma);
1366 ring->buffer_desc = NULL;
1367 }
1368 }
1369
_rtl_pci_free_rx_ring(struct ieee80211_hw * hw,int rxring_idx)1370 static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1371 {
1372 struct rtl_priv *rtlpriv = rtl_priv(hw);
1373 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1374 int i;
1375
1376 /* free every desc in this ring */
1377 for (i = 0; i < rtlpci->rxringcount; i++) {
1378 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i];
1379
1380 if (!skb)
1381 continue;
1382 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb),
1383 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
1384 kfree_skb(skb);
1385 }
1386
1387 /* free dma of this ring */
1388 if (rtlpriv->use_new_trx_flow) {
1389 pci_free_consistent(rtlpci->pdev,
1390 sizeof(*rtlpci->rx_ring[rxring_idx].
1391 buffer_desc) * rtlpci->rxringcount,
1392 rtlpci->rx_ring[rxring_idx].buffer_desc,
1393 rtlpci->rx_ring[rxring_idx].dma);
1394 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL;
1395 } else {
1396 pci_free_consistent(rtlpci->pdev,
1397 sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1398 rtlpci->rxringcount,
1399 rtlpci->rx_ring[rxring_idx].desc,
1400 rtlpci->rx_ring[rxring_idx].dma);
1401 rtlpci->rx_ring[rxring_idx].desc = NULL;
1402 }
1403 }
1404
_rtl_pci_init_trx_ring(struct ieee80211_hw * hw)1405 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1406 {
1407 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1408 int ret;
1409 int i, rxring_idx;
1410
1411 /* rxring_idx 0:RX_MPDU_QUEUE
1412 * rxring_idx 1:RX_CMD_QUEUE
1413 */
1414 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1415 ret = _rtl_pci_init_rx_ring(hw, rxring_idx);
1416 if (ret)
1417 return ret;
1418 }
1419
1420 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1421 ret = _rtl_pci_init_tx_ring(hw, i, rtlpci->txringcount[i]);
1422 if (ret)
1423 goto err_free_rings;
1424 }
1425
1426 return 0;
1427
1428 err_free_rings:
1429 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1430 _rtl_pci_free_rx_ring(hw, rxring_idx);
1431
1432 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1433 if (rtlpci->tx_ring[i].desc ||
1434 rtlpci->tx_ring[i].buffer_desc)
1435 _rtl_pci_free_tx_ring(hw, i);
1436
1437 return 1;
1438 }
1439
_rtl_pci_deinit_trx_ring(struct ieee80211_hw * hw)1440 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1441 {
1442 u32 i, rxring_idx;
1443
1444 /*free rx rings */
1445 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1446 _rtl_pci_free_rx_ring(hw, rxring_idx);
1447
1448 /*free tx rings */
1449 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1450 _rtl_pci_free_tx_ring(hw, i);
1451
1452 return 0;
1453 }
1454
rtl_pci_reset_trx_ring(struct ieee80211_hw * hw)1455 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1456 {
1457 struct rtl_priv *rtlpriv = rtl_priv(hw);
1458 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1459 int i, rxring_idx;
1460 unsigned long flags;
1461 u8 tmp_one = 1;
1462 u32 bufferaddress;
1463 /* rxring_idx 0:RX_MPDU_QUEUE */
1464 /* rxring_idx 1:RX_CMD_QUEUE */
1465 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1466 /* force the rx_ring[RX_MPDU_QUEUE/
1467 * RX_CMD_QUEUE].idx to the first one
1468 *new trx flow, do nothing
1469 */
1470 if (!rtlpriv->use_new_trx_flow &&
1471 rtlpci->rx_ring[rxring_idx].desc) {
1472 struct rtl_rx_desc *entry = NULL;
1473
1474 rtlpci->rx_ring[rxring_idx].idx = 0;
1475 for (i = 0; i < rtlpci->rxringcount; i++) {
1476 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1477 bufferaddress =
1478 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1479 false, HW_DESC_RXBUFF_ADDR);
1480 memset((u8 *)entry, 0,
1481 sizeof(*rtlpci->rx_ring
1482 [rxring_idx].desc));/*clear one entry*/
1483 if (rtlpriv->use_new_trx_flow) {
1484 rtlpriv->cfg->ops->set_desc(hw,
1485 (u8 *)entry, false,
1486 HW_DESC_RX_PREPARE,
1487 (u8 *)&bufferaddress);
1488 } else {
1489 rtlpriv->cfg->ops->set_desc(hw,
1490 (u8 *)entry, false,
1491 HW_DESC_RXBUFF_ADDR,
1492 (u8 *)&bufferaddress);
1493 rtlpriv->cfg->ops->set_desc(hw,
1494 (u8 *)entry, false,
1495 HW_DESC_RXPKT_LEN,
1496 (u8 *)&rtlpci->rxbuffersize);
1497 rtlpriv->cfg->ops->set_desc(hw,
1498 (u8 *)entry, false,
1499 HW_DESC_RXOWN,
1500 (u8 *)&tmp_one);
1501 }
1502 }
1503 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1504 HW_DESC_RXERO, (u8 *)&tmp_one);
1505 }
1506 rtlpci->rx_ring[rxring_idx].idx = 0;
1507 }
1508
1509 /*after reset, release previous pending packet,
1510 *and force the tx idx to the first one
1511 */
1512 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1513 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1514 if (rtlpci->tx_ring[i].desc ||
1515 rtlpci->tx_ring[i].buffer_desc) {
1516 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1517
1518 while (skb_queue_len(&ring->queue)) {
1519 u8 *entry;
1520 struct sk_buff *skb =
1521 __skb_dequeue(&ring->queue);
1522 if (rtlpriv->use_new_trx_flow)
1523 entry = (u8 *)(&ring->buffer_desc
1524 [ring->idx]);
1525 else
1526 entry = (u8 *)(&ring->desc[ring->idx]);
1527
1528 pci_unmap_single(rtlpci->pdev,
1529 rtlpriv->cfg->ops->
1530 get_desc(hw, (u8 *)
1531 entry,
1532 true,
1533 HW_DESC_TXBUFF_ADDR),
1534 skb->len, PCI_DMA_TODEVICE);
1535 dev_kfree_skb_irq(skb);
1536 ring->idx = (ring->idx + 1) % ring->entries;
1537 }
1538
1539 if (rtlpriv->use_new_trx_flow) {
1540 rtlpci->tx_ring[i].cur_tx_rp = 0;
1541 rtlpci->tx_ring[i].cur_tx_wp = 0;
1542 }
1543
1544 ring->idx = 0;
1545 ring->entries = rtlpci->txringcount[i];
1546 }
1547 }
1548 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1549
1550 return 0;
1551 }
1552
rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw * hw,struct ieee80211_sta * sta,struct sk_buff * skb)1553 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1554 struct ieee80211_sta *sta,
1555 struct sk_buff *skb)
1556 {
1557 struct rtl_priv *rtlpriv = rtl_priv(hw);
1558 struct rtl_sta_info *sta_entry = NULL;
1559 u8 tid = rtl_get_tid(skb);
1560 __le16 fc = rtl_get_fc(skb);
1561
1562 if (!sta)
1563 return false;
1564 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1565
1566 if (!rtlpriv->rtlhal.earlymode_enable)
1567 return false;
1568 if (ieee80211_is_nullfunc(fc))
1569 return false;
1570 if (ieee80211_is_qos_nullfunc(fc))
1571 return false;
1572 if (ieee80211_is_pspoll(fc))
1573 return false;
1574 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1575 return false;
1576 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1577 return false;
1578 if (tid > 7)
1579 return false;
1580
1581 /* maybe every tid should be checked */
1582 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1583 return false;
1584
1585 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1586 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1587 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1588
1589 return true;
1590 }
1591
rtl_pci_tx(struct ieee80211_hw * hw,struct ieee80211_sta * sta,struct sk_buff * skb,struct rtl_tcb_desc * ptcb_desc)1592 static int rtl_pci_tx(struct ieee80211_hw *hw,
1593 struct ieee80211_sta *sta,
1594 struct sk_buff *skb,
1595 struct rtl_tcb_desc *ptcb_desc)
1596 {
1597 struct rtl_priv *rtlpriv = rtl_priv(hw);
1598 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1599 struct rtl8192_tx_ring *ring;
1600 struct rtl_tx_desc *pdesc;
1601 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL;
1602 u16 idx;
1603 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1604 unsigned long flags;
1605 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1606 __le16 fc = rtl_get_fc(skb);
1607 u8 *pda_addr = hdr->addr1;
1608 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1609 u8 own;
1610 u8 temp_one = 1;
1611
1612 if (ieee80211_is_mgmt(fc))
1613 rtl_tx_mgmt_proc(hw, skb);
1614
1615 if (rtlpriv->psc.sw_ps_enabled) {
1616 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1617 !ieee80211_has_pm(fc))
1618 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1619 }
1620
1621 rtl_action_proc(hw, skb, true);
1622
1623 if (is_multicast_ether_addr(pda_addr))
1624 rtlpriv->stats.txbytesmulticast += skb->len;
1625 else if (is_broadcast_ether_addr(pda_addr))
1626 rtlpriv->stats.txbytesbroadcast += skb->len;
1627 else
1628 rtlpriv->stats.txbytesunicast += skb->len;
1629
1630 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1631 ring = &rtlpci->tx_ring[hw_queue];
1632 if (hw_queue != BEACON_QUEUE) {
1633 if (rtlpriv->use_new_trx_flow)
1634 idx = ring->cur_tx_wp;
1635 else
1636 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1637 ring->entries;
1638 } else {
1639 idx = 0;
1640 }
1641
1642 pdesc = &ring->desc[idx];
1643 if (rtlpriv->use_new_trx_flow) {
1644 ptx_bd_desc = &ring->buffer_desc[idx];
1645 } else {
1646 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
1647 true, HW_DESC_OWN);
1648
1649 if (own == 1 && hw_queue != BEACON_QUEUE) {
1650 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1651 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1652 hw_queue, ring->idx, idx,
1653 skb_queue_len(&ring->queue));
1654
1655 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1656 flags);
1657 return skb->len;
1658 }
1659 }
1660
1661 if (rtlpriv->cfg->ops->get_available_desc &&
1662 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) {
1663 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1664 "get_available_desc fail\n");
1665 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1666 return skb->len;
1667 }
1668
1669 if (ieee80211_is_data(fc))
1670 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1671
1672 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1673 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc);
1674
1675 __skb_queue_tail(&ring->queue, skb);
1676
1677 if (rtlpriv->use_new_trx_flow) {
1678 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1679 HW_DESC_OWN, &hw_queue);
1680 } else {
1681 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1682 HW_DESC_OWN, &temp_one);
1683 }
1684
1685 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1686 hw_queue != BEACON_QUEUE) {
1687 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1688 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1689 hw_queue, ring->idx, idx,
1690 skb_queue_len(&ring->queue));
1691
1692 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1693 }
1694
1695 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1696
1697 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1698
1699 return 0;
1700 }
1701
rtl_pci_flush(struct ieee80211_hw * hw,u32 queues,bool drop)1702 static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
1703 {
1704 struct rtl_priv *rtlpriv = rtl_priv(hw);
1705 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1706 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1707 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1708 u16 i = 0;
1709 int queue_id;
1710 struct rtl8192_tx_ring *ring;
1711
1712 if (mac->skip_scan)
1713 return;
1714
1715 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1716 u32 queue_len;
1717
1718 if (((queues >> queue_id) & 0x1) == 0) {
1719 queue_id--;
1720 continue;
1721 }
1722 ring = &pcipriv->dev.tx_ring[queue_id];
1723 queue_len = skb_queue_len(&ring->queue);
1724 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1725 queue_id == TXCMD_QUEUE) {
1726 queue_id--;
1727 continue;
1728 } else {
1729 msleep(20);
1730 i++;
1731 }
1732
1733 /* we just wait 1s for all queues */
1734 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1735 is_hal_stop(rtlhal) || i >= 200)
1736 return;
1737 }
1738 }
1739
rtl_pci_deinit(struct ieee80211_hw * hw)1740 static void rtl_pci_deinit(struct ieee80211_hw *hw)
1741 {
1742 struct rtl_priv *rtlpriv = rtl_priv(hw);
1743 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1744
1745 _rtl_pci_deinit_trx_ring(hw);
1746
1747 synchronize_irq(rtlpci->pdev->irq);
1748 tasklet_kill(&rtlpriv->works.irq_tasklet);
1749 cancel_work_sync(&rtlpriv->works.lps_change_work);
1750
1751 flush_workqueue(rtlpriv->works.rtl_wq);
1752 destroy_workqueue(rtlpriv->works.rtl_wq);
1753 }
1754
rtl_pci_init(struct ieee80211_hw * hw,struct pci_dev * pdev)1755 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1756 {
1757 int err;
1758
1759 _rtl_pci_init_struct(hw, pdev);
1760
1761 err = _rtl_pci_init_trx_ring(hw);
1762 if (err) {
1763 pr_err("tx ring initialization failed\n");
1764 return err;
1765 }
1766
1767 return 0;
1768 }
1769
rtl_pci_start(struct ieee80211_hw * hw)1770 static int rtl_pci_start(struct ieee80211_hw *hw)
1771 {
1772 struct rtl_priv *rtlpriv = rtl_priv(hw);
1773 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1774 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1775 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1776 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
1777 struct rtl_btc_ops *btc_ops = rtlpriv->btcoexist.btc_ops;
1778
1779 int err;
1780
1781 rtl_pci_reset_trx_ring(hw);
1782
1783 rtlpci->driver_is_goingto_unload = false;
1784 if (rtlpriv->cfg->ops->get_btc_status &&
1785 rtlpriv->cfg->ops->get_btc_status()) {
1786 rtlpriv->btcoexist.btc_info.ap_num = 36;
1787 btc_ops->btc_init_variables(rtlpriv);
1788 btc_ops->btc_init_hal_vars(rtlpriv);
1789 } else if (btc_ops) {
1790 btc_ops->btc_init_variables_wifi_only(rtlpriv);
1791 }
1792
1793 err = rtlpriv->cfg->ops->hw_init(hw);
1794 if (err) {
1795 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1796 "Failed to config hardware!\n");
1797 kfree(rtlpriv->btcoexist.btc_context);
1798 kfree(rtlpriv->btcoexist.wifi_only_context);
1799 return err;
1800 }
1801 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
1802 &rtlmac->retry_long);
1803
1804 rtlpriv->cfg->ops->enable_interrupt(hw);
1805 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
1806
1807 rtl_init_rx_config(hw);
1808
1809 /*should be after adapter start and interrupt enable. */
1810 set_hal_start(rtlhal);
1811
1812 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1813
1814 rtlpci->up_first_time = false;
1815
1816 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__);
1817 return 0;
1818 }
1819
rtl_pci_stop(struct ieee80211_hw * hw)1820 static void rtl_pci_stop(struct ieee80211_hw *hw)
1821 {
1822 struct rtl_priv *rtlpriv = rtl_priv(hw);
1823 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1824 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1825 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1826 unsigned long flags;
1827 u8 rf_timeout = 0;
1828
1829 if (rtlpriv->cfg->ops->get_btc_status())
1830 rtlpriv->btcoexist.btc_ops->btc_halt_notify(rtlpriv);
1831
1832 if (rtlpriv->btcoexist.btc_ops)
1833 rtlpriv->btcoexist.btc_ops->btc_deinit_variables(rtlpriv);
1834
1835 /*should be before disable interrupt&adapter
1836 *and will do it immediately.
1837 */
1838 set_hal_stop(rtlhal);
1839
1840 rtlpci->driver_is_goingto_unload = true;
1841 rtlpriv->cfg->ops->disable_interrupt(hw);
1842 cancel_work_sync(&rtlpriv->works.lps_change_work);
1843
1844 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1845 while (ppsc->rfchange_inprogress) {
1846 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1847 if (rf_timeout > 100) {
1848 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1849 break;
1850 }
1851 mdelay(1);
1852 rf_timeout++;
1853 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1854 }
1855 ppsc->rfchange_inprogress = true;
1856 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1857
1858 rtlpriv->cfg->ops->hw_disable(hw);
1859 /* some things are not needed if firmware not available */
1860 if (!rtlpriv->max_fw_size)
1861 return;
1862 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1863
1864 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1865 ppsc->rfchange_inprogress = false;
1866 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1867
1868 rtl_pci_enable_aspm(hw);
1869 }
1870
_rtl_pci_find_adapter(struct pci_dev * pdev,struct ieee80211_hw * hw)1871 static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1872 struct ieee80211_hw *hw)
1873 {
1874 struct rtl_priv *rtlpriv = rtl_priv(hw);
1875 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1876 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1877 struct pci_dev *bridge_pdev = pdev->bus->self;
1878 u16 venderid;
1879 u16 deviceid;
1880 u8 revisionid;
1881 u16 irqline;
1882 u8 tmp;
1883
1884 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1885 venderid = pdev->vendor;
1886 deviceid = pdev->device;
1887 pci_read_config_byte(pdev, 0x8, &revisionid);
1888 pci_read_config_word(pdev, 0x3C, &irqline);
1889
1890 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1891 * r8192e_pci, and RTL8192SE, which uses this driver. If the
1892 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1893 * the correct driver is r8192e_pci, thus this routine should
1894 * return false.
1895 */
1896 if (deviceid == RTL_PCI_8192SE_DID &&
1897 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1898 return false;
1899
1900 if (deviceid == RTL_PCI_8192_DID ||
1901 deviceid == RTL_PCI_0044_DID ||
1902 deviceid == RTL_PCI_0047_DID ||
1903 deviceid == RTL_PCI_8192SE_DID ||
1904 deviceid == RTL_PCI_8174_DID ||
1905 deviceid == RTL_PCI_8173_DID ||
1906 deviceid == RTL_PCI_8172_DID ||
1907 deviceid == RTL_PCI_8171_DID) {
1908 switch (revisionid) {
1909 case RTL_PCI_REVISION_ID_8192PCIE:
1910 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1911 "8192 PCI-E is found - vid/did=%x/%x\n",
1912 venderid, deviceid);
1913 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1914 return false;
1915 case RTL_PCI_REVISION_ID_8192SE:
1916 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1917 "8192SE is found - vid/did=%x/%x\n",
1918 venderid, deviceid);
1919 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1920 break;
1921 default:
1922 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1923 "Err: Unknown device - vid/did=%x/%x\n",
1924 venderid, deviceid);
1925 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1926 break;
1927 }
1928 } else if (deviceid == RTL_PCI_8723AE_DID) {
1929 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
1930 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1931 "8723AE PCI-E is found - vid/did=%x/%x\n",
1932 venderid, deviceid);
1933 } else if (deviceid == RTL_PCI_8192CET_DID ||
1934 deviceid == RTL_PCI_8192CE_DID ||
1935 deviceid == RTL_PCI_8191CE_DID ||
1936 deviceid == RTL_PCI_8188CE_DID) {
1937 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1938 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1939 "8192C PCI-E is found - vid/did=%x/%x\n",
1940 venderid, deviceid);
1941 } else if (deviceid == RTL_PCI_8192DE_DID ||
1942 deviceid == RTL_PCI_8192DE_DID2) {
1943 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1944 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1945 "8192D PCI-E is found - vid/did=%x/%x\n",
1946 venderid, deviceid);
1947 } else if (deviceid == RTL_PCI_8188EE_DID) {
1948 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE;
1949 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1950 "Find adapter, Hardware type is 8188EE\n");
1951 } else if (deviceid == RTL_PCI_8723BE_DID) {
1952 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE;
1953 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1954 "Find adapter, Hardware type is 8723BE\n");
1955 } else if (deviceid == RTL_PCI_8192EE_DID) {
1956 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE;
1957 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1958 "Find adapter, Hardware type is 8192EE\n");
1959 } else if (deviceid == RTL_PCI_8821AE_DID) {
1960 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE;
1961 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1962 "Find adapter, Hardware type is 8821AE\n");
1963 } else if (deviceid == RTL_PCI_8812AE_DID) {
1964 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE;
1965 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1966 "Find adapter, Hardware type is 8812AE\n");
1967 } else if (deviceid == RTL_PCI_8822BE_DID) {
1968 rtlhal->hw_type = HARDWARE_TYPE_RTL8822BE;
1969 rtlhal->bandset = BAND_ON_BOTH;
1970 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1971 "Find adapter, Hardware type is 8822BE\n");
1972 } else {
1973 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1974 "Err: Unknown device - vid/did=%x/%x\n",
1975 venderid, deviceid);
1976
1977 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1978 }
1979
1980 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1981 if (revisionid == 0 || revisionid == 1) {
1982 if (revisionid == 0) {
1983 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1984 "Find 92DE MAC0\n");
1985 rtlhal->interfaceindex = 0;
1986 } else if (revisionid == 1) {
1987 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1988 "Find 92DE MAC1\n");
1989 rtlhal->interfaceindex = 1;
1990 }
1991 } else {
1992 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1993 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
1994 venderid, deviceid, revisionid);
1995 rtlhal->interfaceindex = 0;
1996 }
1997 }
1998
1999 switch (rtlhal->hw_type) {
2000 case HARDWARE_TYPE_RTL8192EE:
2001 case HARDWARE_TYPE_RTL8822BE:
2002 /* use new trx flow */
2003 rtlpriv->use_new_trx_flow = true;
2004 break;
2005
2006 default:
2007 rtlpriv->use_new_trx_flow = false;
2008 break;
2009 }
2010
2011 /*find bus info */
2012 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
2013 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
2014 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
2015
2016 /*find bridge info */
2017 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
2018 /* some ARM have no bridge_pdev and will crash here
2019 * so we should check if bridge_pdev is NULL
2020 */
2021 if (bridge_pdev) {
2022 /*find bridge info if available */
2023 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
2024 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
2025 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
2026 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
2027 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2028 "Pci Bridge Vendor is found index: %d\n",
2029 tmp);
2030 break;
2031 }
2032 }
2033 }
2034
2035 if (pcipriv->ndis_adapter.pcibridge_vendor !=
2036 PCI_BRIDGE_VENDOR_UNKNOWN) {
2037 pcipriv->ndis_adapter.pcibridge_busnum =
2038 bridge_pdev->bus->number;
2039 pcipriv->ndis_adapter.pcibridge_devnum =
2040 PCI_SLOT(bridge_pdev->devfn);
2041 pcipriv->ndis_adapter.pcibridge_funcnum =
2042 PCI_FUNC(bridge_pdev->devfn);
2043 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
2044 pci_pcie_cap(bridge_pdev);
2045 pcipriv->ndis_adapter.num4bytes =
2046 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
2047
2048 rtl_pci_get_linkcontrol_field(hw);
2049
2050 if (pcipriv->ndis_adapter.pcibridge_vendor ==
2051 PCI_BRIDGE_VENDOR_AMD) {
2052 pcipriv->ndis_adapter.amd_l1_patch =
2053 rtl_pci_get_amd_l1_patch(hw);
2054 }
2055 }
2056
2057 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2058 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
2059 pcipriv->ndis_adapter.busnumber,
2060 pcipriv->ndis_adapter.devnumber,
2061 pcipriv->ndis_adapter.funcnumber,
2062 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
2063
2064 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2065 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
2066 pcipriv->ndis_adapter.pcibridge_busnum,
2067 pcipriv->ndis_adapter.pcibridge_devnum,
2068 pcipriv->ndis_adapter.pcibridge_funcnum,
2069 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
2070 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
2071 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
2072 pcipriv->ndis_adapter.amd_l1_patch);
2073
2074 rtl_pci_parse_configuration(pdev, hw);
2075 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list);
2076
2077 return true;
2078 }
2079
rtl_pci_intr_mode_msi(struct ieee80211_hw * hw)2080 static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw)
2081 {
2082 struct rtl_priv *rtlpriv = rtl_priv(hw);
2083 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2084 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2085 int ret;
2086
2087 ret = pci_enable_msi(rtlpci->pdev);
2088 if (ret < 0)
2089 return ret;
2090
2091 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2092 IRQF_SHARED, KBUILD_MODNAME, hw);
2093 if (ret < 0) {
2094 pci_disable_msi(rtlpci->pdev);
2095 return ret;
2096 }
2097
2098 rtlpci->using_msi = true;
2099
2100 RT_TRACE(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2101 "MSI Interrupt Mode!\n");
2102 return 0;
2103 }
2104
rtl_pci_intr_mode_legacy(struct ieee80211_hw * hw)2105 static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw)
2106 {
2107 struct rtl_priv *rtlpriv = rtl_priv(hw);
2108 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2109 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2110 int ret;
2111
2112 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2113 IRQF_SHARED, KBUILD_MODNAME, hw);
2114 if (ret < 0)
2115 return ret;
2116
2117 rtlpci->using_msi = false;
2118 RT_TRACE(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2119 "Pin-based Interrupt Mode!\n");
2120 return 0;
2121 }
2122
rtl_pci_intr_mode_decide(struct ieee80211_hw * hw)2123 static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw)
2124 {
2125 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2126 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2127 int ret;
2128
2129 if (rtlpci->msi_support) {
2130 ret = rtl_pci_intr_mode_msi(hw);
2131 if (ret < 0)
2132 ret = rtl_pci_intr_mode_legacy(hw);
2133 } else {
2134 ret = rtl_pci_intr_mode_legacy(hw);
2135 }
2136 return ret;
2137 }
2138
platform_enable_dma64(struct pci_dev * pdev,bool dma64)2139 static void platform_enable_dma64(struct pci_dev *pdev, bool dma64)
2140 {
2141 u8 value;
2142
2143 pci_read_config_byte(pdev, 0x719, &value);
2144
2145 /* 0x719 Bit5 is DMA64 bit fetch. */
2146 if (dma64)
2147 value |= BIT(5);
2148 else
2149 value &= ~BIT(5);
2150
2151 pci_write_config_byte(pdev, 0x719, value);
2152 }
2153
rtl_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)2154 int rtl_pci_probe(struct pci_dev *pdev,
2155 const struct pci_device_id *id)
2156 {
2157 struct ieee80211_hw *hw = NULL;
2158
2159 struct rtl_priv *rtlpriv = NULL;
2160 struct rtl_pci_priv *pcipriv = NULL;
2161 struct rtl_pci *rtlpci;
2162 unsigned long pmem_start, pmem_len, pmem_flags;
2163 int err;
2164
2165 err = pci_enable_device(pdev);
2166 if (err) {
2167 WARN_ONCE(true, "%s : Cannot enable new PCI device\n",
2168 pci_name(pdev));
2169 return err;
2170 }
2171
2172 if (((struct rtl_hal_cfg *)id->driver_data)->mod_params->dma64 &&
2173 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
2174 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2175 WARN_ONCE(true,
2176 "Unable to obtain 64bit DMA for consistent allocations\n");
2177 err = -ENOMEM;
2178 goto fail1;
2179 }
2180
2181 platform_enable_dma64(pdev, true);
2182 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
2183 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
2184 WARN_ONCE(true,
2185 "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n");
2186 err = -ENOMEM;
2187 goto fail1;
2188 }
2189
2190 platform_enable_dma64(pdev, false);
2191 }
2192
2193 pci_set_master(pdev);
2194
2195 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
2196 sizeof(struct rtl_priv), &rtl_ops);
2197 if (!hw) {
2198 WARN_ONCE(true,
2199 "%s : ieee80211 alloc failed\n", pci_name(pdev));
2200 err = -ENOMEM;
2201 goto fail1;
2202 }
2203
2204 SET_IEEE80211_DEV(hw, &pdev->dev);
2205 pci_set_drvdata(pdev, hw);
2206
2207 rtlpriv = hw->priv;
2208 rtlpriv->hw = hw;
2209 pcipriv = (void *)rtlpriv->priv;
2210 pcipriv->dev.pdev = pdev;
2211 init_completion(&rtlpriv->firmware_loading_complete);
2212 /*proximity init here*/
2213 rtlpriv->proximity.proxim_on = false;
2214
2215 pcipriv = (void *)rtlpriv->priv;
2216 pcipriv->dev.pdev = pdev;
2217
2218 /* init cfg & intf_ops */
2219 rtlpriv->rtlhal.interface = INTF_PCI;
2220 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
2221 rtlpriv->intf_ops = &rtl_pci_ops;
2222 rtlpriv->glb_var = &rtl_global_var;
2223 rtl_efuse_ops_init(hw);
2224
2225 /* MEM map */
2226 err = pci_request_regions(pdev, KBUILD_MODNAME);
2227 if (err) {
2228 WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n");
2229 goto fail1;
2230 }
2231
2232 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
2233 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
2234 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
2235
2236 /*shared mem start */
2237 rtlpriv->io.pci_mem_start =
2238 (unsigned long)pci_iomap(pdev,
2239 rtlpriv->cfg->bar_id, pmem_len);
2240 if (rtlpriv->io.pci_mem_start == 0) {
2241 WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n");
2242 err = -ENOMEM;
2243 goto fail2;
2244 }
2245
2246 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2247 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
2248 pmem_start, pmem_len, pmem_flags,
2249 rtlpriv->io.pci_mem_start);
2250
2251 /* Disable Clk Request */
2252 pci_write_config_byte(pdev, 0x81, 0);
2253 /* leave D3 mode */
2254 pci_write_config_byte(pdev, 0x44, 0);
2255 pci_write_config_byte(pdev, 0x04, 0x06);
2256 pci_write_config_byte(pdev, 0x04, 0x07);
2257
2258 /* find adapter */
2259 if (!_rtl_pci_find_adapter(pdev, hw)) {
2260 err = -ENODEV;
2261 goto fail2;
2262 }
2263
2264 /* Init IO handler */
2265 _rtl_pci_io_handler_init(&pdev->dev, hw);
2266
2267 /*like read eeprom and so on */
2268 rtlpriv->cfg->ops->read_eeprom_info(hw);
2269
2270 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
2271 pr_err("Can't init_sw_vars\n");
2272 err = -ENODEV;
2273 goto fail3;
2274 }
2275 rtlpriv->cfg->ops->init_sw_leds(hw);
2276
2277 /*aspm */
2278 rtl_pci_init_aspm(hw);
2279
2280 /* Init mac80211 sw */
2281 err = rtl_init_core(hw);
2282 if (err) {
2283 pr_err("Can't allocate sw for mac80211\n");
2284 goto fail3;
2285 }
2286
2287 /* Init PCI sw */
2288 err = rtl_pci_init(hw, pdev);
2289 if (err) {
2290 pr_err("Failed to init PCI\n");
2291 goto fail3;
2292 }
2293
2294 err = ieee80211_register_hw(hw);
2295 if (err) {
2296 pr_err("Can't register mac80211 hw.\n");
2297 err = -ENODEV;
2298 goto fail3;
2299 }
2300 rtlpriv->mac80211.mac80211_registered = 1;
2301
2302 /* add for debug */
2303 rtl_debug_add_one(hw);
2304
2305 /*init rfkill */
2306 rtl_init_rfkill(hw); /* Init PCI sw */
2307
2308 rtlpci = rtl_pcidev(pcipriv);
2309 err = rtl_pci_intr_mode_decide(hw);
2310 if (err) {
2311 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2312 "%s: failed to register IRQ handler\n",
2313 wiphy_name(hw->wiphy));
2314 goto fail3;
2315 }
2316 rtlpci->irq_alloc = 1;
2317
2318 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2319 return 0;
2320
2321 fail3:
2322 pci_set_drvdata(pdev, NULL);
2323 rtl_deinit_core(hw);
2324
2325 fail2:
2326 if (rtlpriv->io.pci_mem_start != 0)
2327 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2328
2329 pci_release_regions(pdev);
2330 complete(&rtlpriv->firmware_loading_complete);
2331
2332 fail1:
2333 if (hw)
2334 ieee80211_free_hw(hw);
2335 pci_disable_device(pdev);
2336
2337 return err;
2338 }
2339 EXPORT_SYMBOL(rtl_pci_probe);
2340
rtl_pci_disconnect(struct pci_dev * pdev)2341 void rtl_pci_disconnect(struct pci_dev *pdev)
2342 {
2343 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2344 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2345 struct rtl_priv *rtlpriv = rtl_priv(hw);
2346 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2347 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
2348
2349 /* just in case driver is removed before firmware callback */
2350 wait_for_completion(&rtlpriv->firmware_loading_complete);
2351 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2352
2353 /* remove form debug */
2354 rtl_debug_remove_one(hw);
2355
2356 /*ieee80211_unregister_hw will call ops_stop */
2357 if (rtlmac->mac80211_registered == 1) {
2358 ieee80211_unregister_hw(hw);
2359 rtlmac->mac80211_registered = 0;
2360 } else {
2361 rtl_deinit_deferred_work(hw, false);
2362 rtlpriv->intf_ops->adapter_stop(hw);
2363 }
2364 rtlpriv->cfg->ops->disable_interrupt(hw);
2365
2366 /*deinit rfkill */
2367 rtl_deinit_rfkill(hw);
2368
2369 rtl_pci_deinit(hw);
2370 rtl_deinit_core(hw);
2371 rtlpriv->cfg->ops->deinit_sw_vars(hw);
2372
2373 if (rtlpci->irq_alloc) {
2374 free_irq(rtlpci->pdev->irq, hw);
2375 rtlpci->irq_alloc = 0;
2376 }
2377
2378 if (rtlpci->using_msi)
2379 pci_disable_msi(rtlpci->pdev);
2380
2381 list_del(&rtlpriv->list);
2382 if (rtlpriv->io.pci_mem_start != 0) {
2383 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2384 pci_release_regions(pdev);
2385 }
2386
2387 pci_disable_device(pdev);
2388
2389 rtl_pci_disable_aspm(hw);
2390
2391 pci_set_drvdata(pdev, NULL);
2392
2393 ieee80211_free_hw(hw);
2394 }
2395 EXPORT_SYMBOL(rtl_pci_disconnect);
2396
2397 #ifdef CONFIG_PM_SLEEP
2398 /***************************************
2399 * kernel pci power state define:
2400 * PCI_D0 ((pci_power_t __force) 0)
2401 * PCI_D1 ((pci_power_t __force) 1)
2402 * PCI_D2 ((pci_power_t __force) 2)
2403 * PCI_D3hot ((pci_power_t __force) 3)
2404 * PCI_D3cold ((pci_power_t __force) 4)
2405 * PCI_UNKNOWN ((pci_power_t __force) 5)
2406
2407 * This function is called when system
2408 * goes into suspend state mac80211 will
2409 * call rtl_mac_stop() from the mac80211
2410 * suspend function first, So there is
2411 * no need to call hw_disable here.
2412 ****************************************/
rtl_pci_suspend(struct device * dev)2413 int rtl_pci_suspend(struct device *dev)
2414 {
2415 struct ieee80211_hw *hw = dev_get_drvdata(dev);
2416 struct rtl_priv *rtlpriv = rtl_priv(hw);
2417
2418 rtlpriv->cfg->ops->hw_suspend(hw);
2419 rtl_deinit_rfkill(hw);
2420
2421 return 0;
2422 }
2423 EXPORT_SYMBOL(rtl_pci_suspend);
2424
rtl_pci_resume(struct device * dev)2425 int rtl_pci_resume(struct device *dev)
2426 {
2427 struct ieee80211_hw *hw = dev_get_drvdata(dev);
2428 struct rtl_priv *rtlpriv = rtl_priv(hw);
2429
2430 rtlpriv->cfg->ops->hw_resume(hw);
2431 rtl_init_rfkill(hw);
2432 return 0;
2433 }
2434 EXPORT_SYMBOL(rtl_pci_resume);
2435 #endif /* CONFIG_PM_SLEEP */
2436
2437 const struct rtl_intf_ops rtl_pci_ops = {
2438 .read_efuse_byte = read_efuse_byte,
2439 .adapter_start = rtl_pci_start,
2440 .adapter_stop = rtl_pci_stop,
2441 .check_buddy_priv = rtl_pci_check_buddy_priv,
2442 .adapter_tx = rtl_pci_tx,
2443 .flush = rtl_pci_flush,
2444 .reset_trx_ring = rtl_pci_reset_trx_ring,
2445 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
2446
2447 .disable_aspm = rtl_pci_disable_aspm,
2448 .enable_aspm = rtl_pci_enable_aspm,
2449 };
2450
