1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
3
4 #include "../wifi.h"
5 #include "../pci.h"
6 #include "../ps.h"
7 #include "../core.h"
8 #include "reg.h"
9 #include "def.h"
10 #include "phy.h"
11 #include "rf.h"
12 #include "dm.h"
13 #include "fw.h"
14 #include "hw.h"
15 #include "table.h"
16
_rtl92s_phy_calculate_bit_shift(u32 bitmask)17 static u32 _rtl92s_phy_calculate_bit_shift(u32 bitmask)
18 {
19 u32 i = ffs(bitmask);
20
21 return i ? i - 1 : 32;
22 }
23
rtl92s_phy_query_bb_reg(struct ieee80211_hw * hw,u32 regaddr,u32 bitmask)24 u32 rtl92s_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
25 {
26 struct rtl_priv *rtlpriv = rtl_priv(hw);
27 u32 returnvalue = 0, originalvalue, bitshift;
28
29 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
30 regaddr, bitmask);
31
32 originalvalue = rtl_read_dword(rtlpriv, regaddr);
33 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
34 returnvalue = (originalvalue & bitmask) >> bitshift;
35
36 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
37 bitmask, regaddr, originalvalue);
38
39 return returnvalue;
40
41 }
42
rtl92s_phy_set_bb_reg(struct ieee80211_hw * hw,u32 regaddr,u32 bitmask,u32 data)43 void rtl92s_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
44 u32 data)
45 {
46 struct rtl_priv *rtlpriv = rtl_priv(hw);
47 u32 originalvalue, bitshift;
48
49 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
50 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
51 regaddr, bitmask, data);
52
53 if (bitmask != MASKDWORD) {
54 originalvalue = rtl_read_dword(rtlpriv, regaddr);
55 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
56 data = ((originalvalue & (~bitmask)) | (data << bitshift));
57 }
58
59 rtl_write_dword(rtlpriv, regaddr, data);
60
61 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
62 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
63 regaddr, bitmask, data);
64
65 }
66
_rtl92s_phy_rf_serial_read(struct ieee80211_hw * hw,enum radio_path rfpath,u32 offset)67 static u32 _rtl92s_phy_rf_serial_read(struct ieee80211_hw *hw,
68 enum radio_path rfpath, u32 offset)
69 {
70
71 struct rtl_priv *rtlpriv = rtl_priv(hw);
72 struct rtl_phy *rtlphy = &(rtlpriv->phy);
73 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
74 u32 newoffset;
75 u32 tmplong, tmplong2;
76 u8 rfpi_enable = 0;
77 u32 retvalue = 0;
78
79 offset &= 0x3f;
80 newoffset = offset;
81
82 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
83
84 if (rfpath == RF90_PATH_A)
85 tmplong2 = tmplong;
86 else
87 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
88
89 tmplong2 = (tmplong2 & (~BLSSI_READADDRESS)) | (newoffset << 23) |
90 BLSSI_READEDGE;
91
92 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
93 tmplong & (~BLSSI_READEDGE));
94
95 mdelay(1);
96
97 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
98 mdelay(1);
99
100 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, tmplong |
101 BLSSI_READEDGE);
102 mdelay(1);
103
104 if (rfpath == RF90_PATH_A)
105 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
106 BIT(8));
107 else if (rfpath == RF90_PATH_B)
108 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
109 BIT(8));
110
111 if (rfpi_enable)
112 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
113 BLSSI_READBACK_DATA);
114 else
115 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
116 BLSSI_READBACK_DATA);
117
118 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n",
119 rfpath, pphyreg->rf_rb, retvalue);
120
121 return retvalue;
122
123 }
124
_rtl92s_phy_rf_serial_write(struct ieee80211_hw * hw,enum radio_path rfpath,u32 offset,u32 data)125 static void _rtl92s_phy_rf_serial_write(struct ieee80211_hw *hw,
126 enum radio_path rfpath, u32 offset,
127 u32 data)
128 {
129 struct rtl_priv *rtlpriv = rtl_priv(hw);
130 struct rtl_phy *rtlphy = &(rtlpriv->phy);
131 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
132 u32 data_and_addr = 0;
133 u32 newoffset;
134
135 offset &= 0x3f;
136 newoffset = offset;
137
138 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
139 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
140
141 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
142 rfpath, pphyreg->rf3wire_offset, data_and_addr);
143 }
144
145
rtl92s_phy_query_rf_reg(struct ieee80211_hw * hw,enum radio_path rfpath,u32 regaddr,u32 bitmask)146 u32 rtl92s_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
147 u32 regaddr, u32 bitmask)
148 {
149 struct rtl_priv *rtlpriv = rtl_priv(hw);
150 u32 original_value, readback_value, bitshift;
151
152 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
153 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
154 regaddr, rfpath, bitmask);
155
156 spin_lock(&rtlpriv->locks.rf_lock);
157
158 original_value = _rtl92s_phy_rf_serial_read(hw, rfpath, regaddr);
159
160 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
161 readback_value = (original_value & bitmask) >> bitshift;
162
163 spin_unlock(&rtlpriv->locks.rf_lock);
164
165 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
166 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
167 regaddr, rfpath, bitmask, original_value);
168
169 return readback_value;
170 }
171
rtl92s_phy_set_rf_reg(struct ieee80211_hw * hw,enum radio_path rfpath,u32 regaddr,u32 bitmask,u32 data)172 void rtl92s_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
173 u32 regaddr, u32 bitmask, u32 data)
174 {
175 struct rtl_priv *rtlpriv = rtl_priv(hw);
176 struct rtl_phy *rtlphy = &(rtlpriv->phy);
177 u32 original_value, bitshift;
178
179 if (!((rtlphy->rf_pathmap >> rfpath) & 0x1))
180 return;
181
182 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
183 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
184 regaddr, bitmask, data, rfpath);
185
186 spin_lock(&rtlpriv->locks.rf_lock);
187
188 if (bitmask != RFREG_OFFSET_MASK) {
189 original_value = _rtl92s_phy_rf_serial_read(hw, rfpath,
190 regaddr);
191 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
192 data = ((original_value & (~bitmask)) | (data << bitshift));
193 }
194
195 _rtl92s_phy_rf_serial_write(hw, rfpath, regaddr, data);
196
197 spin_unlock(&rtlpriv->locks.rf_lock);
198
199 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE,
200 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
201 regaddr, bitmask, data, rfpath);
202
203 }
204
rtl92s_phy_scan_operation_backup(struct ieee80211_hw * hw,u8 operation)205 void rtl92s_phy_scan_operation_backup(struct ieee80211_hw *hw,
206 u8 operation)
207 {
208 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
209
210 if (!is_hal_stop(rtlhal)) {
211 switch (operation) {
212 case SCAN_OPT_BACKUP:
213 rtl92s_phy_set_fw_cmd(hw, FW_CMD_PAUSE_DM_BY_SCAN);
214 break;
215 case SCAN_OPT_RESTORE:
216 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RESUME_DM_BY_SCAN);
217 break;
218 default:
219 pr_err("Unknown operation\n");
220 break;
221 }
222 }
223 }
224
rtl92s_phy_set_bw_mode(struct ieee80211_hw * hw,enum nl80211_channel_type ch_type)225 void rtl92s_phy_set_bw_mode(struct ieee80211_hw *hw,
226 enum nl80211_channel_type ch_type)
227 {
228 struct rtl_priv *rtlpriv = rtl_priv(hw);
229 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
230 struct rtl_phy *rtlphy = &(rtlpriv->phy);
231 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
232 u8 reg_bw_opmode;
233
234 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
235 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
236 "20MHz" : "40MHz");
237
238 if (rtlphy->set_bwmode_inprogress)
239 return;
240 if (is_hal_stop(rtlhal))
241 return;
242
243 rtlphy->set_bwmode_inprogress = true;
244
245 reg_bw_opmode = rtl_read_byte(rtlpriv, BW_OPMODE);
246 /* dummy read */
247 rtl_read_byte(rtlpriv, RRSR + 2);
248
249 switch (rtlphy->current_chan_bw) {
250 case HT_CHANNEL_WIDTH_20:
251 reg_bw_opmode |= BW_OPMODE_20MHZ;
252 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
253 break;
254 case HT_CHANNEL_WIDTH_20_40:
255 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
256 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
257 break;
258 default:
259 pr_err("unknown bandwidth: %#X\n",
260 rtlphy->current_chan_bw);
261 break;
262 }
263
264 switch (rtlphy->current_chan_bw) {
265 case HT_CHANNEL_WIDTH_20:
266 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
267 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
268
269 if (rtlhal->version >= VERSION_8192S_BCUT)
270 rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x58);
271 break;
272 case HT_CHANNEL_WIDTH_20_40:
273 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
274 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
275
276 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
277 (mac->cur_40_prime_sc >> 1));
278 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
279
280 if (rtlhal->version >= VERSION_8192S_BCUT)
281 rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x18);
282 break;
283 default:
284 pr_err("unknown bandwidth: %#X\n",
285 rtlphy->current_chan_bw);
286 break;
287 }
288
289 rtl92s_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
290 rtlphy->set_bwmode_inprogress = false;
291 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
292 }
293
_rtl92s_phy_set_sw_chnl_cmdarray(struct swchnlcmd * cmdtable,u32 cmdtableidx,u32 cmdtablesz,enum swchnlcmd_id cmdid,u32 para1,u32 para2,u32 msdelay)294 static bool _rtl92s_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
295 u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid,
296 u32 para1, u32 para2, u32 msdelay)
297 {
298 struct swchnlcmd *pcmd;
299
300 if (cmdtable == NULL) {
301 WARN_ONCE(true, "rtl8192se: cmdtable cannot be NULL\n");
302 return false;
303 }
304
305 if (cmdtableidx >= cmdtablesz)
306 return false;
307
308 pcmd = cmdtable + cmdtableidx;
309 pcmd->cmdid = cmdid;
310 pcmd->para1 = para1;
311 pcmd->para2 = para2;
312 pcmd->msdelay = msdelay;
313
314 return true;
315 }
316
_rtl92s_phy_sw_chnl_step_by_step(struct ieee80211_hw * hw,u8 channel,u8 * stage,u8 * step,u32 * delay)317 static bool _rtl92s_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
318 u8 channel, u8 *stage, u8 *step, u32 *delay)
319 {
320 struct rtl_priv *rtlpriv = rtl_priv(hw);
321 struct rtl_phy *rtlphy = &(rtlpriv->phy);
322 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
323 u32 precommoncmdcnt;
324 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
325 u32 postcommoncmdcnt;
326 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
327 u32 rfdependcmdcnt;
328 struct swchnlcmd *currentcmd = NULL;
329 u8 rfpath;
330 u8 num_total_rfpath = rtlphy->num_total_rfpath;
331
332 precommoncmdcnt = 0;
333 _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
334 MAX_PRECMD_CNT, CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
335 _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
336 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
337
338 postcommoncmdcnt = 0;
339
340 _rtl92s_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
341 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
342
343 rfdependcmdcnt = 0;
344
345 WARN_ONCE((channel < 1 || channel > 14),
346 "rtl8192se: invalid channel for Zebra: %d\n", channel);
347
348 _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
349 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
350 RF_CHNLBW, channel, 10);
351
352 _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
353 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, 0);
354
355 do {
356 switch (*stage) {
357 case 0:
358 currentcmd = &precommoncmd[*step];
359 break;
360 case 1:
361 currentcmd = &rfdependcmd[*step];
362 break;
363 case 2:
364 currentcmd = &postcommoncmd[*step];
365 break;
366 default:
367 return true;
368 }
369
370 if (currentcmd->cmdid == CMDID_END) {
371 if ((*stage) == 2) {
372 return true;
373 } else {
374 (*stage)++;
375 (*step) = 0;
376 continue;
377 }
378 }
379
380 switch (currentcmd->cmdid) {
381 case CMDID_SET_TXPOWEROWER_LEVEL:
382 rtl92s_phy_set_txpower(hw, channel);
383 break;
384 case CMDID_WRITEPORT_ULONG:
385 rtl_write_dword(rtlpriv, currentcmd->para1,
386 currentcmd->para2);
387 break;
388 case CMDID_WRITEPORT_USHORT:
389 rtl_write_word(rtlpriv, currentcmd->para1,
390 (u16)currentcmd->para2);
391 break;
392 case CMDID_WRITEPORT_UCHAR:
393 rtl_write_byte(rtlpriv, currentcmd->para1,
394 (u8)currentcmd->para2);
395 break;
396 case CMDID_RF_WRITEREG:
397 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
398 rtlphy->rfreg_chnlval[rfpath] =
399 ((rtlphy->rfreg_chnlval[rfpath] &
400 0xfffffc00) | currentcmd->para2);
401 rtl_set_rfreg(hw, (enum radio_path)rfpath,
402 currentcmd->para1,
403 RFREG_OFFSET_MASK,
404 rtlphy->rfreg_chnlval[rfpath]);
405 }
406 break;
407 default:
408 pr_err("switch case %#x not processed\n",
409 currentcmd->cmdid);
410 break;
411 }
412
413 break;
414 } while (true);
415
416 (*delay) = currentcmd->msdelay;
417 (*step)++;
418 return false;
419 }
420
rtl92s_phy_sw_chnl(struct ieee80211_hw * hw)421 u8 rtl92s_phy_sw_chnl(struct ieee80211_hw *hw)
422 {
423 struct rtl_priv *rtlpriv = rtl_priv(hw);
424 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
425 struct rtl_phy *rtlphy = &(rtlpriv->phy);
426 u32 delay;
427 bool ret;
428
429 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "switch to channel%d\n",
430 rtlphy->current_channel);
431
432 if (rtlphy->sw_chnl_inprogress)
433 return 0;
434
435 if (rtlphy->set_bwmode_inprogress)
436 return 0;
437
438 if (is_hal_stop(rtlhal))
439 return 0;
440
441 rtlphy->sw_chnl_inprogress = true;
442 rtlphy->sw_chnl_stage = 0;
443 rtlphy->sw_chnl_step = 0;
444
445 do {
446 if (!rtlphy->sw_chnl_inprogress)
447 break;
448
449 ret = _rtl92s_phy_sw_chnl_step_by_step(hw,
450 rtlphy->current_channel,
451 &rtlphy->sw_chnl_stage,
452 &rtlphy->sw_chnl_step, &delay);
453 if (!ret) {
454 if (delay > 0)
455 mdelay(delay);
456 else
457 continue;
458 } else {
459 rtlphy->sw_chnl_inprogress = false;
460 }
461 break;
462 } while (true);
463
464 rtlphy->sw_chnl_inprogress = false;
465
466 rtl_dbg(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
467
468 return 1;
469 }
470
_rtl92se_phy_set_rf_sleep(struct ieee80211_hw * hw)471 static void _rtl92se_phy_set_rf_sleep(struct ieee80211_hw *hw)
472 {
473 struct rtl_priv *rtlpriv = rtl_priv(hw);
474 u8 u1btmp;
475
476 u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
477 u1btmp |= BIT(0);
478
479 rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
480 rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
481 rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
482 rtl_write_word(rtlpriv, CMDR, 0x57FC);
483 udelay(100);
484
485 rtl_write_word(rtlpriv, CMDR, 0x77FC);
486 rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
487 udelay(10);
488
489 rtl_write_word(rtlpriv, CMDR, 0x37FC);
490 udelay(10);
491
492 rtl_write_word(rtlpriv, CMDR, 0x77FC);
493 udelay(10);
494
495 rtl_write_word(rtlpriv, CMDR, 0x57FC);
496
497 /* we should chnge GPIO to input mode
498 * this will drop away current about 25mA*/
499 rtl8192se_gpiobit3_cfg_inputmode(hw);
500 }
501
rtl92s_phy_set_rf_power_state(struct ieee80211_hw * hw,enum rf_pwrstate rfpwr_state)502 bool rtl92s_phy_set_rf_power_state(struct ieee80211_hw *hw,
503 enum rf_pwrstate rfpwr_state)
504 {
505 struct rtl_priv *rtlpriv = rtl_priv(hw);
506 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
507 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
508 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
509 bool bresult = true;
510 u8 i, queue_id;
511 struct rtl8192_tx_ring *ring = NULL;
512
513 if (rfpwr_state == ppsc->rfpwr_state)
514 return false;
515
516 switch (rfpwr_state) {
517 case ERFON:{
518 if ((ppsc->rfpwr_state == ERFOFF) &&
519 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
520
521 bool rtstatus;
522 u32 initializecount = 0;
523 do {
524 initializecount++;
525 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
526 "IPS Set eRf nic enable\n");
527 rtstatus = rtl_ps_enable_nic(hw);
528 } while (!rtstatus && (initializecount < 10));
529
530 RT_CLEAR_PS_LEVEL(ppsc,
531 RT_RF_OFF_LEVL_HALT_NIC);
532 } else {
533 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
534 "awake, slept:%d ms state_inap:%x\n",
535 jiffies_to_msecs(jiffies -
536 ppsc->last_sleep_jiffies),
537 rtlpriv->psc.state_inap);
538 ppsc->last_awake_jiffies = jiffies;
539 rtl_write_word(rtlpriv, CMDR, 0x37FC);
540 rtl_write_byte(rtlpriv, TXPAUSE, 0x00);
541 rtl_write_byte(rtlpriv, PHY_CCA, 0x3);
542 }
543
544 if (mac->link_state == MAC80211_LINKED)
545 rtlpriv->cfg->ops->led_control(hw,
546 LED_CTL_LINK);
547 else
548 rtlpriv->cfg->ops->led_control(hw,
549 LED_CTL_NO_LINK);
550 break;
551 }
552 case ERFOFF:{
553 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
554 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
555 "IPS Set eRf nic disable\n");
556 rtl_ps_disable_nic(hw);
557 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
558 } else {
559 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
560 rtlpriv->cfg->ops->led_control(hw,
561 LED_CTL_NO_LINK);
562 else
563 rtlpriv->cfg->ops->led_control(hw,
564 LED_CTL_POWER_OFF);
565 }
566 break;
567 }
568 case ERFSLEEP:
569 if (ppsc->rfpwr_state == ERFOFF)
570 return false;
571
572 for (queue_id = 0, i = 0;
573 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
574 ring = &pcipriv->dev.tx_ring[queue_id];
575 if (skb_queue_len(&ring->queue) == 0 ||
576 queue_id == BEACON_QUEUE) {
577 queue_id++;
578 continue;
579 } else {
580 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
581 "eRf Off/Sleep: %d times TcbBusyQueue[%d] = %d before doze!\n",
582 i + 1, queue_id,
583 skb_queue_len(&ring->queue));
584
585 udelay(10);
586 i++;
587 }
588
589 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
590 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
591 "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
592 MAX_DOZE_WAITING_TIMES_9x,
593 queue_id,
594 skb_queue_len(&ring->queue));
595 break;
596 }
597 }
598
599 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
600 "Set ERFSLEEP awaked:%d ms\n",
601 jiffies_to_msecs(jiffies -
602 ppsc->last_awake_jiffies));
603
604 rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
605 "sleep awaked:%d ms state_inap:%x\n",
606 jiffies_to_msecs(jiffies -
607 ppsc->last_awake_jiffies),
608 rtlpriv->psc.state_inap);
609 ppsc->last_sleep_jiffies = jiffies;
610 _rtl92se_phy_set_rf_sleep(hw);
611 break;
612 default:
613 pr_err("switch case %#x not processed\n",
614 rfpwr_state);
615 bresult = false;
616 break;
617 }
618
619 if (bresult)
620 ppsc->rfpwr_state = rfpwr_state;
621
622 return bresult;
623 }
624
_rtl92s_phy_config_rfpa_bias_current(struct ieee80211_hw * hw,enum radio_path rfpath)625 static bool _rtl92s_phy_config_rfpa_bias_current(struct ieee80211_hw *hw,
626 enum radio_path rfpath)
627 {
628 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
629 bool rtstatus = true;
630 u32 tmpval = 0;
631
632 /* If inferiority IC, we have to increase the PA bias current */
633 if (rtlhal->ic_class != IC_INFERIORITY_A) {
634 tmpval = rtl92s_phy_query_rf_reg(hw, rfpath, RF_IPA, 0xf);
635 rtl92s_phy_set_rf_reg(hw, rfpath, RF_IPA, 0xf, tmpval + 1);
636 }
637
638 return rtstatus;
639 }
640
_rtl92s_store_pwrindex_diffrate_offset(struct ieee80211_hw * hw,u32 reg_addr,u32 bitmask,u32 data)641 static void _rtl92s_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
642 u32 reg_addr, u32 bitmask, u32 data)
643 {
644 struct rtl_priv *rtlpriv = rtl_priv(hw);
645 struct rtl_phy *rtlphy = &(rtlpriv->phy);
646 int index;
647
648 if (reg_addr == RTXAGC_RATE18_06)
649 index = 0;
650 else if (reg_addr == RTXAGC_RATE54_24)
651 index = 1;
652 else if (reg_addr == RTXAGC_CCK_MCS32)
653 index = 6;
654 else if (reg_addr == RTXAGC_MCS03_MCS00)
655 index = 2;
656 else if (reg_addr == RTXAGC_MCS07_MCS04)
657 index = 3;
658 else if (reg_addr == RTXAGC_MCS11_MCS08)
659 index = 4;
660 else if (reg_addr == RTXAGC_MCS15_MCS12)
661 index = 5;
662 else
663 return;
664
665 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data;
666 if (index == 5)
667 rtlphy->pwrgroup_cnt++;
668 }
669
_rtl92s_phy_init_register_definition(struct ieee80211_hw * hw)670 static void _rtl92s_phy_init_register_definition(struct ieee80211_hw *hw)
671 {
672 struct rtl_priv *rtlpriv = rtl_priv(hw);
673 struct rtl_phy *rtlphy = &(rtlpriv->phy);
674
675 /*RF Interface Sowrtware Control */
676 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
677 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
678 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
679 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
680
681 /* RF Interface Readback Value */
682 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
683 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
684 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
685 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
686
687 /* RF Interface Output (and Enable) */
688 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
689 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
690 rtlphy->phyreg_def[RF90_PATH_C].rfintfo = RFPGA0_XC_RFINTERFACEOE;
691 rtlphy->phyreg_def[RF90_PATH_D].rfintfo = RFPGA0_XD_RFINTERFACEOE;
692
693 /* RF Interface (Output and) Enable */
694 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
695 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
696 rtlphy->phyreg_def[RF90_PATH_C].rfintfe = RFPGA0_XC_RFINTERFACEOE;
697 rtlphy->phyreg_def[RF90_PATH_D].rfintfe = RFPGA0_XD_RFINTERFACEOE;
698
699 /* Addr of LSSI. Wirte RF register by driver */
700 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
701 RFPGA0_XA_LSSIPARAMETER;
702 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
703 RFPGA0_XB_LSSIPARAMETER;
704 rtlphy->phyreg_def[RF90_PATH_C].rf3wire_offset =
705 RFPGA0_XC_LSSIPARAMETER;
706 rtlphy->phyreg_def[RF90_PATH_D].rf3wire_offset =
707 RFPGA0_XD_LSSIPARAMETER;
708
709 /* RF parameter */
710 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
711 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
712 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
713 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
714
715 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
716 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
717 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
718 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
719 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
720
721 /* Tranceiver A~D HSSI Parameter-1 */
722 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
723 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
724 rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para1 = RFPGA0_XC_HSSIPARAMETER1;
725 rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para1 = RFPGA0_XD_HSSIPARAMETER1;
726
727 /* Tranceiver A~D HSSI Parameter-2 */
728 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
729 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
730 rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para2 = RFPGA0_XC_HSSIPARAMETER2;
731 rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para2 = RFPGA0_XD_HSSIPARAMETER2;
732
733 /* RF switch Control */
734 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
735 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
736 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
737 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
738
739 /* AGC control 1 */
740 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
741 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
742 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
743 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
744
745 /* AGC control 2 */
746 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
747 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
748 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
749 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
750
751 /* RX AFE control 1 */
752 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
753 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
754 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE;
755 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
756
757 /* RX AFE control 1 */
758 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
759 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
760 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
761 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
762
763 /* Tx AFE control 1 */
764 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
765 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
766 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
767 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
768
769 /* Tx AFE control 2 */
770 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
771 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
772 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
773 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
774
775 /* Tranceiver LSSI Readback */
776 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
777 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
778 rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
779 rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
780
781 /* Tranceiver LSSI Readback PI mode */
782 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK;
783 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK;
784 }
785
786
_rtl92s_phy_config_bb(struct ieee80211_hw * hw,u8 configtype)787 static bool _rtl92s_phy_config_bb(struct ieee80211_hw *hw, u8 configtype)
788 {
789 int i;
790 u32 *phy_reg_table;
791 u32 *agc_table;
792 u16 phy_reg_len, agc_len;
793
794 agc_len = AGCTAB_ARRAYLENGTH;
795 agc_table = rtl8192seagctab_array;
796 /* Default RF_type: 2T2R */
797 phy_reg_len = PHY_REG_2T2RARRAYLENGTH;
798 phy_reg_table = rtl8192sephy_reg_2t2rarray;
799
800 if (configtype == BASEBAND_CONFIG_PHY_REG) {
801 for (i = 0; i < phy_reg_len; i = i + 2) {
802 rtl_addr_delay(phy_reg_table[i]);
803
804 /* Add delay for ECS T20 & LG malow platform, */
805 udelay(1);
806
807 rtl92s_phy_set_bb_reg(hw, phy_reg_table[i], MASKDWORD,
808 phy_reg_table[i + 1]);
809 }
810 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
811 for (i = 0; i < agc_len; i = i + 2) {
812 rtl92s_phy_set_bb_reg(hw, agc_table[i], MASKDWORD,
813 agc_table[i + 1]);
814
815 /* Add delay for ECS T20 & LG malow platform */
816 udelay(1);
817 }
818 }
819
820 return true;
821 }
822
_rtl92s_phy_set_bb_to_diff_rf(struct ieee80211_hw * hw,u8 configtype)823 static bool _rtl92s_phy_set_bb_to_diff_rf(struct ieee80211_hw *hw,
824 u8 configtype)
825 {
826 struct rtl_priv *rtlpriv = rtl_priv(hw);
827 struct rtl_phy *rtlphy = &(rtlpriv->phy);
828 u32 *phy_regarray2xtxr_table;
829 u16 phy_regarray2xtxr_len;
830 int i;
831
832 if (rtlphy->rf_type == RF_1T1R) {
833 phy_regarray2xtxr_table = rtl8192sephy_changeto_1t1rarray;
834 phy_regarray2xtxr_len = PHY_CHANGETO_1T1RARRAYLENGTH;
835 } else if (rtlphy->rf_type == RF_1T2R) {
836 phy_regarray2xtxr_table = rtl8192sephy_changeto_1t2rarray;
837 phy_regarray2xtxr_len = PHY_CHANGETO_1T2RARRAYLENGTH;
838 } else {
839 return false;
840 }
841
842 if (configtype == BASEBAND_CONFIG_PHY_REG) {
843 for (i = 0; i < phy_regarray2xtxr_len; i = i + 3) {
844 rtl_addr_delay(phy_regarray2xtxr_table[i]);
845
846 rtl92s_phy_set_bb_reg(hw, phy_regarray2xtxr_table[i],
847 phy_regarray2xtxr_table[i + 1],
848 phy_regarray2xtxr_table[i + 2]);
849 }
850 }
851
852 return true;
853 }
854
_rtl92s_phy_config_bb_with_pg(struct ieee80211_hw * hw,u8 configtype)855 static bool _rtl92s_phy_config_bb_with_pg(struct ieee80211_hw *hw,
856 u8 configtype)
857 {
858 int i;
859 u32 *phy_table_pg;
860 u16 phy_pg_len;
861
862 phy_pg_len = PHY_REG_ARRAY_PGLENGTH;
863 phy_table_pg = rtl8192sephy_reg_array_pg;
864
865 if (configtype == BASEBAND_CONFIG_PHY_REG) {
866 for (i = 0; i < phy_pg_len; i = i + 3) {
867 rtl_addr_delay(phy_table_pg[i]);
868
869 _rtl92s_store_pwrindex_diffrate_offset(hw,
870 phy_table_pg[i],
871 phy_table_pg[i + 1],
872 phy_table_pg[i + 2]);
873 rtl92s_phy_set_bb_reg(hw, phy_table_pg[i],
874 phy_table_pg[i + 1],
875 phy_table_pg[i + 2]);
876 }
877 }
878
879 return true;
880 }
881
_rtl92s_phy_bb_config_parafile(struct ieee80211_hw * hw)882 static bool _rtl92s_phy_bb_config_parafile(struct ieee80211_hw *hw)
883 {
884 struct rtl_priv *rtlpriv = rtl_priv(hw);
885 struct rtl_phy *rtlphy = &(rtlpriv->phy);
886 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
887 bool rtstatus = true;
888
889 /* 1. Read PHY_REG.TXT BB INIT!! */
890 /* We will separate as 1T1R/1T2R/1T2R_GREEN/2T2R */
891 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_2T2R ||
892 rtlphy->rf_type == RF_1T1R || rtlphy->rf_type == RF_2T2R_GREEN) {
893 rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_PHY_REG);
894
895 if (rtlphy->rf_type != RF_2T2R &&
896 rtlphy->rf_type != RF_2T2R_GREEN)
897 /* so we should reconfig BB reg with the right
898 * PHY parameters. */
899 rtstatus = _rtl92s_phy_set_bb_to_diff_rf(hw,
900 BASEBAND_CONFIG_PHY_REG);
901 } else {
902 rtstatus = false;
903 }
904
905 if (!rtstatus) {
906 pr_err("Write BB Reg Fail!!\n");
907 goto phy_bb8190_config_parafile_fail;
908 }
909
910 /* 2. If EEPROM or EFUSE autoload OK, We must config by
911 * PHY_REG_PG.txt */
912 if (rtlefuse->autoload_failflag == false) {
913 rtlphy->pwrgroup_cnt = 0;
914
915 rtstatus = _rtl92s_phy_config_bb_with_pg(hw,
916 BASEBAND_CONFIG_PHY_REG);
917 }
918 if (!rtstatus) {
919 pr_err("_rtl92s_phy_bb_config_parafile(): BB_PG Reg Fail!!\n");
920 goto phy_bb8190_config_parafile_fail;
921 }
922
923 /* 3. BB AGC table Initialization */
924 rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_AGC_TAB);
925
926 if (!rtstatus) {
927 pr_err("%s(): AGC Table Fail\n", __func__);
928 goto phy_bb8190_config_parafile_fail;
929 }
930
931 /* Check if the CCK HighPower is turned ON. */
932 /* This is used to calculate PWDB. */
933 rtlphy->cck_high_power = (bool)(rtl92s_phy_query_bb_reg(hw,
934 RFPGA0_XA_HSSIPARAMETER2, 0x200));
935
936 phy_bb8190_config_parafile_fail:
937 return rtstatus;
938 }
939
rtl92s_phy_config_rf(struct ieee80211_hw * hw,enum radio_path rfpath)940 u8 rtl92s_phy_config_rf(struct ieee80211_hw *hw, enum radio_path rfpath)
941 {
942 struct rtl_priv *rtlpriv = rtl_priv(hw);
943 struct rtl_phy *rtlphy = &(rtlpriv->phy);
944 int i;
945 bool rtstatus = true;
946 u32 *radio_a_table;
947 u32 *radio_b_table;
948 u16 radio_a_tblen, radio_b_tblen;
949
950 radio_a_tblen = RADIOA_1T_ARRAYLENGTH;
951 radio_a_table = rtl8192seradioa_1t_array;
952
953 /* Using Green mode array table for RF_2T2R_GREEN */
954 if (rtlphy->rf_type == RF_2T2R_GREEN) {
955 radio_b_table = rtl8192seradiob_gm_array;
956 radio_b_tblen = RADIOB_GM_ARRAYLENGTH;
957 } else {
958 radio_b_table = rtl8192seradiob_array;
959 radio_b_tblen = RADIOB_ARRAYLENGTH;
960 }
961
962 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
963 rtstatus = true;
964
965 switch (rfpath) {
966 case RF90_PATH_A:
967 for (i = 0; i < radio_a_tblen; i = i + 2) {
968 rtl_rfreg_delay(hw, rfpath, radio_a_table[i],
969 MASK20BITS, radio_a_table[i + 1]);
970
971 }
972
973 /* PA Bias current for inferiority IC */
974 _rtl92s_phy_config_rfpa_bias_current(hw, rfpath);
975 break;
976 case RF90_PATH_B:
977 for (i = 0; i < radio_b_tblen; i = i + 2) {
978 rtl_rfreg_delay(hw, rfpath, radio_b_table[i],
979 MASK20BITS, radio_b_table[i + 1]);
980 }
981 break;
982 case RF90_PATH_C:
983 ;
984 break;
985 case RF90_PATH_D:
986 ;
987 break;
988 default:
989 break;
990 }
991
992 return rtstatus;
993 }
994
995
rtl92s_phy_mac_config(struct ieee80211_hw * hw)996 bool rtl92s_phy_mac_config(struct ieee80211_hw *hw)
997 {
998 struct rtl_priv *rtlpriv = rtl_priv(hw);
999 u32 i;
1000 u32 arraylength;
1001 u32 *ptrarray;
1002
1003 arraylength = MAC_2T_ARRAYLENGTH;
1004 ptrarray = rtl8192semac_2t_array;
1005
1006 for (i = 0; i < arraylength; i = i + 2)
1007 rtl_write_byte(rtlpriv, ptrarray[i], (u8)ptrarray[i + 1]);
1008
1009 return true;
1010 }
1011
1012
rtl92s_phy_bb_config(struct ieee80211_hw * hw)1013 bool rtl92s_phy_bb_config(struct ieee80211_hw *hw)
1014 {
1015 struct rtl_priv *rtlpriv = rtl_priv(hw);
1016 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1017 bool rtstatus;
1018 u8 pathmap, index, rf_num = 0;
1019 u8 path1, path2;
1020
1021 _rtl92s_phy_init_register_definition(hw);
1022
1023 /* Config BB and AGC */
1024 rtstatus = _rtl92s_phy_bb_config_parafile(hw);
1025
1026
1027 /* Check BB/RF confiuration setting. */
1028 /* We only need to configure RF which is turned on. */
1029 path1 = (u8)(rtl92s_phy_query_bb_reg(hw, RFPGA0_TXINFO, 0xf));
1030 mdelay(10);
1031 path2 = (u8)(rtl92s_phy_query_bb_reg(hw, ROFDM0_TRXPATHENABLE, 0xf));
1032 pathmap = path1 | path2;
1033
1034 rtlphy->rf_pathmap = pathmap;
1035 for (index = 0; index < 4; index++) {
1036 if ((pathmap >> index) & 0x1)
1037 rf_num++;
1038 }
1039
1040 if ((rtlphy->rf_type == RF_1T1R && rf_num != 1) ||
1041 (rtlphy->rf_type == RF_1T2R && rf_num != 2) ||
1042 (rtlphy->rf_type == RF_2T2R && rf_num != 2) ||
1043 (rtlphy->rf_type == RF_2T2R_GREEN && rf_num != 2)) {
1044 pr_err("RF_Type(%x) does not match RF_Num(%x)!!\n",
1045 rtlphy->rf_type, rf_num);
1046 pr_err("path1 0x%x, path2 0x%x, pathmap 0x%x\n",
1047 path1, path2, pathmap);
1048 }
1049
1050 return rtstatus;
1051 }
1052
rtl92s_phy_rf_config(struct ieee80211_hw * hw)1053 bool rtl92s_phy_rf_config(struct ieee80211_hw *hw)
1054 {
1055 struct rtl_priv *rtlpriv = rtl_priv(hw);
1056 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1057
1058 /* Initialize general global value */
1059 if (rtlphy->rf_type == RF_1T1R)
1060 rtlphy->num_total_rfpath = 1;
1061 else
1062 rtlphy->num_total_rfpath = 2;
1063
1064 /* Config BB and RF */
1065 return rtl92s_phy_rf6052_config(hw);
1066 }
1067
rtl92s_phy_get_hw_reg_originalvalue(struct ieee80211_hw * hw)1068 void rtl92s_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
1069 {
1070 struct rtl_priv *rtlpriv = rtl_priv(hw);
1071 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1072
1073 /* read rx initial gain */
1074 rtlphy->default_initialgain[0] = rtl_get_bbreg(hw,
1075 ROFDM0_XAAGCCORE1, MASKBYTE0);
1076 rtlphy->default_initialgain[1] = rtl_get_bbreg(hw,
1077 ROFDM0_XBAGCCORE1, MASKBYTE0);
1078 rtlphy->default_initialgain[2] = rtl_get_bbreg(hw,
1079 ROFDM0_XCAGCCORE1, MASKBYTE0);
1080 rtlphy->default_initialgain[3] = rtl_get_bbreg(hw,
1081 ROFDM0_XDAGCCORE1, MASKBYTE0);
1082 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1083 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
1084 rtlphy->default_initialgain[0],
1085 rtlphy->default_initialgain[1],
1086 rtlphy->default_initialgain[2],
1087 rtlphy->default_initialgain[3]);
1088
1089 /* read framesync */
1090 rtlphy->framesync = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, MASKBYTE0);
1091 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
1092 MASKDWORD);
1093 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1094 "Default framesync (0x%x) = 0x%x\n",
1095 ROFDM0_RXDETECTOR3, rtlphy->framesync);
1096
1097 }
1098
_rtl92s_phy_get_txpower_index(struct ieee80211_hw * hw,u8 channel,u8 * cckpowerlevel,u8 * ofdmpowerlevel)1099 static void _rtl92s_phy_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
1100 u8 *cckpowerlevel, u8 *ofdmpowerlevel)
1101 {
1102 struct rtl_priv *rtlpriv = rtl_priv(hw);
1103 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1104 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1105 u8 index = (channel - 1);
1106
1107 /* 1. CCK */
1108 /* RF-A */
1109 cckpowerlevel[0] = rtlefuse->txpwrlevel_cck[0][index];
1110 /* RF-B */
1111 cckpowerlevel[1] = rtlefuse->txpwrlevel_cck[1][index];
1112
1113 /* 2. OFDM for 1T or 2T */
1114 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {
1115 /* Read HT 40 OFDM TX power */
1116 ofdmpowerlevel[0] = rtlefuse->txpwrlevel_ht40_1s[0][index];
1117 ofdmpowerlevel[1] = rtlefuse->txpwrlevel_ht40_1s[1][index];
1118 } else if (rtlphy->rf_type == RF_2T2R) {
1119 /* Read HT 40 OFDM TX power */
1120 ofdmpowerlevel[0] = rtlefuse->txpwrlevel_ht40_2s[0][index];
1121 ofdmpowerlevel[1] = rtlefuse->txpwrlevel_ht40_2s[1][index];
1122 } else {
1123 ofdmpowerlevel[0] = 0;
1124 ofdmpowerlevel[1] = 0;
1125 }
1126 }
1127
_rtl92s_phy_ccxpower_indexcheck(struct ieee80211_hw * hw,u8 channel,u8 * cckpowerlevel,u8 * ofdmpowerlevel)1128 static void _rtl92s_phy_ccxpower_indexcheck(struct ieee80211_hw *hw,
1129 u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel)
1130 {
1131 struct rtl_priv *rtlpriv = rtl_priv(hw);
1132 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1133
1134 rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
1135 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
1136 }
1137
rtl92s_phy_set_txpower(struct ieee80211_hw * hw,u8 channel)1138 void rtl92s_phy_set_txpower(struct ieee80211_hw *hw, u8 channel)
1139 {
1140 struct rtl_priv *rtlpriv = rtl_priv(hw);
1141 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1142 /* [0]:RF-A, [1]:RF-B */
1143 u8 cckpowerlevel[2], ofdmpowerlevel[2];
1144
1145 if (!rtlefuse->txpwr_fromeprom)
1146 return;
1147
1148 /* Mainly we use RF-A Tx Power to write the Tx Power registers,
1149 * but the RF-B Tx Power must be calculated by the antenna diff.
1150 * So we have to rewrite Antenna gain offset register here.
1151 * Please refer to BB register 0x80c
1152 * 1. For CCK.
1153 * 2. For OFDM 1T or 2T */
1154 _rtl92s_phy_get_txpower_index(hw, channel, &cckpowerlevel[0],
1155 &ofdmpowerlevel[0]);
1156
1157 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
1158 "Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n",
1159 channel, cckpowerlevel[0], cckpowerlevel[1],
1160 ofdmpowerlevel[0], ofdmpowerlevel[1]);
1161
1162 _rtl92s_phy_ccxpower_indexcheck(hw, channel, &cckpowerlevel[0],
1163 &ofdmpowerlevel[0]);
1164
1165 rtl92s_phy_rf6052_set_ccktxpower(hw, cckpowerlevel[0]);
1166 rtl92s_phy_rf6052_set_ofdmtxpower(hw, &ofdmpowerlevel[0], channel);
1167
1168 }
1169
rtl92s_phy_chk_fwcmd_iodone(struct ieee80211_hw * hw)1170 void rtl92s_phy_chk_fwcmd_iodone(struct ieee80211_hw *hw)
1171 {
1172 struct rtl_priv *rtlpriv = rtl_priv(hw);
1173 u16 pollingcnt = 10000;
1174 u32 tmpvalue;
1175
1176 /* Make sure that CMD IO has be accepted by FW. */
1177 do {
1178 udelay(10);
1179
1180 tmpvalue = rtl_read_dword(rtlpriv, WFM5);
1181 if (tmpvalue == 0)
1182 break;
1183 } while (--pollingcnt);
1184
1185 if (pollingcnt == 0)
1186 pr_err("Set FW Cmd fail!!\n");
1187 }
1188
1189
_rtl92s_phy_set_fwcmd_io(struct ieee80211_hw * hw)1190 static void _rtl92s_phy_set_fwcmd_io(struct ieee80211_hw *hw)
1191 {
1192 struct rtl_priv *rtlpriv = rtl_priv(hw);
1193 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1194 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1195 u32 input, current_aid = 0;
1196
1197 if (is_hal_stop(rtlhal))
1198 return;
1199
1200 if (hal_get_firmwareversion(rtlpriv) < 0x34)
1201 goto skip;
1202 /* We re-map RA related CMD IO to combinational ones */
1203 /* if FW version is v.52 or later. */
1204 switch (rtlhal->current_fwcmd_io) {
1205 case FW_CMD_RA_REFRESH_N:
1206 rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_N_COMB;
1207 break;
1208 case FW_CMD_RA_REFRESH_BG:
1209 rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_BG_COMB;
1210 break;
1211 default:
1212 break;
1213 }
1214
1215 skip:
1216 switch (rtlhal->current_fwcmd_io) {
1217 case FW_CMD_RA_RESET:
1218 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_RESET\n");
1219 rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET);
1220 rtl92s_phy_chk_fwcmd_iodone(hw);
1221 break;
1222 case FW_CMD_RA_ACTIVE:
1223 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_ACTIVE\n");
1224 rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE);
1225 rtl92s_phy_chk_fwcmd_iodone(hw);
1226 break;
1227 case FW_CMD_RA_REFRESH_N:
1228 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_REFRESH_N\n");
1229 input = FW_RA_REFRESH;
1230 rtl_write_dword(rtlpriv, WFM5, input);
1231 rtl92s_phy_chk_fwcmd_iodone(hw);
1232 rtl_write_dword(rtlpriv, WFM5, FW_RA_ENABLE_RSSI_MASK);
1233 rtl92s_phy_chk_fwcmd_iodone(hw);
1234 break;
1235 case FW_CMD_RA_REFRESH_BG:
1236 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG,
1237 "FW_CMD_RA_REFRESH_BG\n");
1238 rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH);
1239 rtl92s_phy_chk_fwcmd_iodone(hw);
1240 rtl_write_dword(rtlpriv, WFM5, FW_RA_DISABLE_RSSI_MASK);
1241 rtl92s_phy_chk_fwcmd_iodone(hw);
1242 break;
1243 case FW_CMD_RA_REFRESH_N_COMB:
1244 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG,
1245 "FW_CMD_RA_REFRESH_N_COMB\n");
1246 input = FW_RA_IOT_N_COMB;
1247 rtl_write_dword(rtlpriv, WFM5, input);
1248 rtl92s_phy_chk_fwcmd_iodone(hw);
1249 break;
1250 case FW_CMD_RA_REFRESH_BG_COMB:
1251 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG,
1252 "FW_CMD_RA_REFRESH_BG_COMB\n");
1253 input = FW_RA_IOT_BG_COMB;
1254 rtl_write_dword(rtlpriv, WFM5, input);
1255 rtl92s_phy_chk_fwcmd_iodone(hw);
1256 break;
1257 case FW_CMD_IQK_ENABLE:
1258 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_IQK_ENABLE\n");
1259 rtl_write_dword(rtlpriv, WFM5, FW_IQK_ENABLE);
1260 rtl92s_phy_chk_fwcmd_iodone(hw);
1261 break;
1262 case FW_CMD_PAUSE_DM_BY_SCAN:
1263 /* Lower initial gain */
1264 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17);
1265 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17);
1266 /* CCA threshold */
1267 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);
1268 break;
1269 case FW_CMD_RESUME_DM_BY_SCAN:
1270 /* CCA threshold */
1271 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
1272 rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
1273 break;
1274 case FW_CMD_HIGH_PWR_DISABLE:
1275 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE)
1276 break;
1277
1278 /* Lower initial gain */
1279 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17);
1280 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17);
1281 /* CCA threshold */
1282 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);
1283 break;
1284 case FW_CMD_HIGH_PWR_ENABLE:
1285 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) ||
1286 rtlpriv->dm.dynamic_txpower_enable)
1287 break;
1288
1289 /* CCA threshold */
1290 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
1291 break;
1292 case FW_CMD_LPS_ENTER:
1293 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_ENTER\n");
1294 current_aid = rtlpriv->mac80211.assoc_id;
1295 rtl_write_dword(rtlpriv, WFM5, (FW_LPS_ENTER |
1296 ((current_aid | 0xc000) << 8)));
1297 rtl92s_phy_chk_fwcmd_iodone(hw);
1298 /* FW set TXOP disable here, so disable EDCA
1299 * turbo mode until driver leave LPS */
1300 break;
1301 case FW_CMD_LPS_LEAVE:
1302 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_LEAVE\n");
1303 rtl_write_dword(rtlpriv, WFM5, FW_LPS_LEAVE);
1304 rtl92s_phy_chk_fwcmd_iodone(hw);
1305 break;
1306 case FW_CMD_ADD_A2_ENTRY:
1307 rtl_dbg(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_ADD_A2_ENTRY\n");
1308 rtl_write_dword(rtlpriv, WFM5, FW_ADD_A2_ENTRY);
1309 rtl92s_phy_chk_fwcmd_iodone(hw);
1310 break;
1311 case FW_CMD_CTRL_DM_BY_DRIVER:
1312 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1313 "FW_CMD_CTRL_DM_BY_DRIVER\n");
1314 rtl_write_dword(rtlpriv, WFM5, FW_CTRL_DM_BY_DRIVER);
1315 rtl92s_phy_chk_fwcmd_iodone(hw);
1316 break;
1317
1318 default:
1319 break;
1320 }
1321
1322 rtl92s_phy_chk_fwcmd_iodone(hw);
1323
1324 /* Clear FW CMD operation flag. */
1325 rtlhal->set_fwcmd_inprogress = false;
1326 }
1327
rtl92s_phy_set_fw_cmd(struct ieee80211_hw * hw,enum fwcmd_iotype fw_cmdio)1328 bool rtl92s_phy_set_fw_cmd(struct ieee80211_hw *hw, enum fwcmd_iotype fw_cmdio)
1329 {
1330 struct rtl_priv *rtlpriv = rtl_priv(hw);
1331 struct dig_t *digtable = &rtlpriv->dm_digtable;
1332 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1333 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1334 u32 fw_param = FW_CMD_IO_PARA_QUERY(rtlpriv);
1335 u16 fw_cmdmap = FW_CMD_IO_QUERY(rtlpriv);
1336 bool postprocessing = false;
1337
1338 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1339 "Set FW Cmd(%#x), set_fwcmd_inprogress(%d)\n",
1340 fw_cmdio, rtlhal->set_fwcmd_inprogress);
1341
1342 do {
1343 /* We re-map to combined FW CMD ones if firmware version */
1344 /* is v.53 or later. */
1345 if (hal_get_firmwareversion(rtlpriv) >= 0x35) {
1346 switch (fw_cmdio) {
1347 case FW_CMD_RA_REFRESH_N:
1348 fw_cmdio = FW_CMD_RA_REFRESH_N_COMB;
1349 break;
1350 case FW_CMD_RA_REFRESH_BG:
1351 fw_cmdio = FW_CMD_RA_REFRESH_BG_COMB;
1352 break;
1353 default:
1354 break;
1355 }
1356 } else {
1357 if ((fw_cmdio == FW_CMD_IQK_ENABLE) ||
1358 (fw_cmdio == FW_CMD_RA_REFRESH_N) ||
1359 (fw_cmdio == FW_CMD_RA_REFRESH_BG)) {
1360 postprocessing = true;
1361 break;
1362 }
1363 }
1364
1365 /* If firmware version is v.62 or later,
1366 * use FW_CMD_IO_SET for FW_CMD_CTRL_DM_BY_DRIVER */
1367 if (hal_get_firmwareversion(rtlpriv) >= 0x3E) {
1368 if (fw_cmdio == FW_CMD_CTRL_DM_BY_DRIVER)
1369 fw_cmdio = FW_CMD_CTRL_DM_BY_DRIVER_NEW;
1370 }
1371
1372
1373 /* We shall revise all FW Cmd IO into Reg0x364
1374 * DM map table in the future. */
1375 switch (fw_cmdio) {
1376 case FW_CMD_RA_INIT:
1377 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD, "RA init!!\n");
1378 fw_cmdmap |= FW_RA_INIT_CTL;
1379 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1380 /* Clear control flag to sync with FW. */
1381 FW_CMD_IO_CLR(rtlpriv, FW_RA_INIT_CTL);
1382 break;
1383 case FW_CMD_DIG_DISABLE:
1384 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1385 "Set DIG disable!!\n");
1386 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1387 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1388 break;
1389 case FW_CMD_DIG_ENABLE:
1390 case FW_CMD_DIG_RESUME:
1391 if (!(rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE)) {
1392 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1393 "Set DIG enable or resume!!\n");
1394 fw_cmdmap |= (FW_DIG_ENABLE_CTL | FW_SS_CTL);
1395 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1396 }
1397 break;
1398 case FW_CMD_DIG_HALT:
1399 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1400 "Set DIG halt!!\n");
1401 fw_cmdmap &= ~(FW_DIG_ENABLE_CTL | FW_SS_CTL);
1402 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1403 break;
1404 case FW_CMD_TXPWR_TRACK_THERMAL: {
1405 u8 thermalval = 0;
1406 fw_cmdmap |= FW_PWR_TRK_CTL;
1407
1408 /* Clear FW parameter in terms of thermal parts. */
1409 fw_param &= FW_PWR_TRK_PARAM_CLR;
1410
1411 thermalval = rtlpriv->dm.thermalvalue;
1412 fw_param |= ((thermalval << 24) |
1413 (rtlefuse->thermalmeter[0] << 16));
1414
1415 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1416 "Set TxPwr tracking!! FwCmdMap(%#x), FwParam(%#x)\n",
1417 fw_cmdmap, fw_param);
1418
1419 FW_CMD_PARA_SET(rtlpriv, fw_param);
1420 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1421
1422 /* Clear control flag to sync with FW. */
1423 FW_CMD_IO_CLR(rtlpriv, FW_PWR_TRK_CTL);
1424 }
1425 break;
1426 /* The following FW CMDs are only compatible to
1427 * v.53 or later. */
1428 case FW_CMD_RA_REFRESH_N_COMB:
1429 fw_cmdmap |= FW_RA_N_CTL;
1430
1431 /* Clear RA BG mode control. */
1432 fw_cmdmap &= ~(FW_RA_BG_CTL | FW_RA_INIT_CTL);
1433
1434 /* Clear FW parameter in terms of RA parts. */
1435 fw_param &= FW_RA_PARAM_CLR;
1436
1437 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1438 "[FW CMD] [New Version] Set RA/IOT Comb in n mode!! FwCmdMap(%#x), FwParam(%#x)\n",
1439 fw_cmdmap, fw_param);
1440
1441 FW_CMD_PARA_SET(rtlpriv, fw_param);
1442 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1443
1444 /* Clear control flag to sync with FW. */
1445 FW_CMD_IO_CLR(rtlpriv, FW_RA_N_CTL);
1446 break;
1447 case FW_CMD_RA_REFRESH_BG_COMB:
1448 fw_cmdmap |= FW_RA_BG_CTL;
1449
1450 /* Clear RA n-mode control. */
1451 fw_cmdmap &= ~(FW_RA_N_CTL | FW_RA_INIT_CTL);
1452 /* Clear FW parameter in terms of RA parts. */
1453 fw_param &= FW_RA_PARAM_CLR;
1454
1455 FW_CMD_PARA_SET(rtlpriv, fw_param);
1456 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1457
1458 /* Clear control flag to sync with FW. */
1459 FW_CMD_IO_CLR(rtlpriv, FW_RA_BG_CTL);
1460 break;
1461 case FW_CMD_IQK_ENABLE:
1462 fw_cmdmap |= FW_IQK_CTL;
1463 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1464 /* Clear control flag to sync with FW. */
1465 FW_CMD_IO_CLR(rtlpriv, FW_IQK_CTL);
1466 break;
1467 /* The following FW CMD is compatible to v.62 or later. */
1468 case FW_CMD_CTRL_DM_BY_DRIVER_NEW:
1469 fw_cmdmap |= FW_DRIVER_CTRL_DM_CTL;
1470 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1471 break;
1472 /* The followed FW Cmds needs post-processing later. */
1473 case FW_CMD_RESUME_DM_BY_SCAN:
1474 fw_cmdmap |= (FW_DIG_ENABLE_CTL |
1475 FW_HIGH_PWR_ENABLE_CTL |
1476 FW_SS_CTL);
1477
1478 if (rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE ||
1479 !digtable->dig_enable_flag)
1480 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1481
1482 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) ||
1483 rtlpriv->dm.dynamic_txpower_enable)
1484 fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL;
1485
1486 if ((digtable->dig_ext_port_stage ==
1487 DIG_EXT_PORT_STAGE_0) ||
1488 (digtable->dig_ext_port_stage ==
1489 DIG_EXT_PORT_STAGE_1))
1490 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1491
1492 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1493 postprocessing = true;
1494 break;
1495 case FW_CMD_PAUSE_DM_BY_SCAN:
1496 fw_cmdmap &= ~(FW_DIG_ENABLE_CTL |
1497 FW_HIGH_PWR_ENABLE_CTL |
1498 FW_SS_CTL);
1499 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1500 postprocessing = true;
1501 break;
1502 case FW_CMD_HIGH_PWR_DISABLE:
1503 fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL;
1504 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1505 postprocessing = true;
1506 break;
1507 case FW_CMD_HIGH_PWR_ENABLE:
1508 if (!(rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) &&
1509 !rtlpriv->dm.dynamic_txpower_enable) {
1510 fw_cmdmap |= (FW_HIGH_PWR_ENABLE_CTL |
1511 FW_SS_CTL);
1512 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1513 postprocessing = true;
1514 }
1515 break;
1516 case FW_CMD_DIG_MODE_FA:
1517 fw_cmdmap |= FW_FA_CTL;
1518 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1519 break;
1520 case FW_CMD_DIG_MODE_SS:
1521 fw_cmdmap &= ~FW_FA_CTL;
1522 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1523 break;
1524 case FW_CMD_PAPE_CONTROL:
1525 rtl_dbg(rtlpriv, COMP_CMD, DBG_LOUD,
1526 "[FW CMD] Set PAPE Control\n");
1527 fw_cmdmap &= ~FW_PAPE_CTL_BY_SW_HW;
1528
1529 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1530 break;
1531 default:
1532 /* Pass to original FW CMD processing callback
1533 * routine. */
1534 postprocessing = true;
1535 break;
1536 }
1537 } while (false);
1538
1539 /* We shall post processing these FW CMD if
1540 * variable postprocessing is set.
1541 */
1542 if (postprocessing && !rtlhal->set_fwcmd_inprogress) {
1543 rtlhal->set_fwcmd_inprogress = true;
1544 /* Update current FW Cmd for callback use. */
1545 rtlhal->current_fwcmd_io = fw_cmdio;
1546 } else {
1547 return false;
1548 }
1549
1550 _rtl92s_phy_set_fwcmd_io(hw);
1551 return true;
1552 }
1553
_rtl92s_phy_check_ephy_switchready(struct ieee80211_hw * hw)1554 static void _rtl92s_phy_check_ephy_switchready(struct ieee80211_hw *hw)
1555 {
1556 struct rtl_priv *rtlpriv = rtl_priv(hw);
1557 u32 delay = 100;
1558 u8 regu1;
1559
1560 regu1 = rtl_read_byte(rtlpriv, 0x554);
1561 while ((regu1 & BIT(5)) && (delay > 0)) {
1562 regu1 = rtl_read_byte(rtlpriv, 0x554);
1563 delay--;
1564 /* We delay only 50us to prevent
1565 * being scheduled out. */
1566 udelay(50);
1567 }
1568 }
1569
rtl92s_phy_switch_ephy_parameter(struct ieee80211_hw * hw)1570 void rtl92s_phy_switch_ephy_parameter(struct ieee80211_hw *hw)
1571 {
1572 struct rtl_priv *rtlpriv = rtl_priv(hw);
1573 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1574
1575 /* The way to be capable to switch clock request
1576 * when the PG setting does not support clock request.
1577 * This is the backdoor solution to switch clock
1578 * request before ASPM or D3. */
1579 rtl_write_dword(rtlpriv, 0x540, 0x73c11);
1580 rtl_write_dword(rtlpriv, 0x548, 0x2407c);
1581
1582 /* Switch EPHY parameter!!!! */
1583 rtl_write_word(rtlpriv, 0x550, 0x1000);
1584 rtl_write_byte(rtlpriv, 0x554, 0x20);
1585 _rtl92s_phy_check_ephy_switchready(hw);
1586
1587 rtl_write_word(rtlpriv, 0x550, 0xa0eb);
1588 rtl_write_byte(rtlpriv, 0x554, 0x3e);
1589 _rtl92s_phy_check_ephy_switchready(hw);
1590
1591 rtl_write_word(rtlpriv, 0x550, 0xff80);
1592 rtl_write_byte(rtlpriv, 0x554, 0x39);
1593 _rtl92s_phy_check_ephy_switchready(hw);
1594
1595 /* Delay L1 enter time */
1596 if (ppsc->support_aspm && !ppsc->support_backdoor)
1597 rtl_write_byte(rtlpriv, 0x560, 0x40);
1598 else
1599 rtl_write_byte(rtlpriv, 0x560, 0x00);
1600
1601 }
1602
rtl92s_phy_set_beacon_hwreg(struct ieee80211_hw * hw,u16 beaconinterval)1603 void rtl92s_phy_set_beacon_hwreg(struct ieee80211_hw *hw, u16 beaconinterval)
1604 {
1605 struct rtl_priv *rtlpriv = rtl_priv(hw);
1606 u32 new_bcn_num = 0;
1607
1608 if (hal_get_firmwareversion(rtlpriv) >= 0x33) {
1609 /* Fw v.51 and later. */
1610 rtl_write_dword(rtlpriv, WFM5, 0xF1000000 |
1611 (beaconinterval << 8));
1612 } else {
1613 new_bcn_num = beaconinterval * 32 - 64;
1614 rtl_write_dword(rtlpriv, WFM3 + 4, new_bcn_num);
1615 rtl_write_dword(rtlpriv, WFM3, 0xB026007C);
1616 }
1617 }
1618
