1 /******************************************************************************
2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
3 *
4 * This program is distributed in the hope that it will be useful, but WITHOUT
5 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
6 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
7 * more details.
8 *
9 * The full GNU General Public License is included in this distribution in the
10 * file called LICENSE.
11 *
12 * Contact Information:
13 * wlanfae <wlanfae@realtek.com>
14 *****************************************************************************/
15
16 #include <linux/bitops.h>
17 #include "rtl_core.h"
18 #include "r8192E_hw.h"
19 #include "r8192E_phyreg.h"
20 #include "r8190P_rtl8256.h"
21 #include "r8192E_phy.h"
22 #include "rtl_dm.h"
23
24 #include "r8192E_hwimg.h"
25
26 static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
27 0,
28 0x085c,
29 0x08dc,
30 0x095c,
31 0x09dc,
32 0x0a5c,
33 0x0adc,
34 0x0b5c,
35 0x0bdc,
36 0x0c5c,
37 0x0cdc,
38 0x0d5c,
39 0x0ddc,
40 0x0e5c,
41 0x0f72,
42 };
43
44 /*************************Define local function prototype**********************/
45
46 static u32 _rtl92e_phy_rf_fw_read(struct net_device *dev,
47 enum rf90_radio_path eRFPath, u32 Offset);
48 static void _rtl92e_phy_rf_fw_write(struct net_device *dev,
49 enum rf90_radio_path eRFPath, u32 Offset,
50 u32 Data);
51
_rtl92e_calculate_bit_shift(u32 dwBitMask)52 static u32 _rtl92e_calculate_bit_shift(u32 dwBitMask)
53 {
54 if (!dwBitMask)
55 return 32;
56 return ffs(dwBitMask) - 1;
57 }
58
rtl92e_is_legal_rf_path(struct net_device * dev,u32 eRFPath)59 u8 rtl92e_is_legal_rf_path(struct net_device *dev, u32 eRFPath)
60 {
61 u8 ret = 1;
62 struct r8192_priv *priv = rtllib_priv(dev);
63
64 if (priv->rf_type == RF_2T4R)
65 ret = 0;
66 else if (priv->rf_type == RF_1T2R) {
67 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
68 ret = 1;
69 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
70 ret = 0;
71 }
72 return ret;
73 }
74
rtl92e_set_bb_reg(struct net_device * dev,u32 dwRegAddr,u32 dwBitMask,u32 dwData)75 void rtl92e_set_bb_reg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask,
76 u32 dwData)
77 {
78
79 u32 OriginalValue, BitShift, NewValue;
80
81 if (dwBitMask != bMaskDWord) {
82 OriginalValue = rtl92e_readl(dev, dwRegAddr);
83 BitShift = _rtl92e_calculate_bit_shift(dwBitMask);
84 NewValue = (((OriginalValue) & (~dwBitMask)) |
85 (dwData << BitShift));
86 rtl92e_writel(dev, dwRegAddr, NewValue);
87 } else
88 rtl92e_writel(dev, dwRegAddr, dwData);
89 }
90
rtl92e_get_bb_reg(struct net_device * dev,u32 dwRegAddr,u32 dwBitMask)91 u32 rtl92e_get_bb_reg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask)
92 {
93 u32 OriginalValue, BitShift;
94
95 OriginalValue = rtl92e_readl(dev, dwRegAddr);
96 BitShift = _rtl92e_calculate_bit_shift(dwBitMask);
97
98 return (OriginalValue & dwBitMask) >> BitShift;
99 }
100
_rtl92e_phy_rf_read(struct net_device * dev,enum rf90_radio_path eRFPath,u32 Offset)101 static u32 _rtl92e_phy_rf_read(struct net_device *dev,
102 enum rf90_radio_path eRFPath, u32 Offset)
103 {
104 struct r8192_priv *priv = rtllib_priv(dev);
105 u32 ret = 0;
106 u32 NewOffset = 0;
107 struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath];
108
109 Offset &= 0x3f;
110
111 if (priv->rf_chip == RF_8256) {
112 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
113 if (Offset >= 31) {
114 priv->RfReg0Value[eRFPath] |= 0x140;
115 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
116 bMaskDWord,
117 (priv->RfReg0Value[eRFPath]<<16));
118 NewOffset = Offset - 30;
119 } else if (Offset >= 16) {
120 priv->RfReg0Value[eRFPath] |= 0x100;
121 priv->RfReg0Value[eRFPath] &= (~0x40);
122 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
123 bMaskDWord,
124 (priv->RfReg0Value[eRFPath]<<16));
125
126 NewOffset = Offset - 15;
127 } else
128 NewOffset = Offset;
129 } else {
130 RT_TRACE((COMP_PHY|COMP_ERR),
131 "check RF type here, need to be 8256\n");
132 NewOffset = Offset;
133 }
134 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress,
135 NewOffset);
136 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
137 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
138
139 mdelay(1);
140
141 ret = rtl92e_get_bb_reg(dev, pPhyReg->rfLSSIReadBack,
142 bLSSIReadBackData);
143
144 if (priv->rf_chip == RF_8256) {
145 priv->RfReg0Value[eRFPath] &= 0xebf;
146
147 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
148 (priv->RfReg0Value[eRFPath] << 16));
149
150 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
151 }
152
153
154 return ret;
155
156 }
157
_rtl92e_phy_rf_write(struct net_device * dev,enum rf90_radio_path eRFPath,u32 Offset,u32 Data)158 static void _rtl92e_phy_rf_write(struct net_device *dev,
159 enum rf90_radio_path eRFPath, u32 Offset,
160 u32 Data)
161 {
162 struct r8192_priv *priv = rtllib_priv(dev);
163 u32 DataAndAddr = 0, NewOffset = 0;
164 struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath];
165
166 Offset &= 0x3f;
167 if (priv->rf_chip == RF_8256) {
168 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
169
170 if (Offset >= 31) {
171 priv->RfReg0Value[eRFPath] |= 0x140;
172 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
173 bMaskDWord,
174 (priv->RfReg0Value[eRFPath] << 16));
175 NewOffset = Offset - 30;
176 } else if (Offset >= 16) {
177 priv->RfReg0Value[eRFPath] |= 0x100;
178 priv->RfReg0Value[eRFPath] &= (~0x40);
179 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
180 bMaskDWord,
181 (priv->RfReg0Value[eRFPath] << 16));
182 NewOffset = Offset - 15;
183 } else
184 NewOffset = Offset;
185 } else {
186 RT_TRACE((COMP_PHY|COMP_ERR),
187 "check RF type here, need to be 8256\n");
188 NewOffset = Offset;
189 }
190
191 DataAndAddr = (Data<<16) | (NewOffset&0x3f);
192
193 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
194
195 if (Offset == 0x0)
196 priv->RfReg0Value[eRFPath] = Data;
197
198 if (priv->rf_chip == RF_8256) {
199 if (Offset != 0) {
200 priv->RfReg0Value[eRFPath] &= 0xebf;
201 rtl92e_set_bb_reg(dev, pPhyReg->rf3wireOffset,
202 bMaskDWord,
203 (priv->RfReg0Value[eRFPath] << 16));
204 }
205 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
206 }
207 }
208
rtl92e_set_rf_reg(struct net_device * dev,enum rf90_radio_path eRFPath,u32 RegAddr,u32 BitMask,u32 Data)209 void rtl92e_set_rf_reg(struct net_device *dev, enum rf90_radio_path eRFPath,
210 u32 RegAddr, u32 BitMask, u32 Data)
211 {
212 struct r8192_priv *priv = rtllib_priv(dev);
213 u32 Original_Value, BitShift, New_Value;
214
215 if (!rtl92e_is_legal_rf_path(dev, eRFPath))
216 return;
217 if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter)
218 return;
219
220 RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n");
221 if (priv->Rf_Mode == RF_OP_By_FW) {
222 if (BitMask != bMask12Bits) {
223 Original_Value = _rtl92e_phy_rf_fw_read(dev, eRFPath,
224 RegAddr);
225 BitShift = _rtl92e_calculate_bit_shift(BitMask);
226 New_Value = (((Original_Value) & (~BitMask)) |
227 (Data << BitShift));
228
229 _rtl92e_phy_rf_fw_write(dev, eRFPath, RegAddr,
230 New_Value);
231 } else
232 _rtl92e_phy_rf_fw_write(dev, eRFPath, RegAddr, Data);
233 udelay(200);
234
235 } else {
236 if (BitMask != bMask12Bits) {
237 Original_Value = _rtl92e_phy_rf_read(dev, eRFPath,
238 RegAddr);
239 BitShift = _rtl92e_calculate_bit_shift(BitMask);
240 New_Value = (((Original_Value) & (~BitMask)) |
241 (Data << BitShift));
242
243 _rtl92e_phy_rf_write(dev, eRFPath, RegAddr, New_Value);
244 } else
245 _rtl92e_phy_rf_write(dev, eRFPath, RegAddr, Data);
246 }
247 }
248
rtl92e_get_rf_reg(struct net_device * dev,enum rf90_radio_path eRFPath,u32 RegAddr,u32 BitMask)249 u32 rtl92e_get_rf_reg(struct net_device *dev, enum rf90_radio_path eRFPath,
250 u32 RegAddr, u32 BitMask)
251 {
252 u32 Original_Value, Readback_Value, BitShift;
253 struct r8192_priv *priv = rtllib_priv(dev);
254
255 if (!rtl92e_is_legal_rf_path(dev, eRFPath))
256 return 0;
257 if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter)
258 return 0;
259 mutex_lock(&priv->rf_mutex);
260 if (priv->Rf_Mode == RF_OP_By_FW) {
261 Original_Value = _rtl92e_phy_rf_fw_read(dev, eRFPath, RegAddr);
262 udelay(200);
263 } else {
264 Original_Value = _rtl92e_phy_rf_read(dev, eRFPath, RegAddr);
265 }
266 BitShift = _rtl92e_calculate_bit_shift(BitMask);
267 Readback_Value = (Original_Value & BitMask) >> BitShift;
268 mutex_unlock(&priv->rf_mutex);
269 return Readback_Value;
270 }
271
_rtl92e_phy_rf_fw_read(struct net_device * dev,enum rf90_radio_path eRFPath,u32 Offset)272 static u32 _rtl92e_phy_rf_fw_read(struct net_device *dev,
273 enum rf90_radio_path eRFPath, u32 Offset)
274 {
275 u32 Data = 0;
276 u8 time = 0;
277
278 Data |= ((Offset & 0xFF) << 12);
279 Data |= ((eRFPath & 0x3) << 20);
280 Data |= 0x80000000;
281 while (rtl92e_readl(dev, QPNR) & 0x80000000) {
282 if (time++ < 100)
283 udelay(10);
284 else
285 break;
286 }
287 rtl92e_writel(dev, QPNR, Data);
288 while (rtl92e_readl(dev, QPNR) & 0x80000000) {
289 if (time++ < 100)
290 udelay(10);
291 else
292 return 0;
293 }
294 return rtl92e_readl(dev, RF_DATA);
295
296 }
297
_rtl92e_phy_rf_fw_write(struct net_device * dev,enum rf90_radio_path eRFPath,u32 Offset,u32 Data)298 static void _rtl92e_phy_rf_fw_write(struct net_device *dev,
299 enum rf90_radio_path eRFPath, u32 Offset,
300 u32 Data)
301 {
302 u8 time = 0;
303
304 Data |= ((Offset & 0xFF) << 12);
305 Data |= ((eRFPath & 0x3) << 20);
306 Data |= 0x400000;
307 Data |= 0x80000000;
308
309 while (rtl92e_readl(dev, QPNR) & 0x80000000) {
310 if (time++ < 100)
311 udelay(10);
312 else
313 break;
314 }
315 rtl92e_writel(dev, QPNR, Data);
316
317 }
318
319
rtl92e_config_mac(struct net_device * dev)320 void rtl92e_config_mac(struct net_device *dev)
321 {
322 u32 dwArrayLen = 0, i = 0;
323 u32 *pdwArray = NULL;
324 struct r8192_priv *priv = rtllib_priv(dev);
325
326 if (priv->bTXPowerDataReadFromEEPORM) {
327 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
328 dwArrayLen = MACPHY_Array_PGLength;
329 pdwArray = Rtl819XMACPHY_Array_PG;
330
331 } else {
332 RT_TRACE(COMP_PHY, "Read rtl819XMACPHY_Array\n");
333 dwArrayLen = MACPHY_ArrayLength;
334 pdwArray = Rtl819XMACPHY_Array;
335 }
336 for (i = 0; i < dwArrayLen; i += 3) {
337 RT_TRACE(COMP_DBG,
338 "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n",
339 pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
340 if (pdwArray[i] == 0x318)
341 pdwArray[i+2] = 0x00000800;
342 rtl92e_set_bb_reg(dev, pdwArray[i], pdwArray[i+1],
343 pdwArray[i+2]);
344 }
345 return;
346
347 }
348
_rtl92e_phy_config_bb(struct net_device * dev,u8 ConfigType)349 static void _rtl92e_phy_config_bb(struct net_device *dev, u8 ConfigType)
350 {
351 int i;
352 u32 *Rtl819XPHY_REGArray_Table = NULL;
353 u32 *Rtl819XAGCTAB_Array_Table = NULL;
354 u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0;
355 struct r8192_priv *priv = rtllib_priv(dev);
356
357 AGCTAB_ArrayLen = AGCTAB_ArrayLength;
358 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
359 if (priv->rf_type == RF_2T4R) {
360 PHY_REGArrayLen = PHY_REGArrayLength;
361 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray;
362 } else if (priv->rf_type == RF_1T2R) {
363 PHY_REGArrayLen = PHY_REG_1T2RArrayLength;
364 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray;
365 }
366
367 if (ConfigType == BaseBand_Config_PHY_REG) {
368 for (i = 0; i < PHY_REGArrayLen; i += 2) {
369 rtl92e_set_bb_reg(dev, Rtl819XPHY_REGArray_Table[i],
370 bMaskDWord,
371 Rtl819XPHY_REGArray_Table[i+1]);
372 RT_TRACE(COMP_DBG,
373 "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x\n",
374 i, Rtl819XPHY_REGArray_Table[i],
375 Rtl819XPHY_REGArray_Table[i+1]);
376 }
377 } else if (ConfigType == BaseBand_Config_AGC_TAB) {
378 for (i = 0; i < AGCTAB_ArrayLen; i += 2) {
379 rtl92e_set_bb_reg(dev, Rtl819XAGCTAB_Array_Table[i],
380 bMaskDWord,
381 Rtl819XAGCTAB_Array_Table[i+1]);
382 RT_TRACE(COMP_DBG,
383 "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x\n",
384 i, Rtl819XAGCTAB_Array_Table[i],
385 Rtl819XAGCTAB_Array_Table[i+1]);
386 }
387 }
388 }
389
_rtl92e_init_bb_rf_reg_def(struct net_device * dev)390 static void _rtl92e_init_bb_rf_reg_def(struct net_device *dev)
391 {
392 struct r8192_priv *priv = rtllib_priv(dev);
393
394 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
395 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
396 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
397 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
398
399 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
400 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
401 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
402 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
403
404 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
405 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
406 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;
407 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;
408
409 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
410 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
411 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;
412 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;
413
414 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
415 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
416 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
417 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
418
419 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
420 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
421 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
422 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
423
424 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
425 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
426 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
427 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
428
429 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
430 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
431 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;
432 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;
433
434 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
435 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
436 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
437 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
438
439 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
440 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
441 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
442 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
443
444 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
445 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
446 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
447 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
448
449 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
450 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
451 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
452 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
453
454 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
455 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
456 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
457 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
458
459 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
460 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
461 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
462 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
463
464 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
465 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
466 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
467 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
468
469 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
470 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
471 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
472 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
473
474 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
475 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
476 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
477 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
478
479 }
480
rtl92e_check_bb_and_rf(struct net_device * dev,enum hw90_block CheckBlock,enum rf90_radio_path eRFPath)481 bool rtl92e_check_bb_and_rf(struct net_device *dev, enum hw90_block CheckBlock,
482 enum rf90_radio_path eRFPath)
483 {
484 bool ret = true;
485 u32 i, CheckTimes = 4, dwRegRead = 0;
486 u32 WriteAddr[4];
487 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
488
489 WriteAddr[HW90_BLOCK_MAC] = 0x100;
490 WriteAddr[HW90_BLOCK_PHY0] = 0x900;
491 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
492 WriteAddr[HW90_BLOCK_RF] = 0x3;
493 RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __func__,
494 CheckBlock);
495
496 if (CheckBlock == HW90_BLOCK_MAC) {
497 netdev_warn(dev, "%s(): No checks available for MAC block.\n",
498 __func__);
499 return ret;
500 }
501
502 for (i = 0; i < CheckTimes; i++) {
503 switch (CheckBlock) {
504 case HW90_BLOCK_PHY0:
505 case HW90_BLOCK_PHY1:
506 rtl92e_writel(dev, WriteAddr[CheckBlock],
507 WriteData[i]);
508 dwRegRead = rtl92e_readl(dev, WriteAddr[CheckBlock]);
509 break;
510
511 case HW90_BLOCK_RF:
512 WriteData[i] &= 0xfff;
513 rtl92e_set_rf_reg(dev, eRFPath,
514 WriteAddr[HW90_BLOCK_RF],
515 bMask12Bits, WriteData[i]);
516 mdelay(10);
517 dwRegRead = rtl92e_get_rf_reg(dev, eRFPath,
518 WriteAddr[HW90_BLOCK_RF],
519 bMaskDWord);
520 mdelay(10);
521 break;
522
523 default:
524 ret = false;
525 break;
526 }
527
528
529 if (dwRegRead != WriteData[i]) {
530 netdev_warn(dev, "%s(): Check failed.\n", __func__);
531 ret = false;
532 break;
533 }
534 }
535
536 return ret;
537 }
538
_rtl92e_bb_config_para_file(struct net_device * dev)539 static bool _rtl92e_bb_config_para_file(struct net_device *dev)
540 {
541 struct r8192_priv *priv = rtllib_priv(dev);
542 bool rtStatus = true;
543 u8 bRegValue = 0, eCheckItem = 0;
544 u32 dwRegValue = 0;
545
546 bRegValue = rtl92e_readb(dev, BB_GLOBAL_RESET);
547 rtl92e_writeb(dev, BB_GLOBAL_RESET, (bRegValue|BB_GLOBAL_RESET_BIT));
548
549 dwRegValue = rtl92e_readl(dev, CPU_GEN);
550 rtl92e_writel(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
551
552 for (eCheckItem = (enum hw90_block)HW90_BLOCK_PHY0;
553 eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) {
554 rtStatus = rtl92e_check_bb_and_rf(dev,
555 (enum hw90_block)eCheckItem,
556 (enum rf90_radio_path)0);
557 if (!rtStatus) {
558 RT_TRACE((COMP_ERR | COMP_PHY),
559 "rtl92e_config_rf():Check PHY%d Fail!!\n",
560 eCheckItem-1);
561 return rtStatus;
562 }
563 }
564 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
565 _rtl92e_phy_config_bb(dev, BaseBand_Config_PHY_REG);
566
567 dwRegValue = rtl92e_readl(dev, CPU_GEN);
568 rtl92e_writel(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
569
570 _rtl92e_phy_config_bb(dev, BaseBand_Config_AGC_TAB);
571
572 if (priv->IC_Cut > VERSION_8190_BD) {
573 if (priv->rf_type == RF_2T4R)
574 dwRegValue = (priv->AntennaTxPwDiff[2]<<8 |
575 priv->AntennaTxPwDiff[1]<<4 |
576 priv->AntennaTxPwDiff[0]);
577 else
578 dwRegValue = 0x0;
579 rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage,
580 (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue);
581
582
583 dwRegValue = priv->CrystalCap;
584 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, bXtalCap92x,
585 dwRegValue);
586 }
587
588 return rtStatus;
589 }
rtl92e_config_bb(struct net_device * dev)590 bool rtl92e_config_bb(struct net_device *dev)
591 {
592 _rtl92e_init_bb_rf_reg_def(dev);
593 return _rtl92e_bb_config_para_file(dev);
594 }
595
rtl92e_get_tx_power(struct net_device * dev)596 void rtl92e_get_tx_power(struct net_device *dev)
597 {
598 struct r8192_priv *priv = rtllib_priv(dev);
599
600 priv->MCSTxPowerLevelOriginalOffset[0] =
601 rtl92e_readl(dev, rTxAGC_Rate18_06);
602 priv->MCSTxPowerLevelOriginalOffset[1] =
603 rtl92e_readl(dev, rTxAGC_Rate54_24);
604 priv->MCSTxPowerLevelOriginalOffset[2] =
605 rtl92e_readl(dev, rTxAGC_Mcs03_Mcs00);
606 priv->MCSTxPowerLevelOriginalOffset[3] =
607 rtl92e_readl(dev, rTxAGC_Mcs07_Mcs04);
608 priv->MCSTxPowerLevelOriginalOffset[4] =
609 rtl92e_readl(dev, rTxAGC_Mcs11_Mcs08);
610 priv->MCSTxPowerLevelOriginalOffset[5] =
611 rtl92e_readl(dev, rTxAGC_Mcs15_Mcs12);
612
613 priv->DefaultInitialGain[0] = rtl92e_readb(dev, rOFDM0_XAAGCCore1);
614 priv->DefaultInitialGain[1] = rtl92e_readb(dev, rOFDM0_XBAGCCore1);
615 priv->DefaultInitialGain[2] = rtl92e_readb(dev, rOFDM0_XCAGCCore1);
616 priv->DefaultInitialGain[3] = rtl92e_readb(dev, rOFDM0_XDAGCCore1);
617 RT_TRACE(COMP_INIT,
618 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
619 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
620 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
621
622 priv->framesync = rtl92e_readb(dev, rOFDM0_RxDetector3);
623 priv->framesyncC34 = rtl92e_readl(dev, rOFDM0_RxDetector2);
624 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n",
625 rOFDM0_RxDetector3, priv->framesync);
626 priv->SifsTime = rtl92e_readw(dev, SIFS);
627 }
628
rtl92e_set_tx_power(struct net_device * dev,u8 channel)629 void rtl92e_set_tx_power(struct net_device *dev, u8 channel)
630 {
631 struct r8192_priv *priv = rtllib_priv(dev);
632 u8 powerlevel = 0, powerlevelOFDM24G = 0;
633 s8 ant_pwr_diff;
634 u32 u4RegValue;
635
636 if (priv->epromtype == EEPROM_93C46) {
637 powerlevel = priv->TxPowerLevelCCK[channel-1];
638 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
639 } else if (priv->epromtype == EEPROM_93C56) {
640 if (priv->rf_type == RF_1T2R) {
641 powerlevel = priv->TxPowerLevelCCK_C[channel-1];
642 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1];
643 } else if (priv->rf_type == RF_2T4R) {
644 powerlevel = priv->TxPowerLevelCCK_A[channel-1];
645 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1];
646
647 ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1]
648 - priv->TxPowerLevelOFDM24G_A[channel-1];
649
650 priv->RF_C_TxPwDiff = ant_pwr_diff;
651
652 ant_pwr_diff &= 0xf;
653
654 priv->AntennaTxPwDiff[2] = 0;
655 priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff);
656 priv->AntennaTxPwDiff[0] = 0;
657
658 u4RegValue = (priv->AntennaTxPwDiff[2]<<8 |
659 priv->AntennaTxPwDiff[1]<<4 |
660 priv->AntennaTxPwDiff[0]);
661
662 rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage,
663 (bXBTxAGC|bXCTxAGC|bXDTxAGC),
664 u4RegValue);
665 }
666 }
667 switch (priv->rf_chip) {
668 case RF_8225:
669 break;
670 case RF_8256:
671 rtl92e_set_cck_tx_power(dev, powerlevel);
672 rtl92e_set_ofdm_tx_power(dev, powerlevelOFDM24G);
673 break;
674 case RF_8258:
675 break;
676 default:
677 netdev_err(dev, "Invalid RF Chip ID.\n");
678 break;
679 }
680 }
681
rtl92e_config_phy(struct net_device * dev)682 bool rtl92e_config_phy(struct net_device *dev)
683 {
684 struct r8192_priv *priv = rtllib_priv(dev);
685 bool rtStatus = true;
686
687 switch (priv->rf_chip) {
688 case RF_8225:
689 break;
690 case RF_8256:
691 rtStatus = rtl92e_config_rf(dev);
692 break;
693
694 case RF_8258:
695 break;
696 case RF_PSEUDO_11N:
697 break;
698
699 default:
700 netdev_err(dev, "Invalid RF Chip ID.\n");
701 break;
702 }
703 return rtStatus;
704 }
705
rtl92e_config_rf_path(struct net_device * dev,enum rf90_radio_path eRFPath)706 u8 rtl92e_config_rf_path(struct net_device *dev, enum rf90_radio_path eRFPath)
707 {
708
709 int i;
710
711 switch (eRFPath) {
712 case RF90_PATH_A:
713 for (i = 0; i < RadioA_ArrayLength; i += 2) {
714 if (Rtl819XRadioA_Array[i] == 0xfe) {
715 msleep(100);
716 continue;
717 }
718 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioA_Array[i],
719 bMask12Bits,
720 Rtl819XRadioA_Array[i+1]);
721
722 }
723 break;
724 case RF90_PATH_B:
725 for (i = 0; i < RadioB_ArrayLength; i += 2) {
726 if (Rtl819XRadioB_Array[i] == 0xfe) {
727 msleep(100);
728 continue;
729 }
730 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioB_Array[i],
731 bMask12Bits,
732 Rtl819XRadioB_Array[i+1]);
733
734 }
735 break;
736 case RF90_PATH_C:
737 for (i = 0; i < RadioC_ArrayLength; i += 2) {
738 if (Rtl819XRadioC_Array[i] == 0xfe) {
739 msleep(100);
740 continue;
741 }
742 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioC_Array[i],
743 bMask12Bits,
744 Rtl819XRadioC_Array[i+1]);
745
746 }
747 break;
748 case RF90_PATH_D:
749 for (i = 0; i < RadioD_ArrayLength; i += 2) {
750 if (Rtl819XRadioD_Array[i] == 0xfe) {
751 msleep(100);
752 continue;
753 }
754 rtl92e_set_rf_reg(dev, eRFPath, Rtl819XRadioD_Array[i],
755 bMask12Bits,
756 Rtl819XRadioD_Array[i+1]);
757
758 }
759 break;
760 default:
761 break;
762 }
763
764 return 0;
765
766 }
767
_rtl92e_set_tx_power_level(struct net_device * dev,u8 channel)768 static void _rtl92e_set_tx_power_level(struct net_device *dev, u8 channel)
769 {
770 struct r8192_priv *priv = rtllib_priv(dev);
771 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
772 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
773
774 switch (priv->rf_chip) {
775 case RF_8225:
776 break;
777
778 case RF_8256:
779 rtl92e_set_cck_tx_power(dev, powerlevel);
780 rtl92e_set_ofdm_tx_power(dev, powerlevelOFDM24G);
781 break;
782
783 case RF_8258:
784 break;
785 default:
786 netdev_warn(dev, "%s(): Invalid RF Chip ID\n", __func__);
787 break;
788 }
789 }
790
_rtl92e_phy_set_sw_chnl_cmd_array(struct net_device * dev,struct sw_chnl_cmd * CmdTable,u32 CmdTableIdx,u32 CmdTableSz,enum sw_chnl_cmd_id CmdID,u32 Para1,u32 Para2,u32 msDelay)791 static u8 _rtl92e_phy_set_sw_chnl_cmd_array(struct net_device *dev,
792 struct sw_chnl_cmd *CmdTable,
793 u32 CmdTableIdx, u32 CmdTableSz,
794 enum sw_chnl_cmd_id CmdID,
795 u32 Para1, u32 Para2, u32 msDelay)
796 {
797 struct sw_chnl_cmd *pCmd;
798
799 if (CmdTable == NULL) {
800 netdev_err(dev, "%s(): CmdTable cannot be NULL.\n", __func__);
801 return false;
802 }
803 if (CmdTableIdx >= CmdTableSz) {
804 netdev_err(dev, "%s(): Invalid index requested.\n", __func__);
805 return false;
806 }
807
808 pCmd = CmdTable + CmdTableIdx;
809 pCmd->CmdID = CmdID;
810 pCmd->Para1 = Para1;
811 pCmd->Para2 = Para2;
812 pCmd->msDelay = msDelay;
813
814 return true;
815 }
816
_rtl92e_phy_switch_channel_step(struct net_device * dev,u8 channel,u8 * stage,u8 * step,u32 * delay)817 static u8 _rtl92e_phy_switch_channel_step(struct net_device *dev, u8 channel,
818 u8 *stage, u8 *step, u32 *delay)
819 {
820 struct r8192_priv *priv = rtllib_priv(dev);
821 struct rtllib_device *ieee = priv->rtllib;
822 u32 PreCommonCmdCnt;
823 u32 PostCommonCmdCnt;
824 u32 RfDependCmdCnt;
825 struct sw_chnl_cmd *CurrentCmd = NULL;
826 u8 eRFPath;
827
828 RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n",
829 __func__, *stage, *step, channel);
830
831 if (!rtllib_legal_channel(priv->rtllib, channel)) {
832 netdev_err(dev, "Invalid channel requested: %d\n", channel);
833 return true;
834 }
835
836 {
837 PreCommonCmdCnt = 0;
838 _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PreCommonCmd,
839 PreCommonCmdCnt++,
840 MAX_PRECMD_CNT,
841 CmdID_SetTxPowerLevel,
842 0, 0, 0);
843 _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PreCommonCmd,
844 PreCommonCmdCnt++,
845 MAX_PRECMD_CNT, CmdID_End,
846 0, 0, 0);
847
848 PostCommonCmdCnt = 0;
849
850 _rtl92e_phy_set_sw_chnl_cmd_array(dev, ieee->PostCommonCmd,
851 PostCommonCmdCnt++,
852 MAX_POSTCMD_CNT, CmdID_End,
853 0, 0, 0);
854
855 RfDependCmdCnt = 0;
856 switch (priv->rf_chip) {
857 case RF_8225:
858 if (!(channel >= 1 && channel <= 14)) {
859 netdev_err(dev,
860 "Invalid channel requested for 8225: %d\n",
861 channel);
862 return false;
863 }
864 _rtl92e_phy_set_sw_chnl_cmd_array(dev,
865 ieee->RfDependCmd,
866 RfDependCmdCnt++,
867 MAX_RFDEPENDCMD_CNT,
868 CmdID_RF_WriteReg,
869 rZebra1_Channel,
870 RF_CHANNEL_TABLE_ZEBRA[channel],
871 10);
872 _rtl92e_phy_set_sw_chnl_cmd_array(dev,
873 ieee->RfDependCmd,
874 RfDependCmdCnt++,
875 MAX_RFDEPENDCMD_CNT,
876 CmdID_End, 0, 0, 0);
877 break;
878
879 case RF_8256:
880 if (!(channel >= 1 && channel <= 14)) {
881 netdev_err(dev,
882 "Invalid channel requested for 8256: %d\n",
883 channel);
884 return false;
885 }
886 _rtl92e_phy_set_sw_chnl_cmd_array(dev,
887 ieee->RfDependCmd,
888 RfDependCmdCnt++,
889 MAX_RFDEPENDCMD_CNT,
890 CmdID_RF_WriteReg,
891 rZebra1_Channel,
892 channel, 10);
893 _rtl92e_phy_set_sw_chnl_cmd_array(dev,
894 ieee->RfDependCmd,
895 RfDependCmdCnt++,
896 MAX_RFDEPENDCMD_CNT,
897 CmdID_End, 0, 0, 0);
898 break;
899
900 case RF_8258:
901 break;
902
903 default:
904 netdev_warn(dev, "Unknown RF Chip ID\n");
905 return false;
906 }
907
908
909 do {
910 switch (*stage) {
911 case 0:
912 CurrentCmd = &ieee->PreCommonCmd[*step];
913 break;
914 case 1:
915 CurrentCmd = &ieee->RfDependCmd[*step];
916 break;
917 case 2:
918 CurrentCmd = &ieee->PostCommonCmd[*step];
919 break;
920 }
921
922 if (CurrentCmd && CurrentCmd->CmdID == CmdID_End) {
923 if ((*stage) == 2)
924 return true;
925 (*stage)++;
926 (*step) = 0;
927 continue;
928 }
929
930 if (!CurrentCmd)
931 continue;
932 switch (CurrentCmd->CmdID) {
933 case CmdID_SetTxPowerLevel:
934 if (priv->IC_Cut > (u8)VERSION_8190_BD)
935 _rtl92e_set_tx_power_level(dev,
936 channel);
937 break;
938 case CmdID_WritePortUlong:
939 rtl92e_writel(dev, CurrentCmd->Para1,
940 CurrentCmd->Para2);
941 break;
942 case CmdID_WritePortUshort:
943 rtl92e_writew(dev, CurrentCmd->Para1,
944 (u16)CurrentCmd->Para2);
945 break;
946 case CmdID_WritePortUchar:
947 rtl92e_writeb(dev, CurrentCmd->Para1,
948 (u8)CurrentCmd->Para2);
949 break;
950 case CmdID_RF_WriteReg:
951 for (eRFPath = 0; eRFPath <
952 priv->NumTotalRFPath; eRFPath++)
953 rtl92e_set_rf_reg(dev,
954 (enum rf90_radio_path)eRFPath,
955 CurrentCmd->Para1, bMask12Bits,
956 CurrentCmd->Para2<<7);
957 break;
958 default:
959 break;
960 }
961
962 break;
963 } while (true);
964 } /*for (Number of RF paths)*/
965
966 (*delay) = CurrentCmd->msDelay;
967 (*step)++;
968 return false;
969 }
970
_rtl92e_phy_switch_channel(struct net_device * dev,u8 channel)971 static void _rtl92e_phy_switch_channel(struct net_device *dev, u8 channel)
972 {
973 struct r8192_priv *priv = rtllib_priv(dev);
974 u32 delay = 0;
975
976 while (!_rtl92e_phy_switch_channel_step(dev, channel,
977 &priv->SwChnlStage,
978 &priv->SwChnlStep, &delay)) {
979 if (delay > 0)
980 msleep(delay);
981 if (!priv->up)
982 break;
983 }
984 }
985
_rtl92e_phy_switch_channel_work_item(struct net_device * dev)986 static void _rtl92e_phy_switch_channel_work_item(struct net_device *dev)
987 {
988
989 struct r8192_priv *priv = rtllib_priv(dev);
990
991 RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n");
992
993 RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __func__,
994 priv->chan, priv);
995
996 _rtl92e_phy_switch_channel(dev, priv->chan);
997
998 RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n");
999 }
1000
rtl92e_set_channel(struct net_device * dev,u8 channel)1001 u8 rtl92e_set_channel(struct net_device *dev, u8 channel)
1002 {
1003 struct r8192_priv *priv = rtllib_priv(dev);
1004
1005 RT_TRACE(COMP_PHY, "=====>%s()\n", __func__);
1006 if (!priv->up) {
1007 netdev_err(dev, "%s(): Driver is not initialized\n", __func__);
1008 return false;
1009 }
1010 if (priv->SwChnlInProgress)
1011 return false;
1012
1013
1014 switch (priv->rtllib->mode) {
1015 case WIRELESS_MODE_A:
1016 case WIRELESS_MODE_N_5G:
1017 if (channel <= 14) {
1018 netdev_warn(dev,
1019 "Channel %d not available in 802.11a.\n",
1020 channel);
1021 return false;
1022 }
1023 break;
1024 case WIRELESS_MODE_B:
1025 if (channel > 14) {
1026 netdev_warn(dev,
1027 "Channel %d not available in 802.11b.\n",
1028 channel);
1029 return false;
1030 }
1031 break;
1032 case WIRELESS_MODE_G:
1033 case WIRELESS_MODE_N_24G:
1034 if (channel > 14) {
1035 netdev_warn(dev,
1036 "Channel %d not available in 802.11g.\n",
1037 channel);
1038 return false;
1039 }
1040 break;
1041 }
1042
1043 priv->SwChnlInProgress = true;
1044 if (channel == 0)
1045 channel = 1;
1046
1047 priv->chan = channel;
1048
1049 priv->SwChnlStage = 0;
1050 priv->SwChnlStep = 0;
1051
1052 if (priv->up)
1053 _rtl92e_phy_switch_channel_work_item(dev);
1054 priv->SwChnlInProgress = false;
1055 return true;
1056 }
1057
_rtl92e_cck_tx_power_track_bw_switch_tssi(struct net_device * dev)1058 static void _rtl92e_cck_tx_power_track_bw_switch_tssi(struct net_device *dev)
1059 {
1060 struct r8192_priv *priv = rtllib_priv(dev);
1061
1062 switch (priv->CurrentChannelBW) {
1063 case HT_CHANNEL_WIDTH_20:
1064 priv->CCKPresentAttentuation =
1065 priv->CCKPresentAttentuation_20Mdefault +
1066 priv->CCKPresentAttentuation_difference;
1067
1068 if (priv->CCKPresentAttentuation >
1069 (CCKTxBBGainTableLength-1))
1070 priv->CCKPresentAttentuation =
1071 CCKTxBBGainTableLength-1;
1072 if (priv->CCKPresentAttentuation < 0)
1073 priv->CCKPresentAttentuation = 0;
1074
1075 RT_TRACE(COMP_POWER_TRACKING,
1076 "20M, priv->CCKPresentAttentuation = %d\n",
1077 priv->CCKPresentAttentuation);
1078
1079 if (priv->rtllib->current_network.channel == 14 &&
1080 !priv->bcck_in_ch14) {
1081 priv->bcck_in_ch14 = true;
1082 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1083 } else if (priv->rtllib->current_network.channel !=
1084 14 && priv->bcck_in_ch14) {
1085 priv->bcck_in_ch14 = false;
1086 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1087 } else {
1088 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1089 }
1090 break;
1091
1092 case HT_CHANNEL_WIDTH_20_40:
1093 priv->CCKPresentAttentuation =
1094 priv->CCKPresentAttentuation_40Mdefault +
1095 priv->CCKPresentAttentuation_difference;
1096
1097 RT_TRACE(COMP_POWER_TRACKING,
1098 "40M, priv->CCKPresentAttentuation = %d\n",
1099 priv->CCKPresentAttentuation);
1100 if (priv->CCKPresentAttentuation >
1101 (CCKTxBBGainTableLength - 1))
1102 priv->CCKPresentAttentuation =
1103 CCKTxBBGainTableLength-1;
1104 if (priv->CCKPresentAttentuation < 0)
1105 priv->CCKPresentAttentuation = 0;
1106
1107 if (priv->rtllib->current_network.channel == 14 &&
1108 !priv->bcck_in_ch14) {
1109 priv->bcck_in_ch14 = true;
1110 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1111 } else if (priv->rtllib->current_network.channel != 14
1112 && priv->bcck_in_ch14) {
1113 priv->bcck_in_ch14 = false;
1114 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1115 } else {
1116 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1117 }
1118 break;
1119 }
1120 }
1121
_rtl92e_cck_tx_power_track_bw_switch_thermal(struct net_device * dev)1122 static void _rtl92e_cck_tx_power_track_bw_switch_thermal(struct net_device *dev)
1123 {
1124 struct r8192_priv *priv = rtllib_priv(dev);
1125
1126 if (priv->rtllib->current_network.channel == 14 &&
1127 !priv->bcck_in_ch14)
1128 priv->bcck_in_ch14 = true;
1129 else if (priv->rtllib->current_network.channel != 14 &&
1130 priv->bcck_in_ch14)
1131 priv->bcck_in_ch14 = false;
1132
1133 switch (priv->CurrentChannelBW) {
1134 case HT_CHANNEL_WIDTH_20:
1135 if (priv->Record_CCK_20Mindex == 0)
1136 priv->Record_CCK_20Mindex = 6;
1137 priv->CCK_index = priv->Record_CCK_20Mindex;
1138 RT_TRACE(COMP_POWER_TRACKING,
1139 "20MHz, _rtl92e_cck_tx_power_track_bw_switch_thermal(),CCK_index = %d\n",
1140 priv->CCK_index);
1141 break;
1142
1143 case HT_CHANNEL_WIDTH_20_40:
1144 priv->CCK_index = priv->Record_CCK_40Mindex;
1145 RT_TRACE(COMP_POWER_TRACKING,
1146 "40MHz, _rtl92e_cck_tx_power_track_bw_switch_thermal(), CCK_index = %d\n",
1147 priv->CCK_index);
1148 break;
1149 }
1150 rtl92e_dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
1151 }
1152
_rtl92e_cck_tx_power_track_bw_switch(struct net_device * dev)1153 static void _rtl92e_cck_tx_power_track_bw_switch(struct net_device *dev)
1154 {
1155 struct r8192_priv *priv = rtllib_priv(dev);
1156
1157 if (priv->IC_Cut >= IC_VersionCut_D)
1158 _rtl92e_cck_tx_power_track_bw_switch_tssi(dev);
1159 else
1160 _rtl92e_cck_tx_power_track_bw_switch_thermal(dev);
1161 }
1162
_rtl92e_set_bw_mode_work_item(struct net_device * dev)1163 static void _rtl92e_set_bw_mode_work_item(struct net_device *dev)
1164 {
1165
1166 struct r8192_priv *priv = rtllib_priv(dev);
1167 u8 regBwOpMode;
1168
1169 RT_TRACE(COMP_SWBW,
1170 "==>_rtl92e_set_bw_mode_work_item() Switch to %s bandwidth\n",
1171 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ?
1172 "20MHz" : "40MHz");
1173
1174
1175 if (priv->rf_chip == RF_PSEUDO_11N) {
1176 priv->SetBWModeInProgress = false;
1177 return;
1178 }
1179 if (!priv->up) {
1180 netdev_err(dev, "%s(): Driver is not initialized\n", __func__);
1181 return;
1182 }
1183 regBwOpMode = rtl92e_readb(dev, BW_OPMODE);
1184
1185 switch (priv->CurrentChannelBW) {
1186 case HT_CHANNEL_WIDTH_20:
1187 regBwOpMode |= BW_OPMODE_20MHZ;
1188 rtl92e_writeb(dev, BW_OPMODE, regBwOpMode);
1189 break;
1190
1191 case HT_CHANNEL_WIDTH_20_40:
1192 regBwOpMode &= ~BW_OPMODE_20MHZ;
1193 rtl92e_writeb(dev, BW_OPMODE, regBwOpMode);
1194 break;
1195
1196 default:
1197 netdev_err(dev, "%s(): unknown Bandwidth: %#X\n", __func__,
1198 priv->CurrentChannelBW);
1199 break;
1200 }
1201
1202 switch (priv->CurrentChannelBW) {
1203 case HT_CHANNEL_WIDTH_20:
1204 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
1205 rtl92e_set_bb_reg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
1206
1207 if (!priv->btxpower_tracking) {
1208 rtl92e_writel(dev, rCCK0_TxFilter1, 0x1a1b0000);
1209 rtl92e_writel(dev, rCCK0_TxFilter2, 0x090e1317);
1210 rtl92e_writel(dev, rCCK0_DebugPort, 0x00000204);
1211 } else {
1212 _rtl92e_cck_tx_power_track_bw_switch(dev);
1213 }
1214
1215 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
1216
1217 break;
1218 case HT_CHANNEL_WIDTH_20_40:
1219 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
1220 rtl92e_set_bb_reg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
1221
1222 if (!priv->btxpower_tracking) {
1223 rtl92e_writel(dev, rCCK0_TxFilter1, 0x35360000);
1224 rtl92e_writel(dev, rCCK0_TxFilter2, 0x121c252e);
1225 rtl92e_writel(dev, rCCK0_DebugPort, 0x00000409);
1226 } else {
1227 _rtl92e_cck_tx_power_track_bw_switch(dev);
1228 }
1229
1230 rtl92e_set_bb_reg(dev, rCCK0_System, bCCKSideBand,
1231 (priv->nCur40MhzPrimeSC>>1));
1232 rtl92e_set_bb_reg(dev, rOFDM1_LSTF, 0xC00,
1233 priv->nCur40MhzPrimeSC);
1234
1235 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
1236 break;
1237 default:
1238 netdev_err(dev, "%s(): unknown Bandwidth: %#X\n", __func__,
1239 priv->CurrentChannelBW);
1240 break;
1241
1242 }
1243
1244 switch (priv->rf_chip) {
1245 case RF_8225:
1246 break;
1247
1248 case RF_8256:
1249 rtl92e_set_bandwidth(dev, priv->CurrentChannelBW);
1250 break;
1251
1252 case RF_8258:
1253 break;
1254
1255 case RF_PSEUDO_11N:
1256 break;
1257
1258 default:
1259 netdev_info(dev, "%s(): Unknown RFChipID: %d\n", __func__,
1260 priv->rf_chip);
1261 break;
1262 }
1263
1264 atomic_dec(&(priv->rtllib->atm_swbw));
1265 priv->SetBWModeInProgress = false;
1266
1267 RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()");
1268 }
1269
rtl92e_set_bw_mode(struct net_device * dev,enum ht_channel_width Bandwidth,enum ht_extchnl_offset Offset)1270 void rtl92e_set_bw_mode(struct net_device *dev, enum ht_channel_width Bandwidth,
1271 enum ht_extchnl_offset Offset)
1272 {
1273 struct r8192_priv *priv = rtllib_priv(dev);
1274
1275
1276 if (priv->SetBWModeInProgress)
1277 return;
1278
1279 atomic_inc(&(priv->rtllib->atm_swbw));
1280 priv->SetBWModeInProgress = true;
1281
1282 priv->CurrentChannelBW = Bandwidth;
1283
1284 if (Offset == HT_EXTCHNL_OFFSET_LOWER)
1285 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
1286 else if (Offset == HT_EXTCHNL_OFFSET_UPPER)
1287 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
1288 else
1289 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
1290
1291 _rtl92e_set_bw_mode_work_item(dev);
1292
1293 }
1294
rtl92e_init_gain(struct net_device * dev,u8 Operation)1295 void rtl92e_init_gain(struct net_device *dev, u8 Operation)
1296 {
1297 #define SCAN_RX_INITIAL_GAIN 0x17
1298 #define POWER_DETECTION_TH 0x08
1299 struct r8192_priv *priv = rtllib_priv(dev);
1300 u32 BitMask;
1301 u8 initial_gain;
1302
1303 if (priv->up) {
1304 switch (Operation) {
1305 case IG_Backup:
1306 RT_TRACE(COMP_SCAN,
1307 "IG_Backup, backup the initial gain.\n");
1308 initial_gain = SCAN_RX_INITIAL_GAIN;
1309 BitMask = bMaskByte0;
1310 if (dm_digtable.dig_algorithm ==
1311 DIG_ALGO_BY_FALSE_ALARM)
1312 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8);
1313 priv->initgain_backup.xaagccore1 =
1314 (u8)rtl92e_get_bb_reg(dev, rOFDM0_XAAGCCore1,
1315 BitMask);
1316 priv->initgain_backup.xbagccore1 =
1317 (u8)rtl92e_get_bb_reg(dev, rOFDM0_XBAGCCore1,
1318 BitMask);
1319 priv->initgain_backup.xcagccore1 =
1320 (u8)rtl92e_get_bb_reg(dev, rOFDM0_XCAGCCore1,
1321 BitMask);
1322 priv->initgain_backup.xdagccore1 =
1323 (u8)rtl92e_get_bb_reg(dev, rOFDM0_XDAGCCore1,
1324 BitMask);
1325 BitMask = bMaskByte2;
1326 priv->initgain_backup.cca = (u8)rtl92e_get_bb_reg(dev,
1327 rCCK0_CCA, BitMask);
1328
1329 RT_TRACE(COMP_SCAN,
1330 "Scan InitialGainBackup 0xc50 is %x\n",
1331 priv->initgain_backup.xaagccore1);
1332 RT_TRACE(COMP_SCAN,
1333 "Scan InitialGainBackup 0xc58 is %x\n",
1334 priv->initgain_backup.xbagccore1);
1335 RT_TRACE(COMP_SCAN,
1336 "Scan InitialGainBackup 0xc60 is %x\n",
1337 priv->initgain_backup.xcagccore1);
1338 RT_TRACE(COMP_SCAN,
1339 "Scan InitialGainBackup 0xc68 is %x\n",
1340 priv->initgain_backup.xdagccore1);
1341 RT_TRACE(COMP_SCAN,
1342 "Scan InitialGainBackup 0xa0a is %x\n",
1343 priv->initgain_backup.cca);
1344
1345 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x\n",
1346 initial_gain);
1347 rtl92e_writeb(dev, rOFDM0_XAAGCCore1, initial_gain);
1348 rtl92e_writeb(dev, rOFDM0_XBAGCCore1, initial_gain);
1349 rtl92e_writeb(dev, rOFDM0_XCAGCCore1, initial_gain);
1350 rtl92e_writeb(dev, rOFDM0_XDAGCCore1, initial_gain);
1351 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x\n",
1352 POWER_DETECTION_TH);
1353 rtl92e_writeb(dev, 0xa0a, POWER_DETECTION_TH);
1354 break;
1355 case IG_Restore:
1356 RT_TRACE(COMP_SCAN,
1357 "IG_Restore, restore the initial gain.\n");
1358 BitMask = 0x7f;
1359 if (dm_digtable.dig_algorithm ==
1360 DIG_ALGO_BY_FALSE_ALARM)
1361 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x8);
1362
1363 rtl92e_set_bb_reg(dev, rOFDM0_XAAGCCore1, BitMask,
1364 (u32)priv->initgain_backup.xaagccore1);
1365 rtl92e_set_bb_reg(dev, rOFDM0_XBAGCCore1, BitMask,
1366 (u32)priv->initgain_backup.xbagccore1);
1367 rtl92e_set_bb_reg(dev, rOFDM0_XCAGCCore1, BitMask,
1368 (u32)priv->initgain_backup.xcagccore1);
1369 rtl92e_set_bb_reg(dev, rOFDM0_XDAGCCore1, BitMask,
1370 (u32)priv->initgain_backup.xdagccore1);
1371 BitMask = bMaskByte2;
1372 rtl92e_set_bb_reg(dev, rCCK0_CCA, BitMask,
1373 (u32)priv->initgain_backup.cca);
1374
1375 RT_TRACE(COMP_SCAN,
1376 "Scan BBInitialGainRestore 0xc50 is %x\n",
1377 priv->initgain_backup.xaagccore1);
1378 RT_TRACE(COMP_SCAN,
1379 "Scan BBInitialGainRestore 0xc58 is %x\n",
1380 priv->initgain_backup.xbagccore1);
1381 RT_TRACE(COMP_SCAN,
1382 "Scan BBInitialGainRestore 0xc60 is %x\n",
1383 priv->initgain_backup.xcagccore1);
1384 RT_TRACE(COMP_SCAN,
1385 "Scan BBInitialGainRestore 0xc68 is %x\n",
1386 priv->initgain_backup.xdagccore1);
1387 RT_TRACE(COMP_SCAN,
1388 "Scan BBInitialGainRestore 0xa0a is %x\n",
1389 priv->initgain_backup.cca);
1390
1391 rtl92e_set_tx_power(dev,
1392 priv->rtllib->current_network.channel);
1393
1394 if (dm_digtable.dig_algorithm ==
1395 DIG_ALGO_BY_FALSE_ALARM)
1396 rtl92e_set_bb_reg(dev, UFWP, bMaskByte1, 0x1);
1397 break;
1398 default:
1399 RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n");
1400 break;
1401 }
1402 }
1403 }
1404
rtl92e_set_rf_off(struct net_device * dev)1405 void rtl92e_set_rf_off(struct net_device *dev)
1406 {
1407
1408 rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0);
1409 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4, 0x300, 0x0);
1410 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0);
1411 rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);
1412 rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);
1413 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0);
1414 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1, 0x4, 0x0);
1415 rtl92e_writeb(dev, ANAPAR_FOR_8192PciE, 0x07);
1416
1417 }
1418
_rtl92e_set_rf_power_state(struct net_device * dev,enum rt_rf_power_state eRFPowerState)1419 static bool _rtl92e_set_rf_power_state(struct net_device *dev,
1420 enum rt_rf_power_state eRFPowerState)
1421 {
1422 struct r8192_priv *priv = rtllib_priv(dev);
1423 struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *)
1424 (&(priv->rtllib->PowerSaveControl));
1425 bool bResult = true;
1426 u8 i = 0, QueueID = 0;
1427 struct rtl8192_tx_ring *ring = NULL;
1428
1429 if (priv->SetRFPowerStateInProgress)
1430 return false;
1431 RT_TRACE(COMP_PS, "===========> _rtl92e_set_rf_power_state()!\n");
1432 priv->SetRFPowerStateInProgress = true;
1433
1434 switch (priv->rf_chip) {
1435 case RF_8256:
1436 switch (eRFPowerState) {
1437 case eRfOn:
1438 RT_TRACE(COMP_PS,
1439 "_rtl92e_set_rf_power_state() eRfOn!\n");
1440 if ((priv->rtllib->eRFPowerState == eRfOff) &&
1441 RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) {
1442 bool rtstatus = true;
1443 u32 InitilizeCount = 3;
1444
1445 do {
1446 InitilizeCount--;
1447 priv->RegRfOff = false;
1448 rtstatus = rtl92e_enable_nic(dev);
1449 } while (!rtstatus && (InitilizeCount > 0));
1450
1451 if (!rtstatus) {
1452 netdev_err(dev,
1453 "%s(): Failed to initialize Adapter.\n",
1454 __func__);
1455 priv->SetRFPowerStateInProgress = false;
1456 return false;
1457 }
1458
1459 RT_CLEAR_PS_LEVEL(pPSC,
1460 RT_RF_OFF_LEVL_HALT_NIC);
1461 } else {
1462 rtl92e_writeb(dev, ANAPAR, 0x37);
1463 mdelay(1);
1464 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1,
1465 0x4, 0x1);
1466 priv->bHwRfOffAction = 0;
1467
1468 rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE,
1469 BIT4, 0x1);
1470 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter4,
1471 0x300, 0x3);
1472 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1,
1473 0x18, 0x3);
1474 rtl92e_set_bb_reg(dev, rOFDM0_TRxPathEnable,
1475 0x3, 0x3);
1476 rtl92e_set_bb_reg(dev, rOFDM1_TRxPathEnable,
1477 0x3, 0x3);
1478 rtl92e_set_bb_reg(dev, rFPGA0_AnalogParameter1,
1479 0x60, 0x3);
1480
1481 }
1482
1483 break;
1484
1485 case eRfSleep:
1486 if (priv->rtllib->eRFPowerState == eRfOff)
1487 break;
1488
1489
1490 for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
1491 ring = &priv->tx_ring[QueueID];
1492
1493 if (skb_queue_len(&ring->queue) == 0) {
1494 QueueID++;
1495 continue;
1496 } else {
1497 RT_TRACE((COMP_POWER|COMP_RF),
1498 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n",
1499 (i+1), QueueID);
1500 udelay(10);
1501 i++;
1502 }
1503
1504 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
1505 RT_TRACE(COMP_POWER,
1506 "\n\n\n TimeOut!! _rtl92e_set_rf_power_state(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n",
1507 MAX_DOZE_WAITING_TIMES_9x,
1508 QueueID);
1509 break;
1510 }
1511 }
1512 rtl92e_set_rf_off(dev);
1513 break;
1514
1515 case eRfOff:
1516 RT_TRACE(COMP_PS,
1517 "_rtl92e_set_rf_power_state() eRfOff/Sleep !\n");
1518
1519 for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
1520 ring = &priv->tx_ring[QueueID];
1521
1522 if (skb_queue_len(&ring->queue) == 0) {
1523 QueueID++;
1524 continue;
1525 } else {
1526 RT_TRACE(COMP_POWER,
1527 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n",
1528 (i+1), QueueID);
1529 udelay(10);
1530 i++;
1531 }
1532
1533 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
1534 RT_TRACE(COMP_POWER,
1535 "\n\n\n SetZebra: RFPowerState8185B(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n",
1536 MAX_DOZE_WAITING_TIMES_9x,
1537 QueueID);
1538 break;
1539 }
1540 }
1541
1542 if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC &&
1543 !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) {
1544 rtl92e_disable_nic(dev);
1545 RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
1546 } else if (!(pPSC->RegRfPsLevel &
1547 RT_RF_OFF_LEVL_HALT_NIC)) {
1548 rtl92e_set_rf_off(dev);
1549 }
1550
1551 break;
1552
1553 default:
1554 bResult = false;
1555 netdev_warn(dev,
1556 "%s(): Unknown state requested: 0x%X.\n",
1557 __func__, eRFPowerState);
1558 break;
1559 }
1560
1561 break;
1562
1563 default:
1564 netdev_warn(dev, "%s(): Unknown RF type\n", __func__);
1565 break;
1566 }
1567
1568 if (bResult) {
1569 priv->rtllib->eRFPowerState = eRFPowerState;
1570
1571 switch (priv->rf_chip) {
1572 case RF_8256:
1573 break;
1574
1575 default:
1576 netdev_warn(dev, "%s(): Unknown RF type\n", __func__);
1577 break;
1578 }
1579 }
1580
1581 priv->SetRFPowerStateInProgress = false;
1582 RT_TRACE(COMP_PS,
1583 "<=========== _rtl92e_set_rf_power_state() bResult = %d!\n",
1584 bResult);
1585 return bResult;
1586 }
1587
rtl92e_set_rf_power_state(struct net_device * dev,enum rt_rf_power_state eRFPowerState)1588 bool rtl92e_set_rf_power_state(struct net_device *dev,
1589 enum rt_rf_power_state eRFPowerState)
1590 {
1591 struct r8192_priv *priv = rtllib_priv(dev);
1592
1593 bool bResult = false;
1594
1595 RT_TRACE(COMP_PS,
1596 "---------> rtl92e_set_rf_power_state(): eRFPowerState(%d)\n",
1597 eRFPowerState);
1598 if (eRFPowerState == priv->rtllib->eRFPowerState &&
1599 priv->bHwRfOffAction == 0) {
1600 RT_TRACE(COMP_PS,
1601 "<--------- rtl92e_set_rf_power_state(): discard the request for eRFPowerState(%d) is the same.\n",
1602 eRFPowerState);
1603 return bResult;
1604 }
1605
1606 bResult = _rtl92e_set_rf_power_state(dev, eRFPowerState);
1607
1608 RT_TRACE(COMP_PS,
1609 "<--------- rtl92e_set_rf_power_state(): bResult(%d)\n",
1610 bResult);
1611
1612 return bResult;
1613 }
1614
rtl92e_scan_op_backup(struct net_device * dev,u8 Operation)1615 void rtl92e_scan_op_backup(struct net_device *dev, u8 Operation)
1616 {
1617 struct r8192_priv *priv = rtllib_priv(dev);
1618
1619 if (priv->up) {
1620 switch (Operation) {
1621 case SCAN_OPT_BACKUP:
1622 priv->rtllib->InitialGainHandler(dev, IG_Backup);
1623 break;
1624
1625 case SCAN_OPT_RESTORE:
1626 priv->rtllib->InitialGainHandler(dev, IG_Restore);
1627 break;
1628
1629 default:
1630 RT_TRACE(COMP_SCAN, "Unknown Scan Backup Operation.\n");
1631 break;
1632 }
1633 }
1634
1635 }
1636
