1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * RTL8XXXU mac80211 USB driver
4 *
5 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
6 *
7 * Portions, notably calibration code:
8 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
9 *
10 * This driver was written as a replacement for the vendor provided
11 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
12 * their programming interface, I have started adding support for
13 * additional 8xxx chips like the 8192cu, 8188cus, etc.
14 */
15
16 #include <linux/init.h>
17 #include <linux/kernel.h>
18 #include <linux/sched.h>
19 #include <linux/errno.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/list.h>
24 #include <linux/usb.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/ethtool.h>
28 #include <linux/wireless.h>
29 #include <linux/firmware.h>
30 #include <linux/moduleparam.h>
31 #include <net/mac80211.h>
32 #include "rtl8xxxu.h"
33 #include "rtl8xxxu_regs.h"
34
35 #define DRIVER_NAME "rtl8xxxu"
36
37 int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
38 static bool rtl8xxxu_ht40_2g;
39 static bool rtl8xxxu_dma_aggregation;
40 static int rtl8xxxu_dma_agg_timeout = -1;
41 static int rtl8xxxu_dma_agg_pages = -1;
42
43 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@gmail.com>");
44 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
45 MODULE_LICENSE("GPL");
46 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
47 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
48 MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
49 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
50 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
51 MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
52 MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
53 MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
54 MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
55
56 module_param_named(debug, rtl8xxxu_debug, int, 0600);
57 MODULE_PARM_DESC(debug, "Set debug mask");
58 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
59 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
60 module_param_named(dma_aggregation, rtl8xxxu_dma_aggregation, bool, 0600);
61 MODULE_PARM_DESC(dma_aggregation, "Enable DMA packet aggregation");
62 module_param_named(dma_agg_timeout, rtl8xxxu_dma_agg_timeout, int, 0600);
63 MODULE_PARM_DESC(dma_agg_timeout, "Set DMA aggregation timeout (range 1-127)");
64 module_param_named(dma_agg_pages, rtl8xxxu_dma_agg_pages, int, 0600);
65 MODULE_PARM_DESC(dma_agg_pages, "Set DMA aggregation pages (range 1-127, 0 to disable)");
66
67 #define USB_VENDOR_ID_REALTEK 0x0bda
68 #define RTL8XXXU_RX_URBS 32
69 #define RTL8XXXU_RX_URB_PENDING_WATER 8
70 #define RTL8XXXU_TX_URBS 64
71 #define RTL8XXXU_TX_URB_LOW_WATER 25
72 #define RTL8XXXU_TX_URB_HIGH_WATER 32
73
74 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
75 struct rtl8xxxu_rx_urb *rx_urb);
76
77 static struct ieee80211_rate rtl8xxxu_rates[] = {
78 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
79 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
80 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
81 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
82 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
83 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
84 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
85 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
86 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
87 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
88 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
89 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
90 };
91
92 static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
93 { .band = NL80211_BAND_2GHZ, .center_freq = 2412,
94 .hw_value = 1, .max_power = 30 },
95 { .band = NL80211_BAND_2GHZ, .center_freq = 2417,
96 .hw_value = 2, .max_power = 30 },
97 { .band = NL80211_BAND_2GHZ, .center_freq = 2422,
98 .hw_value = 3, .max_power = 30 },
99 { .band = NL80211_BAND_2GHZ, .center_freq = 2427,
100 .hw_value = 4, .max_power = 30 },
101 { .band = NL80211_BAND_2GHZ, .center_freq = 2432,
102 .hw_value = 5, .max_power = 30 },
103 { .band = NL80211_BAND_2GHZ, .center_freq = 2437,
104 .hw_value = 6, .max_power = 30 },
105 { .band = NL80211_BAND_2GHZ, .center_freq = 2442,
106 .hw_value = 7, .max_power = 30 },
107 { .band = NL80211_BAND_2GHZ, .center_freq = 2447,
108 .hw_value = 8, .max_power = 30 },
109 { .band = NL80211_BAND_2GHZ, .center_freq = 2452,
110 .hw_value = 9, .max_power = 30 },
111 { .band = NL80211_BAND_2GHZ, .center_freq = 2457,
112 .hw_value = 10, .max_power = 30 },
113 { .band = NL80211_BAND_2GHZ, .center_freq = 2462,
114 .hw_value = 11, .max_power = 30 },
115 { .band = NL80211_BAND_2GHZ, .center_freq = 2467,
116 .hw_value = 12, .max_power = 30 },
117 { .band = NL80211_BAND_2GHZ, .center_freq = 2472,
118 .hw_value = 13, .max_power = 30 },
119 { .band = NL80211_BAND_2GHZ, .center_freq = 2484,
120 .hw_value = 14, .max_power = 30 }
121 };
122
123 static struct ieee80211_supported_band rtl8xxxu_supported_band = {
124 .channels = rtl8xxxu_channels_2g,
125 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
126 .bitrates = rtl8xxxu_rates,
127 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
128 };
129
130 struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[] = {
131 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
132 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
133 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
134 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
135 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
136 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
137 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
138 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
139 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
140 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
141 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
142 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
143 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
144 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
145 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
146 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
147 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
148 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
149 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
150 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
151 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
152 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
153 };
154
155 static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
156 {0x800, 0x80040000}, {0x804, 0x00000003},
157 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
158 {0x810, 0x10001331}, {0x814, 0x020c3d10},
159 {0x818, 0x02200385}, {0x81c, 0x00000000},
160 {0x820, 0x01000100}, {0x824, 0x00390004},
161 {0x828, 0x00000000}, {0x82c, 0x00000000},
162 {0x830, 0x00000000}, {0x834, 0x00000000},
163 {0x838, 0x00000000}, {0x83c, 0x00000000},
164 {0x840, 0x00010000}, {0x844, 0x00000000},
165 {0x848, 0x00000000}, {0x84c, 0x00000000},
166 {0x850, 0x00000000}, {0x854, 0x00000000},
167 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
168 {0x860, 0x66f60110}, {0x864, 0x061f0130},
169 {0x868, 0x00000000}, {0x86c, 0x32323200},
170 {0x870, 0x07000760}, {0x874, 0x22004000},
171 {0x878, 0x00000808}, {0x87c, 0x00000000},
172 {0x880, 0xc0083070}, {0x884, 0x000004d5},
173 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
174 {0x890, 0x00000800}, {0x894, 0xfffffffe},
175 {0x898, 0x40302010}, {0x89c, 0x00706050},
176 {0x900, 0x00000000}, {0x904, 0x00000023},
177 {0x908, 0x00000000}, {0x90c, 0x81121111},
178 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
179 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
180 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
181 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
182 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
183 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
184 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
185 {0xa78, 0x00000900},
186 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
187 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
188 {0xc10, 0x08800000}, {0xc14, 0x40000100},
189 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
190 {0xc20, 0x00000000}, {0xc24, 0x00000000},
191 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
192 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
193 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
194 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
195 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
196 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
197 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
198 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
199 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
200 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
201 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
202 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
203 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
204 {0xc90, 0x00121820}, {0xc94, 0x00000000},
205 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
206 {0xca0, 0x00000000}, {0xca4, 0x00000080},
207 {0xca8, 0x00000000}, {0xcac, 0x00000000},
208 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
209 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
210 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
211 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
212 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
213 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
214 {0xce0, 0x00222222}, {0xce4, 0x00000000},
215 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
216 {0xd00, 0x00080740}, {0xd04, 0x00020401},
217 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
218 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
219 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
220 {0xd30, 0x00000000}, {0xd34, 0x80608000},
221 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
222 {0xd40, 0x00000000}, {0xd44, 0x00000000},
223 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
224 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
225 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
226 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
227 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
228 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
229 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
230 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
231 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
232 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
233 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
234 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
235 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
236 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
237 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
238 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
239 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
240 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
241 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
242 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
243 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
244 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
245 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
246 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
247 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
248 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
249 {0xf00, 0x00000300},
250 {0xffff, 0xffffffff},
251 };
252
253 static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
254 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
255 {0x800, 0x80040002}, {0x804, 0x00000003},
256 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
257 {0x810, 0x10000330}, {0x814, 0x020c3d10},
258 {0x818, 0x02200385}, {0x81c, 0x00000000},
259 {0x820, 0x01000100}, {0x824, 0x00390004},
260 {0x828, 0x01000100}, {0x82c, 0x00390004},
261 {0x830, 0x27272727}, {0x834, 0x27272727},
262 {0x838, 0x27272727}, {0x83c, 0x27272727},
263 {0x840, 0x00010000}, {0x844, 0x00010000},
264 {0x848, 0x27272727}, {0x84c, 0x27272727},
265 {0x850, 0x00000000}, {0x854, 0x00000000},
266 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
267 {0x860, 0x66e60230}, {0x864, 0x061f0130},
268 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
269 {0x870, 0x07000700}, {0x874, 0x22184000},
270 {0x878, 0x08080808}, {0x87c, 0x00000000},
271 {0x880, 0xc0083070}, {0x884, 0x000004d5},
272 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
273 {0x890, 0x00000800}, {0x894, 0xfffffffe},
274 {0x898, 0x40302010}, {0x89c, 0x00706050},
275 {0x900, 0x00000000}, {0x904, 0x00000023},
276 {0x908, 0x00000000}, {0x90c, 0x81121313},
277 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
278 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
279 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
280 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
281 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
282 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
283 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
284 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
285 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
286 {0xc10, 0x08800000}, {0xc14, 0x40000100},
287 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
288 {0xc20, 0x00000000}, {0xc24, 0x00000000},
289 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
290 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
291 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
292 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
293 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
294 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
295 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
296 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
297 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
298 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
299 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
300 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
301 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
302 {0xc90, 0x00121820}, {0xc94, 0x00000000},
303 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
304 {0xca0, 0x00000000}, {0xca4, 0x00000080},
305 {0xca8, 0x00000000}, {0xcac, 0x00000000},
306 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
307 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
308 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
309 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
310 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
311 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
312 {0xce0, 0x00222222}, {0xce4, 0x00000000},
313 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
314 {0xd00, 0x00080740}, {0xd04, 0x00020403},
315 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
316 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
317 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
318 {0xd30, 0x00000000}, {0xd34, 0x80608000},
319 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
320 {0xd40, 0x00000000}, {0xd44, 0x00000000},
321 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
322 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
323 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
324 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
325 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
326 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
327 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
328 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
329 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
330 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
331 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
332 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
333 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
334 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
335 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
336 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
337 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
338 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
339 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
340 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
341 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
342 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
343 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
344 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
345 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
346 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
347 {0xf00, 0x00000300},
348 {0xffff, 0xffffffff},
349 };
350
351 static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
352 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
353 {0x040, 0x000c0004}, {0x800, 0x80040000},
354 {0x804, 0x00000001}, {0x808, 0x0000fc00},
355 {0x80c, 0x0000000a}, {0x810, 0x10005388},
356 {0x814, 0x020c3d10}, {0x818, 0x02200385},
357 {0x81c, 0x00000000}, {0x820, 0x01000100},
358 {0x824, 0x00390204}, {0x828, 0x00000000},
359 {0x82c, 0x00000000}, {0x830, 0x00000000},
360 {0x834, 0x00000000}, {0x838, 0x00000000},
361 {0x83c, 0x00000000}, {0x840, 0x00010000},
362 {0x844, 0x00000000}, {0x848, 0x00000000},
363 {0x84c, 0x00000000}, {0x850, 0x00000000},
364 {0x854, 0x00000000}, {0x858, 0x569a569a},
365 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
366 {0x864, 0x061f0130}, {0x868, 0x00000000},
367 {0x86c, 0x20202000}, {0x870, 0x03000300},
368 {0x874, 0x22004000}, {0x878, 0x00000808},
369 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
370 {0x884, 0x000004d5}, {0x888, 0x00000000},
371 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
372 {0x894, 0xfffffffe}, {0x898, 0x40302010},
373 {0x89c, 0x00706050}, {0x900, 0x00000000},
374 {0x904, 0x00000023}, {0x908, 0x00000000},
375 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
376 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
377 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
378 {0xa14, 0x11144028}, {0xa18, 0x00881117},
379 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
380 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
381 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
382 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
383 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
384 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
385 {0xc14, 0x40000100}, {0xc18, 0x08800000},
386 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
387 {0xc24, 0x00000000}, {0xc28, 0x00000000},
388 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
389 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
390 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
391 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
392 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
393 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
394 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
395 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
396 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
397 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
398 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
399 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
400 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
401 {0xc94, 0x00000000}, {0xc98, 0x00121820},
402 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
403 {0xca4, 0x00000080}, {0xca8, 0x00000000},
404 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
405 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
406 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
407 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
408 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
409 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
410 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
411 {0xce4, 0x00000000}, {0xce8, 0x37644302},
412 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
413 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
414 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
415 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
416 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
417 {0xd34, 0x80608000}, {0xd38, 0x00000000},
418 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
419 {0xd44, 0x00000000}, {0xd48, 0x00000000},
420 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
421 {0xd54, 0x00000000}, {0xd58, 0x00000000},
422 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
423 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
424 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
425 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
426 {0xe00, 0x24242424}, {0xe04, 0x24242424},
427 {0xe08, 0x03902024}, {0xe10, 0x24242424},
428 {0xe14, 0x24242424}, {0xe18, 0x24242424},
429 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
430 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
431 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
432 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
433 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
434 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
435 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
436 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
437 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
438 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
439 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
440 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
441 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
442 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
443 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
444 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
445 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
446 {0xf00, 0x00000300},
447 {0xffff, 0xffffffff},
448 };
449
450 static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
451 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
452 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
453 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
454 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
455 {0xc78, 0x78080001}, {0xc78, 0x77090001},
456 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
457 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
458 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
459 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
460 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
461 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
462 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
463 {0xc78, 0x68180001}, {0xc78, 0x67190001},
464 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
465 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
466 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
467 {0xc78, 0x60200001}, {0xc78, 0x49210001},
468 {0xc78, 0x48220001}, {0xc78, 0x47230001},
469 {0xc78, 0x46240001}, {0xc78, 0x45250001},
470 {0xc78, 0x44260001}, {0xc78, 0x43270001},
471 {0xc78, 0x42280001}, {0xc78, 0x41290001},
472 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
473 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
474 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
475 {0xc78, 0x21300001}, {0xc78, 0x20310001},
476 {0xc78, 0x06320001}, {0xc78, 0x05330001},
477 {0xc78, 0x04340001}, {0xc78, 0x03350001},
478 {0xc78, 0x02360001}, {0xc78, 0x01370001},
479 {0xc78, 0x00380001}, {0xc78, 0x00390001},
480 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
481 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
482 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
483 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
484 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
485 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
486 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
487 {0xc78, 0x78480001}, {0xc78, 0x77490001},
488 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
489 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
490 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
491 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
492 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
493 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
494 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
495 {0xc78, 0x68580001}, {0xc78, 0x67590001},
496 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
497 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
498 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
499 {0xc78, 0x60600001}, {0xc78, 0x49610001},
500 {0xc78, 0x48620001}, {0xc78, 0x47630001},
501 {0xc78, 0x46640001}, {0xc78, 0x45650001},
502 {0xc78, 0x44660001}, {0xc78, 0x43670001},
503 {0xc78, 0x42680001}, {0xc78, 0x41690001},
504 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
505 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
506 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
507 {0xc78, 0x21700001}, {0xc78, 0x20710001},
508 {0xc78, 0x06720001}, {0xc78, 0x05730001},
509 {0xc78, 0x04740001}, {0xc78, 0x03750001},
510 {0xc78, 0x02760001}, {0xc78, 0x01770001},
511 {0xc78, 0x00780001}, {0xc78, 0x00790001},
512 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
513 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
514 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
515 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
516 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
517 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
518 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
519 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
520 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
521 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
522 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
523 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
524 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
525 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
526 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
527 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
528 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
529 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
530 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
531 {0xffff, 0xffffffff}
532 };
533
534 static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
535 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
536 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
537 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
538 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
539 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
540 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
541 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
542 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
543 {0xc78, 0x73100001}, {0xc78, 0x72110001},
544 {0xc78, 0x71120001}, {0xc78, 0x70130001},
545 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
546 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
547 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
548 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
549 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
550 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
551 {0xc78, 0x63200001}, {0xc78, 0x62210001},
552 {0xc78, 0x61220001}, {0xc78, 0x60230001},
553 {0xc78, 0x46240001}, {0xc78, 0x45250001},
554 {0xc78, 0x44260001}, {0xc78, 0x43270001},
555 {0xc78, 0x42280001}, {0xc78, 0x41290001},
556 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
557 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
558 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
559 {0xc78, 0x21300001}, {0xc78, 0x20310001},
560 {0xc78, 0x06320001}, {0xc78, 0x05330001},
561 {0xc78, 0x04340001}, {0xc78, 0x03350001},
562 {0xc78, 0x02360001}, {0xc78, 0x01370001},
563 {0xc78, 0x00380001}, {0xc78, 0x00390001},
564 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
565 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
566 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
567 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
568 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
569 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
570 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
571 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
572 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
573 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
574 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
575 {0xc78, 0x73500001}, {0xc78, 0x72510001},
576 {0xc78, 0x71520001}, {0xc78, 0x70530001},
577 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
578 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
579 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
580 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
581 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
582 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
583 {0xc78, 0x63600001}, {0xc78, 0x62610001},
584 {0xc78, 0x61620001}, {0xc78, 0x60630001},
585 {0xc78, 0x46640001}, {0xc78, 0x45650001},
586 {0xc78, 0x44660001}, {0xc78, 0x43670001},
587 {0xc78, 0x42680001}, {0xc78, 0x41690001},
588 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
589 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
590 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
591 {0xc78, 0x21700001}, {0xc78, 0x20710001},
592 {0xc78, 0x06720001}, {0xc78, 0x05730001},
593 {0xc78, 0x04740001}, {0xc78, 0x03750001},
594 {0xc78, 0x02760001}, {0xc78, 0x01770001},
595 {0xc78, 0x00780001}, {0xc78, 0x00790001},
596 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
597 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
598 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
599 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
600 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
601 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
602 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
603 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
604 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
605 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
606 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
607 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
608 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
609 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
610 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
611 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
612 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
613 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
614 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
615 {0xffff, 0xffffffff}
616 };
617
618 static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
619 { /* RF_A */
620 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
621 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
622 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
623 .hspiread = REG_HSPI_XA_READBACK,
624 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
625 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
626 },
627 { /* RF_B */
628 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
629 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
630 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
631 .hspiread = REG_HSPI_XB_READBACK,
632 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
633 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
634 },
635 };
636
637 const u32 rtl8xxxu_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
638 REG_OFDM0_XA_RX_IQ_IMBALANCE,
639 REG_OFDM0_XB_RX_IQ_IMBALANCE,
640 REG_OFDM0_ENERGY_CCA_THRES,
641 REG_OFDM0_AGCR_SSI_TABLE,
642 REG_OFDM0_XA_TX_IQ_IMBALANCE,
643 REG_OFDM0_XB_TX_IQ_IMBALANCE,
644 REG_OFDM0_XC_TX_AFE,
645 REG_OFDM0_XD_TX_AFE,
646 REG_OFDM0_RX_IQ_EXT_ANTA
647 };
648
rtl8xxxu_read8(struct rtl8xxxu_priv * priv,u16 addr)649 u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
650 {
651 struct usb_device *udev = priv->udev;
652 int len;
653 u8 data;
654
655 mutex_lock(&priv->usb_buf_mutex);
656 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
657 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
658 addr, 0, &priv->usb_buf.val8, sizeof(u8),
659 RTW_USB_CONTROL_MSG_TIMEOUT);
660 data = priv->usb_buf.val8;
661 mutex_unlock(&priv->usb_buf_mutex);
662
663 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
664 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n",
665 __func__, addr, data, len);
666 return data;
667 }
668
rtl8xxxu_read16(struct rtl8xxxu_priv * priv,u16 addr)669 u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
670 {
671 struct usb_device *udev = priv->udev;
672 int len;
673 u16 data;
674
675 mutex_lock(&priv->usb_buf_mutex);
676 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
677 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
678 addr, 0, &priv->usb_buf.val16, sizeof(u16),
679 RTW_USB_CONTROL_MSG_TIMEOUT);
680 data = le16_to_cpu(priv->usb_buf.val16);
681 mutex_unlock(&priv->usb_buf_mutex);
682
683 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
684 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n",
685 __func__, addr, data, len);
686 return data;
687 }
688
rtl8xxxu_read32(struct rtl8xxxu_priv * priv,u16 addr)689 u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
690 {
691 struct usb_device *udev = priv->udev;
692 int len;
693 u32 data;
694
695 mutex_lock(&priv->usb_buf_mutex);
696 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
697 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
698 addr, 0, &priv->usb_buf.val32, sizeof(u32),
699 RTW_USB_CONTROL_MSG_TIMEOUT);
700 data = le32_to_cpu(priv->usb_buf.val32);
701 mutex_unlock(&priv->usb_buf_mutex);
702
703 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
704 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n",
705 __func__, addr, data, len);
706 return data;
707 }
708
rtl8xxxu_write8(struct rtl8xxxu_priv * priv,u16 addr,u8 val)709 int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
710 {
711 struct usb_device *udev = priv->udev;
712 int ret;
713
714 mutex_lock(&priv->usb_buf_mutex);
715 priv->usb_buf.val8 = val;
716 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
717 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
718 addr, 0, &priv->usb_buf.val8, sizeof(u8),
719 RTW_USB_CONTROL_MSG_TIMEOUT);
720
721 mutex_unlock(&priv->usb_buf_mutex);
722
723 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
724 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
725 __func__, addr, val);
726 return ret;
727 }
728
rtl8xxxu_write16(struct rtl8xxxu_priv * priv,u16 addr,u16 val)729 int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
730 {
731 struct usb_device *udev = priv->udev;
732 int ret;
733
734 mutex_lock(&priv->usb_buf_mutex);
735 priv->usb_buf.val16 = cpu_to_le16(val);
736 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
737 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
738 addr, 0, &priv->usb_buf.val16, sizeof(u16),
739 RTW_USB_CONTROL_MSG_TIMEOUT);
740 mutex_unlock(&priv->usb_buf_mutex);
741
742 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
743 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
744 __func__, addr, val);
745 return ret;
746 }
747
rtl8xxxu_write32(struct rtl8xxxu_priv * priv,u16 addr,u32 val)748 int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
749 {
750 struct usb_device *udev = priv->udev;
751 int ret;
752
753 mutex_lock(&priv->usb_buf_mutex);
754 priv->usb_buf.val32 = cpu_to_le32(val);
755 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
756 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
757 addr, 0, &priv->usb_buf.val32, sizeof(u32),
758 RTW_USB_CONTROL_MSG_TIMEOUT);
759 mutex_unlock(&priv->usb_buf_mutex);
760
761 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
762 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
763 __func__, addr, val);
764 return ret;
765 }
766
767 static int
rtl8xxxu_writeN(struct rtl8xxxu_priv * priv,u16 addr,u8 * buf,u16 len)768 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
769 {
770 struct usb_device *udev = priv->udev;
771 int blocksize = priv->fops->writeN_block_size;
772 int ret, i, count, remainder;
773
774 count = len / blocksize;
775 remainder = len % blocksize;
776
777 for (i = 0; i < count; i++) {
778 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
779 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
780 addr, 0, buf, blocksize,
781 RTW_USB_CONTROL_MSG_TIMEOUT);
782 if (ret != blocksize)
783 goto write_error;
784
785 addr += blocksize;
786 buf += blocksize;
787 }
788
789 if (remainder) {
790 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
791 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
792 addr, 0, buf, remainder,
793 RTW_USB_CONTROL_MSG_TIMEOUT);
794 if (ret != remainder)
795 goto write_error;
796 }
797
798 return len;
799
800 write_error:
801 dev_info(&udev->dev,
802 "%s: Failed to write block at addr: %04x size: %04x\n",
803 __func__, addr, blocksize);
804 return -EAGAIN;
805 }
806
rtl8xxxu_read_rfreg(struct rtl8xxxu_priv * priv,enum rtl8xxxu_rfpath path,u8 reg)807 u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
808 enum rtl8xxxu_rfpath path, u8 reg)
809 {
810 u32 hssia, val32, retval;
811
812 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
813 if (path != RF_A)
814 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
815 else
816 val32 = hssia;
817
818 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
819 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
820 val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
821 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
822 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
823
824 udelay(10);
825
826 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
827 udelay(100);
828
829 hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
830 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
831 udelay(10);
832
833 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
834 if (val32 & FPGA0_HSSI_PARM1_PI)
835 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
836 else
837 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
838
839 retval &= 0xfffff;
840
841 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
842 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
843 __func__, reg, retval);
844 return retval;
845 }
846
847 /*
848 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
849 * have write issues in high temperature conditions. We may have to
850 * retry writing them.
851 */
rtl8xxxu_write_rfreg(struct rtl8xxxu_priv * priv,enum rtl8xxxu_rfpath path,u8 reg,u32 data)852 int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
853 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
854 {
855 int ret, retval;
856 u32 dataaddr, val32;
857
858 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
859 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
860 __func__, reg, data);
861
862 data &= FPGA0_LSSI_PARM_DATA_MASK;
863 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
864
865 if (priv->rtl_chip == RTL8192E) {
866 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
867 val32 &= ~0x20000;
868 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
869 }
870
871 /* Use XB for path B */
872 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
873 if (ret != sizeof(dataaddr))
874 retval = -EIO;
875 else
876 retval = 0;
877
878 udelay(1);
879
880 if (priv->rtl_chip == RTL8192E) {
881 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
882 val32 |= 0x20000;
883 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
884 }
885
886 return retval;
887 }
888
889 static int
rtl8xxxu_gen1_h2c_cmd(struct rtl8xxxu_priv * priv,struct h2c_cmd * h2c,int len)890 rtl8xxxu_gen1_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len)
891 {
892 struct device *dev = &priv->udev->dev;
893 int mbox_nr, retry, retval = 0;
894 int mbox_reg, mbox_ext_reg;
895 u8 val8;
896
897 mutex_lock(&priv->h2c_mutex);
898
899 mbox_nr = priv->next_mbox;
900 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
901 mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2);
902
903 /*
904 * MBOX ready?
905 */
906 retry = 100;
907 do {
908 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
909 if (!(val8 & BIT(mbox_nr)))
910 break;
911 } while (retry--);
912
913 if (!retry) {
914 dev_info(dev, "%s: Mailbox busy\n", __func__);
915 retval = -EBUSY;
916 goto error;
917 }
918
919 /*
920 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
921 */
922 if (len > sizeof(u32)) {
923 rtl8xxxu_write16(priv, mbox_ext_reg, le16_to_cpu(h2c->raw.ext));
924 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
925 dev_info(dev, "H2C_EXT %04x\n",
926 le16_to_cpu(h2c->raw.ext));
927 }
928 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
929 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
930 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
931
932 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
933
934 error:
935 mutex_unlock(&priv->h2c_mutex);
936 return retval;
937 }
938
939 int
rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv * priv,struct h2c_cmd * h2c,int len)940 rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len)
941 {
942 struct device *dev = &priv->udev->dev;
943 int mbox_nr, retry, retval = 0;
944 int mbox_reg, mbox_ext_reg;
945 u8 val8;
946
947 mutex_lock(&priv->h2c_mutex);
948
949 mbox_nr = priv->next_mbox;
950 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
951 mbox_ext_reg = REG_HMBOX_EXT0_8723B + (mbox_nr * 4);
952
953 /*
954 * MBOX ready?
955 */
956 retry = 100;
957 do {
958 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
959 if (!(val8 & BIT(mbox_nr)))
960 break;
961 } while (retry--);
962
963 if (!retry) {
964 dev_info(dev, "%s: Mailbox busy\n", __func__);
965 retval = -EBUSY;
966 goto error;
967 }
968
969 /*
970 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
971 */
972 if (len > sizeof(u32)) {
973 rtl8xxxu_write32(priv, mbox_ext_reg,
974 le32_to_cpu(h2c->raw_wide.ext));
975 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
976 dev_info(dev, "H2C_EXT %08x\n",
977 le32_to_cpu(h2c->raw_wide.ext));
978 }
979 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
980 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
981 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
982
983 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
984
985 error:
986 mutex_unlock(&priv->h2c_mutex);
987 return retval;
988 }
989
rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv * priv)990 void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv)
991 {
992 u8 val8;
993 u32 val32;
994
995 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
996 val8 |= BIT(0) | BIT(3);
997 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
998
999 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1000 val32 &= ~(BIT(4) | BIT(5));
1001 val32 |= BIT(3);
1002 if (priv->rf_paths == 2) {
1003 val32 &= ~(BIT(20) | BIT(21));
1004 val32 |= BIT(19);
1005 }
1006 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1007
1008 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1009 val32 &= ~OFDM_RF_PATH_TX_MASK;
1010 if (priv->tx_paths == 2)
1011 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1012 else if (priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C)
1013 val32 |= OFDM_RF_PATH_TX_B;
1014 else
1015 val32 |= OFDM_RF_PATH_TX_A;
1016 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1017
1018 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1019 val32 &= ~FPGA_RF_MODE_JAPAN;
1020 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1021
1022 if (priv->rf_paths == 2)
1023 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1024 else
1025 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1026
1027 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1028 if (priv->rf_paths == 2)
1029 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1030
1031 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1032 }
1033
rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv * priv)1034 void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv)
1035 {
1036 u8 sps0;
1037 u32 val32;
1038
1039 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1040
1041 /* RF RX code for preamble power saving */
1042 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1043 val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1044 if (priv->rf_paths == 2)
1045 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1046 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1047
1048 /* Disable TX for four paths */
1049 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1050 val32 &= ~OFDM_RF_PATH_TX_MASK;
1051 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1052
1053 /* Enable power saving */
1054 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1055 val32 |= FPGA_RF_MODE_JAPAN;
1056 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1057
1058 /* AFE control register to power down bits [30:22] */
1059 if (priv->rf_paths == 2)
1060 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1061 else
1062 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1063
1064 /* Power down RF module */
1065 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1066 if (priv->rf_paths == 2)
1067 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1068
1069 sps0 &= ~(BIT(0) | BIT(3));
1070 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1071 }
1072
rtl8xxxu_stop_tx_beacon(struct rtl8xxxu_priv * priv)1073 static void rtl8xxxu_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1074 {
1075 u8 val8;
1076
1077 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1078 val8 &= ~BIT(6);
1079 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1080
1081 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1082 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1083 val8 &= ~BIT(0);
1084 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1085 }
1086
1087
1088 /*
1089 * The rtl8723a has 3 channel groups for it's efuse settings. It only
1090 * supports the 2.4GHz band, so channels 1 - 14:
1091 * group 0: channels 1 - 3
1092 * group 1: channels 4 - 9
1093 * group 2: channels 10 - 14
1094 *
1095 * Note: We index from 0 in the code
1096 */
rtl8xxxu_gen1_channel_to_group(int channel)1097 static int rtl8xxxu_gen1_channel_to_group(int channel)
1098 {
1099 int group;
1100
1101 if (channel < 4)
1102 group = 0;
1103 else if (channel < 10)
1104 group = 1;
1105 else
1106 group = 2;
1107
1108 return group;
1109 }
1110
1111 /*
1112 * Valid for rtl8723bu and rtl8192eu
1113 */
rtl8xxxu_gen2_channel_to_group(int channel)1114 int rtl8xxxu_gen2_channel_to_group(int channel)
1115 {
1116 int group;
1117
1118 if (channel < 3)
1119 group = 0;
1120 else if (channel < 6)
1121 group = 1;
1122 else if (channel < 9)
1123 group = 2;
1124 else if (channel < 12)
1125 group = 3;
1126 else
1127 group = 4;
1128
1129 return group;
1130 }
1131
rtl8xxxu_gen1_config_channel(struct ieee80211_hw * hw)1132 void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw)
1133 {
1134 struct rtl8xxxu_priv *priv = hw->priv;
1135 u32 val32, rsr;
1136 u8 val8, opmode;
1137 bool ht = true;
1138 int sec_ch_above, channel;
1139 int i;
1140
1141 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1142 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1143 channel = hw->conf.chandef.chan->hw_value;
1144
1145 switch (hw->conf.chandef.width) {
1146 case NL80211_CHAN_WIDTH_20_NOHT:
1147 ht = false;
1148 /* fall through */
1149 case NL80211_CHAN_WIDTH_20:
1150 opmode |= BW_OPMODE_20MHZ;
1151 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1152
1153 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1154 val32 &= ~FPGA_RF_MODE;
1155 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1156
1157 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1158 val32 &= ~FPGA_RF_MODE;
1159 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1160
1161 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1162 val32 |= FPGA0_ANALOG2_20MHZ;
1163 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1164 break;
1165 case NL80211_CHAN_WIDTH_40:
1166 if (hw->conf.chandef.center_freq1 >
1167 hw->conf.chandef.chan->center_freq) {
1168 sec_ch_above = 1;
1169 channel += 2;
1170 } else {
1171 sec_ch_above = 0;
1172 channel -= 2;
1173 }
1174
1175 opmode &= ~BW_OPMODE_20MHZ;
1176 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1177 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1178 if (sec_ch_above)
1179 rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1180 else
1181 rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1182 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1183
1184 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1185 val32 |= FPGA_RF_MODE;
1186 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1187
1188 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1189 val32 |= FPGA_RF_MODE;
1190 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1191
1192 /*
1193 * Set Control channel to upper or lower. These settings
1194 * are required only for 40MHz
1195 */
1196 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1197 val32 &= ~CCK0_SIDEBAND;
1198 if (!sec_ch_above)
1199 val32 |= CCK0_SIDEBAND;
1200 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1201
1202 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1203 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1204 if (sec_ch_above)
1205 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1206 else
1207 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1208 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1209
1210 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1211 val32 &= ~FPGA0_ANALOG2_20MHZ;
1212 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1213
1214 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1215 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1216 if (sec_ch_above)
1217 val32 |= FPGA0_PS_UPPER_CHANNEL;
1218 else
1219 val32 |= FPGA0_PS_LOWER_CHANNEL;
1220 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1221 break;
1222
1223 default:
1224 break;
1225 }
1226
1227 for (i = RF_A; i < priv->rf_paths; i++) {
1228 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1229 val32 &= ~MODE_AG_CHANNEL_MASK;
1230 val32 |= channel;
1231 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1232 }
1233
1234 if (ht)
1235 val8 = 0x0e;
1236 else
1237 val8 = 0x0a;
1238
1239 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1240 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1241
1242 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1243 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1244
1245 for (i = RF_A; i < priv->rf_paths; i++) {
1246 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1247 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1248 val32 &= ~MODE_AG_CHANNEL_20MHZ;
1249 else
1250 val32 |= MODE_AG_CHANNEL_20MHZ;
1251 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1252 }
1253 }
1254
rtl8xxxu_gen2_config_channel(struct ieee80211_hw * hw)1255 void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw)
1256 {
1257 struct rtl8xxxu_priv *priv = hw->priv;
1258 u32 val32, rsr;
1259 u8 val8, subchannel;
1260 u16 rf_mode_bw;
1261 bool ht = true;
1262 int sec_ch_above, channel;
1263 int i;
1264
1265 rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL);
1266 rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK;
1267 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1268 channel = hw->conf.chandef.chan->hw_value;
1269
1270 /* Hack */
1271 subchannel = 0;
1272
1273 switch (hw->conf.chandef.width) {
1274 case NL80211_CHAN_WIDTH_20_NOHT:
1275 ht = false;
1276 /* fall through */
1277 case NL80211_CHAN_WIDTH_20:
1278 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20;
1279 subchannel = 0;
1280
1281 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1282 val32 &= ~FPGA_RF_MODE;
1283 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1284
1285 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1286 val32 &= ~FPGA_RF_MODE;
1287 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1288
1289 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
1290 val32 &= ~(BIT(30) | BIT(31));
1291 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);
1292
1293 break;
1294 case NL80211_CHAN_WIDTH_40:
1295 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40;
1296
1297 if (hw->conf.chandef.center_freq1 >
1298 hw->conf.chandef.chan->center_freq) {
1299 sec_ch_above = 1;
1300 channel += 2;
1301 } else {
1302 sec_ch_above = 0;
1303 channel -= 2;
1304 }
1305
1306 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1307 val32 |= FPGA_RF_MODE;
1308 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1309
1310 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1311 val32 |= FPGA_RF_MODE;
1312 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1313
1314 /*
1315 * Set Control channel to upper or lower. These settings
1316 * are required only for 40MHz
1317 */
1318 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1319 val32 &= ~CCK0_SIDEBAND;
1320 if (!sec_ch_above)
1321 val32 |= CCK0_SIDEBAND;
1322 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1323
1324 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1325 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1326 if (sec_ch_above)
1327 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1328 else
1329 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1330 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1331
1332 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1333 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1334 if (sec_ch_above)
1335 val32 |= FPGA0_PS_UPPER_CHANNEL;
1336 else
1337 val32 |= FPGA0_PS_LOWER_CHANNEL;
1338 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1339 break;
1340 case NL80211_CHAN_WIDTH_80:
1341 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80;
1342 break;
1343 default:
1344 break;
1345 }
1346
1347 for (i = RF_A; i < priv->rf_paths; i++) {
1348 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1349 val32 &= ~MODE_AG_CHANNEL_MASK;
1350 val32 |= channel;
1351 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1352 }
1353
1354 rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw);
1355 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel);
1356
1357 if (ht)
1358 val8 = 0x0e;
1359 else
1360 val8 = 0x0a;
1361
1362 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1363 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1364
1365 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1366 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1367
1368 for (i = RF_A; i < priv->rf_paths; i++) {
1369 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1370 val32 &= ~MODE_AG_BW_MASK;
1371 switch(hw->conf.chandef.width) {
1372 case NL80211_CHAN_WIDTH_80:
1373 val32 |= MODE_AG_BW_80MHZ_8723B;
1374 break;
1375 case NL80211_CHAN_WIDTH_40:
1376 val32 |= MODE_AG_BW_40MHZ_8723B;
1377 break;
1378 default:
1379 val32 |= MODE_AG_BW_20MHZ_8723B;
1380 break;
1381 }
1382 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1383 }
1384 }
1385
1386 void
rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv * priv,int channel,bool ht40)1387 rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1388 {
1389 struct rtl8xxxu_power_base *power_base = priv->power_base;
1390 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1391 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1392 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1393 u8 val8;
1394 int group, i;
1395
1396 group = rtl8xxxu_gen1_channel_to_group(channel);
1397
1398 cck[0] = priv->cck_tx_power_index_A[group] - 1;
1399 cck[1] = priv->cck_tx_power_index_B[group] - 1;
1400
1401 if (priv->hi_pa) {
1402 if (cck[0] > 0x20)
1403 cck[0] = 0x20;
1404 if (cck[1] > 0x20)
1405 cck[1] = 0x20;
1406 }
1407
1408 ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1409 ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1410 if (ofdm[0])
1411 ofdm[0] -= 1;
1412 if (ofdm[1])
1413 ofdm[1] -= 1;
1414
1415 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1416 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1417
1418 mcsbase[0] = ofdm[0];
1419 mcsbase[1] = ofdm[1];
1420 if (!ht40) {
1421 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1422 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1423 }
1424
1425 if (priv->tx_paths > 1) {
1426 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1427 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a;
1428 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1429 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b;
1430 }
1431
1432 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1433 dev_info(&priv->udev->dev,
1434 "%s: Setting TX power CCK A: %02x, "
1435 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1436 __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1437
1438 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1439 if (cck[i] > RF6052_MAX_TX_PWR)
1440 cck[i] = RF6052_MAX_TX_PWR;
1441 if (ofdm[i] > RF6052_MAX_TX_PWR)
1442 ofdm[i] = RF6052_MAX_TX_PWR;
1443 }
1444
1445 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1446 val32 &= 0xffff00ff;
1447 val32 |= (cck[0] << 8);
1448 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
1449
1450 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1451 val32 &= 0xff;
1452 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
1453 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1454
1455 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1456 val32 &= 0xffffff00;
1457 val32 |= cck[1];
1458 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1459
1460 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1461 val32 &= 0xff;
1462 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
1463 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
1464
1465 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
1466 ofdmbase[0] << 16 | ofdmbase[0] << 24;
1467 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
1468 ofdmbase[1] << 16 | ofdmbase[1] << 24;
1469
1470 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06,
1471 ofdm_a + power_base->reg_0e00);
1472 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06,
1473 ofdm_b + power_base->reg_0830);
1474
1475 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24,
1476 ofdm_a + power_base->reg_0e04);
1477 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24,
1478 ofdm_b + power_base->reg_0834);
1479
1480 mcs_a = mcsbase[0] | mcsbase[0] << 8 |
1481 mcsbase[0] << 16 | mcsbase[0] << 24;
1482 mcs_b = mcsbase[1] | mcsbase[1] << 8 |
1483 mcsbase[1] << 16 | mcsbase[1] << 24;
1484
1485 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00,
1486 mcs_a + power_base->reg_0e10);
1487 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00,
1488 mcs_b + power_base->reg_083c);
1489
1490 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04,
1491 mcs_a + power_base->reg_0e14);
1492 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04,
1493 mcs_b + power_base->reg_0848);
1494
1495 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08,
1496 mcs_a + power_base->reg_0e18);
1497 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08,
1498 mcs_b + power_base->reg_084c);
1499
1500 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12,
1501 mcs_a + power_base->reg_0e1c);
1502 for (i = 0; i < 3; i++) {
1503 if (i != 2)
1504 val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
1505 else
1506 val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
1507 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
1508 }
1509 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12,
1510 mcs_b + power_base->reg_0868);
1511 for (i = 0; i < 3; i++) {
1512 if (i != 2)
1513 val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
1514 else
1515 val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
1516 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
1517 }
1518 }
1519
rtl8xxxu_set_linktype(struct rtl8xxxu_priv * priv,enum nl80211_iftype linktype)1520 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
1521 enum nl80211_iftype linktype)
1522 {
1523 u8 val8;
1524
1525 val8 = rtl8xxxu_read8(priv, REG_MSR);
1526 val8 &= ~MSR_LINKTYPE_MASK;
1527
1528 switch (linktype) {
1529 case NL80211_IFTYPE_UNSPECIFIED:
1530 val8 |= MSR_LINKTYPE_NONE;
1531 break;
1532 case NL80211_IFTYPE_ADHOC:
1533 val8 |= MSR_LINKTYPE_ADHOC;
1534 break;
1535 case NL80211_IFTYPE_STATION:
1536 val8 |= MSR_LINKTYPE_STATION;
1537 break;
1538 case NL80211_IFTYPE_AP:
1539 val8 |= MSR_LINKTYPE_AP;
1540 break;
1541 default:
1542 goto out;
1543 }
1544
1545 rtl8xxxu_write8(priv, REG_MSR, val8);
1546 out:
1547 return;
1548 }
1549
1550 static void
rtl8xxxu_set_retry(struct rtl8xxxu_priv * priv,u16 short_retry,u16 long_retry)1551 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
1552 {
1553 u16 val16;
1554
1555 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
1556 RETRY_LIMIT_SHORT_MASK) |
1557 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
1558 RETRY_LIMIT_LONG_MASK);
1559
1560 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
1561 }
1562
1563 static void
rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv * priv,u16 cck,u16 ofdm)1564 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
1565 {
1566 u16 val16;
1567
1568 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
1569 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
1570
1571 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
1572 }
1573
rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv * priv)1574 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
1575 {
1576 struct device *dev = &priv->udev->dev;
1577 char *cut;
1578
1579 switch (priv->chip_cut) {
1580 case 0:
1581 cut = "A";
1582 break;
1583 case 1:
1584 cut = "B";
1585 break;
1586 case 2:
1587 cut = "C";
1588 break;
1589 case 3:
1590 cut = "D";
1591 break;
1592 case 4:
1593 cut = "E";
1594 break;
1595 default:
1596 cut = "unknown";
1597 }
1598
1599 dev_info(dev,
1600 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
1601 priv->chip_name, cut, priv->chip_vendor, priv->tx_paths,
1602 priv->rx_paths, priv->ep_tx_count, priv->has_wifi,
1603 priv->has_bluetooth, priv->has_gps, priv->hi_pa);
1604
1605 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
1606 }
1607
rtl8xxxu_identify_chip(struct rtl8xxxu_priv * priv)1608 static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
1609 {
1610 struct device *dev = &priv->udev->dev;
1611 u32 val32, bonding;
1612 u16 val16;
1613
1614 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
1615 priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
1616 SYS_CFG_CHIP_VERSION_SHIFT;
1617 if (val32 & SYS_CFG_TRP_VAUX_EN) {
1618 dev_info(dev, "Unsupported test chip\n");
1619 return -ENOTSUPP;
1620 }
1621
1622 if (val32 & SYS_CFG_BT_FUNC) {
1623 if (priv->chip_cut >= 3) {
1624 sprintf(priv->chip_name, "8723BU");
1625 priv->rtl_chip = RTL8723B;
1626 } else {
1627 sprintf(priv->chip_name, "8723AU");
1628 priv->usb_interrupts = 1;
1629 priv->rtl_chip = RTL8723A;
1630 }
1631
1632 priv->rf_paths = 1;
1633 priv->rx_paths = 1;
1634 priv->tx_paths = 1;
1635
1636 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
1637 if (val32 & MULTI_WIFI_FUNC_EN)
1638 priv->has_wifi = 1;
1639 if (val32 & MULTI_BT_FUNC_EN)
1640 priv->has_bluetooth = 1;
1641 if (val32 & MULTI_GPS_FUNC_EN)
1642 priv->has_gps = 1;
1643 priv->is_multi_func = 1;
1644 } else if (val32 & SYS_CFG_TYPE_ID) {
1645 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
1646 bonding &= HPON_FSM_BONDING_MASK;
1647 if (priv->fops->tx_desc_size ==
1648 sizeof(struct rtl8xxxu_txdesc40)) {
1649 if (bonding == HPON_FSM_BONDING_1T2R) {
1650 sprintf(priv->chip_name, "8191EU");
1651 priv->rf_paths = 2;
1652 priv->rx_paths = 2;
1653 priv->tx_paths = 1;
1654 priv->rtl_chip = RTL8191E;
1655 } else {
1656 sprintf(priv->chip_name, "8192EU");
1657 priv->rf_paths = 2;
1658 priv->rx_paths = 2;
1659 priv->tx_paths = 2;
1660 priv->rtl_chip = RTL8192E;
1661 }
1662 } else if (bonding == HPON_FSM_BONDING_1T2R) {
1663 sprintf(priv->chip_name, "8191CU");
1664 priv->rf_paths = 2;
1665 priv->rx_paths = 2;
1666 priv->tx_paths = 1;
1667 priv->usb_interrupts = 1;
1668 priv->rtl_chip = RTL8191C;
1669 } else {
1670 sprintf(priv->chip_name, "8192CU");
1671 priv->rf_paths = 2;
1672 priv->rx_paths = 2;
1673 priv->tx_paths = 2;
1674 priv->usb_interrupts = 1;
1675 priv->rtl_chip = RTL8192C;
1676 }
1677 priv->has_wifi = 1;
1678 } else {
1679 sprintf(priv->chip_name, "8188CU");
1680 priv->rf_paths = 1;
1681 priv->rx_paths = 1;
1682 priv->tx_paths = 1;
1683 priv->rtl_chip = RTL8188C;
1684 priv->usb_interrupts = 1;
1685 priv->has_wifi = 1;
1686 }
1687
1688 switch (priv->rtl_chip) {
1689 case RTL8188E:
1690 case RTL8192E:
1691 case RTL8723B:
1692 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) {
1693 case SYS_CFG_VENDOR_ID_TSMC:
1694 sprintf(priv->chip_vendor, "TSMC");
1695 break;
1696 case SYS_CFG_VENDOR_ID_SMIC:
1697 sprintf(priv->chip_vendor, "SMIC");
1698 priv->vendor_smic = 1;
1699 break;
1700 case SYS_CFG_VENDOR_ID_UMC:
1701 sprintf(priv->chip_vendor, "UMC");
1702 priv->vendor_umc = 1;
1703 break;
1704 default:
1705 sprintf(priv->chip_vendor, "unknown");
1706 }
1707 break;
1708 default:
1709 if (val32 & SYS_CFG_VENDOR_ID) {
1710 sprintf(priv->chip_vendor, "UMC");
1711 priv->vendor_umc = 1;
1712 } else {
1713 sprintf(priv->chip_vendor, "TSMC");
1714 }
1715 }
1716
1717 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
1718 priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
1719
1720 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
1721 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
1722 priv->ep_tx_high_queue = 1;
1723 priv->ep_tx_count++;
1724 }
1725
1726 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
1727 priv->ep_tx_normal_queue = 1;
1728 priv->ep_tx_count++;
1729 }
1730
1731 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
1732 priv->ep_tx_low_queue = 1;
1733 priv->ep_tx_count++;
1734 }
1735
1736 /*
1737 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
1738 */
1739 if (!priv->ep_tx_count) {
1740 switch (priv->nr_out_eps) {
1741 case 4:
1742 case 3:
1743 priv->ep_tx_low_queue = 1;
1744 priv->ep_tx_count++;
1745 /* fall through */
1746 case 2:
1747 priv->ep_tx_normal_queue = 1;
1748 priv->ep_tx_count++;
1749 /* fall through */
1750 case 1:
1751 priv->ep_tx_high_queue = 1;
1752 priv->ep_tx_count++;
1753 break;
1754 default:
1755 dev_info(dev, "Unsupported USB TX end-points\n");
1756 return -ENOTSUPP;
1757 }
1758 }
1759
1760 return 0;
1761 }
1762
1763 static int
rtl8xxxu_read_efuse8(struct rtl8xxxu_priv * priv,u16 offset,u8 * data)1764 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
1765 {
1766 int i;
1767 u8 val8;
1768 u32 val32;
1769
1770 /* Write Address */
1771 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
1772 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
1773 val8 &= 0xfc;
1774 val8 |= (offset >> 8) & 0x03;
1775 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
1776
1777 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
1778 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
1779
1780 /* Poll for data read */
1781 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1782 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
1783 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1784 if (val32 & BIT(31))
1785 break;
1786 }
1787
1788 if (i == RTL8XXXU_MAX_REG_POLL)
1789 return -EIO;
1790
1791 udelay(50);
1792 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1793
1794 *data = val32 & 0xff;
1795 return 0;
1796 }
1797
rtl8xxxu_read_efuse(struct rtl8xxxu_priv * priv)1798 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
1799 {
1800 struct device *dev = &priv->udev->dev;
1801 int i, ret = 0;
1802 u8 val8, word_mask, header, extheader;
1803 u16 val16, efuse_addr, offset;
1804 u32 val32;
1805
1806 val16 = rtl8xxxu_read16(priv, REG_9346CR);
1807 if (val16 & EEPROM_ENABLE)
1808 priv->has_eeprom = 1;
1809 if (val16 & EEPROM_BOOT)
1810 priv->boot_eeprom = 1;
1811
1812 if (priv->is_multi_func) {
1813 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
1814 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
1815 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
1816 }
1817
1818 dev_dbg(dev, "Booting from %s\n",
1819 priv->boot_eeprom ? "EEPROM" : "EFUSE");
1820
1821 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
1822
1823 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
1824 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
1825 if (!(val16 & SYS_ISO_PWC_EV12V)) {
1826 val16 |= SYS_ISO_PWC_EV12V;
1827 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
1828 }
1829 /* Reset: 0x0000[28], default valid */
1830 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1831 if (!(val16 & SYS_FUNC_ELDR)) {
1832 val16 |= SYS_FUNC_ELDR;
1833 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1834 }
1835
1836 /*
1837 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
1838 */
1839 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
1840 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
1841 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
1842 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
1843 }
1844
1845 /* Default value is 0xff */
1846 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
1847
1848 efuse_addr = 0;
1849 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
1850 u16 map_addr;
1851
1852 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
1853 if (ret || header == 0xff)
1854 goto exit;
1855
1856 if ((header & 0x1f) == 0x0f) { /* extended header */
1857 offset = (header & 0xe0) >> 5;
1858
1859 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
1860 &extheader);
1861 if (ret)
1862 goto exit;
1863 /* All words disabled */
1864 if ((extheader & 0x0f) == 0x0f)
1865 continue;
1866
1867 offset |= ((extheader & 0xf0) >> 1);
1868 word_mask = extheader & 0x0f;
1869 } else {
1870 offset = (header >> 4) & 0x0f;
1871 word_mask = header & 0x0f;
1872 }
1873
1874 /* Get word enable value from PG header */
1875
1876 /* We have 8 bits to indicate validity */
1877 map_addr = offset * 8;
1878 if (map_addr >= EFUSE_MAP_LEN) {
1879 dev_warn(dev, "%s: Illegal map_addr (%04x), "
1880 "efuse corrupt!\n",
1881 __func__, map_addr);
1882 ret = -EINVAL;
1883 goto exit;
1884 }
1885 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
1886 /* Check word enable condition in the section */
1887 if (word_mask & BIT(i)) {
1888 map_addr += 2;
1889 continue;
1890 }
1891
1892 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
1893 if (ret)
1894 goto exit;
1895 priv->efuse_wifi.raw[map_addr++] = val8;
1896
1897 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
1898 if (ret)
1899 goto exit;
1900 priv->efuse_wifi.raw[map_addr++] = val8;
1901 }
1902 }
1903
1904 exit:
1905 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
1906
1907 return ret;
1908 }
1909
rtl8xxxu_reset_8051(struct rtl8xxxu_priv * priv)1910 void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
1911 {
1912 u8 val8;
1913 u16 sys_func;
1914
1915 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
1916 val8 &= ~BIT(0);
1917 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
1918
1919 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1920 sys_func &= ~SYS_FUNC_CPU_ENABLE;
1921 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
1922
1923 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
1924 val8 |= BIT(0);
1925 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
1926
1927 sys_func |= SYS_FUNC_CPU_ENABLE;
1928 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
1929 }
1930
rtl8xxxu_start_firmware(struct rtl8xxxu_priv * priv)1931 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
1932 {
1933 struct device *dev = &priv->udev->dev;
1934 int ret = 0, i;
1935 u32 val32;
1936
1937 /* Poll checksum report */
1938 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
1939 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
1940 if (val32 & MCU_FW_DL_CSUM_REPORT)
1941 break;
1942 }
1943
1944 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
1945 dev_warn(dev, "Firmware checksum poll timed out\n");
1946 ret = -EAGAIN;
1947 goto exit;
1948 }
1949
1950 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
1951 val32 |= MCU_FW_DL_READY;
1952 val32 &= ~MCU_WINT_INIT_READY;
1953 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
1954
1955 /*
1956 * Reset the 8051 in order for the firmware to start running,
1957 * otherwise it won't come up on the 8192eu
1958 */
1959 priv->fops->reset_8051(priv);
1960
1961 /* Wait for firmware to become ready */
1962 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
1963 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
1964 if (val32 & MCU_WINT_INIT_READY)
1965 break;
1966
1967 udelay(100);
1968 }
1969
1970 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
1971 dev_warn(dev, "Firmware failed to start\n");
1972 ret = -EAGAIN;
1973 goto exit;
1974 }
1975
1976 /*
1977 * Init H2C command
1978 */
1979 if (priv->rtl_chip == RTL8723B)
1980 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f);
1981 exit:
1982 return ret;
1983 }
1984
rtl8xxxu_download_firmware(struct rtl8xxxu_priv * priv)1985 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
1986 {
1987 int pages, remainder, i, ret;
1988 u8 val8;
1989 u16 val16;
1990 u32 val32;
1991 u8 *fwptr;
1992
1993 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
1994 val8 |= 4;
1995 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
1996
1997 /* 8051 enable */
1998 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1999 val16 |= SYS_FUNC_CPU_ENABLE;
2000 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2001
2002 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2003 if (val8 & MCU_FW_RAM_SEL) {
2004 pr_info("do the RAM reset\n");
2005 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
2006 priv->fops->reset_8051(priv);
2007 }
2008
2009 /* MCU firmware download enable */
2010 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2011 val8 |= MCU_FW_DL_ENABLE;
2012 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2013
2014 /* 8051 reset */
2015 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2016 val32 &= ~BIT(19);
2017 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2018
2019 /* Reset firmware download checksum */
2020 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2021 val8 |= MCU_FW_DL_CSUM_REPORT;
2022 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2023
2024 pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2025 remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2026
2027 fwptr = priv->fw_data->data;
2028
2029 for (i = 0; i < pages; i++) {
2030 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2031 val8 |= i;
2032 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2033
2034 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2035 fwptr, RTL_FW_PAGE_SIZE);
2036 if (ret != RTL_FW_PAGE_SIZE) {
2037 ret = -EAGAIN;
2038 goto fw_abort;
2039 }
2040
2041 fwptr += RTL_FW_PAGE_SIZE;
2042 }
2043
2044 if (remainder) {
2045 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2046 val8 |= i;
2047 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2048 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2049 fwptr, remainder);
2050 if (ret != remainder) {
2051 ret = -EAGAIN;
2052 goto fw_abort;
2053 }
2054 }
2055
2056 ret = 0;
2057 fw_abort:
2058 /* MCU firmware download disable */
2059 val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
2060 val16 &= ~MCU_FW_DL_ENABLE;
2061 rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
2062
2063 return ret;
2064 }
2065
rtl8xxxu_load_firmware(struct rtl8xxxu_priv * priv,char * fw_name)2066 int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
2067 {
2068 struct device *dev = &priv->udev->dev;
2069 const struct firmware *fw;
2070 int ret = 0;
2071 u16 signature;
2072
2073 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2074 if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2075 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2076 ret = -EAGAIN;
2077 goto exit;
2078 }
2079 if (!fw) {
2080 dev_warn(dev, "Firmware data not available\n");
2081 ret = -EINVAL;
2082 goto exit;
2083 }
2084
2085 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
2086 if (!priv->fw_data) {
2087 ret = -ENOMEM;
2088 goto exit;
2089 }
2090 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2091
2092 signature = le16_to_cpu(priv->fw_data->signature);
2093 switch (signature & 0xfff0) {
2094 case 0x92e0:
2095 case 0x92c0:
2096 case 0x88c0:
2097 case 0x5300:
2098 case 0x2300:
2099 break;
2100 default:
2101 ret = -EINVAL;
2102 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2103 __func__, signature);
2104 }
2105
2106 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2107 le16_to_cpu(priv->fw_data->major_version),
2108 priv->fw_data->minor_version, signature);
2109
2110 exit:
2111 release_firmware(fw);
2112 return ret;
2113 }
2114
rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv * priv)2115 void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2116 {
2117 u16 val16;
2118 int i = 100;
2119
2120 /* Inform 8051 to perform reset */
2121 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2122
2123 for (i = 100; i > 0; i--) {
2124 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2125
2126 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2127 dev_dbg(&priv->udev->dev,
2128 "%s: Firmware self reset success!\n", __func__);
2129 break;
2130 }
2131 udelay(50);
2132 }
2133
2134 if (!i) {
2135 /* Force firmware reset */
2136 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2137 val16 &= ~SYS_FUNC_CPU_ENABLE;
2138 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2139 }
2140 }
2141
2142 static int
rtl8xxxu_init_mac(struct rtl8xxxu_priv * priv)2143 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv)
2144 {
2145 struct rtl8xxxu_reg8val *array = priv->fops->mactable;
2146 int i, ret;
2147 u16 reg;
2148 u8 val;
2149
2150 for (i = 0; ; i++) {
2151 reg = array[i].reg;
2152 val = array[i].val;
2153
2154 if (reg == 0xffff && val == 0xff)
2155 break;
2156
2157 ret = rtl8xxxu_write8(priv, reg, val);
2158 if (ret != 1) {
2159 dev_warn(&priv->udev->dev,
2160 "Failed to initialize MAC "
2161 "(reg: %04x, val %02x)\n", reg, val);
2162 return -EAGAIN;
2163 }
2164 }
2165
2166 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E)
2167 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
2168
2169 return 0;
2170 }
2171
rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv * priv,struct rtl8xxxu_reg32val * array)2172 int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2173 struct rtl8xxxu_reg32val *array)
2174 {
2175 int i, ret;
2176 u16 reg;
2177 u32 val;
2178
2179 for (i = 0; ; i++) {
2180 reg = array[i].reg;
2181 val = array[i].val;
2182
2183 if (reg == 0xffff && val == 0xffffffff)
2184 break;
2185
2186 ret = rtl8xxxu_write32(priv, reg, val);
2187 if (ret != sizeof(val)) {
2188 dev_warn(&priv->udev->dev,
2189 "Failed to initialize PHY\n");
2190 return -EAGAIN;
2191 }
2192 udelay(1);
2193 }
2194
2195 return 0;
2196 }
2197
rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv * priv)2198 void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv)
2199 {
2200 u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
2201 u16 val16;
2202 u32 val32;
2203
2204 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
2205 udelay(2);
2206 val8 |= AFE_PLL_320_ENABLE;
2207 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
2208 udelay(2);
2209
2210 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
2211 udelay(2);
2212
2213 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2214 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
2215 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2216
2217 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
2218 val32 &= ~AFE_XTAL_RF_GATE;
2219 if (priv->has_bluetooth)
2220 val32 &= ~AFE_XTAL_BT_GATE;
2221 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
2222
2223 /* 6. 0x1f[7:0] = 0x07 */
2224 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
2225 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
2226
2227 if (priv->hi_pa)
2228 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
2229 else if (priv->tx_paths == 2)
2230 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
2231 else
2232 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
2233
2234 if (priv->rtl_chip == RTL8188R && priv->hi_pa &&
2235 priv->vendor_umc && priv->chip_cut == 1)
2236 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
2237
2238 if (priv->hi_pa)
2239 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
2240 else
2241 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
2242
2243 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
2244 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
2245 ldohci12 = 0x57;
2246 lpldo = 1;
2247 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
2248 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
2249 }
2250
2251 /*
2252 * Most of this is black magic retrieved from the old rtl8723au driver
2253 */
rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv * priv)2254 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
2255 {
2256 u8 val8;
2257 u32 val32;
2258
2259 priv->fops->init_phy_bb(priv);
2260
2261 if (priv->tx_paths == 1 && priv->rx_paths == 2) {
2262 /*
2263 * For 1T2R boards, patch the registers.
2264 *
2265 * It looks like 8191/2 1T2R boards use path B for TX
2266 */
2267 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
2268 val32 &= ~(BIT(0) | BIT(1));
2269 val32 |= BIT(1);
2270 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
2271
2272 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
2273 val32 &= ~0x300033;
2274 val32 |= 0x200022;
2275 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
2276
2277 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
2278 val32 &= ~CCK0_AFE_RX_MASK;
2279 val32 &= 0x00ffffff;
2280 val32 |= 0x40000000;
2281 val32 |= CCK0_AFE_RX_ANT_B;
2282 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
2283
2284 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2285 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
2286 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
2287 OFDM_RF_PATH_TX_B);
2288 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2289
2290 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
2291 val32 &= ~(BIT(4) | BIT(5));
2292 val32 |= BIT(4);
2293 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
2294
2295 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
2296 val32 &= ~(BIT(27) | BIT(26));
2297 val32 |= BIT(27);
2298 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
2299
2300 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
2301 val32 &= ~(BIT(27) | BIT(26));
2302 val32 |= BIT(27);
2303 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
2304
2305 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
2306 val32 &= ~(BIT(27) | BIT(26));
2307 val32 |= BIT(27);
2308 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
2309
2310 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
2311 val32 &= ~(BIT(27) | BIT(26));
2312 val32 |= BIT(27);
2313 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
2314
2315 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
2316 val32 &= ~(BIT(27) | BIT(26));
2317 val32 |= BIT(27);
2318 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
2319 }
2320
2321 if (priv->has_xtalk) {
2322 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
2323
2324 val8 = priv->xtalk;
2325 val32 &= 0xff000fff;
2326 val32 |= ((val8 | (val8 << 6)) << 12);
2327
2328 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
2329 }
2330
2331 if (priv->rtl_chip == RTL8192E)
2332 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x000f81fb);
2333
2334 return 0;
2335 }
2336
rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv * priv,struct rtl8xxxu_rfregval * array,enum rtl8xxxu_rfpath path)2337 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
2338 struct rtl8xxxu_rfregval *array,
2339 enum rtl8xxxu_rfpath path)
2340 {
2341 int i, ret;
2342 u8 reg;
2343 u32 val;
2344
2345 for (i = 0; ; i++) {
2346 reg = array[i].reg;
2347 val = array[i].val;
2348
2349 if (reg == 0xff && val == 0xffffffff)
2350 break;
2351
2352 switch (reg) {
2353 case 0xfe:
2354 msleep(50);
2355 continue;
2356 case 0xfd:
2357 mdelay(5);
2358 continue;
2359 case 0xfc:
2360 mdelay(1);
2361 continue;
2362 case 0xfb:
2363 udelay(50);
2364 continue;
2365 case 0xfa:
2366 udelay(5);
2367 continue;
2368 case 0xf9:
2369 udelay(1);
2370 continue;
2371 }
2372
2373 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
2374 if (ret) {
2375 dev_warn(&priv->udev->dev,
2376 "Failed to initialize RF\n");
2377 return -EAGAIN;
2378 }
2379 udelay(1);
2380 }
2381
2382 return 0;
2383 }
2384
rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv * priv,struct rtl8xxxu_rfregval * table,enum rtl8xxxu_rfpath path)2385 int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
2386 struct rtl8xxxu_rfregval *table,
2387 enum rtl8xxxu_rfpath path)
2388 {
2389 u32 val32;
2390 u16 val16, rfsi_rfenv;
2391 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
2392
2393 switch (path) {
2394 case RF_A:
2395 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
2396 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
2397 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
2398 break;
2399 case RF_B:
2400 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
2401 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
2402 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
2403 break;
2404 default:
2405 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
2406 __func__, path + 'A');
2407 return -EINVAL;
2408 }
2409 /* For path B, use XB */
2410 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
2411 rfsi_rfenv &= FPGA0_RF_RFENV;
2412
2413 /*
2414 * These two we might be able to optimize into one
2415 */
2416 val32 = rtl8xxxu_read32(priv, reg_int_oe);
2417 val32 |= BIT(20); /* 0x10 << 16 */
2418 rtl8xxxu_write32(priv, reg_int_oe, val32);
2419 udelay(1);
2420
2421 val32 = rtl8xxxu_read32(priv, reg_int_oe);
2422 val32 |= BIT(4);
2423 rtl8xxxu_write32(priv, reg_int_oe, val32);
2424 udelay(1);
2425
2426 /*
2427 * These two we might be able to optimize into one
2428 */
2429 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2430 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
2431 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2432 udelay(1);
2433
2434 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2435 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
2436 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2437 udelay(1);
2438
2439 rtl8xxxu_init_rf_regs(priv, table, path);
2440
2441 /* For path B, use XB */
2442 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
2443 val16 &= ~FPGA0_RF_RFENV;
2444 val16 |= rfsi_rfenv;
2445 rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
2446
2447 return 0;
2448 }
2449
rtl8xxxu_llt_write(struct rtl8xxxu_priv * priv,u8 address,u8 data)2450 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
2451 {
2452 int ret = -EBUSY;
2453 int count = 0;
2454 u32 value;
2455
2456 value = LLT_OP_WRITE | address << 8 | data;
2457
2458 rtl8xxxu_write32(priv, REG_LLT_INIT, value);
2459
2460 do {
2461 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
2462 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
2463 ret = 0;
2464 break;
2465 }
2466 } while (count++ < 20);
2467
2468 return ret;
2469 }
2470
rtl8xxxu_init_llt_table(struct rtl8xxxu_priv * priv)2471 int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv)
2472 {
2473 int ret;
2474 int i;
2475 u8 last_tx_page;
2476
2477 last_tx_page = priv->fops->total_page_num;
2478
2479 for (i = 0; i < last_tx_page; i++) {
2480 ret = rtl8xxxu_llt_write(priv, i, i + 1);
2481 if (ret)
2482 goto exit;
2483 }
2484
2485 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
2486 if (ret)
2487 goto exit;
2488
2489 /* Mark remaining pages as a ring buffer */
2490 for (i = last_tx_page + 1; i < 0xff; i++) {
2491 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
2492 if (ret)
2493 goto exit;
2494 }
2495
2496 /* Let last entry point to the start entry of ring buffer */
2497 ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
2498 if (ret)
2499 goto exit;
2500
2501 exit:
2502 return ret;
2503 }
2504
rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv * priv)2505 int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv)
2506 {
2507 u32 val32;
2508 int ret = 0;
2509 int i;
2510
2511 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
2512 val32 |= AUTO_LLT_INIT_LLT;
2513 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
2514
2515 for (i = 500; i; i--) {
2516 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
2517 if (!(val32 & AUTO_LLT_INIT_LLT))
2518 break;
2519 usleep_range(2, 4);
2520 }
2521
2522 if (!i) {
2523 ret = -EBUSY;
2524 dev_warn(&priv->udev->dev, "LLT table init failed\n");
2525 }
2526
2527 return ret;
2528 }
2529
rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv * priv)2530 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
2531 {
2532 u16 val16, hi, lo;
2533 u16 hiq, mgq, bkq, beq, viq, voq;
2534 int hip, mgp, bkp, bep, vip, vop;
2535 int ret = 0;
2536
2537 switch (priv->ep_tx_count) {
2538 case 1:
2539 if (priv->ep_tx_high_queue) {
2540 hi = TRXDMA_QUEUE_HIGH;
2541 } else if (priv->ep_tx_low_queue) {
2542 hi = TRXDMA_QUEUE_LOW;
2543 } else if (priv->ep_tx_normal_queue) {
2544 hi = TRXDMA_QUEUE_NORMAL;
2545 } else {
2546 hi = 0;
2547 ret = -EINVAL;
2548 }
2549
2550 hiq = hi;
2551 mgq = hi;
2552 bkq = hi;
2553 beq = hi;
2554 viq = hi;
2555 voq = hi;
2556
2557 hip = 0;
2558 mgp = 0;
2559 bkp = 0;
2560 bep = 0;
2561 vip = 0;
2562 vop = 0;
2563 break;
2564 case 2:
2565 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
2566 hi = TRXDMA_QUEUE_HIGH;
2567 lo = TRXDMA_QUEUE_LOW;
2568 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
2569 hi = TRXDMA_QUEUE_NORMAL;
2570 lo = TRXDMA_QUEUE_LOW;
2571 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
2572 hi = TRXDMA_QUEUE_HIGH;
2573 lo = TRXDMA_QUEUE_NORMAL;
2574 } else {
2575 ret = -EINVAL;
2576 hi = 0;
2577 lo = 0;
2578 }
2579
2580 hiq = hi;
2581 mgq = hi;
2582 bkq = lo;
2583 beq = lo;
2584 viq = hi;
2585 voq = hi;
2586
2587 hip = 0;
2588 mgp = 0;
2589 bkp = 1;
2590 bep = 1;
2591 vip = 0;
2592 vop = 0;
2593 break;
2594 case 3:
2595 beq = TRXDMA_QUEUE_LOW;
2596 bkq = TRXDMA_QUEUE_LOW;
2597 viq = TRXDMA_QUEUE_NORMAL;
2598 voq = TRXDMA_QUEUE_HIGH;
2599 mgq = TRXDMA_QUEUE_HIGH;
2600 hiq = TRXDMA_QUEUE_HIGH;
2601
2602 hip = hiq ^ 3;
2603 mgp = mgq ^ 3;
2604 bkp = bkq ^ 3;
2605 bep = beq ^ 3;
2606 vip = viq ^ 3;
2607 vop = viq ^ 3;
2608 break;
2609 default:
2610 ret = -EINVAL;
2611 }
2612
2613 /*
2614 * None of the vendor drivers are configuring the beacon
2615 * queue here .... why?
2616 */
2617 if (!ret) {
2618 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
2619 val16 &= 0x7;
2620 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
2621 (viq << TRXDMA_CTRL_VIQ_SHIFT) |
2622 (beq << TRXDMA_CTRL_BEQ_SHIFT) |
2623 (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
2624 (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
2625 (hiq << TRXDMA_CTRL_HIQ_SHIFT);
2626 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
2627
2628 priv->pipe_out[TXDESC_QUEUE_VO] =
2629 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
2630 priv->pipe_out[TXDESC_QUEUE_VI] =
2631 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
2632 priv->pipe_out[TXDESC_QUEUE_BE] =
2633 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
2634 priv->pipe_out[TXDESC_QUEUE_BK] =
2635 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
2636 priv->pipe_out[TXDESC_QUEUE_BEACON] =
2637 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2638 priv->pipe_out[TXDESC_QUEUE_MGNT] =
2639 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
2640 priv->pipe_out[TXDESC_QUEUE_HIGH] =
2641 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
2642 priv->pipe_out[TXDESC_QUEUE_CMD] =
2643 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2644 }
2645
2646 return ret;
2647 }
2648
rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv * priv,bool iqk_ok,int result[][8],int candidate,bool tx_only)2649 void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok,
2650 int result[][8], int candidate, bool tx_only)
2651 {
2652 u32 oldval, x, tx0_a, reg;
2653 int y, tx0_c;
2654 u32 val32;
2655
2656 if (!iqk_ok)
2657 return;
2658
2659 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2660 oldval = val32 >> 22;
2661
2662 x = result[candidate][0];
2663 if ((x & 0x00000200) != 0)
2664 x = x | 0xfffffc00;
2665 tx0_a = (x * oldval) >> 8;
2666
2667 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2668 val32 &= ~0x3ff;
2669 val32 |= tx0_a;
2670 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2671
2672 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2673 val32 &= ~BIT(31);
2674 if ((x * oldval >> 7) & 0x1)
2675 val32 |= BIT(31);
2676 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2677
2678 y = result[candidate][1];
2679 if ((y & 0x00000200) != 0)
2680 y = y | 0xfffffc00;
2681 tx0_c = (y * oldval) >> 8;
2682
2683 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
2684 val32 &= ~0xf0000000;
2685 val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
2686 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
2687
2688 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2689 val32 &= ~0x003f0000;
2690 val32 |= ((tx0_c & 0x3f) << 16);
2691 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2692
2693 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2694 val32 &= ~BIT(29);
2695 if ((y * oldval >> 7) & 0x1)
2696 val32 |= BIT(29);
2697 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2698
2699 if (tx_only) {
2700 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2701 return;
2702 }
2703
2704 reg = result[candidate][2];
2705
2706 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2707 val32 &= ~0x3ff;
2708 val32 |= (reg & 0x3ff);
2709 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2710
2711 reg = result[candidate][3] & 0x3F;
2712
2713 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2714 val32 &= ~0xfc00;
2715 val32 |= ((reg << 10) & 0xfc00);
2716 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2717
2718 reg = (result[candidate][3] >> 6) & 0xF;
2719
2720 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
2721 val32 &= ~0xf0000000;
2722 val32 |= (reg << 28);
2723 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
2724 }
2725
rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv * priv,bool iqk_ok,int result[][8],int candidate,bool tx_only)2726 void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok,
2727 int result[][8], int candidate, bool tx_only)
2728 {
2729 u32 oldval, x, tx1_a, reg;
2730 int y, tx1_c;
2731 u32 val32;
2732
2733 if (!iqk_ok)
2734 return;
2735
2736 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2737 oldval = val32 >> 22;
2738
2739 x = result[candidate][4];
2740 if ((x & 0x00000200) != 0)
2741 x = x | 0xfffffc00;
2742 tx1_a = (x * oldval) >> 8;
2743
2744 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2745 val32 &= ~0x3ff;
2746 val32 |= tx1_a;
2747 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2748
2749 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2750 val32 &= ~BIT(27);
2751 if ((x * oldval >> 7) & 0x1)
2752 val32 |= BIT(27);
2753 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2754
2755 y = result[candidate][5];
2756 if ((y & 0x00000200) != 0)
2757 y = y | 0xfffffc00;
2758 tx1_c = (y * oldval) >> 8;
2759
2760 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
2761 val32 &= ~0xf0000000;
2762 val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
2763 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
2764
2765 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2766 val32 &= ~0x003f0000;
2767 val32 |= ((tx1_c & 0x3f) << 16);
2768 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2769
2770 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2771 val32 &= ~BIT(25);
2772 if ((y * oldval >> 7) & 0x1)
2773 val32 |= BIT(25);
2774 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2775
2776 if (tx_only) {
2777 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2778 return;
2779 }
2780
2781 reg = result[candidate][6];
2782
2783 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2784 val32 &= ~0x3ff;
2785 val32 |= (reg & 0x3ff);
2786 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2787
2788 reg = result[candidate][7] & 0x3f;
2789
2790 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2791 val32 &= ~0xfc00;
2792 val32 |= ((reg << 10) & 0xfc00);
2793 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2794
2795 reg = (result[candidate][7] >> 6) & 0xf;
2796
2797 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
2798 val32 &= ~0x0000f000;
2799 val32 |= (reg << 12);
2800 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
2801 }
2802
2803 #define MAX_TOLERANCE 5
2804
rtl8xxxu_simularity_compare(struct rtl8xxxu_priv * priv,int result[][8],int c1,int c2)2805 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
2806 int result[][8], int c1, int c2)
2807 {
2808 u32 i, j, diff, simubitmap, bound = 0;
2809 int candidate[2] = {-1, -1}; /* for path A and path B */
2810 bool retval = true;
2811
2812 if (priv->tx_paths > 1)
2813 bound = 8;
2814 else
2815 bound = 4;
2816
2817 simubitmap = 0;
2818
2819 for (i = 0; i < bound; i++) {
2820 diff = (result[c1][i] > result[c2][i]) ?
2821 (result[c1][i] - result[c2][i]) :
2822 (result[c2][i] - result[c1][i]);
2823 if (diff > MAX_TOLERANCE) {
2824 if ((i == 2 || i == 6) && !simubitmap) {
2825 if (result[c1][i] + result[c1][i + 1] == 0)
2826 candidate[(i / 4)] = c2;
2827 else if (result[c2][i] + result[c2][i + 1] == 0)
2828 candidate[(i / 4)] = c1;
2829 else
2830 simubitmap = simubitmap | (1 << i);
2831 } else {
2832 simubitmap = simubitmap | (1 << i);
2833 }
2834 }
2835 }
2836
2837 if (simubitmap == 0) {
2838 for (i = 0; i < (bound / 4); i++) {
2839 if (candidate[i] >= 0) {
2840 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2841 result[3][j] = result[candidate[i]][j];
2842 retval = false;
2843 }
2844 }
2845 return retval;
2846 } else if (!(simubitmap & 0x0f)) {
2847 /* path A OK */
2848 for (i = 0; i < 4; i++)
2849 result[3][i] = result[c1][i];
2850 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
2851 /* path B OK */
2852 for (i = 4; i < 8; i++)
2853 result[3][i] = result[c1][i];
2854 }
2855
2856 return false;
2857 }
2858
rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv * priv,int result[][8],int c1,int c2)2859 bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv,
2860 int result[][8], int c1, int c2)
2861 {
2862 u32 i, j, diff, simubitmap, bound = 0;
2863 int candidate[2] = {-1, -1}; /* for path A and path B */
2864 int tmp1, tmp2;
2865 bool retval = true;
2866
2867 if (priv->tx_paths > 1)
2868 bound = 8;
2869 else
2870 bound = 4;
2871
2872 simubitmap = 0;
2873
2874 for (i = 0; i < bound; i++) {
2875 if (i & 1) {
2876 if ((result[c1][i] & 0x00000200))
2877 tmp1 = result[c1][i] | 0xfffffc00;
2878 else
2879 tmp1 = result[c1][i];
2880
2881 if ((result[c2][i]& 0x00000200))
2882 tmp2 = result[c2][i] | 0xfffffc00;
2883 else
2884 tmp2 = result[c2][i];
2885 } else {
2886 tmp1 = result[c1][i];
2887 tmp2 = result[c2][i];
2888 }
2889
2890 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
2891
2892 if (diff > MAX_TOLERANCE) {
2893 if ((i == 2 || i == 6) && !simubitmap) {
2894 if (result[c1][i] + result[c1][i + 1] == 0)
2895 candidate[(i / 4)] = c2;
2896 else if (result[c2][i] + result[c2][i + 1] == 0)
2897 candidate[(i / 4)] = c1;
2898 else
2899 simubitmap = simubitmap | (1 << i);
2900 } else {
2901 simubitmap = simubitmap | (1 << i);
2902 }
2903 }
2904 }
2905
2906 if (simubitmap == 0) {
2907 for (i = 0; i < (bound / 4); i++) {
2908 if (candidate[i] >= 0) {
2909 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2910 result[3][j] = result[candidate[i]][j];
2911 retval = false;
2912 }
2913 }
2914 return retval;
2915 } else {
2916 if (!(simubitmap & 0x03)) {
2917 /* path A TX OK */
2918 for (i = 0; i < 2; i++)
2919 result[3][i] = result[c1][i];
2920 }
2921
2922 if (!(simubitmap & 0x0c)) {
2923 /* path A RX OK */
2924 for (i = 2; i < 4; i++)
2925 result[3][i] = result[c1][i];
2926 }
2927
2928 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
2929 /* path B RX OK */
2930 for (i = 4; i < 6; i++)
2931 result[3][i] = result[c1][i];
2932 }
2933
2934 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
2935 /* path B RX OK */
2936 for (i = 6; i < 8; i++)
2937 result[3][i] = result[c1][i];
2938 }
2939 }
2940
2941 return false;
2942 }
2943
2944 void
rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv * priv,const u32 * reg,u32 * backup)2945 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
2946 {
2947 int i;
2948
2949 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
2950 backup[i] = rtl8xxxu_read8(priv, reg[i]);
2951
2952 backup[i] = rtl8xxxu_read32(priv, reg[i]);
2953 }
2954
rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv * priv,const u32 * reg,u32 * backup)2955 void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
2956 const u32 *reg, u32 *backup)
2957 {
2958 int i;
2959
2960 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
2961 rtl8xxxu_write8(priv, reg[i], backup[i]);
2962
2963 rtl8xxxu_write32(priv, reg[i], backup[i]);
2964 }
2965
rtl8xxxu_save_regs(struct rtl8xxxu_priv * priv,const u32 * regs,u32 * backup,int count)2966 void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
2967 u32 *backup, int count)
2968 {
2969 int i;
2970
2971 for (i = 0; i < count; i++)
2972 backup[i] = rtl8xxxu_read32(priv, regs[i]);
2973 }
2974
rtl8xxxu_restore_regs(struct rtl8xxxu_priv * priv,const u32 * regs,u32 * backup,int count)2975 void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
2976 u32 *backup, int count)
2977 {
2978 int i;
2979
2980 for (i = 0; i < count; i++)
2981 rtl8xxxu_write32(priv, regs[i], backup[i]);
2982 }
2983
2984
rtl8xxxu_path_adda_on(struct rtl8xxxu_priv * priv,const u32 * regs,bool path_a_on)2985 void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
2986 bool path_a_on)
2987 {
2988 u32 path_on;
2989 int i;
2990
2991 if (priv->tx_paths == 1) {
2992 path_on = priv->fops->adda_1t_path_on;
2993 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init);
2994 } else {
2995 path_on = path_a_on ? priv->fops->adda_2t_path_on_a :
2996 priv->fops->adda_2t_path_on_b;
2997
2998 rtl8xxxu_write32(priv, regs[0], path_on);
2999 }
3000
3001 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3002 rtl8xxxu_write32(priv, regs[i], path_on);
3003 }
3004
rtl8xxxu_mac_calibration(struct rtl8xxxu_priv * priv,const u32 * regs,u32 * backup)3005 void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3006 const u32 *regs, u32 *backup)
3007 {
3008 int i = 0;
3009
3010 rtl8xxxu_write8(priv, regs[i], 0x3f);
3011
3012 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3013 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3014
3015 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3016 }
3017
rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv * priv)3018 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3019 {
3020 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3021 int result = 0;
3022
3023 /* path-A IQK setting */
3024 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3025 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3026 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3027
3028 val32 = (priv->rf_paths > 1) ? 0x28160202 :
3029 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3030 0x28160502;
3031 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3032
3033 /* path-B IQK setting */
3034 if (priv->rf_paths > 1) {
3035 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3036 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3037 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3038 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3039 }
3040
3041 /* LO calibration setting */
3042 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3043
3044 /* One shot, path A LOK & IQK */
3045 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3046 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3047
3048 mdelay(1);
3049
3050 /* Check failed */
3051 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3052 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3053 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3054 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3055
3056 if (!(reg_eac & BIT(28)) &&
3057 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3058 ((reg_e9c & 0x03ff0000) != 0x00420000))
3059 result |= 0x01;
3060 else /* If TX not OK, ignore RX */
3061 goto out;
3062
3063 /* If TX is OK, check whether RX is OK */
3064 if (!(reg_eac & BIT(27)) &&
3065 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3066 ((reg_eac & 0x03ff0000) != 0x00360000))
3067 result |= 0x02;
3068 else
3069 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3070 __func__);
3071 out:
3072 return result;
3073 }
3074
rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv * priv)3075 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3076 {
3077 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3078 int result = 0;
3079
3080 /* One shot, path B LOK & IQK */
3081 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3082 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3083
3084 mdelay(1);
3085
3086 /* Check failed */
3087 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3088 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3089 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3090 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3091 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3092
3093 if (!(reg_eac & BIT(31)) &&
3094 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3095 ((reg_ebc & 0x03ff0000) != 0x00420000))
3096 result |= 0x01;
3097 else
3098 goto out;
3099
3100 if (!(reg_eac & BIT(30)) &&
3101 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
3102 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
3103 result |= 0x02;
3104 else
3105 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
3106 __func__);
3107 out:
3108 return result;
3109 }
3110
rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv * priv,int result[][8],int t)3111 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
3112 int result[][8], int t)
3113 {
3114 struct device *dev = &priv->udev->dev;
3115 u32 i, val32;
3116 int path_a_ok, path_b_ok;
3117 int retry = 2;
3118 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
3119 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
3120 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
3121 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
3122 REG_TX_OFDM_BBON, REG_TX_TO_RX,
3123 REG_TX_TO_TX, REG_RX_CCK,
3124 REG_RX_OFDM, REG_RX_WAIT_RIFS,
3125 REG_RX_TO_RX, REG_STANDBY,
3126 REG_SLEEP, REG_PMPD_ANAEN
3127 };
3128 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
3129 REG_TXPAUSE, REG_BEACON_CTRL,
3130 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
3131 };
3132 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
3133 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
3134 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
3135 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
3136 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
3137 };
3138
3139 /*
3140 * Note: IQ calibration must be performed after loading
3141 * PHY_REG.txt , and radio_a, radio_b.txt
3142 */
3143
3144 if (t == 0) {
3145 /* Save ADDA parameters, turn Path A ADDA on */
3146 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
3147 RTL8XXXU_ADDA_REGS);
3148 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3149 rtl8xxxu_save_regs(priv, iqk_bb_regs,
3150 priv->bb_backup, RTL8XXXU_BB_REGS);
3151 }
3152
3153 rtl8xxxu_path_adda_on(priv, adda_regs, true);
3154
3155 if (t == 0) {
3156 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
3157 if (val32 & FPGA0_HSSI_PARM1_PI)
3158 priv->pi_enabled = 1;
3159 }
3160
3161 if (!priv->pi_enabled) {
3162 /* Switch BB to PI mode to do IQ Calibration. */
3163 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
3164 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
3165 }
3166
3167 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3168 val32 &= ~FPGA_RF_MODE_CCK;
3169 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
3170
3171 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
3172 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
3173 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
3174
3175 if (!priv->no_pape) {
3176 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
3177 val32 |= (FPGA0_RF_PAPE |
3178 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3179 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
3180 }
3181
3182 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
3183 val32 &= ~BIT(10);
3184 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
3185 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
3186 val32 &= ~BIT(10);
3187 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
3188
3189 if (priv->tx_paths > 1) {
3190 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3191 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
3192 }
3193
3194 /* MAC settings */
3195 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
3196
3197 /* Page B init */
3198 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
3199
3200 if (priv->tx_paths > 1)
3201 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
3202
3203 /* IQ calibration setting */
3204 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3205 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3206 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3207
3208 for (i = 0; i < retry; i++) {
3209 path_a_ok = rtl8xxxu_iqk_path_a(priv);
3210 if (path_a_ok == 0x03) {
3211 val32 = rtl8xxxu_read32(priv,
3212 REG_TX_POWER_BEFORE_IQK_A);
3213 result[t][0] = (val32 >> 16) & 0x3ff;
3214 val32 = rtl8xxxu_read32(priv,
3215 REG_TX_POWER_AFTER_IQK_A);
3216 result[t][1] = (val32 >> 16) & 0x3ff;
3217 val32 = rtl8xxxu_read32(priv,
3218 REG_RX_POWER_BEFORE_IQK_A_2);
3219 result[t][2] = (val32 >> 16) & 0x3ff;
3220 val32 = rtl8xxxu_read32(priv,
3221 REG_RX_POWER_AFTER_IQK_A_2);
3222 result[t][3] = (val32 >> 16) & 0x3ff;
3223 break;
3224 } else if (i == (retry - 1) && path_a_ok == 0x01) {
3225 /* TX IQK OK */
3226 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
3227 __func__);
3228
3229 val32 = rtl8xxxu_read32(priv,
3230 REG_TX_POWER_BEFORE_IQK_A);
3231 result[t][0] = (val32 >> 16) & 0x3ff;
3232 val32 = rtl8xxxu_read32(priv,
3233 REG_TX_POWER_AFTER_IQK_A);
3234 result[t][1] = (val32 >> 16) & 0x3ff;
3235 }
3236 }
3237
3238 if (!path_a_ok)
3239 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
3240
3241 if (priv->tx_paths > 1) {
3242 /*
3243 * Path A into standby
3244 */
3245 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
3246 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3247 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3248
3249 /* Turn Path B ADDA on */
3250 rtl8xxxu_path_adda_on(priv, adda_regs, false);
3251
3252 for (i = 0; i < retry; i++) {
3253 path_b_ok = rtl8xxxu_iqk_path_b(priv);
3254 if (path_b_ok == 0x03) {
3255 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3256 result[t][4] = (val32 >> 16) & 0x3ff;
3257 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3258 result[t][5] = (val32 >> 16) & 0x3ff;
3259 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3260 result[t][6] = (val32 >> 16) & 0x3ff;
3261 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3262 result[t][7] = (val32 >> 16) & 0x3ff;
3263 break;
3264 } else if (i == (retry - 1) && path_b_ok == 0x01) {
3265 /* TX IQK OK */
3266 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3267 result[t][4] = (val32 >> 16) & 0x3ff;
3268 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3269 result[t][5] = (val32 >> 16) & 0x3ff;
3270 }
3271 }
3272
3273 if (!path_b_ok)
3274 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
3275 }
3276
3277 /* Back to BB mode, load original value */
3278 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
3279
3280 if (t) {
3281 if (!priv->pi_enabled) {
3282 /*
3283 * Switch back BB to SI mode after finishing
3284 * IQ Calibration
3285 */
3286 val32 = 0x01000000;
3287 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
3288 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
3289 }
3290
3291 /* Reload ADDA power saving parameters */
3292 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
3293 RTL8XXXU_ADDA_REGS);
3294
3295 /* Reload MAC parameters */
3296 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3297
3298 /* Reload BB parameters */
3299 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
3300 priv->bb_backup, RTL8XXXU_BB_REGS);
3301
3302 /* Restore RX initial gain */
3303 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
3304
3305 if (priv->tx_paths > 1) {
3306 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
3307 0x00032ed3);
3308 }
3309
3310 /* Load 0xe30 IQC default value */
3311 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
3312 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
3313 }
3314 }
3315
rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv * priv,u8 start)3316 void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start)
3317 {
3318 struct h2c_cmd h2c;
3319
3320 memset(&h2c, 0, sizeof(struct h2c_cmd));
3321 h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION;
3322 h2c.bt_wlan_calibration.data = start;
3323
3324 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration));
3325 }
3326
rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv * priv)3327 void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
3328 {
3329 struct device *dev = &priv->udev->dev;
3330 int result[4][8]; /* last is final result */
3331 int i, candidate;
3332 bool path_a_ok, path_b_ok;
3333 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
3334 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3335 s32 reg_tmp = 0;
3336 bool simu;
3337
3338 memset(result, 0, sizeof(result));
3339 candidate = -1;
3340
3341 path_a_ok = false;
3342 path_b_ok = false;
3343
3344 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3345
3346 for (i = 0; i < 3; i++) {
3347 rtl8xxxu_phy_iqcalibrate(priv, result, i);
3348
3349 if (i == 1) {
3350 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
3351 if (simu) {
3352 candidate = 0;
3353 break;
3354 }
3355 }
3356
3357 if (i == 2) {
3358 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
3359 if (simu) {
3360 candidate = 0;
3361 break;
3362 }
3363
3364 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
3365 if (simu) {
3366 candidate = 1;
3367 } else {
3368 for (i = 0; i < 8; i++)
3369 reg_tmp += result[3][i];
3370
3371 if (reg_tmp)
3372 candidate = 3;
3373 else
3374 candidate = -1;
3375 }
3376 }
3377 }
3378
3379 for (i = 0; i < 4; i++) {
3380 reg_e94 = result[i][0];
3381 reg_e9c = result[i][1];
3382 reg_ea4 = result[i][2];
3383 reg_eac = result[i][3];
3384 reg_eb4 = result[i][4];
3385 reg_ebc = result[i][5];
3386 reg_ec4 = result[i][6];
3387 reg_ecc = result[i][7];
3388 }
3389
3390 if (candidate >= 0) {
3391 reg_e94 = result[candidate][0];
3392 priv->rege94 = reg_e94;
3393 reg_e9c = result[candidate][1];
3394 priv->rege9c = reg_e9c;
3395 reg_ea4 = result[candidate][2];
3396 reg_eac = result[candidate][3];
3397 reg_eb4 = result[candidate][4];
3398 priv->regeb4 = reg_eb4;
3399 reg_ebc = result[candidate][5];
3400 priv->regebc = reg_ebc;
3401 reg_ec4 = result[candidate][6];
3402 reg_ecc = result[candidate][7];
3403 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
3404 dev_dbg(dev,
3405 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n",
3406 __func__, reg_e94, reg_e9c,
3407 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
3408 path_a_ok = true;
3409 path_b_ok = true;
3410 } else {
3411 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
3412 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
3413 }
3414
3415 if (reg_e94 && candidate >= 0)
3416 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
3417 candidate, (reg_ea4 == 0));
3418
3419 if (priv->tx_paths > 1 && reg_eb4)
3420 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
3421 candidate, (reg_ec4 == 0));
3422
3423 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,
3424 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
3425 }
3426
rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv * priv)3427 static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
3428 {
3429 u32 val32;
3430 u32 rf_amode, rf_bmode = 0, lstf;
3431
3432 /* Check continuous TX and Packet TX */
3433 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
3434
3435 if (lstf & OFDM_LSTF_MASK) {
3436 /* Disable all continuous TX */
3437 val32 = lstf & ~OFDM_LSTF_MASK;
3438 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
3439
3440 /* Read original RF mode Path A */
3441 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
3442
3443 /* Set RF mode to standby Path A */
3444 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
3445 (rf_amode & 0x8ffff) | 0x10000);
3446
3447 /* Path-B */
3448 if (priv->tx_paths > 1) {
3449 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
3450 RF6052_REG_AC);
3451
3452 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3453 (rf_bmode & 0x8ffff) | 0x10000);
3454 }
3455 } else {
3456 /* Deal with Packet TX case */
3457 /* block all queues */
3458 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3459 }
3460
3461 /* Start LC calibration */
3462 if (priv->fops->has_s0s1)
3463 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0);
3464 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
3465 val32 |= 0x08000;
3466 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
3467
3468 msleep(100);
3469
3470 if (priv->fops->has_s0s1)
3471 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0);
3472
3473 /* Restore original parameters */
3474 if (lstf & OFDM_LSTF_MASK) {
3475 /* Path-A */
3476 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
3477 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
3478
3479 /* Path-B */
3480 if (priv->tx_paths > 1)
3481 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3482 rf_bmode);
3483 } else /* Deal with Packet TX case */
3484 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
3485 }
3486
rtl8xxxu_set_mac(struct rtl8xxxu_priv * priv)3487 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
3488 {
3489 int i;
3490 u16 reg;
3491
3492 reg = REG_MACID;
3493
3494 for (i = 0; i < ETH_ALEN; i++)
3495 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
3496
3497 return 0;
3498 }
3499
rtl8xxxu_set_bssid(struct rtl8xxxu_priv * priv,const u8 * bssid)3500 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
3501 {
3502 int i;
3503 u16 reg;
3504
3505 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
3506
3507 reg = REG_BSSID;
3508
3509 for (i = 0; i < ETH_ALEN; i++)
3510 rtl8xxxu_write8(priv, reg + i, bssid[i]);
3511
3512 return 0;
3513 }
3514
3515 static void
rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv * priv,u8 ampdu_factor)3516 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
3517 {
3518 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
3519 u8 max_agg = 0xf;
3520 int i;
3521
3522 ampdu_factor = 1 << (ampdu_factor + 2);
3523 if (ampdu_factor > max_agg)
3524 ampdu_factor = max_agg;
3525
3526 for (i = 0; i < 4; i++) {
3527 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
3528 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
3529
3530 if ((vals[i] & 0x0f) > ampdu_factor)
3531 vals[i] = (vals[i] & 0xf0) | ampdu_factor;
3532
3533 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
3534 }
3535 }
3536
rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv * priv,u8 density)3537 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
3538 {
3539 u8 val8;
3540
3541 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
3542 val8 &= 0xf8;
3543 val8 |= density;
3544 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
3545 }
3546
rtl8xxxu_active_to_emu(struct rtl8xxxu_priv * priv)3547 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
3548 {
3549 u8 val8;
3550 int count, ret = 0;
3551
3552 /* Start of rtl8723AU_card_enable_flow */
3553 /* Act to Cardemu sequence*/
3554 /* Turn off RF */
3555 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
3556
3557 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
3558 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
3559 val8 &= ~LEDCFG2_DPDT_SELECT;
3560 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
3561
3562 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
3563 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3564 val8 |= BIT(1);
3565 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3566
3567 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3568 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3569 if ((val8 & BIT(1)) == 0)
3570 break;
3571 udelay(10);
3572 }
3573
3574 if (!count) {
3575 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
3576 __func__);
3577 ret = -EBUSY;
3578 goto exit;
3579 }
3580
3581 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
3582 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3583 val8 |= SYS_ISO_ANALOG_IPS;
3584 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3585
3586 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
3587 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3588 val8 &= ~LDOA15_ENABLE;
3589 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3590
3591 exit:
3592 return ret;
3593 }
3594
rtl8xxxu_active_to_lps(struct rtl8xxxu_priv * priv)3595 int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
3596 {
3597 u8 val8;
3598 u8 val32;
3599 int count, ret = 0;
3600
3601 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3602
3603 /*
3604 * Poll - wait for RX packet to complete
3605 */
3606 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3607 val32 = rtl8xxxu_read32(priv, 0x5f8);
3608 if (!val32)
3609 break;
3610 udelay(10);
3611 }
3612
3613 if (!count) {
3614 dev_warn(&priv->udev->dev,
3615 "%s: RX poll timed out (0x05f8)\n", __func__);
3616 ret = -EBUSY;
3617 goto exit;
3618 }
3619
3620 /* Disable CCK and OFDM, clock gated */
3621 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3622 val8 &= ~SYS_FUNC_BBRSTB;
3623 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3624
3625 udelay(2);
3626
3627 /* Reset baseband */
3628 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3629 val8 &= ~SYS_FUNC_BB_GLB_RSTN;
3630 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3631
3632 /* Reset MAC TRX */
3633 val8 = rtl8xxxu_read8(priv, REG_CR);
3634 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
3635 rtl8xxxu_write8(priv, REG_CR, val8);
3636
3637 /* Reset MAC TRX */
3638 val8 = rtl8xxxu_read8(priv, REG_CR + 1);
3639 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
3640 rtl8xxxu_write8(priv, REG_CR + 1, val8);
3641
3642 /* Respond TX OK to scheduler */
3643 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
3644 val8 |= DUAL_TSF_TX_OK;
3645 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
3646
3647 exit:
3648 return ret;
3649 }
3650
rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv * priv)3651 void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv)
3652 {
3653 u8 val8;
3654
3655 /* Clear suspend enable and power down enable*/
3656 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3657 val8 &= ~(BIT(3) | BIT(7));
3658 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3659
3660 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
3661 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3662 val8 &= ~BIT(0);
3663 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3664
3665 /* 0x04[12:11] = 11 enable WL suspend*/
3666 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3667 val8 &= ~(BIT(3) | BIT(4));
3668 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3669 }
3670
rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv * priv)3671 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
3672 {
3673 u8 val8;
3674
3675 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
3676 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
3677
3678 /* 0x04[12:11] = 01 enable WL suspend */
3679 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3680 val8 &= ~BIT(4);
3681 val8 |= BIT(3);
3682 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3683
3684 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3685 val8 |= BIT(7);
3686 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3687
3688 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
3689 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3690 val8 |= BIT(0);
3691 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3692
3693 return 0;
3694 }
3695
rtl8xxxu_flush_fifo(struct rtl8xxxu_priv * priv)3696 int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv)
3697 {
3698 struct device *dev = &priv->udev->dev;
3699 u32 val32;
3700 int retry, retval;
3701
3702 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3703
3704 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
3705 val32 |= RXPKT_NUM_RW_RELEASE_EN;
3706 rtl8xxxu_write32(priv, REG_RXPKT_NUM, val32);
3707
3708 retry = 100;
3709 retval = -EBUSY;
3710
3711 do {
3712 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
3713 if (val32 & RXPKT_NUM_RXDMA_IDLE) {
3714 retval = 0;
3715 break;
3716 }
3717 } while (retry--);
3718
3719 rtl8xxxu_write16(priv, REG_RQPN_NPQ, 0);
3720 rtl8xxxu_write32(priv, REG_RQPN, 0x80000000);
3721 mdelay(2);
3722
3723 if (!retry)
3724 dev_warn(dev, "Failed to flush FIFO\n");
3725
3726 return retval;
3727 }
3728
rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv * priv)3729 void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv)
3730 {
3731 /* Fix USB interface interference issue */
3732 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
3733 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
3734 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3735 /*
3736 * This sets TXDMA_OFFSET_DROP_DATA_EN (bit 9) as well as bits
3737 * 8 and 5, for which I have found no documentation.
3738 */
3739 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
3740
3741 /*
3742 * Solve too many protocol error on USB bus.
3743 * Can't do this for 8188/8192 UMC A cut parts
3744 */
3745 if (!(!priv->chip_cut && priv->vendor_umc)) {
3746 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
3747 rtl8xxxu_write8(priv, 0xfe41, 0x94);
3748 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3749
3750 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
3751 rtl8xxxu_write8(priv, 0xfe41, 0x19);
3752 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3753
3754 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
3755 rtl8xxxu_write8(priv, 0xfe41, 0x91);
3756 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3757
3758 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
3759 rtl8xxxu_write8(priv, 0xfe41, 0x81);
3760 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3761 }
3762 }
3763
rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv * priv)3764 void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv)
3765 {
3766 u32 val32;
3767
3768 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
3769 val32 |= TXDMA_OFFSET_DROP_DATA_EN;
3770 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
3771 }
3772
rtl8xxxu_power_off(struct rtl8xxxu_priv * priv)3773 void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
3774 {
3775 u8 val8;
3776 u16 val16;
3777 u32 val32;
3778
3779 /*
3780 * Workaround for 8188RU LNA power leakage problem.
3781 */
3782 if (priv->rtl_chip == RTL8188R) {
3783 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
3784 val32 |= BIT(1);
3785 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
3786 }
3787
3788 rtl8xxxu_flush_fifo(priv);
3789
3790 rtl8xxxu_active_to_lps(priv);
3791
3792 /* Turn off RF */
3793 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
3794
3795 /* Reset Firmware if running in RAM */
3796 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
3797 rtl8xxxu_firmware_self_reset(priv);
3798
3799 /* Reset MCU */
3800 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3801 val16 &= ~SYS_FUNC_CPU_ENABLE;
3802 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3803
3804 /* Reset MCU ready status */
3805 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
3806
3807 rtl8xxxu_active_to_emu(priv);
3808 rtl8xxxu_emu_to_disabled(priv);
3809
3810 /* Reset MCU IO Wrapper */
3811 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3812 val8 &= ~BIT(0);
3813 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3814
3815 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3816 val8 |= BIT(0);
3817 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3818
3819 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
3820 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
3821 }
3822
3823 #ifdef NEED_PS_TDMA
rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv * priv,u8 arg1,u8 arg2,u8 arg3,u8 arg4,u8 arg5)3824 static void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
3825 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5)
3826 {
3827 struct h2c_cmd h2c;
3828
3829 memset(&h2c, 0, sizeof(struct h2c_cmd));
3830 h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA;
3831 h2c.b_type_dma.data1 = arg1;
3832 h2c.b_type_dma.data2 = arg2;
3833 h2c.b_type_dma.data3 = arg3;
3834 h2c.b_type_dma.data4 = arg4;
3835 h2c.b_type_dma.data5 = arg5;
3836 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma));
3837 }
3838 #endif
3839
rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv * priv)3840 void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv)
3841 {
3842 u32 val32;
3843
3844 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA);
3845 val32 &= ~(BIT(22) | BIT(23));
3846 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32);
3847 }
3848
rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv * priv)3849 static void rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv *priv)
3850 {
3851 struct rtl8xxxu_fileops *fops = priv->fops;
3852 u32 hq, lq, nq, eq, pubq;
3853 u32 val32;
3854
3855 hq = 0;
3856 lq = 0;
3857 nq = 0;
3858 eq = 0;
3859 pubq = 0;
3860
3861 if (priv->ep_tx_high_queue)
3862 hq = fops->page_num_hi;
3863 if (priv->ep_tx_low_queue)
3864 lq = fops->page_num_lo;
3865 if (priv->ep_tx_normal_queue)
3866 nq = fops->page_num_norm;
3867
3868 val32 = (nq << RQPN_NPQ_SHIFT) | (eq << RQPN_EPQ_SHIFT);
3869 rtl8xxxu_write32(priv, REG_RQPN_NPQ, val32);
3870
3871 pubq = fops->total_page_num - hq - lq - nq - 1;
3872
3873 val32 = RQPN_LOAD;
3874 val32 |= (hq << RQPN_HI_PQ_SHIFT);
3875 val32 |= (lq << RQPN_LO_PQ_SHIFT);
3876 val32 |= (pubq << RQPN_PUB_PQ_SHIFT);
3877
3878 rtl8xxxu_write32(priv, REG_RQPN, val32);
3879 }
3880
rtl8xxxu_init_device(struct ieee80211_hw * hw)3881 static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
3882 {
3883 struct rtl8xxxu_priv *priv = hw->priv;
3884 struct device *dev = &priv->udev->dev;
3885 struct rtl8xxxu_fileops *fops = priv->fops;
3886 bool macpower;
3887 int ret;
3888 u8 val8;
3889 u16 val16;
3890 u32 val32;
3891
3892 /* Check if MAC is already powered on */
3893 val8 = rtl8xxxu_read8(priv, REG_CR);
3894 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
3895
3896 /*
3897 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
3898 * initialized. First MAC returns 0xea, second MAC returns 0x00
3899 */
3900 if (val8 == 0xea || !(val16 & SYS_CLK_MAC_CLK_ENABLE))
3901 macpower = false;
3902 else
3903 macpower = true;
3904
3905 ret = fops->power_on(priv);
3906 if (ret < 0) {
3907 dev_warn(dev, "%s: Failed power on\n", __func__);
3908 goto exit;
3909 }
3910
3911 if (!macpower)
3912 rtl8xxxu_init_queue_reserved_page(priv);
3913
3914 ret = rtl8xxxu_init_queue_priority(priv);
3915 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
3916 if (ret)
3917 goto exit;
3918
3919 /*
3920 * Set RX page boundary
3921 */
3922 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, fops->trxff_boundary);
3923
3924 ret = rtl8xxxu_download_firmware(priv);
3925 dev_dbg(dev, "%s: download_firmware %i\n", __func__, ret);
3926 if (ret)
3927 goto exit;
3928 ret = rtl8xxxu_start_firmware(priv);
3929 dev_dbg(dev, "%s: start_firmware %i\n", __func__, ret);
3930 if (ret)
3931 goto exit;
3932
3933 if (fops->phy_init_antenna_selection)
3934 fops->phy_init_antenna_selection(priv);
3935
3936 ret = rtl8xxxu_init_mac(priv);
3937
3938 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
3939 if (ret)
3940 goto exit;
3941
3942 ret = rtl8xxxu_init_phy_bb(priv);
3943 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
3944 if (ret)
3945 goto exit;
3946
3947 ret = fops->init_phy_rf(priv);
3948 if (ret)
3949 goto exit;
3950
3951 /* RFSW Control - clear bit 14 ?? */
3952 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E)
3953 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
3954
3955 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
3956 FPGA0_RF_ANTSWB |
3957 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB) << FPGA0_RF_BD_CTRL_SHIFT);
3958 if (!priv->no_pape) {
3959 val32 |= (FPGA0_RF_PAPE |
3960 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3961 }
3962 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
3963
3964 /* 0x860[6:5]= 00 - why? - this sets antenna B */
3965 if (priv->rtl_chip != RTL8192E)
3966 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210);
3967
3968 if (!macpower) {
3969 /*
3970 * Set TX buffer boundary
3971 */
3972 val8 = fops->total_page_num + 1;
3973
3974 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
3975 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
3976 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
3977 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
3978 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
3979 }
3980
3981 /*
3982 * The vendor drivers set PBP for all devices, except 8192e.
3983 * There is no explanation for this in any of the sources.
3984 */
3985 val8 = (fops->pbp_rx << PBP_PAGE_SIZE_RX_SHIFT) |
3986 (fops->pbp_tx << PBP_PAGE_SIZE_TX_SHIFT);
3987 if (priv->rtl_chip != RTL8192E)
3988 rtl8xxxu_write8(priv, REG_PBP, val8);
3989
3990 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
3991 if (!macpower) {
3992 ret = fops->llt_init(priv);
3993 if (ret) {
3994 dev_warn(dev, "%s: LLT table init failed\n", __func__);
3995 goto exit;
3996 }
3997
3998 /*
3999 * Chip specific quirks
4000 */
4001 fops->usb_quirks(priv);
4002
4003 /*
4004 * Enable TX report and TX report timer for 8723bu/8188eu/...
4005 */
4006 if (fops->has_tx_report) {
4007 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
4008 val8 |= TX_REPORT_CTRL_TIMER_ENABLE;
4009 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
4010 /* Set MAX RPT MACID */
4011 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02);
4012 /* TX report Timer. Unit: 32us */
4013 rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0);
4014
4015 /* tmp ps ? */
4016 val8 = rtl8xxxu_read8(priv, 0xa3);
4017 val8 &= 0xf8;
4018 rtl8xxxu_write8(priv, 0xa3, val8);
4019 }
4020 }
4021
4022 /*
4023 * Unit in 8 bytes, not obvious what it is used for
4024 */
4025 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
4026
4027 if (priv->rtl_chip == RTL8192E) {
4028 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
4029 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
4030 } else {
4031 /*
4032 * Enable all interrupts - not obvious USB needs to do this
4033 */
4034 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
4035 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
4036 }
4037
4038 rtl8xxxu_set_mac(priv);
4039 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
4040
4041 /*
4042 * Configure initial WMAC settings
4043 */
4044 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
4045 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
4046 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
4047 rtl8xxxu_write32(priv, REG_RCR, val32);
4048
4049 /*
4050 * Accept all multicast
4051 */
4052 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
4053 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
4054
4055 /*
4056 * Init adaptive controls
4057 */
4058 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4059 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4060 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
4061 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4062
4063 /* CCK = 0x0a, OFDM = 0x10 */
4064 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
4065 rtl8xxxu_set_retry(priv, 0x30, 0x30);
4066 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
4067
4068 /*
4069 * Init EDCA
4070 */
4071 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
4072
4073 /* Set CCK SIFS */
4074 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
4075
4076 /* Set OFDM SIFS */
4077 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
4078
4079 /* TXOP */
4080 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
4081 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
4082 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
4083 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
4084
4085 /* Set data auto rate fallback retry count */
4086 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
4087 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
4088 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
4089 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
4090
4091 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
4092 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
4093 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
4094
4095 /* Set ACK timeout */
4096 rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
4097
4098 /*
4099 * Initialize beacon parameters
4100 */
4101 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
4102 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
4103 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
4104 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
4105 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
4106 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
4107
4108 /*
4109 * Initialize burst parameters
4110 */
4111 if (priv->rtl_chip == RTL8723B) {
4112 /*
4113 * For USB high speed set 512B packets
4114 */
4115 val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B);
4116 val8 &= ~(BIT(4) | BIT(5));
4117 val8 |= BIT(4);
4118 val8 |= BIT(1) | BIT(2) | BIT(3);
4119 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8);
4120
4121 /*
4122 * For USB high speed set 512B packets
4123 */
4124 val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B);
4125 val8 |= BIT(7);
4126 rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8);
4127
4128 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14);
4129 rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 0x5e);
4130 rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff);
4131 rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18);
4132 rtl8xxxu_write8(priv, REG_PIFS, 0x00);
4133 rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, 0x50);
4134 rtl8xxxu_write8(priv, REG_USTIME_EDCA, 0x50);
4135
4136 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
4137 val8 |= BIT(5) | BIT(6);
4138 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
4139 }
4140
4141 if (fops->init_aggregation)
4142 fops->init_aggregation(priv);
4143
4144 /*
4145 * Enable CCK and OFDM block
4146 */
4147 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4148 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
4149 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4150
4151 /*
4152 * Invalidate all CAM entries - bit 30 is undocumented
4153 */
4154 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
4155
4156 /*
4157 * Start out with default power levels for channel 6, 20MHz
4158 */
4159 fops->set_tx_power(priv, 1, false);
4160
4161 /* Let the 8051 take control of antenna setting */
4162 if (priv->rtl_chip != RTL8192E) {
4163 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4164 val8 |= LEDCFG2_DPDT_SELECT;
4165 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4166 }
4167
4168 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
4169
4170 /* Disable BAR - not sure if this has any effect on USB */
4171 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
4172
4173 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
4174
4175 if (fops->init_statistics)
4176 fops->init_statistics(priv);
4177
4178 if (priv->rtl_chip == RTL8192E) {
4179 /*
4180 * 0x4c6[3] 1: RTS BW = Data BW
4181 * 0: RTS BW depends on CCA / secondary CCA result.
4182 */
4183 val8 = rtl8xxxu_read8(priv, REG_QUEUE_CTRL);
4184 val8 &= ~BIT(3);
4185 rtl8xxxu_write8(priv, REG_QUEUE_CTRL, val8);
4186 /*
4187 * Reset USB mode switch setting
4188 */
4189 rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00);
4190 }
4191
4192 rtl8723a_phy_lc_calibrate(priv);
4193
4194 fops->phy_iq_calibrate(priv);
4195
4196 /*
4197 * This should enable thermal meter
4198 */
4199 if (fops->gen2_thermal_meter)
4200 rtl8xxxu_write_rfreg(priv,
4201 RF_A, RF6052_REG_T_METER_8723B, 0x37cf8);
4202 else
4203 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
4204
4205 /* Set NAV_UPPER to 30000us */
4206 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
4207 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
4208
4209 if (priv->rtl_chip == RTL8723A) {
4210 /*
4211 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
4212 * but we need to find root cause.
4213 * This is 8723au only.
4214 */
4215 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4216 if ((val32 & 0xff000000) != 0x83000000) {
4217 val32 |= FPGA_RF_MODE_CCK;
4218 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4219 }
4220 } else if (priv->rtl_chip == RTL8192E) {
4221 rtl8xxxu_write8(priv, REG_USB_HRPWM, 0x00);
4222 }
4223
4224 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
4225 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
4226 /* ack for xmit mgmt frames. */
4227 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
4228
4229 if (priv->rtl_chip == RTL8192E) {
4230 /*
4231 * Fix LDPC rx hang issue.
4232 */
4233 val32 = rtl8xxxu_read32(priv, REG_AFE_MISC);
4234 rtl8xxxu_write8(priv, REG_8192E_LDOV12_CTRL, 0x75);
4235 val32 &= 0xfff00fff;
4236 val32 |= 0x0007e000;
4237 rtl8xxxu_write32(priv, REG_AFE_MISC, val32);
4238 }
4239 exit:
4240 return ret;
4241 }
4242
rtl8xxxu_cam_write(struct rtl8xxxu_priv * priv,struct ieee80211_key_conf * key,const u8 * mac)4243 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
4244 struct ieee80211_key_conf *key, const u8 *mac)
4245 {
4246 u32 cmd, val32, addr, ctrl;
4247 int j, i, tmp_debug;
4248
4249 tmp_debug = rtl8xxxu_debug;
4250 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
4251 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
4252
4253 /*
4254 * This is a bit of a hack - the lower bits of the cipher
4255 * suite selector happens to match the cipher index in the CAM
4256 */
4257 addr = key->keyidx << CAM_CMD_KEY_SHIFT;
4258 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
4259
4260 for (j = 5; j >= 0; j--) {
4261 switch (j) {
4262 case 0:
4263 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
4264 break;
4265 case 1:
4266 val32 = mac[2] | (mac[3] << 8) |
4267 (mac[4] << 16) | (mac[5] << 24);
4268 break;
4269 default:
4270 i = (j - 2) << 2;
4271 val32 = key->key[i] | (key->key[i + 1] << 8) |
4272 key->key[i + 2] << 16 | key->key[i + 3] << 24;
4273 break;
4274 }
4275
4276 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
4277 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
4278 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
4279 udelay(100);
4280 }
4281
4282 rtl8xxxu_debug = tmp_debug;
4283 }
4284
rtl8xxxu_sw_scan_start(struct ieee80211_hw * hw,struct ieee80211_vif * vif,const u8 * mac)4285 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
4286 struct ieee80211_vif *vif, const u8 *mac)
4287 {
4288 struct rtl8xxxu_priv *priv = hw->priv;
4289 u8 val8;
4290
4291 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4292 val8 |= BEACON_DISABLE_TSF_UPDATE;
4293 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4294 }
4295
rtl8xxxu_sw_scan_complete(struct ieee80211_hw * hw,struct ieee80211_vif * vif)4296 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
4297 struct ieee80211_vif *vif)
4298 {
4299 struct rtl8xxxu_priv *priv = hw->priv;
4300 u8 val8;
4301
4302 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4303 val8 &= ~BEACON_DISABLE_TSF_UPDATE;
4304 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4305 }
4306
rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv * priv,u32 ramask,int sgi)4307 void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv, u32 ramask, int sgi)
4308 {
4309 struct h2c_cmd h2c;
4310
4311 memset(&h2c, 0, sizeof(struct h2c_cmd));
4312
4313 h2c.ramask.cmd = H2C_SET_RATE_MASK;
4314 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
4315 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
4316
4317 h2c.ramask.arg = 0x80;
4318 if (sgi)
4319 h2c.ramask.arg |= 0x20;
4320
4321 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
4322 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask));
4323 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.ramask));
4324 }
4325
rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv * priv,u32 ramask,int sgi)4326 void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv,
4327 u32 ramask, int sgi)
4328 {
4329 struct h2c_cmd h2c;
4330 u8 bw = 0;
4331
4332 memset(&h2c, 0, sizeof(struct h2c_cmd));
4333
4334 h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID;
4335 h2c.b_macid_cfg.ramask0 = ramask & 0xff;
4336 h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff;
4337 h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff;
4338 h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff;
4339
4340 h2c.ramask.arg = 0x80;
4341 h2c.b_macid_cfg.data1 = 0;
4342 if (sgi)
4343 h2c.b_macid_cfg.data1 |= BIT(7);
4344
4345 h2c.b_macid_cfg.data2 = bw;
4346
4347 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
4348 __func__, ramask, h2c.ramask.arg, sizeof(h2c.b_macid_cfg));
4349 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg));
4350 }
4351
rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv * priv,u8 macid,bool connect)4352 void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv,
4353 u8 macid, bool connect)
4354 {
4355 struct h2c_cmd h2c;
4356
4357 memset(&h2c, 0, sizeof(struct h2c_cmd));
4358
4359 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
4360
4361 if (connect)
4362 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
4363 else
4364 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
4365
4366 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss));
4367 }
4368
rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv * priv,u8 macid,bool connect)4369 void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv,
4370 u8 macid, bool connect)
4371 {
4372 #ifdef RTL8XXXU_GEN2_REPORT_CONNECT
4373 /*
4374 * Barry Day reports this causes issues with 8192eu and 8723bu
4375 * devices reconnecting. The reason for this is unclear, but
4376 * until it is better understood, leave the code in place but
4377 * disabled, so it is not lost.
4378 */
4379 struct h2c_cmd h2c;
4380
4381 memset(&h2c, 0, sizeof(struct h2c_cmd));
4382
4383 h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT;
4384 if (connect)
4385 h2c.media_status_rpt.parm |= BIT(0);
4386 else
4387 h2c.media_status_rpt.parm &= ~BIT(0);
4388
4389 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt));
4390 #endif
4391 }
4392
rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv * priv)4393 void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv)
4394 {
4395 u8 agg_ctrl, usb_spec, page_thresh, timeout;
4396
4397 usb_spec = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION);
4398 usb_spec &= ~USB_SPEC_USB_AGG_ENABLE;
4399 rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, usb_spec);
4400
4401 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);
4402 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;
4403
4404 if (!rtl8xxxu_dma_aggregation) {
4405 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
4406 return;
4407 }
4408
4409 agg_ctrl |= TRXDMA_CTRL_RXDMA_AGG_EN;
4410 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
4411
4412 /*
4413 * The number of packets we can take looks to be buffer size / 512
4414 * which matches the 512 byte rounding we have to do when de-muxing
4415 * the packets.
4416 *
4417 * Sample numbers from the vendor driver:
4418 * USB High-Speed mode values:
4419 * RxAggBlockCount = 8 : 512 byte unit
4420 * RxAggBlockTimeout = 6
4421 * RxAggPageCount = 48 : 128 byte unit
4422 * RxAggPageTimeout = 4 or 6 (absolute time 34ms/(2^6))
4423 */
4424
4425 page_thresh = (priv->fops->rx_agg_buf_size / 512);
4426 if (rtl8xxxu_dma_agg_pages >= 0) {
4427 if (rtl8xxxu_dma_agg_pages <= page_thresh)
4428 timeout = page_thresh;
4429 else if (rtl8xxxu_dma_agg_pages <= 6)
4430 dev_err(&priv->udev->dev,
4431 "%s: dma_agg_pages=%i too small, minimum is 6\n",
4432 __func__, rtl8xxxu_dma_agg_pages);
4433 else
4434 dev_err(&priv->udev->dev,
4435 "%s: dma_agg_pages=%i larger than limit %i\n",
4436 __func__, rtl8xxxu_dma_agg_pages, page_thresh);
4437 }
4438 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH, page_thresh);
4439 /*
4440 * REG_RXDMA_AGG_PG_TH + 1 seems to be the timeout register on
4441 * gen2 chips and rtl8188eu. The rtl8723au seems unhappy if we
4442 * don't set it, so better set both.
4443 */
4444 timeout = 4;
4445
4446 if (rtl8xxxu_dma_agg_timeout >= 0) {
4447 if (rtl8xxxu_dma_agg_timeout <= 127)
4448 timeout = rtl8xxxu_dma_agg_timeout;
4449 else
4450 dev_err(&priv->udev->dev,
4451 "%s: Invalid dma_agg_timeout: %i\n",
4452 __func__, rtl8xxxu_dma_agg_timeout);
4453 }
4454
4455 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH + 1, timeout);
4456 rtl8xxxu_write8(priv, REG_USB_DMA_AGG_TO, timeout);
4457 priv->rx_buf_aggregation = 1;
4458 }
4459
rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv * priv,u32 rate_cfg)4460 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
4461 {
4462 u32 val32;
4463 u8 rate_idx = 0;
4464
4465 rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
4466
4467 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4468 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4469 val32 |= rate_cfg;
4470 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4471
4472 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
4473
4474 while (rate_cfg) {
4475 rate_cfg = (rate_cfg >> 1);
4476 rate_idx++;
4477 }
4478 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
4479 }
4480
4481 static void
rtl8xxxu_bss_info_changed(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_bss_conf * bss_conf,u32 changed)4482 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4483 struct ieee80211_bss_conf *bss_conf, u32 changed)
4484 {
4485 struct rtl8xxxu_priv *priv = hw->priv;
4486 struct device *dev = &priv->udev->dev;
4487 struct ieee80211_sta *sta;
4488 u32 val32;
4489 u8 val8;
4490
4491 if (changed & BSS_CHANGED_ASSOC) {
4492 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
4493
4494 rtl8xxxu_set_linktype(priv, vif->type);
4495
4496 if (bss_conf->assoc) {
4497 u32 ramask;
4498 int sgi = 0;
4499
4500 rcu_read_lock();
4501 sta = ieee80211_find_sta(vif, bss_conf->bssid);
4502 if (!sta) {
4503 dev_info(dev, "%s: ASSOC no sta found\n",
4504 __func__);
4505 rcu_read_unlock();
4506 goto error;
4507 }
4508
4509 if (sta->ht_cap.ht_supported)
4510 dev_info(dev, "%s: HT supported\n", __func__);
4511 if (sta->vht_cap.vht_supported)
4512 dev_info(dev, "%s: VHT supported\n", __func__);
4513
4514 /* TODO: Set bits 28-31 for rate adaptive id */
4515 ramask = (sta->supp_rates[0] & 0xfff) |
4516 sta->ht_cap.mcs.rx_mask[0] << 12 |
4517 sta->ht_cap.mcs.rx_mask[1] << 20;
4518 if (sta->ht_cap.cap &
4519 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
4520 sgi = 1;
4521 rcu_read_unlock();
4522
4523 priv->fops->update_rate_mask(priv, ramask, sgi);
4524
4525 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
4526
4527 rtl8xxxu_stop_tx_beacon(priv);
4528
4529 /* joinbss sequence */
4530 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
4531 0xc000 | bss_conf->aid);
4532
4533 priv->fops->report_connect(priv, 0, true);
4534 } else {
4535 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4536 val8 |= BEACON_DISABLE_TSF_UPDATE;
4537 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4538
4539 priv->fops->report_connect(priv, 0, false);
4540 }
4541 }
4542
4543 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
4544 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
4545 bss_conf->use_short_preamble);
4546 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4547 if (bss_conf->use_short_preamble)
4548 val32 |= RSR_ACK_SHORT_PREAMBLE;
4549 else
4550 val32 &= ~RSR_ACK_SHORT_PREAMBLE;
4551 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4552 }
4553
4554 if (changed & BSS_CHANGED_ERP_SLOT) {
4555 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
4556 bss_conf->use_short_slot);
4557
4558 if (bss_conf->use_short_slot)
4559 val8 = 9;
4560 else
4561 val8 = 20;
4562 rtl8xxxu_write8(priv, REG_SLOT, val8);
4563 }
4564
4565 if (changed & BSS_CHANGED_BSSID) {
4566 dev_dbg(dev, "Changed BSSID!\n");
4567 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
4568 }
4569
4570 if (changed & BSS_CHANGED_BASIC_RATES) {
4571 dev_dbg(dev, "Changed BASIC_RATES!\n");
4572 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
4573 }
4574 error:
4575 return;
4576 }
4577
rtl8xxxu_80211_to_rtl_queue(u32 queue)4578 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
4579 {
4580 u32 rtlqueue;
4581
4582 switch (queue) {
4583 case IEEE80211_AC_VO:
4584 rtlqueue = TXDESC_QUEUE_VO;
4585 break;
4586 case IEEE80211_AC_VI:
4587 rtlqueue = TXDESC_QUEUE_VI;
4588 break;
4589 case IEEE80211_AC_BE:
4590 rtlqueue = TXDESC_QUEUE_BE;
4591 break;
4592 case IEEE80211_AC_BK:
4593 rtlqueue = TXDESC_QUEUE_BK;
4594 break;
4595 default:
4596 rtlqueue = TXDESC_QUEUE_BE;
4597 }
4598
4599 return rtlqueue;
4600 }
4601
rtl8xxxu_queue_select(struct ieee80211_hw * hw,struct sk_buff * skb)4602 static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
4603 {
4604 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4605 u32 queue;
4606
4607 if (ieee80211_is_mgmt(hdr->frame_control))
4608 queue = TXDESC_QUEUE_MGNT;
4609 else
4610 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
4611
4612 return queue;
4613 }
4614
4615 /*
4616 * Despite newer chips 8723b/8812/8821 having a larger TX descriptor
4617 * format. The descriptor checksum is still only calculated over the
4618 * initial 32 bytes of the descriptor!
4619 */
rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 * tx_desc)4620 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc)
4621 {
4622 __le16 *ptr = (__le16 *)tx_desc;
4623 u16 csum = 0;
4624 int i;
4625
4626 /*
4627 * Clear csum field before calculation, as the csum field is
4628 * in the middle of the struct.
4629 */
4630 tx_desc->csum = cpu_to_le16(0);
4631
4632 for (i = 0; i < (sizeof(struct rtl8xxxu_txdesc32) / sizeof(u16)); i++)
4633 csum = csum ^ le16_to_cpu(ptr[i]);
4634
4635 tx_desc->csum |= cpu_to_le16(csum);
4636 }
4637
rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv * priv)4638 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
4639 {
4640 struct rtl8xxxu_tx_urb *tx_urb, *tmp;
4641 unsigned long flags;
4642
4643 spin_lock_irqsave(&priv->tx_urb_lock, flags);
4644 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
4645 list_del(&tx_urb->list);
4646 priv->tx_urb_free_count--;
4647 usb_free_urb(&tx_urb->urb);
4648 }
4649 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4650 }
4651
4652 static struct rtl8xxxu_tx_urb *
rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv * priv)4653 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
4654 {
4655 struct rtl8xxxu_tx_urb *tx_urb;
4656 unsigned long flags;
4657
4658 spin_lock_irqsave(&priv->tx_urb_lock, flags);
4659 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
4660 struct rtl8xxxu_tx_urb, list);
4661 if (tx_urb) {
4662 list_del(&tx_urb->list);
4663 priv->tx_urb_free_count--;
4664 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
4665 !priv->tx_stopped) {
4666 priv->tx_stopped = true;
4667 ieee80211_stop_queues(priv->hw);
4668 }
4669 }
4670
4671 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4672
4673 return tx_urb;
4674 }
4675
rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv * priv,struct rtl8xxxu_tx_urb * tx_urb)4676 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
4677 struct rtl8xxxu_tx_urb *tx_urb)
4678 {
4679 unsigned long flags;
4680
4681 INIT_LIST_HEAD(&tx_urb->list);
4682
4683 spin_lock_irqsave(&priv->tx_urb_lock, flags);
4684
4685 list_add(&tx_urb->list, &priv->tx_urb_free_list);
4686 priv->tx_urb_free_count++;
4687 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
4688 priv->tx_stopped) {
4689 priv->tx_stopped = false;
4690 ieee80211_wake_queues(priv->hw);
4691 }
4692
4693 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4694 }
4695
rtl8xxxu_tx_complete(struct urb * urb)4696 static void rtl8xxxu_tx_complete(struct urb *urb)
4697 {
4698 struct sk_buff *skb = (struct sk_buff *)urb->context;
4699 struct ieee80211_tx_info *tx_info;
4700 struct ieee80211_hw *hw;
4701 struct rtl8xxxu_priv *priv;
4702 struct rtl8xxxu_tx_urb *tx_urb =
4703 container_of(urb, struct rtl8xxxu_tx_urb, urb);
4704
4705 tx_info = IEEE80211_SKB_CB(skb);
4706 hw = tx_info->rate_driver_data[0];
4707 priv = hw->priv;
4708
4709 skb_pull(skb, priv->fops->tx_desc_size);
4710
4711 ieee80211_tx_info_clear_status(tx_info);
4712 tx_info->status.rates[0].idx = -1;
4713 tx_info->status.rates[0].count = 0;
4714
4715 if (!urb->status)
4716 tx_info->flags |= IEEE80211_TX_STAT_ACK;
4717
4718 ieee80211_tx_status_irqsafe(hw, skb);
4719
4720 rtl8xxxu_free_tx_urb(priv, tx_urb);
4721 }
4722
rtl8xxxu_dump_action(struct device * dev,struct ieee80211_hdr * hdr)4723 static void rtl8xxxu_dump_action(struct device *dev,
4724 struct ieee80211_hdr *hdr)
4725 {
4726 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
4727 u16 cap, timeout;
4728
4729 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
4730 return;
4731
4732 switch (mgmt->u.action.u.addba_resp.action_code) {
4733 case WLAN_ACTION_ADDBA_RESP:
4734 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
4735 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
4736 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
4737 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
4738 "status %02x\n",
4739 timeout,
4740 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
4741 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
4742 (cap >> 1) & 0x1,
4743 le16_to_cpu(mgmt->u.action.u.addba_resp.status));
4744 break;
4745 case WLAN_ACTION_ADDBA_REQ:
4746 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
4747 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
4748 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
4749 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
4750 timeout,
4751 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
4752 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
4753 (cap >> 1) & 0x1);
4754 break;
4755 default:
4756 dev_info(dev, "action frame %02x\n",
4757 mgmt->u.action.u.addba_resp.action_code);
4758 break;
4759 }
4760 }
4761
4762 /*
4763 * Fill in v1 (gen1) specific TX descriptor bits.
4764 * This format is used on 8188cu/8192cu/8723au
4765 */
4766 void
rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw * hw,struct ieee80211_hdr * hdr,struct ieee80211_tx_info * tx_info,struct rtl8xxxu_txdesc32 * tx_desc,bool sgi,bool short_preamble,bool ampdu_enable,u32 rts_rate)4767 rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
4768 struct ieee80211_tx_info *tx_info,
4769 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi,
4770 bool short_preamble, bool ampdu_enable, u32 rts_rate)
4771 {
4772 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
4773 struct rtl8xxxu_priv *priv = hw->priv;
4774 struct device *dev = &priv->udev->dev;
4775 u32 rate;
4776 u16 rate_flags = tx_info->control.rates[0].flags;
4777 u16 seq_number;
4778
4779 if (rate_flags & IEEE80211_TX_RC_MCS &&
4780 !ieee80211_is_mgmt(hdr->frame_control))
4781 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
4782 else
4783 rate = tx_rate->hw_value;
4784
4785 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
4786 dev_info(dev, "%s: TX rate: %d, pkt size %d\n",
4787 __func__, rate, cpu_to_le16(tx_desc->pkt_size));
4788
4789 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
4790
4791 tx_desc->txdw5 = cpu_to_le32(rate);
4792
4793 if (ieee80211_is_data(hdr->frame_control))
4794 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
4795
4796 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT);
4797
4798 if (ampdu_enable)
4799 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE);
4800 else
4801 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK);
4802
4803 if (ieee80211_is_mgmt(hdr->frame_control)) {
4804 tx_desc->txdw5 = cpu_to_le32(rate);
4805 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE);
4806 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT);
4807 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE);
4808 }
4809
4810 if (ieee80211_is_data_qos(hdr->frame_control))
4811 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS);
4812
4813 if (short_preamble)
4814 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE);
4815
4816 if (sgi)
4817 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI);
4818
4819 /*
4820 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled
4821 */
4822 tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT);
4823 if (rate_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
4824 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE);
4825 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
4826 } else if (rate_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
4827 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE);
4828 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
4829 }
4830 }
4831
4832 /*
4833 * Fill in v2 (gen2) specific TX descriptor bits.
4834 * This format is used on 8192eu/8723bu
4835 */
4836 void
rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw * hw,struct ieee80211_hdr * hdr,struct ieee80211_tx_info * tx_info,struct rtl8xxxu_txdesc32 * tx_desc32,bool sgi,bool short_preamble,bool ampdu_enable,u32 rts_rate)4837 rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
4838 struct ieee80211_tx_info *tx_info,
4839 struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi,
4840 bool short_preamble, bool ampdu_enable, u32 rts_rate)
4841 {
4842 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
4843 struct rtl8xxxu_priv *priv = hw->priv;
4844 struct device *dev = &priv->udev->dev;
4845 struct rtl8xxxu_txdesc40 *tx_desc40;
4846 u32 rate;
4847 u16 rate_flags = tx_info->control.rates[0].flags;
4848 u16 seq_number;
4849
4850 tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc32;
4851
4852 if (rate_flags & IEEE80211_TX_RC_MCS &&
4853 !ieee80211_is_mgmt(hdr->frame_control))
4854 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
4855 else
4856 rate = tx_rate->hw_value;
4857
4858 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
4859 dev_info(dev, "%s: TX rate: %d, pkt size %d\n",
4860 __func__, rate, cpu_to_le16(tx_desc40->pkt_size));
4861
4862 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
4863
4864 tx_desc40->txdw4 = cpu_to_le32(rate);
4865 if (ieee80211_is_data(hdr->frame_control)) {
4866 tx_desc40->txdw4 |= cpu_to_le32(0x1f <<
4867 TXDESC40_DATA_RATE_FB_SHIFT);
4868 }
4869
4870 tx_desc40->txdw9 = cpu_to_le32((u32)seq_number << TXDESC40_SEQ_SHIFT);
4871
4872 if (ampdu_enable)
4873 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE);
4874 else
4875 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK);
4876
4877 if (ieee80211_is_mgmt(hdr->frame_control)) {
4878 tx_desc40->txdw4 = cpu_to_le32(rate);
4879 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_USE_DRIVER_RATE);
4880 tx_desc40->txdw4 |=
4881 cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT);
4882 tx_desc40->txdw4 |= cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE);
4883 }
4884
4885 if (short_preamble)
4886 tx_desc40->txdw5 |= cpu_to_le32(TXDESC40_SHORT_PREAMBLE);
4887
4888 tx_desc40->txdw4 |= cpu_to_le32(rts_rate << TXDESC40_RTS_RATE_SHIFT);
4889 /*
4890 * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled
4891 */
4892 if (rate_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
4893 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE);
4894 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE);
4895 } else if (rate_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
4896 /*
4897 * For some reason the vendor driver doesn't set
4898 * TXDESC40_HW_RTS_ENABLE for CTS to SELF
4899 */
4900 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_CTS_SELF_ENABLE);
4901 }
4902 }
4903
rtl8xxxu_tx(struct ieee80211_hw * hw,struct ieee80211_tx_control * control,struct sk_buff * skb)4904 static void rtl8xxxu_tx(struct ieee80211_hw *hw,
4905 struct ieee80211_tx_control *control,
4906 struct sk_buff *skb)
4907 {
4908 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4909 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
4910 struct rtl8xxxu_priv *priv = hw->priv;
4911 struct rtl8xxxu_txdesc32 *tx_desc;
4912 struct rtl8xxxu_tx_urb *tx_urb;
4913 struct ieee80211_sta *sta = NULL;
4914 struct ieee80211_vif *vif = tx_info->control.vif;
4915 struct device *dev = &priv->udev->dev;
4916 u32 queue, rts_rate;
4917 u16 pktlen = skb->len;
4918 u16 rate_flag = tx_info->control.rates[0].flags;
4919 int tx_desc_size = priv->fops->tx_desc_size;
4920 int ret;
4921 bool ampdu_enable, sgi = false, short_preamble = false;
4922
4923 if (skb_headroom(skb) < tx_desc_size) {
4924 dev_warn(dev,
4925 "%s: Not enough headroom (%i) for tx descriptor\n",
4926 __func__, skb_headroom(skb));
4927 goto error;
4928 }
4929
4930 if (unlikely(skb->len > (65535 - tx_desc_size))) {
4931 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
4932 __func__, skb->len);
4933 goto error;
4934 }
4935
4936 tx_urb = rtl8xxxu_alloc_tx_urb(priv);
4937 if (!tx_urb) {
4938 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
4939 goto error;
4940 }
4941
4942 if (ieee80211_is_action(hdr->frame_control))
4943 rtl8xxxu_dump_action(dev, hdr);
4944
4945 tx_info->rate_driver_data[0] = hw;
4946
4947 if (control && control->sta)
4948 sta = control->sta;
4949
4950 tx_desc = skb_push(skb, tx_desc_size);
4951
4952 memset(tx_desc, 0, tx_desc_size);
4953 tx_desc->pkt_size = cpu_to_le16(pktlen);
4954 tx_desc->pkt_offset = tx_desc_size;
4955
4956 tx_desc->txdw0 =
4957 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
4958 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
4959 is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
4960 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
4961
4962 queue = rtl8xxxu_queue_select(hw, skb);
4963 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
4964
4965 if (tx_info->control.hw_key) {
4966 switch (tx_info->control.hw_key->cipher) {
4967 case WLAN_CIPHER_SUITE_WEP40:
4968 case WLAN_CIPHER_SUITE_WEP104:
4969 case WLAN_CIPHER_SUITE_TKIP:
4970 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
4971 break;
4972 case WLAN_CIPHER_SUITE_CCMP:
4973 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
4974 break;
4975 default:
4976 break;
4977 }
4978 }
4979
4980 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
4981 ampdu_enable = false;
4982 if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
4983 if (sta->ht_cap.ht_supported) {
4984 u32 ampdu, val32;
4985
4986 ampdu = (u32)sta->ht_cap.ampdu_density;
4987 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
4988 tx_desc->txdw2 |= cpu_to_le32(val32);
4989
4990 ampdu_enable = true;
4991 }
4992 }
4993
4994 if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
4995 (ieee80211_is_data_qos(hdr->frame_control) &&
4996 sta && sta->ht_cap.cap &
4997 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)))
4998 sgi = true;
4999
5000 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
5001 (sta && vif && vif->bss_conf.use_short_preamble))
5002 short_preamble = true;
5003
5004 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS)
5005 rts_rate = ieee80211_get_rts_cts_rate(hw, tx_info)->hw_value;
5006 else if (rate_flag & IEEE80211_TX_RC_USE_CTS_PROTECT)
5007 rts_rate = ieee80211_get_rts_cts_rate(hw, tx_info)->hw_value;
5008 else
5009 rts_rate = 0;
5010
5011
5012 priv->fops->fill_txdesc(hw, hdr, tx_info, tx_desc, sgi, short_preamble,
5013 ampdu_enable, rts_rate);
5014
5015 rtl8xxxu_calc_tx_desc_csum(tx_desc);
5016
5017 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
5018 skb->data, skb->len, rtl8xxxu_tx_complete, skb);
5019
5020 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
5021 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
5022 if (ret) {
5023 usb_unanchor_urb(&tx_urb->urb);
5024 rtl8xxxu_free_tx_urb(priv, tx_urb);
5025 goto error;
5026 }
5027 return;
5028 error:
5029 dev_kfree_skb(skb);
5030 }
5031
rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv * priv,struct ieee80211_rx_status * rx_status,struct rtl8723au_phy_stats * phy_stats,u32 rxmcs)5032 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
5033 struct ieee80211_rx_status *rx_status,
5034 struct rtl8723au_phy_stats *phy_stats,
5035 u32 rxmcs)
5036 {
5037 if (phy_stats->sgi_en)
5038 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
5039
5040 if (rxmcs < DESC_RATE_6M) {
5041 /*
5042 * Handle PHY stats for CCK rates
5043 */
5044 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
5045
5046 switch (cck_agc_rpt & 0xc0) {
5047 case 0xc0:
5048 rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
5049 break;
5050 case 0x80:
5051 rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
5052 break;
5053 case 0x40:
5054 rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
5055 break;
5056 case 0x00:
5057 rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
5058 break;
5059 }
5060 } else {
5061 rx_status->signal =
5062 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
5063 }
5064 }
5065
rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv * priv)5066 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
5067 {
5068 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5069 unsigned long flags;
5070
5071 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5072
5073 list_for_each_entry_safe(rx_urb, tmp,
5074 &priv->rx_urb_pending_list, list) {
5075 list_del(&rx_urb->list);
5076 priv->rx_urb_pending_count--;
5077 usb_free_urb(&rx_urb->urb);
5078 }
5079
5080 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5081 }
5082
rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv * priv,struct rtl8xxxu_rx_urb * rx_urb)5083 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
5084 struct rtl8xxxu_rx_urb *rx_urb)
5085 {
5086 struct sk_buff *skb;
5087 unsigned long flags;
5088 int pending = 0;
5089
5090 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5091
5092 if (!priv->shutdown) {
5093 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
5094 priv->rx_urb_pending_count++;
5095 pending = priv->rx_urb_pending_count;
5096 } else {
5097 skb = (struct sk_buff *)rx_urb->urb.context;
5098 dev_kfree_skb(skb);
5099 usb_free_urb(&rx_urb->urb);
5100 }
5101
5102 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5103
5104 if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
5105 schedule_work(&priv->rx_urb_wq);
5106 }
5107
rtl8xxxu_rx_urb_work(struct work_struct * work)5108 static void rtl8xxxu_rx_urb_work(struct work_struct *work)
5109 {
5110 struct rtl8xxxu_priv *priv;
5111 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5112 struct list_head local;
5113 struct sk_buff *skb;
5114 unsigned long flags;
5115 int ret;
5116
5117 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
5118 INIT_LIST_HEAD(&local);
5119
5120 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5121
5122 list_splice_init(&priv->rx_urb_pending_list, &local);
5123 priv->rx_urb_pending_count = 0;
5124
5125 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5126
5127 list_for_each_entry_safe(rx_urb, tmp, &local, list) {
5128 list_del_init(&rx_urb->list);
5129 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5130 /*
5131 * If out of memory or temporary error, put it back on the
5132 * queue and try again. Otherwise the device is dead/gone
5133 * and we should drop it.
5134 */
5135 switch (ret) {
5136 case 0:
5137 break;
5138 case -ENOMEM:
5139 case -EAGAIN:
5140 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5141 break;
5142 default:
5143 pr_info("failed to requeue urb %i\n", ret);
5144 skb = (struct sk_buff *)rx_urb->urb.context;
5145 dev_kfree_skb(skb);
5146 usb_free_urb(&rx_urb->urb);
5147 }
5148 }
5149 }
5150
rtl8723bu_handle_c2h(struct rtl8xxxu_priv * priv,struct sk_buff * skb)5151 static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv,
5152 struct sk_buff *skb)
5153 {
5154 struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data;
5155 struct device *dev = &priv->udev->dev;
5156 int len;
5157
5158 len = skb->len - 2;
5159
5160 dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n",
5161 c2h->id, c2h->seq, len, c2h->bt_info.response_source);
5162
5163 switch(c2h->id) {
5164 case C2H_8723B_BT_INFO:
5165 if (c2h->bt_info.response_source >
5166 BT_INFO_SRC_8723B_BT_ACTIVE_SEND)
5167 dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n");
5168 else
5169 dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n");
5170
5171 if (c2h->bt_info.bt_has_reset)
5172 dev_dbg(dev, "BT has been reset\n");
5173 if (c2h->bt_info.tx_rx_mask)
5174 dev_dbg(dev, "BT TRx mask\n");
5175
5176 break;
5177 case C2H_8723B_BT_MP_INFO:
5178 dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n",
5179 c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status);
5180 break;
5181 case C2H_8723B_RA_REPORT:
5182 dev_dbg(dev,
5183 "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n",
5184 c2h->ra_report.rate, c2h->ra_report.dummy0_0,
5185 c2h->ra_report.macid, c2h->ra_report.noisy_state);
5186 break;
5187 default:
5188 dev_info(dev, "Unhandled C2H event %02x seq %02x\n",
5189 c2h->id, c2h->seq);
5190 print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE,
5191 16, 1, c2h->raw.payload, len, false);
5192 break;
5193 }
5194 }
5195
rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv * priv,struct sk_buff * skb)5196 int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb)
5197 {
5198 struct ieee80211_hw *hw = priv->hw;
5199 struct ieee80211_rx_status *rx_status;
5200 struct rtl8xxxu_rxdesc16 *rx_desc;
5201 struct rtl8723au_phy_stats *phy_stats;
5202 struct sk_buff *next_skb = NULL;
5203 __le32 *_rx_desc_le;
5204 u32 *_rx_desc;
5205 int drvinfo_sz, desc_shift;
5206 int i, pkt_cnt, pkt_len, urb_len, pkt_offset;
5207
5208 urb_len = skb->len;
5209 pkt_cnt = 0;
5210
5211 do {
5212 rx_desc = (struct rtl8xxxu_rxdesc16 *)skb->data;
5213 _rx_desc_le = (__le32 *)skb->data;
5214 _rx_desc = (u32 *)skb->data;
5215
5216 for (i = 0;
5217 i < (sizeof(struct rtl8xxxu_rxdesc16) / sizeof(u32)); i++)
5218 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
5219
5220 /*
5221 * Only read pkt_cnt from the header if we're parsing the
5222 * first packet
5223 */
5224 if (!pkt_cnt)
5225 pkt_cnt = rx_desc->pkt_cnt;
5226 pkt_len = rx_desc->pktlen;
5227
5228 drvinfo_sz = rx_desc->drvinfo_sz * 8;
5229 desc_shift = rx_desc->shift;
5230 pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift +
5231 sizeof(struct rtl8xxxu_rxdesc16), 128);
5232
5233 /*
5234 * Only clone the skb if there's enough data at the end to
5235 * at least cover the rx descriptor
5236 */
5237 if (pkt_cnt > 1 &&
5238 urb_len > (pkt_offset + sizeof(struct rtl8xxxu_rxdesc16)))
5239 next_skb = skb_clone(skb, GFP_ATOMIC);
5240
5241 rx_status = IEEE80211_SKB_RXCB(skb);
5242 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
5243
5244 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc16));
5245
5246 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
5247
5248 skb_pull(skb, drvinfo_sz + desc_shift);
5249
5250 skb_trim(skb, pkt_len);
5251
5252 if (rx_desc->phy_stats)
5253 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats,
5254 rx_desc->rxmcs);
5255
5256 rx_status->mactime = rx_desc->tsfl;
5257 rx_status->flag |= RX_FLAG_MACTIME_START;
5258
5259 if (!rx_desc->swdec)
5260 rx_status->flag |= RX_FLAG_DECRYPTED;
5261 if (rx_desc->crc32)
5262 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
5263 if (rx_desc->bw)
5264 rx_status->bw = RATE_INFO_BW_40;
5265
5266 if (rx_desc->rxht) {
5267 rx_status->encoding = RX_ENC_HT;
5268 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
5269 } else {
5270 rx_status->rate_idx = rx_desc->rxmcs;
5271 }
5272
5273 rx_status->freq = hw->conf.chandef.chan->center_freq;
5274 rx_status->band = hw->conf.chandef.chan->band;
5275
5276 ieee80211_rx_irqsafe(hw, skb);
5277
5278 skb = next_skb;
5279 if (skb)
5280 skb_pull(next_skb, pkt_offset);
5281
5282 pkt_cnt--;
5283 urb_len -= pkt_offset;
5284 } while (skb && urb_len > 0 && pkt_cnt > 0);
5285
5286 return RX_TYPE_DATA_PKT;
5287 }
5288
rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv * priv,struct sk_buff * skb)5289 int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb)
5290 {
5291 struct ieee80211_hw *hw = priv->hw;
5292 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
5293 struct rtl8xxxu_rxdesc24 *rx_desc =
5294 (struct rtl8xxxu_rxdesc24 *)skb->data;
5295 struct rtl8723au_phy_stats *phy_stats;
5296 __le32 *_rx_desc_le = (__le32 *)skb->data;
5297 u32 *_rx_desc = (u32 *)skb->data;
5298 int drvinfo_sz, desc_shift;
5299 int i;
5300
5301 for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc24) / sizeof(u32)); i++)
5302 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
5303
5304 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
5305
5306 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc24));
5307
5308 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
5309
5310 drvinfo_sz = rx_desc->drvinfo_sz * 8;
5311 desc_shift = rx_desc->shift;
5312 skb_pull(skb, drvinfo_sz + desc_shift);
5313
5314 if (rx_desc->rpt_sel) {
5315 struct device *dev = &priv->udev->dev;
5316 dev_dbg(dev, "%s: C2H packet\n", __func__);
5317 rtl8723bu_handle_c2h(priv, skb);
5318 dev_kfree_skb(skb);
5319 return RX_TYPE_C2H;
5320 }
5321
5322 if (rx_desc->phy_stats)
5323 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats,
5324 rx_desc->rxmcs);
5325
5326 rx_status->mactime = rx_desc->tsfl;
5327 rx_status->flag |= RX_FLAG_MACTIME_START;
5328
5329 if (!rx_desc->swdec)
5330 rx_status->flag |= RX_FLAG_DECRYPTED;
5331 if (rx_desc->crc32)
5332 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
5333 if (rx_desc->bw)
5334 rx_status->bw = RATE_INFO_BW_40;
5335
5336 if (rx_desc->rxmcs >= DESC_RATE_MCS0) {
5337 rx_status->encoding = RX_ENC_HT;
5338 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
5339 } else {
5340 rx_status->rate_idx = rx_desc->rxmcs;
5341 }
5342
5343 rx_status->freq = hw->conf.chandef.chan->center_freq;
5344 rx_status->band = hw->conf.chandef.chan->band;
5345
5346 ieee80211_rx_irqsafe(hw, skb);
5347 return RX_TYPE_DATA_PKT;
5348 }
5349
rtl8xxxu_rx_complete(struct urb * urb)5350 static void rtl8xxxu_rx_complete(struct urb *urb)
5351 {
5352 struct rtl8xxxu_rx_urb *rx_urb =
5353 container_of(urb, struct rtl8xxxu_rx_urb, urb);
5354 struct ieee80211_hw *hw = rx_urb->hw;
5355 struct rtl8xxxu_priv *priv = hw->priv;
5356 struct sk_buff *skb = (struct sk_buff *)urb->context;
5357 struct device *dev = &priv->udev->dev;
5358
5359 skb_put(skb, urb->actual_length);
5360
5361 if (urb->status == 0) {
5362 priv->fops->parse_rx_desc(priv, skb);
5363
5364 skb = NULL;
5365 rx_urb->urb.context = NULL;
5366 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5367 } else {
5368 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5369 goto cleanup;
5370 }
5371 return;
5372
5373 cleanup:
5374 usb_free_urb(urb);
5375 dev_kfree_skb(skb);
5376 return;
5377 }
5378
rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv * priv,struct rtl8xxxu_rx_urb * rx_urb)5379 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
5380 struct rtl8xxxu_rx_urb *rx_urb)
5381 {
5382 struct rtl8xxxu_fileops *fops = priv->fops;
5383 struct sk_buff *skb;
5384 int skb_size;
5385 int ret, rx_desc_sz;
5386
5387 rx_desc_sz = fops->rx_desc_size;
5388
5389 if (priv->rx_buf_aggregation && fops->rx_agg_buf_size) {
5390 skb_size = fops->rx_agg_buf_size;
5391 skb_size += (rx_desc_sz + sizeof(struct rtl8723au_phy_stats));
5392 } else {
5393 skb_size = IEEE80211_MAX_FRAME_LEN;
5394 }
5395
5396 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
5397 if (!skb)
5398 return -ENOMEM;
5399
5400 memset(skb->data, 0, rx_desc_sz);
5401 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
5402 skb_size, rtl8xxxu_rx_complete, skb);
5403 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
5404 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
5405 if (ret)
5406 usb_unanchor_urb(&rx_urb->urb);
5407 return ret;
5408 }
5409
rtl8xxxu_int_complete(struct urb * urb)5410 static void rtl8xxxu_int_complete(struct urb *urb)
5411 {
5412 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
5413 struct device *dev = &priv->udev->dev;
5414 int ret;
5415
5416 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_INTERRUPT)
5417 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5418 if (urb->status == 0) {
5419 usb_anchor_urb(urb, &priv->int_anchor);
5420 ret = usb_submit_urb(urb, GFP_ATOMIC);
5421 if (ret)
5422 usb_unanchor_urb(urb);
5423 } else {
5424 dev_dbg(dev, "%s: Error %i\n", __func__, urb->status);
5425 }
5426 }
5427
5428
rtl8xxxu_submit_int_urb(struct ieee80211_hw * hw)5429 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
5430 {
5431 struct rtl8xxxu_priv *priv = hw->priv;
5432 struct urb *urb;
5433 u32 val32;
5434 int ret;
5435
5436 urb = usb_alloc_urb(0, GFP_KERNEL);
5437 if (!urb)
5438 return -ENOMEM;
5439
5440 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
5441 priv->int_buf, USB_INTR_CONTENT_LENGTH,
5442 rtl8xxxu_int_complete, priv, 1);
5443 usb_anchor_urb(urb, &priv->int_anchor);
5444 ret = usb_submit_urb(urb, GFP_KERNEL);
5445 if (ret) {
5446 usb_unanchor_urb(urb);
5447 goto error;
5448 }
5449
5450 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
5451 val32 |= USB_HIMR_CPWM;
5452 rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
5453
5454 error:
5455 return ret;
5456 }
5457
rtl8xxxu_add_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif)5458 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
5459 struct ieee80211_vif *vif)
5460 {
5461 struct rtl8xxxu_priv *priv = hw->priv;
5462 int ret;
5463 u8 val8;
5464
5465 switch (vif->type) {
5466 case NL80211_IFTYPE_STATION:
5467 rtl8xxxu_stop_tx_beacon(priv);
5468
5469 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5470 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
5471 BEACON_DISABLE_TSF_UPDATE;
5472 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5473 ret = 0;
5474 break;
5475 default:
5476 ret = -EOPNOTSUPP;
5477 }
5478
5479 rtl8xxxu_set_linktype(priv, vif->type);
5480
5481 return ret;
5482 }
5483
rtl8xxxu_remove_interface(struct ieee80211_hw * hw,struct ieee80211_vif * vif)5484 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
5485 struct ieee80211_vif *vif)
5486 {
5487 struct rtl8xxxu_priv *priv = hw->priv;
5488
5489 dev_dbg(&priv->udev->dev, "%s\n", __func__);
5490 }
5491
rtl8xxxu_config(struct ieee80211_hw * hw,u32 changed)5492 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
5493 {
5494 struct rtl8xxxu_priv *priv = hw->priv;
5495 struct device *dev = &priv->udev->dev;
5496 u16 val16;
5497 int ret = 0, channel;
5498 bool ht40;
5499
5500 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
5501 dev_info(dev,
5502 "%s: channel: %i (changed %08x chandef.width %02x)\n",
5503 __func__, hw->conf.chandef.chan->hw_value,
5504 changed, hw->conf.chandef.width);
5505
5506 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
5507 val16 = ((hw->conf.long_frame_max_tx_count <<
5508 RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
5509 ((hw->conf.short_frame_max_tx_count <<
5510 RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
5511 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
5512 }
5513
5514 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
5515 switch (hw->conf.chandef.width) {
5516 case NL80211_CHAN_WIDTH_20_NOHT:
5517 case NL80211_CHAN_WIDTH_20:
5518 ht40 = false;
5519 break;
5520 case NL80211_CHAN_WIDTH_40:
5521 ht40 = true;
5522 break;
5523 default:
5524 ret = -ENOTSUPP;
5525 goto exit;
5526 }
5527
5528 channel = hw->conf.chandef.chan->hw_value;
5529
5530 priv->fops->set_tx_power(priv, channel, ht40);
5531
5532 priv->fops->config_channel(hw);
5533 }
5534
5535 exit:
5536 return ret;
5537 }
5538
rtl8xxxu_conf_tx(struct ieee80211_hw * hw,struct ieee80211_vif * vif,u16 queue,const struct ieee80211_tx_queue_params * param)5539 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
5540 struct ieee80211_vif *vif, u16 queue,
5541 const struct ieee80211_tx_queue_params *param)
5542 {
5543 struct rtl8xxxu_priv *priv = hw->priv;
5544 struct device *dev = &priv->udev->dev;
5545 u32 val32;
5546 u8 aifs, acm_ctrl, acm_bit;
5547
5548 aifs = param->aifs;
5549
5550 val32 = aifs |
5551 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
5552 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
5553 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
5554
5555 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
5556 dev_dbg(dev,
5557 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
5558 __func__, queue, val32, param->acm, acm_ctrl);
5559
5560 switch (queue) {
5561 case IEEE80211_AC_VO:
5562 acm_bit = ACM_HW_CTRL_VO;
5563 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
5564 break;
5565 case IEEE80211_AC_VI:
5566 acm_bit = ACM_HW_CTRL_VI;
5567 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
5568 break;
5569 case IEEE80211_AC_BE:
5570 acm_bit = ACM_HW_CTRL_BE;
5571 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
5572 break;
5573 case IEEE80211_AC_BK:
5574 acm_bit = ACM_HW_CTRL_BK;
5575 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
5576 break;
5577 default:
5578 acm_bit = 0;
5579 break;
5580 }
5581
5582 if (param->acm)
5583 acm_ctrl |= acm_bit;
5584 else
5585 acm_ctrl &= ~acm_bit;
5586 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
5587
5588 return 0;
5589 }
5590
rtl8xxxu_configure_filter(struct ieee80211_hw * hw,unsigned int changed_flags,unsigned int * total_flags,u64 multicast)5591 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
5592 unsigned int changed_flags,
5593 unsigned int *total_flags, u64 multicast)
5594 {
5595 struct rtl8xxxu_priv *priv = hw->priv;
5596 u32 rcr = rtl8xxxu_read32(priv, REG_RCR);
5597
5598 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
5599 __func__, changed_flags, *total_flags);
5600
5601 /*
5602 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
5603 */
5604
5605 if (*total_flags & FIF_FCSFAIL)
5606 rcr |= RCR_ACCEPT_CRC32;
5607 else
5608 rcr &= ~RCR_ACCEPT_CRC32;
5609
5610 /*
5611 * FIF_PLCPFAIL not supported?
5612 */
5613
5614 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
5615 rcr &= ~RCR_CHECK_BSSID_BEACON;
5616 else
5617 rcr |= RCR_CHECK_BSSID_BEACON;
5618
5619 if (*total_flags & FIF_CONTROL)
5620 rcr |= RCR_ACCEPT_CTRL_FRAME;
5621 else
5622 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
5623
5624 if (*total_flags & FIF_OTHER_BSS) {
5625 rcr |= RCR_ACCEPT_AP;
5626 rcr &= ~RCR_CHECK_BSSID_MATCH;
5627 } else {
5628 rcr &= ~RCR_ACCEPT_AP;
5629 rcr |= RCR_CHECK_BSSID_MATCH;
5630 }
5631
5632 if (*total_flags & FIF_PSPOLL)
5633 rcr |= RCR_ACCEPT_PM;
5634 else
5635 rcr &= ~RCR_ACCEPT_PM;
5636
5637 /*
5638 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
5639 */
5640
5641 rtl8xxxu_write32(priv, REG_RCR, rcr);
5642
5643 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
5644 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
5645 FIF_PROBE_REQ);
5646 }
5647
rtl8xxxu_set_rts_threshold(struct ieee80211_hw * hw,u32 rts)5648 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
5649 {
5650 if (rts > 2347)
5651 return -EINVAL;
5652
5653 return 0;
5654 }
5655
rtl8xxxu_set_key(struct ieee80211_hw * hw,enum set_key_cmd cmd,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct ieee80211_key_conf * key)5656 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
5657 struct ieee80211_vif *vif,
5658 struct ieee80211_sta *sta,
5659 struct ieee80211_key_conf *key)
5660 {
5661 struct rtl8xxxu_priv *priv = hw->priv;
5662 struct device *dev = &priv->udev->dev;
5663 u8 mac_addr[ETH_ALEN];
5664 u8 val8;
5665 u16 val16;
5666 u32 val32;
5667 int retval = -EOPNOTSUPP;
5668
5669 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
5670 __func__, cmd, key->cipher, key->keyidx);
5671
5672 if (vif->type != NL80211_IFTYPE_STATION)
5673 return -EOPNOTSUPP;
5674
5675 if (key->keyidx > 3)
5676 return -EOPNOTSUPP;
5677
5678 switch (key->cipher) {
5679 case WLAN_CIPHER_SUITE_WEP40:
5680 case WLAN_CIPHER_SUITE_WEP104:
5681
5682 break;
5683 case WLAN_CIPHER_SUITE_CCMP:
5684 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
5685 break;
5686 case WLAN_CIPHER_SUITE_TKIP:
5687 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
5688 break;
5689 default:
5690 return -EOPNOTSUPP;
5691 }
5692
5693 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
5694 dev_dbg(dev, "%s: pairwise key\n", __func__);
5695 ether_addr_copy(mac_addr, sta->addr);
5696 } else {
5697 dev_dbg(dev, "%s: group key\n", __func__);
5698 eth_broadcast_addr(mac_addr);
5699 }
5700
5701 val16 = rtl8xxxu_read16(priv, REG_CR);
5702 val16 |= CR_SECURITY_ENABLE;
5703 rtl8xxxu_write16(priv, REG_CR, val16);
5704
5705 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
5706 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
5707 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
5708 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
5709
5710 switch (cmd) {
5711 case SET_KEY:
5712 key->hw_key_idx = key->keyidx;
5713 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
5714 rtl8xxxu_cam_write(priv, key, mac_addr);
5715 retval = 0;
5716 break;
5717 case DISABLE_KEY:
5718 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
5719 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
5720 key->keyidx << CAM_CMD_KEY_SHIFT;
5721 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
5722 retval = 0;
5723 break;
5724 default:
5725 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
5726 }
5727
5728 return retval;
5729 }
5730
5731 static int
rtl8xxxu_ampdu_action(struct ieee80211_hw * hw,struct ieee80211_vif * vif,struct ieee80211_ampdu_params * params)5732 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5733 struct ieee80211_ampdu_params *params)
5734 {
5735 struct rtl8xxxu_priv *priv = hw->priv;
5736 struct device *dev = &priv->udev->dev;
5737 u8 ampdu_factor, ampdu_density;
5738 struct ieee80211_sta *sta = params->sta;
5739 enum ieee80211_ampdu_mlme_action action = params->action;
5740
5741 switch (action) {
5742 case IEEE80211_AMPDU_TX_START:
5743 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
5744 ampdu_factor = sta->ht_cap.ampdu_factor;
5745 ampdu_density = sta->ht_cap.ampdu_density;
5746 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
5747 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
5748 dev_dbg(dev,
5749 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
5750 ampdu_factor, ampdu_density);
5751 break;
5752 case IEEE80211_AMPDU_TX_STOP_FLUSH:
5753 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
5754 rtl8xxxu_set_ampdu_factor(priv, 0);
5755 rtl8xxxu_set_ampdu_min_space(priv, 0);
5756 break;
5757 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
5758 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
5759 __func__);
5760 rtl8xxxu_set_ampdu_factor(priv, 0);
5761 rtl8xxxu_set_ampdu_min_space(priv, 0);
5762 break;
5763 case IEEE80211_AMPDU_RX_START:
5764 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
5765 break;
5766 case IEEE80211_AMPDU_RX_STOP:
5767 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
5768 break;
5769 default:
5770 break;
5771 }
5772 return 0;
5773 }
5774
rtl8xxxu_start(struct ieee80211_hw * hw)5775 static int rtl8xxxu_start(struct ieee80211_hw *hw)
5776 {
5777 struct rtl8xxxu_priv *priv = hw->priv;
5778 struct rtl8xxxu_rx_urb *rx_urb;
5779 struct rtl8xxxu_tx_urb *tx_urb;
5780 unsigned long flags;
5781 int ret, i;
5782
5783 ret = 0;
5784
5785 init_usb_anchor(&priv->rx_anchor);
5786 init_usb_anchor(&priv->tx_anchor);
5787 init_usb_anchor(&priv->int_anchor);
5788
5789 priv->fops->enable_rf(priv);
5790 if (priv->usb_interrupts) {
5791 ret = rtl8xxxu_submit_int_urb(hw);
5792 if (ret)
5793 goto exit;
5794 }
5795
5796 for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
5797 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
5798 if (!tx_urb) {
5799 if (!i)
5800 ret = -ENOMEM;
5801
5802 goto error_out;
5803 }
5804 usb_init_urb(&tx_urb->urb);
5805 INIT_LIST_HEAD(&tx_urb->list);
5806 tx_urb->hw = hw;
5807 list_add(&tx_urb->list, &priv->tx_urb_free_list);
5808 priv->tx_urb_free_count++;
5809 }
5810
5811 priv->tx_stopped = false;
5812
5813 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5814 priv->shutdown = false;
5815 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5816
5817 for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
5818 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
5819 if (!rx_urb) {
5820 if (!i)
5821 ret = -ENOMEM;
5822
5823 goto error_out;
5824 }
5825 usb_init_urb(&rx_urb->urb);
5826 INIT_LIST_HEAD(&rx_urb->list);
5827 rx_urb->hw = hw;
5828
5829 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5830 }
5831 exit:
5832 /*
5833 * Accept all data and mgmt frames
5834 */
5835 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
5836 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
5837
5838 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
5839
5840 return ret;
5841
5842 error_out:
5843 rtl8xxxu_free_tx_resources(priv);
5844 /*
5845 * Disable all data and mgmt frames
5846 */
5847 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5848 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
5849
5850 return ret;
5851 }
5852
rtl8xxxu_stop(struct ieee80211_hw * hw)5853 static void rtl8xxxu_stop(struct ieee80211_hw *hw)
5854 {
5855 struct rtl8xxxu_priv *priv = hw->priv;
5856 unsigned long flags;
5857
5858 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5859
5860 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
5861 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5862
5863 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5864 priv->shutdown = true;
5865 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5866
5867 usb_kill_anchored_urbs(&priv->rx_anchor);
5868 usb_kill_anchored_urbs(&priv->tx_anchor);
5869 if (priv->usb_interrupts)
5870 usb_kill_anchored_urbs(&priv->int_anchor);
5871
5872 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5873
5874 priv->fops->disable_rf(priv);
5875
5876 /*
5877 * Disable interrupts
5878 */
5879 if (priv->usb_interrupts)
5880 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
5881
5882 rtl8xxxu_free_rx_resources(priv);
5883 rtl8xxxu_free_tx_resources(priv);
5884 }
5885
5886 static const struct ieee80211_ops rtl8xxxu_ops = {
5887 .tx = rtl8xxxu_tx,
5888 .add_interface = rtl8xxxu_add_interface,
5889 .remove_interface = rtl8xxxu_remove_interface,
5890 .config = rtl8xxxu_config,
5891 .conf_tx = rtl8xxxu_conf_tx,
5892 .bss_info_changed = rtl8xxxu_bss_info_changed,
5893 .configure_filter = rtl8xxxu_configure_filter,
5894 .set_rts_threshold = rtl8xxxu_set_rts_threshold,
5895 .start = rtl8xxxu_start,
5896 .stop = rtl8xxxu_stop,
5897 .sw_scan_start = rtl8xxxu_sw_scan_start,
5898 .sw_scan_complete = rtl8xxxu_sw_scan_complete,
5899 .set_key = rtl8xxxu_set_key,
5900 .ampdu_action = rtl8xxxu_ampdu_action,
5901 };
5902
rtl8xxxu_parse_usb(struct rtl8xxxu_priv * priv,struct usb_interface * interface)5903 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
5904 struct usb_interface *interface)
5905 {
5906 struct usb_interface_descriptor *interface_desc;
5907 struct usb_host_interface *host_interface;
5908 struct usb_endpoint_descriptor *endpoint;
5909 struct device *dev = &priv->udev->dev;
5910 int i, j = 0, endpoints;
5911 u8 dir, xtype, num;
5912 int ret = 0;
5913
5914 host_interface = &interface->altsetting[0];
5915 interface_desc = &host_interface->desc;
5916 endpoints = interface_desc->bNumEndpoints;
5917
5918 for (i = 0; i < endpoints; i++) {
5919 endpoint = &host_interface->endpoint[i].desc;
5920
5921 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
5922 num = usb_endpoint_num(endpoint);
5923 xtype = usb_endpoint_type(endpoint);
5924 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5925 dev_dbg(dev,
5926 "%s: endpoint: dir %02x, # %02x, type %02x\n",
5927 __func__, dir, num, xtype);
5928 if (usb_endpoint_dir_in(endpoint) &&
5929 usb_endpoint_xfer_bulk(endpoint)) {
5930 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5931 dev_dbg(dev, "%s: in endpoint num %i\n",
5932 __func__, num);
5933
5934 if (priv->pipe_in) {
5935 dev_warn(dev,
5936 "%s: Too many IN pipes\n", __func__);
5937 ret = -EINVAL;
5938 goto exit;
5939 }
5940
5941 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
5942 }
5943
5944 if (usb_endpoint_dir_in(endpoint) &&
5945 usb_endpoint_xfer_int(endpoint)) {
5946 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5947 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
5948 __func__, num);
5949
5950 if (priv->pipe_interrupt) {
5951 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
5952 __func__);
5953 ret = -EINVAL;
5954 goto exit;
5955 }
5956
5957 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
5958 }
5959
5960 if (usb_endpoint_dir_out(endpoint) &&
5961 usb_endpoint_xfer_bulk(endpoint)) {
5962 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5963 dev_dbg(dev, "%s: out endpoint num %i\n",
5964 __func__, num);
5965 if (j >= RTL8XXXU_OUT_ENDPOINTS) {
5966 dev_warn(dev,
5967 "%s: Too many OUT pipes\n", __func__);
5968 ret = -EINVAL;
5969 goto exit;
5970 }
5971 priv->out_ep[j++] = num;
5972 }
5973 }
5974 exit:
5975 priv->nr_out_eps = j;
5976 return ret;
5977 }
5978
rtl8xxxu_probe(struct usb_interface * interface,const struct usb_device_id * id)5979 static int rtl8xxxu_probe(struct usb_interface *interface,
5980 const struct usb_device_id *id)
5981 {
5982 struct rtl8xxxu_priv *priv;
5983 struct ieee80211_hw *hw;
5984 struct usb_device *udev;
5985 struct ieee80211_supported_band *sband;
5986 int ret;
5987 int untested = 1;
5988
5989 udev = usb_get_dev(interface_to_usbdev(interface));
5990
5991 switch (id->idVendor) {
5992 case USB_VENDOR_ID_REALTEK:
5993 switch(id->idProduct) {
5994 case 0x1724:
5995 case 0x8176:
5996 case 0x8178:
5997 case 0x817f:
5998 case 0x818b:
5999 untested = 0;
6000 break;
6001 }
6002 break;
6003 case 0x7392:
6004 if (id->idProduct == 0x7811)
6005 untested = 0;
6006 break;
6007 case 0x050d:
6008 if (id->idProduct == 0x1004)
6009 untested = 0;
6010 break;
6011 case 0x20f4:
6012 if (id->idProduct == 0x648b)
6013 untested = 0;
6014 break;
6015 case 0x2001:
6016 if (id->idProduct == 0x3308)
6017 untested = 0;
6018 break;
6019 case 0x2357:
6020 if (id->idProduct == 0x0109)
6021 untested = 0;
6022 break;
6023 default:
6024 break;
6025 }
6026
6027 if (untested) {
6028 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE;
6029 dev_info(&udev->dev,
6030 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
6031 id->idVendor, id->idProduct);
6032 dev_info(&udev->dev,
6033 "Please report results to Jes.Sorensen@gmail.com\n");
6034 }
6035
6036 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
6037 if (!hw) {
6038 ret = -ENOMEM;
6039 priv = NULL;
6040 goto exit;
6041 }
6042
6043 priv = hw->priv;
6044 priv->hw = hw;
6045 priv->udev = udev;
6046 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
6047 mutex_init(&priv->usb_buf_mutex);
6048 mutex_init(&priv->h2c_mutex);
6049 INIT_LIST_HEAD(&priv->tx_urb_free_list);
6050 spin_lock_init(&priv->tx_urb_lock);
6051 INIT_LIST_HEAD(&priv->rx_urb_pending_list);
6052 spin_lock_init(&priv->rx_urb_lock);
6053 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
6054
6055 usb_set_intfdata(interface, hw);
6056
6057 ret = rtl8xxxu_parse_usb(priv, interface);
6058 if (ret)
6059 goto exit;
6060
6061 ret = rtl8xxxu_identify_chip(priv);
6062 if (ret) {
6063 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
6064 goto exit;
6065 }
6066
6067 ret = rtl8xxxu_read_efuse(priv);
6068 if (ret) {
6069 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
6070 goto exit;
6071 }
6072
6073 ret = priv->fops->parse_efuse(priv);
6074 if (ret) {
6075 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
6076 goto exit;
6077 }
6078
6079 rtl8xxxu_print_chipinfo(priv);
6080
6081 ret = priv->fops->load_firmware(priv);
6082 if (ret) {
6083 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
6084 goto exit;
6085 }
6086
6087 ret = rtl8xxxu_init_device(hw);
6088 if (ret)
6089 goto exit;
6090
6091 hw->wiphy->max_scan_ssids = 1;
6092 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
6093 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
6094 hw->queues = 4;
6095
6096 sband = &rtl8xxxu_supported_band;
6097 sband->ht_cap.ht_supported = true;
6098 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
6099 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
6100 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
6101 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
6102 sband->ht_cap.mcs.rx_mask[0] = 0xff;
6103 sband->ht_cap.mcs.rx_mask[4] = 0x01;
6104 if (priv->rf_paths > 1) {
6105 sband->ht_cap.mcs.rx_mask[1] = 0xff;
6106 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
6107 }
6108 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
6109 /*
6110 * Some APs will negotiate HT20_40 in a noisy environment leading
6111 * to miserable performance. Rather than defaulting to this, only
6112 * enable it if explicitly requested at module load time.
6113 */
6114 if (rtl8xxxu_ht40_2g) {
6115 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
6116 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
6117 }
6118 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
6119
6120 hw->wiphy->rts_threshold = 2347;
6121
6122 SET_IEEE80211_DEV(priv->hw, &interface->dev);
6123 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
6124
6125 hw->extra_tx_headroom = priv->fops->tx_desc_size;
6126 ieee80211_hw_set(hw, SIGNAL_DBM);
6127 /*
6128 * The firmware handles rate control
6129 */
6130 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
6131 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
6132
6133 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
6134
6135 ret = ieee80211_register_hw(priv->hw);
6136 if (ret) {
6137 dev_err(&udev->dev, "%s: Failed to register: %i\n",
6138 __func__, ret);
6139 goto exit;
6140 }
6141
6142 return 0;
6143
6144 exit:
6145 usb_set_intfdata(interface, NULL);
6146
6147 if (priv) {
6148 kfree(priv->fw_data);
6149 mutex_destroy(&priv->usb_buf_mutex);
6150 mutex_destroy(&priv->h2c_mutex);
6151 }
6152 usb_put_dev(udev);
6153
6154 ieee80211_free_hw(hw);
6155
6156 return ret;
6157 }
6158
rtl8xxxu_disconnect(struct usb_interface * interface)6159 static void rtl8xxxu_disconnect(struct usb_interface *interface)
6160 {
6161 struct rtl8xxxu_priv *priv;
6162 struct ieee80211_hw *hw;
6163
6164 hw = usb_get_intfdata(interface);
6165 priv = hw->priv;
6166
6167 ieee80211_unregister_hw(hw);
6168
6169 priv->fops->power_off(priv);
6170
6171 usb_set_intfdata(interface, NULL);
6172
6173 dev_info(&priv->udev->dev, "disconnecting\n");
6174
6175 kfree(priv->fw_data);
6176 mutex_destroy(&priv->usb_buf_mutex);
6177 mutex_destroy(&priv->h2c_mutex);
6178
6179 if (priv->udev->state != USB_STATE_NOTATTACHED) {
6180 dev_info(&priv->udev->dev,
6181 "Device still attached, trying to reset\n");
6182 usb_reset_device(priv->udev);
6183 }
6184 usb_put_dev(priv->udev);
6185 ieee80211_free_hw(hw);
6186 }
6187
6188 static const struct usb_device_id dev_table[] = {
6189 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
6190 .driver_info = (unsigned long)&rtl8723au_fops},
6191 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
6192 .driver_info = (unsigned long)&rtl8723au_fops},
6193 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
6194 .driver_info = (unsigned long)&rtl8723au_fops},
6195 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
6196 .driver_info = (unsigned long)&rtl8192eu_fops},
6197 /* TP-Link TL-WN822N v4 */
6198 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0108, 0xff, 0xff, 0xff),
6199 .driver_info = (unsigned long)&rtl8192eu_fops},
6200 /* D-Link DWA-131 rev E1, tested by David Patiño */
6201 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3319, 0xff, 0xff, 0xff),
6202 .driver_info = (unsigned long)&rtl8192eu_fops},
6203 /* Tested by Myckel Habets */
6204 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0109, 0xff, 0xff, 0xff),
6205 .driver_info = (unsigned long)&rtl8192eu_fops},
6206 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
6207 .driver_info = (unsigned long)&rtl8723bu_fops},
6208 #ifdef CONFIG_RTL8XXXU_UNTESTED
6209 /* Still supported by rtlwifi */
6210 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
6211 .driver_info = (unsigned long)&rtl8192cu_fops},
6212 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
6213 .driver_info = (unsigned long)&rtl8192cu_fops},
6214 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
6215 .driver_info = (unsigned long)&rtl8192cu_fops},
6216 /* Tested by Larry Finger */
6217 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
6218 .driver_info = (unsigned long)&rtl8192cu_fops},
6219 /* Tested by Andrea Merello */
6220 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
6221 .driver_info = (unsigned long)&rtl8192cu_fops},
6222 /* Tested by Jocelyn Mayer */
6223 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
6224 .driver_info = (unsigned long)&rtl8192cu_fops},
6225 /* Tested by Stefano Bravi */
6226 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
6227 .driver_info = (unsigned long)&rtl8192cu_fops},
6228 /* Currently untested 8188 series devices */
6229 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x018a, 0xff, 0xff, 0xff),
6230 .driver_info = (unsigned long)&rtl8192cu_fops},
6231 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
6232 .driver_info = (unsigned long)&rtl8192cu_fops},
6233 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
6234 .driver_info = (unsigned long)&rtl8192cu_fops},
6235 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
6236 .driver_info = (unsigned long)&rtl8192cu_fops},
6237 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
6238 .driver_info = (unsigned long)&rtl8192cu_fops},
6239 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
6240 .driver_info = (unsigned long)&rtl8192cu_fops},
6241 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
6242 .driver_info = (unsigned long)&rtl8192cu_fops},
6243 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
6244 .driver_info = (unsigned long)&rtl8192cu_fops},
6245 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
6246 .driver_info = (unsigned long)&rtl8192cu_fops},
6247 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
6248 .driver_info = (unsigned long)&rtl8192cu_fops},
6249 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
6250 .driver_info = (unsigned long)&rtl8192cu_fops},
6251 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
6252 .driver_info = (unsigned long)&rtl8192cu_fops},
6253 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
6254 .driver_info = (unsigned long)&rtl8192cu_fops},
6255 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
6256 .driver_info = (unsigned long)&rtl8192cu_fops},
6257 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
6258 .driver_info = (unsigned long)&rtl8192cu_fops},
6259 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
6260 .driver_info = (unsigned long)&rtl8192cu_fops},
6261 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
6262 .driver_info = (unsigned long)&rtl8192cu_fops},
6263 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
6264 .driver_info = (unsigned long)&rtl8192cu_fops},
6265 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
6266 .driver_info = (unsigned long)&rtl8192cu_fops},
6267 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
6268 .driver_info = (unsigned long)&rtl8192cu_fops},
6269 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
6270 .driver_info = (unsigned long)&rtl8192cu_fops},
6271 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
6272 .driver_info = (unsigned long)&rtl8192cu_fops},
6273 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
6274 .driver_info = (unsigned long)&rtl8192cu_fops},
6275 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
6276 .driver_info = (unsigned long)&rtl8192cu_fops},
6277 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
6278 .driver_info = (unsigned long)&rtl8192cu_fops},
6279 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
6280 .driver_info = (unsigned long)&rtl8192cu_fops},
6281 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
6282 .driver_info = (unsigned long)&rtl8192cu_fops},
6283 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
6284 .driver_info = (unsigned long)&rtl8192cu_fops},
6285 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
6286 .driver_info = (unsigned long)&rtl8192cu_fops},
6287 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
6288 .driver_info = (unsigned long)&rtl8192cu_fops},
6289 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
6290 .driver_info = (unsigned long)&rtl8192cu_fops},
6291 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
6292 .driver_info = (unsigned long)&rtl8192cu_fops},
6293 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
6294 .driver_info = (unsigned long)&rtl8192cu_fops},
6295 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
6296 .driver_info = (unsigned long)&rtl8192cu_fops},
6297 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
6298 .driver_info = (unsigned long)&rtl8192cu_fops},
6299 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
6300 .driver_info = (unsigned long)&rtl8192cu_fops},
6301 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
6302 .driver_info = (unsigned long)&rtl8192cu_fops},
6303 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
6304 .driver_info = (unsigned long)&rtl8192cu_fops},
6305 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
6306 .driver_info = (unsigned long)&rtl8192cu_fops},
6307 /* Currently untested 8192 series devices */
6308 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
6309 .driver_info = (unsigned long)&rtl8192cu_fops},
6310 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
6311 .driver_info = (unsigned long)&rtl8192cu_fops},
6312 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
6313 .driver_info = (unsigned long)&rtl8192cu_fops},
6314 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
6315 .driver_info = (unsigned long)&rtl8192cu_fops},
6316 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
6317 .driver_info = (unsigned long)&rtl8192cu_fops},
6318 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
6319 .driver_info = (unsigned long)&rtl8192cu_fops},
6320 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
6321 .driver_info = (unsigned long)&rtl8192cu_fops},
6322 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
6323 .driver_info = (unsigned long)&rtl8192cu_fops},
6324 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
6325 .driver_info = (unsigned long)&rtl8192cu_fops},
6326 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
6327 .driver_info = (unsigned long)&rtl8192cu_fops},
6328 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
6329 .driver_info = (unsigned long)&rtl8192cu_fops},
6330 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
6331 .driver_info = (unsigned long)&rtl8192cu_fops},
6332 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
6333 .driver_info = (unsigned long)&rtl8192cu_fops},
6334 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
6335 .driver_info = (unsigned long)&rtl8192cu_fops},
6336 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
6337 .driver_info = (unsigned long)&rtl8192cu_fops},
6338 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
6339 .driver_info = (unsigned long)&rtl8192cu_fops},
6340 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
6341 .driver_info = (unsigned long)&rtl8192cu_fops},
6342 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
6343 .driver_info = (unsigned long)&rtl8192cu_fops},
6344 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
6345 .driver_info = (unsigned long)&rtl8192cu_fops},
6346 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
6347 .driver_info = (unsigned long)&rtl8192cu_fops},
6348 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
6349 .driver_info = (unsigned long)&rtl8192cu_fops},
6350 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
6351 .driver_info = (unsigned long)&rtl8192cu_fops},
6352 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
6353 .driver_info = (unsigned long)&rtl8192cu_fops},
6354 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
6355 .driver_info = (unsigned long)&rtl8192cu_fops},
6356 /* found in rtl8192eu vendor driver */
6357 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0107, 0xff, 0xff, 0xff),
6358 .driver_info = (unsigned long)&rtl8192eu_fops},
6359 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab33, 0xff, 0xff, 0xff),
6360 .driver_info = (unsigned long)&rtl8192eu_fops},
6361 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818c, 0xff, 0xff, 0xff),
6362 .driver_info = (unsigned long)&rtl8192eu_fops},
6363 #endif
6364 { }
6365 };
6366
6367 static struct usb_driver rtl8xxxu_driver = {
6368 .name = DRIVER_NAME,
6369 .probe = rtl8xxxu_probe,
6370 .disconnect = rtl8xxxu_disconnect,
6371 .id_table = dev_table,
6372 .no_dynamic_id = 1,
6373 .disable_hub_initiated_lpm = 1,
6374 };
6375
rtl8xxxu_module_init(void)6376 static int __init rtl8xxxu_module_init(void)
6377 {
6378 int res;
6379
6380 res = usb_register(&rtl8xxxu_driver);
6381 if (res < 0)
6382 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
6383
6384 return res;
6385 }
6386
rtl8xxxu_module_exit(void)6387 static void __exit rtl8xxxu_module_exit(void)
6388 {
6389 usb_deregister(&rtl8xxxu_driver);
6390 }
6391
6392
6393 MODULE_DEVICE_TABLE(usb, dev_table);
6394
6395 module_init(rtl8xxxu_module_init);
6396 module_exit(rtl8xxxu_module_exit);
6397
