1 // SPDX-License-Identifier: GPL-2.0
2 /******************************************************************************
3 *
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 *
6 ******************************************************************************/
7
8 #include "odm_precomp.h"
9 #include "phy.h"
10
dm_rx_hw_antena_div_init(struct odm_dm_struct * dm_odm)11 static void dm_rx_hw_antena_div_init(struct odm_dm_struct *dm_odm)
12 {
13 struct adapter *adapter = dm_odm->Adapter;
14 u32 value32;
15
16 if (*(dm_odm->mp_mode) == 1) {
17 dm_odm->AntDivType = CGCS_RX_SW_ANTDIV;
18 phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0);
19 phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);
20 return;
21 }
22
23 /* MAC Setting */
24 value32 = phy_query_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
25 phy_set_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord,
26 value32|(BIT(23) | BIT(25)));
27 /* Pin Settings */
28 phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
29 phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
30 phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(22), 1);
31 phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);
32 /* OFDM Settings */
33 phy_set_bb_reg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord,
34 0x000000a0);
35 /* CCK Settings */
36 phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1);
37 phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);
38 rtl88eu_dm_update_rx_idle_ant(dm_odm, MAIN_ANT);
39 phy_set_bb_reg(adapter, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0201);
40 }
41
dm_trx_hw_antenna_div_init(struct odm_dm_struct * dm_odm)42 static void dm_trx_hw_antenna_div_init(struct odm_dm_struct *dm_odm)
43 {
44 struct adapter *adapter = dm_odm->Adapter;
45 u32 value32;
46
47 if (*(dm_odm->mp_mode) == 1) {
48 dm_odm->AntDivType = CGCS_RX_SW_ANTDIV;
49 phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0);
50 phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
51 BIT(5) | BIT(4) | BIT(3), 0);
52 return;
53 }
54
55 /* MAC Setting */
56 value32 = phy_query_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
57 phy_set_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord,
58 value32|(BIT(23) | BIT(25)));
59 /* Pin Settings */
60 phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
61 phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
62 phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(22), 0);
63 phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);
64 /* OFDM Settings */
65 phy_set_bb_reg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord,
66 0x000000a0);
67 /* CCK Settings */
68 phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1);
69 phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);
70 /* Tx Settings */
71 phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT(21), 0);
72 rtl88eu_dm_update_rx_idle_ant(dm_odm, MAIN_ANT);
73
74 /* antenna mapping table */
75 if (!dm_odm->bIsMPChip) { /* testchip */
76 phy_set_bb_reg(adapter, ODM_REG_RX_DEFAULT_A_11N,
77 BIT(10) | BIT(9) | BIT(8), 1);
78 phy_set_bb_reg(adapter, ODM_REG_RX_DEFAULT_A_11N,
79 BIT(13) | BIT(12) | BIT(11), 2);
80 } else { /* MPchip */
81 phy_set_bb_reg(adapter, ODM_REG_ANT_MAPPING1_11N, bMaskDWord,
82 0x0201);
83 }
84 }
85
dm_fast_training_init(struct odm_dm_struct * dm_odm)86 static void dm_fast_training_init(struct odm_dm_struct *dm_odm)
87 {
88 struct adapter *adapter = dm_odm->Adapter;
89 u32 value32, i;
90 struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
91 u32 AntCombination = 2;
92
93 if (*(dm_odm->mp_mode) == 1) {
94 return;
95 }
96
97 for (i = 0; i < 6; i++) {
98 dm_fat_tbl->Bssid[i] = 0;
99 dm_fat_tbl->antSumRSSI[i] = 0;
100 dm_fat_tbl->antRSSIcnt[i] = 0;
101 dm_fat_tbl->antAveRSSI[i] = 0;
102 }
103 dm_fat_tbl->TrainIdx = 0;
104 dm_fat_tbl->FAT_State = FAT_NORMAL_STATE;
105
106 /* MAC Setting */
107 value32 = phy_query_bb_reg(adapter, 0x4c, bMaskDWord);
108 phy_set_bb_reg(adapter, 0x4c, bMaskDWord, value32|(BIT(23) | BIT(25)));
109 value32 = phy_query_bb_reg(adapter, 0x7B4, bMaskDWord);
110 phy_set_bb_reg(adapter, 0x7b4, bMaskDWord, value32|(BIT(16) | BIT(17)));
111
112 /* Match MAC ADDR */
113 phy_set_bb_reg(adapter, 0x7b4, 0xFFFF, 0);
114 phy_set_bb_reg(adapter, 0x7b0, bMaskDWord, 0);
115
116 phy_set_bb_reg(adapter, 0x870, BIT(9) | BIT(8), 0);
117 phy_set_bb_reg(adapter, 0x864, BIT(10), 0);
118 phy_set_bb_reg(adapter, 0xb2c, BIT(22), 0);
119 phy_set_bb_reg(adapter, 0xb2c, BIT(31), 1);
120 phy_set_bb_reg(adapter, 0xca4, bMaskDWord, 0x000000a0);
121
122 /* antenna mapping table */
123 if (AntCombination == 2) {
124 if (!dm_odm->bIsMPChip) { /* testchip */
125 phy_set_bb_reg(adapter, 0x858, BIT(10) | BIT(9) | BIT(8), 1);
126 phy_set_bb_reg(adapter, 0x858, BIT(13) | BIT(12) | BIT(11), 2);
127 } else { /* MPchip */
128 phy_set_bb_reg(adapter, 0x914, bMaskByte0, 1);
129 phy_set_bb_reg(adapter, 0x914, bMaskByte1, 2);
130 }
131 } else if (AntCombination == 7) {
132 if (!dm_odm->bIsMPChip) { /* testchip */
133 phy_set_bb_reg(adapter, 0x858, BIT(10) | BIT(9) | BIT(8), 0);
134 phy_set_bb_reg(adapter, 0x858, BIT(13) | BIT(12) | BIT(11), 1);
135 phy_set_bb_reg(adapter, 0x878, BIT(16), 0);
136 phy_set_bb_reg(adapter, 0x858, BIT(15) | BIT(14), 2);
137 phy_set_bb_reg(adapter, 0x878, BIT(19) | BIT(18) | BIT(17), 3);
138 phy_set_bb_reg(adapter, 0x878, BIT(22) | BIT(21) | BIT(20), 4);
139 phy_set_bb_reg(adapter, 0x878, BIT(25) | BIT(24) | BIT(23), 5);
140 phy_set_bb_reg(adapter, 0x878, BIT(28) | BIT(27) | BIT(26), 6);
141 phy_set_bb_reg(adapter, 0x878, BIT(31) | BIT(30) | BIT(29), 7);
142 } else { /* MPchip */
143 phy_set_bb_reg(adapter, 0x914, bMaskByte0, 0);
144 phy_set_bb_reg(adapter, 0x914, bMaskByte1, 1);
145 phy_set_bb_reg(adapter, 0x914, bMaskByte2, 2);
146 phy_set_bb_reg(adapter, 0x914, bMaskByte3, 3);
147 phy_set_bb_reg(adapter, 0x918, bMaskByte0, 4);
148 phy_set_bb_reg(adapter, 0x918, bMaskByte1, 5);
149 phy_set_bb_reg(adapter, 0x918, bMaskByte2, 6);
150 phy_set_bb_reg(adapter, 0x918, bMaskByte3, 7);
151 }
152 }
153
154 /* Default Ant Setting when no fast training */
155 phy_set_bb_reg(adapter, 0x80c, BIT(21), 1);
156 phy_set_bb_reg(adapter, 0x864, BIT(5) | BIT(4) | BIT(3), 0);
157 phy_set_bb_reg(adapter, 0x864, BIT(8) | BIT(7) | BIT(6), 1);
158
159 /* Enter Traing state */
160 phy_set_bb_reg(adapter, 0x864, BIT(2) | BIT(1) | BIT(0), (AntCombination-1));
161 phy_set_bb_reg(adapter, 0xc50, BIT(7), 1);
162 }
163
rtl88eu_dm_antenna_div_init(struct odm_dm_struct * dm_odm)164 void rtl88eu_dm_antenna_div_init(struct odm_dm_struct *dm_odm)
165 {
166 if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV)
167 dm_rx_hw_antena_div_init(dm_odm);
168 else if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
169 dm_trx_hw_antenna_div_init(dm_odm);
170 else if (dm_odm->AntDivType == CG_TRX_SMART_ANTDIV)
171 dm_fast_training_init(dm_odm);
172 }
173
rtl88eu_dm_update_rx_idle_ant(struct odm_dm_struct * dm_odm,u8 ant)174 void rtl88eu_dm_update_rx_idle_ant(struct odm_dm_struct *dm_odm, u8 ant)
175 {
176 struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
177 struct adapter *adapter = dm_odm->Adapter;
178 u32 default_ant, optional_ant;
179
180 if (dm_fat_tbl->RxIdleAnt != ant) {
181 if (ant == MAIN_ANT) {
182 default_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ?
183 MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
184 optional_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ?
185 AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
186 } else {
187 default_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ?
188 AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
189 optional_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ?
190 MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
191 }
192
193 if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) {
194 phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
195 BIT(5) | BIT(4) | BIT(3), default_ant);
196 phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
197 BIT(8) | BIT(7) | BIT(6), optional_ant);
198 phy_set_bb_reg(adapter, ODM_REG_ANTSEL_CTRL_11N,
199 BIT(14) | BIT(13) | BIT(12), default_ant);
200 phy_set_bb_reg(adapter, ODM_REG_RESP_TX_11N,
201 BIT(6) | BIT(7), default_ant);
202 } else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) {
203 phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
204 BIT(5) | BIT(4) | BIT(3), default_ant);
205 phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
206 BIT(8) | BIT(7) | BIT(6), optional_ant);
207 }
208 }
209 dm_fat_tbl->RxIdleAnt = ant;
210 }
211
update_tx_ant_88eu(struct odm_dm_struct * dm_odm,u8 ant,u32 mac_id)212 static void update_tx_ant_88eu(struct odm_dm_struct *dm_odm, u8 ant, u32 mac_id)
213 {
214 struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
215 u8 target_ant;
216
217 if (ant == MAIN_ANT)
218 target_ant = MAIN_ANT_CG_TRX;
219 else
220 target_ant = AUX_ANT_CG_TRX;
221 dm_fat_tbl->antsel_a[mac_id] = target_ant & BIT(0);
222 dm_fat_tbl->antsel_b[mac_id] = (target_ant & BIT(1))>>1;
223 dm_fat_tbl->antsel_c[mac_id] = (target_ant & BIT(2))>>2;
224 }
225
rtl88eu_dm_set_tx_ant_by_tx_info(struct odm_dm_struct * dm_odm,u8 * desc,u8 mac_id)226 void rtl88eu_dm_set_tx_ant_by_tx_info(struct odm_dm_struct *dm_odm,
227 u8 *desc, u8 mac_id)
228 {
229 struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
230
231 if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ||
232 (dm_odm->AntDivType == CG_TRX_SMART_ANTDIV)) {
233 SET_TX_DESC_ANTSEL_A_88E(desc, dm_fat_tbl->antsel_a[mac_id]);
234 SET_TX_DESC_ANTSEL_B_88E(desc, dm_fat_tbl->antsel_b[mac_id]);
235 SET_TX_DESC_ANTSEL_C_88E(desc, dm_fat_tbl->antsel_c[mac_id]);
236 }
237 }
238
rtl88eu_dm_ant_sel_statistics(struct odm_dm_struct * dm_odm,u8 antsel_tr_mux,u32 mac_id,u8 rx_pwdb_all)239 void rtl88eu_dm_ant_sel_statistics(struct odm_dm_struct *dm_odm,
240 u8 antsel_tr_mux, u32 mac_id, u8 rx_pwdb_all)
241 {
242 struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
243
244 if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) {
245 if (antsel_tr_mux == MAIN_ANT_CG_TRX) {
246 dm_fat_tbl->MainAnt_Sum[mac_id] += rx_pwdb_all;
247 dm_fat_tbl->MainAnt_Cnt[mac_id]++;
248 } else {
249 dm_fat_tbl->AuxAnt_Sum[mac_id] += rx_pwdb_all;
250 dm_fat_tbl->AuxAnt_Cnt[mac_id]++;
251 }
252 } else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) {
253 if (antsel_tr_mux == MAIN_ANT_CGCS_RX) {
254 dm_fat_tbl->MainAnt_Sum[mac_id] += rx_pwdb_all;
255 dm_fat_tbl->MainAnt_Cnt[mac_id]++;
256 } else {
257 dm_fat_tbl->AuxAnt_Sum[mac_id] += rx_pwdb_all;
258 dm_fat_tbl->AuxAnt_Cnt[mac_id]++;
259 }
260 }
261 }
262
rtl88eu_dm_hw_ant_div(struct odm_dm_struct * dm_odm)263 static void rtl88eu_dm_hw_ant_div(struct odm_dm_struct *dm_odm)
264 {
265 struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
266 struct rtw_dig *dig_table = &dm_odm->DM_DigTable;
267 struct sta_info *entry;
268 u32 i, min_rssi = 0xFF, ant_div_max_rssi = 0, max_rssi = 0;
269 u32 local_min_rssi, local_max_rssi;
270 u32 main_rssi, aux_rssi;
271 u8 RxIdleAnt = 0, target_ant = 7;
272
273 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
274 entry = dm_odm->pODM_StaInfo[i];
275 if (IS_STA_VALID(entry)) {
276 /* 2 Caculate RSSI per Antenna */
277 main_rssi = (dm_fat_tbl->MainAnt_Cnt[i] != 0) ?
278 (dm_fat_tbl->MainAnt_Sum[i]/dm_fat_tbl->MainAnt_Cnt[i]) : 0;
279 aux_rssi = (dm_fat_tbl->AuxAnt_Cnt[i] != 0) ?
280 (dm_fat_tbl->AuxAnt_Sum[i]/dm_fat_tbl->AuxAnt_Cnt[i]) : 0;
281 target_ant = (main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT;
282 /* 2 Select max_rssi for DIG */
283 local_max_rssi = max(main_rssi, aux_rssi);
284 if ((local_max_rssi > ant_div_max_rssi) &&
285 (local_max_rssi < 40))
286 ant_div_max_rssi = local_max_rssi;
287 if (local_max_rssi > max_rssi)
288 max_rssi = local_max_rssi;
289
290 /* 2 Select RX Idle Antenna */
291 if ((dm_fat_tbl->RxIdleAnt == MAIN_ANT) &&
292 (main_rssi == 0))
293 main_rssi = aux_rssi;
294 else if ((dm_fat_tbl->RxIdleAnt == AUX_ANT) &&
295 (aux_rssi == 0))
296 aux_rssi = main_rssi;
297
298 local_min_rssi = min(main_rssi, aux_rssi);
299 if (local_min_rssi < min_rssi) {
300 min_rssi = local_min_rssi;
301 RxIdleAnt = target_ant;
302 }
303 /* 2 Select TRX Antenna */
304 if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
305 update_tx_ant_88eu(dm_odm, target_ant, i);
306 }
307 dm_fat_tbl->MainAnt_Sum[i] = 0;
308 dm_fat_tbl->AuxAnt_Sum[i] = 0;
309 dm_fat_tbl->MainAnt_Cnt[i] = 0;
310 dm_fat_tbl->AuxAnt_Cnt[i] = 0;
311 }
312
313 /* 2 Set RX Idle Antenna */
314 rtl88eu_dm_update_rx_idle_ant(dm_odm, RxIdleAnt);
315
316 dig_table->AntDiv_RSSI_max = ant_div_max_rssi;
317 dig_table->RSSI_max = max_rssi;
318 }
319
rtl88eu_dm_antenna_diversity(struct odm_dm_struct * dm_odm)320 void rtl88eu_dm_antenna_diversity(struct odm_dm_struct *dm_odm)
321 {
322 struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
323 struct adapter *adapter = dm_odm->Adapter;
324
325 if (!(dm_odm->SupportAbility & ODM_BB_ANT_DIV))
326 return;
327 if (!dm_odm->bLinked) {
328 ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
329 ("ODM_AntennaDiversity_88E(): No Link.\n"));
330 if (dm_fat_tbl->bBecomeLinked) {
331 ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
332 ("Need to Turn off HW AntDiv\n"));
333 phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0);
334 phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N,
335 BIT(15), 0);
336 if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
337 phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N,
338 BIT(21), 0);
339 dm_fat_tbl->bBecomeLinked = dm_odm->bLinked;
340 }
341 return;
342 } else {
343 if (!dm_fat_tbl->bBecomeLinked) {
344 ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
345 ("Need to Turn on HW AntDiv\n"));
346 phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 1);
347 phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N,
348 BIT(15), 1);
349 if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
350 phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N,
351 BIT(21), 1);
352 dm_fat_tbl->bBecomeLinked = dm_odm->bLinked;
353 }
354 }
355 if ((dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ||
356 (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV))
357 rtl88eu_dm_hw_ant_div(dm_odm);
358 }
359
