1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2013 Realtek Corporation.*/
3
4 #include "../wifi.h"
5 #include "../efuse.h"
6 #include "../base.h"
7 #include "../regd.h"
8 #include "../cam.h"
9 #include "../ps.h"
10 #include "../pci.h"
11 #include "../pwrseqcmd.h"
12 #include "reg.h"
13 #include "def.h"
14 #include "phy.h"
15 #include "dm.h"
16 #include "fw.h"
17 #include "led.h"
18 #include "hw.h"
19 #include "pwrseq.h"
20
21 #define LLT_CONFIG 5
22
_rtl88ee_set_bcn_ctrl_reg(struct ieee80211_hw * hw,u8 set_bits,u8 clear_bits)23 static void _rtl88ee_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
24 u8 set_bits, u8 clear_bits)
25 {
26 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
27 struct rtl_priv *rtlpriv = rtl_priv(hw);
28
29 rtlpci->reg_bcn_ctrl_val |= set_bits;
30 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
31
32 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
33 }
34
_rtl88ee_stop_tx_beacon(struct ieee80211_hw * hw)35 static void _rtl88ee_stop_tx_beacon(struct ieee80211_hw *hw)
36 {
37 struct rtl_priv *rtlpriv = rtl_priv(hw);
38 u8 tmp1byte;
39
40 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
41 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
42 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
43 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
44 tmp1byte &= ~(BIT(0));
45 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
46 }
47
_rtl88ee_resume_tx_beacon(struct ieee80211_hw * hw)48 static void _rtl88ee_resume_tx_beacon(struct ieee80211_hw *hw)
49 {
50 struct rtl_priv *rtlpriv = rtl_priv(hw);
51 u8 tmp1byte;
52
53 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
54 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
55 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
56 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
57 tmp1byte |= BIT(0);
58 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
59 }
60
_rtl88ee_enable_bcn_sub_func(struct ieee80211_hw * hw)61 static void _rtl88ee_enable_bcn_sub_func(struct ieee80211_hw *hw)
62 {
63 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(1));
64 }
65
_rtl88ee_return_beacon_queue_skb(struct ieee80211_hw * hw)66 static void _rtl88ee_return_beacon_queue_skb(struct ieee80211_hw *hw)
67 {
68 struct rtl_priv *rtlpriv = rtl_priv(hw);
69 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
70 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
71 unsigned long flags;
72
73 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
74 while (skb_queue_len(&ring->queue)) {
75 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
76 struct sk_buff *skb = __skb_dequeue(&ring->queue);
77
78 dma_unmap_single(&rtlpci->pdev->dev,
79 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
80 true, HW_DESC_TXBUFF_ADDR),
81 skb->len, DMA_TO_DEVICE);
82 kfree_skb(skb);
83 ring->idx = (ring->idx + 1) % ring->entries;
84 }
85 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
86 }
87
_rtl88ee_disable_bcn_sub_func(struct ieee80211_hw * hw)88 static void _rtl88ee_disable_bcn_sub_func(struct ieee80211_hw *hw)
89 {
90 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(1), 0);
91 }
92
_rtl88ee_set_fw_clock_on(struct ieee80211_hw * hw,u8 rpwm_val,bool b_need_turn_off_ckk)93 static void _rtl88ee_set_fw_clock_on(struct ieee80211_hw *hw,
94 u8 rpwm_val, bool b_need_turn_off_ckk)
95 {
96 struct rtl_priv *rtlpriv = rtl_priv(hw);
97 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
98 bool b_support_remote_wake_up;
99 u32 count = 0, isr_regaddr, content;
100 bool schedule_timer = b_need_turn_off_ckk;
101 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
102 (u8 *)(&b_support_remote_wake_up));
103
104 if (!rtlhal->fw_ready)
105 return;
106 if (!rtlpriv->psc.fw_current_inpsmode)
107 return;
108
109 while (1) {
110 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
111 if (rtlhal->fw_clk_change_in_progress) {
112 while (rtlhal->fw_clk_change_in_progress) {
113 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
114 count++;
115 udelay(100);
116 if (count > 1000)
117 return;
118 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
119 }
120 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
121 } else {
122 rtlhal->fw_clk_change_in_progress = false;
123 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
124 break;
125 }
126 }
127
128 if (IS_IN_LOW_POWER_STATE_88E(rtlhal->fw_ps_state)) {
129 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
130 if (FW_PS_IS_ACK(rpwm_val)) {
131 isr_regaddr = REG_HISR;
132 content = rtl_read_dword(rtlpriv, isr_regaddr);
133 while (!(content & IMR_CPWM) && (count < 500)) {
134 udelay(50);
135 count++;
136 content = rtl_read_dword(rtlpriv, isr_regaddr);
137 }
138
139 if (content & IMR_CPWM) {
140 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
141 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_88E;
142 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
143 "Receive CPWM INT!!! Set pHalData->FwPSState = %X\n",
144 rtlhal->fw_ps_state);
145 }
146 }
147
148 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
149 rtlhal->fw_clk_change_in_progress = false;
150 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
151 if (schedule_timer) {
152 mod_timer(&rtlpriv->works.fw_clockoff_timer,
153 jiffies + MSECS(10));
154 }
155
156 } else {
157 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
158 rtlhal->fw_clk_change_in_progress = false;
159 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
160 }
161 }
162
_rtl88ee_set_fw_clock_off(struct ieee80211_hw * hw,u8 rpwm_val)163 static void _rtl88ee_set_fw_clock_off(struct ieee80211_hw *hw,
164 u8 rpwm_val)
165 {
166 struct rtl_priv *rtlpriv = rtl_priv(hw);
167 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
168 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
169 struct rtl8192_tx_ring *ring;
170 enum rf_pwrstate rtstate;
171 bool schedule_timer = false;
172 u8 queue;
173
174 if (!rtlhal->fw_ready)
175 return;
176 if (!rtlpriv->psc.fw_current_inpsmode)
177 return;
178 if (!rtlhal->allow_sw_to_change_hwclc)
179 return;
180 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
181 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
182 return;
183
184 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
185 ring = &rtlpci->tx_ring[queue];
186 if (skb_queue_len(&ring->queue)) {
187 schedule_timer = true;
188 break;
189 }
190 }
191
192 if (schedule_timer) {
193 mod_timer(&rtlpriv->works.fw_clockoff_timer,
194 jiffies + MSECS(10));
195 return;
196 }
197
198 if (FW_PS_STATE(rtlhal->fw_ps_state) !=
199 FW_PS_STATE_RF_OFF_LOW_PWR_88E) {
200 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
201 if (!rtlhal->fw_clk_change_in_progress) {
202 rtlhal->fw_clk_change_in_progress = true;
203 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
204 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
205 rtl_write_word(rtlpriv, REG_HISR, 0x0100);
206 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
207 &rpwm_val);
208 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
209 rtlhal->fw_clk_change_in_progress = false;
210 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
211 } else {
212 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
213 mod_timer(&rtlpriv->works.fw_clockoff_timer,
214 jiffies + MSECS(10));
215 }
216 }
217 }
218
_rtl88ee_set_fw_ps_rf_on(struct ieee80211_hw * hw)219 static void _rtl88ee_set_fw_ps_rf_on(struct ieee80211_hw *hw)
220 {
221 u8 rpwm_val = 0;
222
223 rpwm_val |= (FW_PS_STATE_RF_OFF_88E | FW_PS_ACK);
224 _rtl88ee_set_fw_clock_on(hw, rpwm_val, true);
225 }
226
_rtl88ee_set_fw_ps_rf_off_low_power(struct ieee80211_hw * hw)227 static void _rtl88ee_set_fw_ps_rf_off_low_power(struct ieee80211_hw *hw)
228 {
229 u8 rpwm_val = 0;
230 rpwm_val |= FW_PS_STATE_RF_OFF_LOW_PWR_88E;
231 _rtl88ee_set_fw_clock_off(hw, rpwm_val);
232 }
233
rtl88ee_fw_clk_off_timer_callback(struct timer_list * t)234 void rtl88ee_fw_clk_off_timer_callback(struct timer_list *t)
235 {
236 struct rtl_priv *rtlpriv = from_timer(rtlpriv, t,
237 works.fw_clockoff_timer);
238 struct ieee80211_hw *hw = rtlpriv->hw;
239
240 _rtl88ee_set_fw_ps_rf_off_low_power(hw);
241 }
242
_rtl88ee_fwlps_leave(struct ieee80211_hw * hw)243 static void _rtl88ee_fwlps_leave(struct ieee80211_hw *hw)
244 {
245 struct rtl_priv *rtlpriv = rtl_priv(hw);
246 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
247 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
248 bool fw_current_inps = false;
249 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
250
251 if (ppsc->low_power_enable) {
252 rpwm_val = (FW_PS_STATE_ALL_ON_88E|FW_PS_ACK);/* RF on */
253 _rtl88ee_set_fw_clock_on(hw, rpwm_val, false);
254 rtlhal->allow_sw_to_change_hwclc = false;
255 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
256 &fw_pwrmode);
257 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
258 (u8 *)(&fw_current_inps));
259 } else {
260 rpwm_val = FW_PS_STATE_ALL_ON_88E; /* RF on */
261 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
262 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
263 &fw_pwrmode);
264 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
265 (u8 *)(&fw_current_inps));
266 }
267 }
268
_rtl88ee_fwlps_enter(struct ieee80211_hw * hw)269 static void _rtl88ee_fwlps_enter(struct ieee80211_hw *hw)
270 {
271 struct rtl_priv *rtlpriv = rtl_priv(hw);
272 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
273 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
274 bool fw_current_inps = true;
275 u8 rpwm_val;
276
277 if (ppsc->low_power_enable) {
278 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_88E; /* RF off */
279 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
280 (u8 *)(&fw_current_inps));
281 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
282 &ppsc->fwctrl_psmode);
283 rtlhal->allow_sw_to_change_hwclc = true;
284 _rtl88ee_set_fw_clock_off(hw, rpwm_val);
285 } else {
286 rpwm_val = FW_PS_STATE_RF_OFF_88E; /* RF off */
287 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
288 (u8 *)(&fw_current_inps));
289 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
290 &ppsc->fwctrl_psmode);
291 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
292 }
293 }
294
rtl88ee_get_hw_reg(struct ieee80211_hw * hw,u8 variable,u8 * val)295 void rtl88ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
296 {
297 struct rtl_priv *rtlpriv = rtl_priv(hw);
298 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
299 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
300
301 switch (variable) {
302 case HW_VAR_RCR:
303 *((u32 *)(val)) = rtlpci->receive_config;
304 break;
305 case HW_VAR_RF_STATE:
306 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
307 break;
308 case HW_VAR_FWLPS_RF_ON:{
309 enum rf_pwrstate rfstate;
310 u32 val_rcr;
311
312 rtlpriv->cfg->ops->get_hw_reg(hw,
313 HW_VAR_RF_STATE,
314 (u8 *)(&rfstate));
315 if (rfstate == ERFOFF) {
316 *((bool *)(val)) = true;
317 } else {
318 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
319 val_rcr &= 0x00070000;
320 if (val_rcr)
321 *((bool *)(val)) = false;
322 else
323 *((bool *)(val)) = true;
324 }
325 break; }
326 case HW_VAR_FW_PSMODE_STATUS:
327 *((bool *)(val)) = ppsc->fw_current_inpsmode;
328 break;
329 case HW_VAR_CORRECT_TSF:{
330 u64 tsf;
331 u32 *ptsf_low = (u32 *)&tsf;
332 u32 *ptsf_high = ((u32 *)&tsf) + 1;
333
334 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
335 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
336
337 *((u64 *)(val)) = tsf;
338 break; }
339 case HAL_DEF_WOWLAN:
340 break;
341 default:
342 pr_err("switch case %#x not processed\n", variable);
343 break;
344 }
345 }
346
rtl88ee_set_hw_reg(struct ieee80211_hw * hw,u8 variable,u8 * val)347 void rtl88ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
348 {
349 struct rtl_priv *rtlpriv = rtl_priv(hw);
350 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
351 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
352 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
353 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
354 u8 idx;
355
356 switch (variable) {
357 case HW_VAR_ETHER_ADDR:
358 for (idx = 0; idx < ETH_ALEN; idx++) {
359 rtl_write_byte(rtlpriv, (REG_MACID + idx),
360 val[idx]);
361 }
362 break;
363 case HW_VAR_BASIC_RATE:{
364 u16 b_rate_cfg = ((u16 *)val)[0];
365 u8 rate_index = 0;
366 b_rate_cfg = b_rate_cfg & 0x15f;
367 b_rate_cfg |= 0x01;
368 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
369 rtl_write_byte(rtlpriv, REG_RRSR + 1,
370 (b_rate_cfg >> 8) & 0xff);
371 while (b_rate_cfg > 0x1) {
372 b_rate_cfg = (b_rate_cfg >> 1);
373 rate_index++;
374 }
375 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
376 rate_index);
377 break;
378 }
379 case HW_VAR_BSSID:
380 for (idx = 0; idx < ETH_ALEN; idx++) {
381 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
382 val[idx]);
383 }
384 break;
385 case HW_VAR_SIFS:
386 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
387 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
388
389 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
390 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
391
392 if (!mac->ht_enable)
393 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
394 0x0e0e);
395 else
396 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
397 *((u16 *)val));
398 break;
399 case HW_VAR_SLOT_TIME:{
400 u8 e_aci;
401
402 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
403 "HW_VAR_SLOT_TIME %x\n", val[0]);
404
405 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
406
407 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
408 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
409 &e_aci);
410 }
411 break;
412 }
413 case HW_VAR_ACK_PREAMBLE:{
414 u8 reg_tmp;
415 u8 short_preamble = (bool)*val;
416 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
417 if (short_preamble) {
418 reg_tmp |= 0x02;
419 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL +
420 2, reg_tmp);
421 } else {
422 reg_tmp |= 0xFD;
423 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL +
424 2, reg_tmp);
425 }
426 break; }
427 case HW_VAR_WPA_CONFIG:
428 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
429 break;
430 case HW_VAR_AMPDU_MIN_SPACE:{
431 u8 min_spacing_to_set;
432 u8 sec_min_space;
433
434 min_spacing_to_set = *val;
435 if (min_spacing_to_set <= 7) {
436 sec_min_space = 0;
437
438 if (min_spacing_to_set < sec_min_space)
439 min_spacing_to_set = sec_min_space;
440
441 mac->min_space_cfg = ((mac->min_space_cfg &
442 0xf8) |
443 min_spacing_to_set);
444
445 *val = min_spacing_to_set;
446
447 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
448 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
449 mac->min_space_cfg);
450
451 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
452 mac->min_space_cfg);
453 }
454 break; }
455 case HW_VAR_SHORTGI_DENSITY:{
456 u8 density_to_set;
457
458 density_to_set = *val;
459 mac->min_space_cfg |= (density_to_set << 3);
460
461 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
462 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
463 mac->min_space_cfg);
464
465 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
466 mac->min_space_cfg);
467 break;
468 }
469 case HW_VAR_AMPDU_FACTOR:{
470 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
471 u8 factor_toset;
472 u8 *p_regtoset = NULL;
473 u8 index = 0;
474
475 p_regtoset = regtoset_normal;
476
477 factor_toset = *val;
478 if (factor_toset <= 3) {
479 factor_toset = (1 << (factor_toset + 2));
480 if (factor_toset > 0xf)
481 factor_toset = 0xf;
482
483 for (index = 0; index < 4; index++) {
484 if ((p_regtoset[index] & 0xf0) >
485 (factor_toset << 4))
486 p_regtoset[index] =
487 (p_regtoset[index] & 0x0f) |
488 (factor_toset << 4);
489
490 if ((p_regtoset[index] & 0x0f) >
491 factor_toset)
492 p_regtoset[index] =
493 (p_regtoset[index] & 0xf0) |
494 (factor_toset);
495
496 rtl_write_byte(rtlpriv,
497 (REG_AGGLEN_LMT + index),
498 p_regtoset[index]);
499
500 }
501
502 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
503 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
504 factor_toset);
505 }
506 break; }
507 case HW_VAR_AC_PARAM:{
508 u8 e_aci = *val;
509 rtl88e_dm_init_edca_turbo(hw);
510
511 if (rtlpci->acm_method != EACMWAY2_SW)
512 rtlpriv->cfg->ops->set_hw_reg(hw,
513 HW_VAR_ACM_CTRL,
514 &e_aci);
515 break; }
516 case HW_VAR_ACM_CTRL:{
517 u8 e_aci = *val;
518 union aci_aifsn *p_aci_aifsn =
519 (union aci_aifsn *)(&(mac->ac[0].aifs));
520 u8 acm = p_aci_aifsn->f.acm;
521 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
522
523 acm_ctrl = acm_ctrl |
524 ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
525
526 if (acm) {
527 switch (e_aci) {
528 case AC0_BE:
529 acm_ctrl |= ACMHW_BEQEN;
530 break;
531 case AC2_VI:
532 acm_ctrl |= ACMHW_VIQEN;
533 break;
534 case AC3_VO:
535 acm_ctrl |= ACMHW_VOQEN;
536 break;
537 default:
538 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
539 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
540 acm);
541 break;
542 }
543 } else {
544 switch (e_aci) {
545 case AC0_BE:
546 acm_ctrl &= (~ACMHW_BEQEN);
547 break;
548 case AC2_VI:
549 acm_ctrl &= (~ACMHW_VIQEN);
550 break;
551 case AC3_VO:
552 acm_ctrl &= (~ACMHW_VOQEN);
553 break;
554 default:
555 pr_err("switch case %#x not processed\n",
556 e_aci);
557 break;
558 }
559 }
560
561 rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE,
562 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
563 acm_ctrl);
564 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
565 break; }
566 case HW_VAR_RCR:
567 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
568 rtlpci->receive_config = ((u32 *)(val))[0];
569 break;
570 case HW_VAR_RETRY_LIMIT:{
571 u8 retry_limit = *val;
572
573 rtl_write_word(rtlpriv, REG_RL,
574 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
575 retry_limit << RETRY_LIMIT_LONG_SHIFT);
576 break; }
577 case HW_VAR_DUAL_TSF_RST:
578 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
579 break;
580 case HW_VAR_EFUSE_BYTES:
581 rtlefuse->efuse_usedbytes = *((u16 *)val);
582 break;
583 case HW_VAR_EFUSE_USAGE:
584 rtlefuse->efuse_usedpercentage = *val;
585 break;
586 case HW_VAR_IO_CMD:
587 rtl88e_phy_set_io_cmd(hw, (*(enum io_type *)val));
588 break;
589 case HW_VAR_SET_RPWM:{
590 u8 rpwm_val;
591
592 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
593 udelay(1);
594
595 if (rpwm_val & BIT(7)) {
596 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val);
597 } else {
598 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val | BIT(7));
599 }
600 break; }
601 case HW_VAR_H2C_FW_PWRMODE:
602 rtl88e_set_fw_pwrmode_cmd(hw, *val);
603 break;
604 case HW_VAR_FW_PSMODE_STATUS:
605 ppsc->fw_current_inpsmode = *((bool *)val);
606 break;
607 case HW_VAR_RESUME_CLK_ON:
608 _rtl88ee_set_fw_ps_rf_on(hw);
609 break;
610 case HW_VAR_FW_LPS_ACTION:{
611 bool enter_fwlps = *((bool *)val);
612
613 if (enter_fwlps)
614 _rtl88ee_fwlps_enter(hw);
615 else
616 _rtl88ee_fwlps_leave(hw);
617
618 break; }
619 case HW_VAR_H2C_FW_JOINBSSRPT:{
620 u8 mstatus = *val;
621 u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
622 u8 count = 0, dlbcn_count = 0;
623 bool b_recover = false;
624
625 if (mstatus == RT_MEDIA_CONNECT) {
626 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
627 NULL);
628
629 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
630 rtl_write_byte(rtlpriv, REG_CR + 1,
631 (tmp_regcr | BIT(0)));
632
633 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
634 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
635
636 tmp_reg422 =
637 rtl_read_byte(rtlpriv,
638 REG_FWHW_TXQ_CTRL + 2);
639 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
640 tmp_reg422 & (~BIT(6)));
641 if (tmp_reg422 & BIT(6))
642 b_recover = true;
643
644 do {
645 bcnvalid_reg = rtl_read_byte(rtlpriv,
646 REG_TDECTRL+2);
647 rtl_write_byte(rtlpriv, REG_TDECTRL+2,
648 (bcnvalid_reg | BIT(0)));
649 _rtl88ee_return_beacon_queue_skb(hw);
650
651 rtl88e_set_fw_rsvdpagepkt(hw, 0);
652 bcnvalid_reg = rtl_read_byte(rtlpriv,
653 REG_TDECTRL+2);
654 count = 0;
655 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
656 count++;
657 udelay(10);
658 bcnvalid_reg =
659 rtl_read_byte(rtlpriv, REG_TDECTRL+2);
660 }
661 dlbcn_count++;
662 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
663
664 if (bcnvalid_reg & BIT(0))
665 rtl_write_byte(rtlpriv, REG_TDECTRL+2, BIT(0));
666
667 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
668 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
669
670 if (b_recover) {
671 rtl_write_byte(rtlpriv,
672 REG_FWHW_TXQ_CTRL + 2,
673 tmp_reg422);
674 }
675
676 rtl_write_byte(rtlpriv, REG_CR + 1,
677 (tmp_regcr & ~(BIT(0))));
678 }
679 rtl88e_set_fw_joinbss_report_cmd(hw, (*(u8 *)val));
680 break; }
681 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
682 rtl88e_set_p2p_ps_offload_cmd(hw, *val);
683 break;
684 case HW_VAR_AID:{
685 u16 u2btmp;
686
687 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
688 u2btmp &= 0xC000;
689 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
690 mac->assoc_id));
691 break; }
692 case HW_VAR_CORRECT_TSF:{
693 u8 btype_ibss = *val;
694
695 if (btype_ibss)
696 _rtl88ee_stop_tx_beacon(hw);
697
698 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
699
700 rtl_write_dword(rtlpriv, REG_TSFTR,
701 (u32)(mac->tsf & 0xffffffff));
702 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
703 (u32)((mac->tsf >> 32) & 0xffffffff));
704
705 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
706
707 if (btype_ibss)
708 _rtl88ee_resume_tx_beacon(hw);
709 break; }
710 case HW_VAR_KEEP_ALIVE: {
711 u8 array[2];
712
713 array[0] = 0xff;
714 array[1] = *((u8 *)val);
715 rtl88e_fill_h2c_cmd(hw, H2C_88E_KEEP_ALIVE_CTRL,
716 2, array);
717 break; }
718 default:
719 pr_err("switch case %#x not processed\n", variable);
720 break;
721 }
722 }
723
_rtl88ee_llt_write(struct ieee80211_hw * hw,u32 address,u32 data)724 static bool _rtl88ee_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
725 {
726 struct rtl_priv *rtlpriv = rtl_priv(hw);
727 bool status = true;
728 long count = 0;
729 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
730 _LLT_OP(_LLT_WRITE_ACCESS);
731
732 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
733
734 do {
735 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
736 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
737 break;
738
739 if (count > POLLING_LLT_THRESHOLD) {
740 pr_err("Failed to polling write LLT done at address %d!\n",
741 address);
742 status = false;
743 break;
744 }
745 } while (++count);
746
747 return status;
748 }
749
_rtl88ee_llt_table_init(struct ieee80211_hw * hw)750 static bool _rtl88ee_llt_table_init(struct ieee80211_hw *hw)
751 {
752 struct rtl_priv *rtlpriv = rtl_priv(hw);
753 unsigned short i;
754 u8 txpktbuf_bndy;
755 u8 maxpage;
756 bool status;
757
758 maxpage = 0xAF;
759 txpktbuf_bndy = 0xAB;
760
761 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x01);
762 rtl_write_dword(rtlpriv, REG_RQPN, 0x80730d29);
763
764 /*0x2600 MaxRxBuff=10k-max(TxReportSize(64*8), WOLPattern(16*24)) */
765 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x25FF0000 | txpktbuf_bndy));
766 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
767
768 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
769 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
770
771 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
772 rtl_write_byte(rtlpriv, REG_PBP, 0x11);
773 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
774
775 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
776 status = _rtl88ee_llt_write(hw, i, i + 1);
777 if (!status)
778 return status;
779 }
780
781 status = _rtl88ee_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
782 if (!status)
783 return status;
784
785 for (i = txpktbuf_bndy; i < maxpage; i++) {
786 status = _rtl88ee_llt_write(hw, i, (i + 1));
787 if (!status)
788 return status;
789 }
790
791 status = _rtl88ee_llt_write(hw, maxpage, txpktbuf_bndy);
792 if (!status)
793 return status;
794
795 return true;
796 }
797
_rtl88ee_gen_refresh_led_state(struct ieee80211_hw * hw)798 static void _rtl88ee_gen_refresh_led_state(struct ieee80211_hw *hw)
799 {
800 struct rtl_priv *rtlpriv = rtl_priv(hw);
801 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
802 struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
803
804 if (rtlpriv->rtlhal.up_first_time)
805 return;
806
807 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
808 rtl88ee_sw_led_on(hw, pled0);
809 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
810 rtl88ee_sw_led_on(hw, pled0);
811 else
812 rtl88ee_sw_led_off(hw, pled0);
813 }
814
_rtl88ee_init_mac(struct ieee80211_hw * hw)815 static bool _rtl88ee_init_mac(struct ieee80211_hw *hw)
816 {
817 struct rtl_priv *rtlpriv = rtl_priv(hw);
818 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
819 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
820
821 u8 bytetmp;
822 u16 wordtmp;
823
824 /*Disable XTAL OUTPUT for power saving. YJ,add,111206. */
825 bytetmp = rtl_read_byte(rtlpriv, REG_XCK_OUT_CTRL) & (~BIT(0));
826 rtl_write_byte(rtlpriv, REG_XCK_OUT_CTRL, bytetmp);
827 /*Auto Power Down to CHIP-off State*/
828 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
829 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
830
831 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
832 /* HW Power on sequence */
833 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
834 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
835 RTL8188EE_NIC_ENABLE_FLOW)) {
836 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
837 "init MAC Fail as rtl_hal_pwrseqcmdparsing\n");
838 return false;
839 }
840
841 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
842 rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
843
844 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+2);
845 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp|BIT(2));
846
847 bytetmp = rtl_read_byte(rtlpriv, REG_WATCH_DOG+1);
848 rtl_write_byte(rtlpriv, REG_WATCH_DOG+1, bytetmp|BIT(7));
849
850 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1);
851 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1, bytetmp|BIT(1));
852
853 bytetmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL);
854 rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, bytetmp|BIT(1)|BIT(0));
855 rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL+1, 2);
856 rtl_write_word(rtlpriv, REG_TX_RPT_TIME, 0xcdf0);
857
858 /*Add for wake up online*/
859 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
860
861 rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp|BIT(3));
862 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG+1);
863 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+1, (bytetmp & (~BIT(4))));
864 rtl_write_byte(rtlpriv, 0x367, 0x80);
865
866 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
867 rtl_write_byte(rtlpriv, REG_CR+1, 0x06);
868 rtl_write_byte(rtlpriv, MSR, 0x00);
869
870 if (!rtlhal->mac_func_enable) {
871 if (!_rtl88ee_llt_table_init(hw)) {
872 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
873 "LLT table init fail\n");
874 return false;
875 }
876 }
877 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
878 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
879
880 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
881 wordtmp &= 0xf;
882 wordtmp |= 0xE771;
883 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
884
885 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
886 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xffff);
887 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
888
889 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
890 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
891 DMA_BIT_MASK(32));
892 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
893 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
894 DMA_BIT_MASK(32));
895 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
896 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
897 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
898 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
899 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
900 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
901 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
902 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
903 rtl_write_dword(rtlpriv, REG_HQ_DESA,
904 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
905 DMA_BIT_MASK(32));
906 rtl_write_dword(rtlpriv, REG_RX_DESA,
907 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
908 DMA_BIT_MASK(32));
909
910 /* if we want to support 64 bit DMA, we should set it here,
911 * but now we do not support 64 bit DMA
912 */
913 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
914
915 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
916 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0);/*Enable RX DMA */
917
918 if (rtlhal->earlymode_enable) {/*Early mode enable*/
919 bytetmp = rtl_read_byte(rtlpriv, REG_EARLY_MODE_CONTROL);
920 bytetmp |= 0x1f;
921 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, bytetmp);
922 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL+3, 0x81);
923 }
924 _rtl88ee_gen_refresh_led_state(hw);
925 return true;
926 }
927
_rtl88ee_hw_configure(struct ieee80211_hw * hw)928 static void _rtl88ee_hw_configure(struct ieee80211_hw *hw)
929 {
930 struct rtl_priv *rtlpriv = rtl_priv(hw);
931 u32 reg_prsr;
932
933 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
934
935 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
936 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
937 }
938
_rtl88ee_enable_aspm_back_door(struct ieee80211_hw * hw)939 static void _rtl88ee_enable_aspm_back_door(struct ieee80211_hw *hw)
940 {
941 struct rtl_priv *rtlpriv = rtl_priv(hw);
942 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
943 u8 tmp1byte = 0;
944 u32 tmp4byte = 0, count = 0;
945
946 rtl_write_word(rtlpriv, 0x354, 0x8104);
947 rtl_write_word(rtlpriv, 0x358, 0x24);
948
949 rtl_write_word(rtlpriv, 0x350, 0x70c);
950 rtl_write_byte(rtlpriv, 0x352, 0x2);
951 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
952 count = 0;
953 while (tmp1byte && count < 20) {
954 udelay(10);
955 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
956 count++;
957 }
958 if (0 == tmp1byte) {
959 tmp4byte = rtl_read_dword(rtlpriv, 0x34c);
960 rtl_write_dword(rtlpriv, 0x348, tmp4byte|BIT(31));
961 rtl_write_word(rtlpriv, 0x350, 0xf70c);
962 rtl_write_byte(rtlpriv, 0x352, 0x1);
963 }
964
965 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
966 count = 0;
967 while (tmp1byte && count < 20) {
968 udelay(10);
969 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
970 count++;
971 }
972
973 rtl_write_word(rtlpriv, 0x350, 0x718);
974 rtl_write_byte(rtlpriv, 0x352, 0x2);
975 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
976 count = 0;
977 while (tmp1byte && count < 20) {
978 udelay(10);
979 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
980 count++;
981 }
982
983 if (ppsc->support_backdoor || (0 == tmp1byte)) {
984 tmp4byte = rtl_read_dword(rtlpriv, 0x34c);
985 rtl_write_dword(rtlpriv, 0x348, tmp4byte|BIT(11)|BIT(12));
986 rtl_write_word(rtlpriv, 0x350, 0xf718);
987 rtl_write_byte(rtlpriv, 0x352, 0x1);
988 }
989
990 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
991 count = 0;
992 while (tmp1byte && count < 20) {
993 udelay(10);
994 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
995 count++;
996 }
997 }
998
rtl88ee_enable_hw_security_config(struct ieee80211_hw * hw)999 void rtl88ee_enable_hw_security_config(struct ieee80211_hw *hw)
1000 {
1001 struct rtl_priv *rtlpriv = rtl_priv(hw);
1002 u8 sec_reg_value;
1003
1004 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1005 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1006 rtlpriv->sec.pairwise_enc_algorithm,
1007 rtlpriv->sec.group_enc_algorithm);
1008
1009 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1010 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
1011 "not open hw encryption\n");
1012 return;
1013 }
1014
1015 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1016
1017 if (rtlpriv->sec.use_defaultkey) {
1018 sec_reg_value |= SCR_TXUSEDK;
1019 sec_reg_value |= SCR_RXUSEDK;
1020 }
1021
1022 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1023
1024 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1025
1026 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
1027 "The SECR-value %x\n", sec_reg_value);
1028
1029 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1030 }
1031
rtl88ee_hw_init(struct ieee80211_hw * hw)1032 int rtl88ee_hw_init(struct ieee80211_hw *hw)
1033 {
1034 struct rtl_priv *rtlpriv = rtl_priv(hw);
1035 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1036 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1037 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1038 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1039 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1040 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1041 bool rtstatus;
1042 int err = 0;
1043 u8 tmp_u1b, u1byte;
1044 unsigned long flags;
1045
1046 rtlpriv->rtlhal.being_init_adapter = true;
1047 /* As this function can take a very long time (up to 350 ms)
1048 * and can be called with irqs disabled, reenable the irqs
1049 * to let the other devices continue being serviced.
1050 *
1051 * It is safe doing so since our own interrupts will only be enabled
1052 * in a subsequent step.
1053 */
1054 local_save_flags(flags);
1055 local_irq_enable();
1056 rtlhal->fw_ready = false;
1057
1058 rtlpriv->intf_ops->disable_aspm(hw);
1059
1060 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CLKR+1);
1061 u1byte = rtl_read_byte(rtlpriv, REG_CR);
1062 if ((tmp_u1b & BIT(3)) && (u1byte != 0 && u1byte != 0xEA)) {
1063 rtlhal->mac_func_enable = true;
1064 } else {
1065 rtlhal->mac_func_enable = false;
1066 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E;
1067 }
1068
1069 rtstatus = _rtl88ee_init_mac(hw);
1070 if (!rtstatus) {
1071 pr_info("Init MAC failed\n");
1072 err = 1;
1073 goto exit;
1074 }
1075
1076 err = rtl88e_download_fw(hw, false);
1077 if (err) {
1078 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1079 "Failed to download FW. Init HW without FW now..\n");
1080 err = 1;
1081 goto exit;
1082 }
1083 rtlhal->fw_ready = true;
1084 /*fw related variable initialize */
1085 rtlhal->last_hmeboxnum = 0;
1086 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E;
1087 rtlhal->fw_clk_change_in_progress = false;
1088 rtlhal->allow_sw_to_change_hwclc = false;
1089 ppsc->fw_current_inpsmode = false;
1090
1091 rtl88e_phy_mac_config(hw);
1092 /* because last function modify RCR, so we update
1093 * rcr var here, or TP will unstable for receive_config
1094 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1095 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1096 */
1097 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1098 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1099
1100 rtl88e_phy_bb_config(hw);
1101 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1102 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1103
1104 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1105 rtl88e_phy_rf_config(hw);
1106
1107 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1108 RF_CHNLBW, RFREG_OFFSET_MASK);
1109 rtlphy->rfreg_chnlval[0] = rtlphy->rfreg_chnlval[0] & 0xfff00fff;
1110
1111 _rtl88ee_hw_configure(hw);
1112 rtl_cam_reset_all_entry(hw);
1113 rtl88ee_enable_hw_security_config(hw);
1114
1115 rtlhal->mac_func_enable = true;
1116 ppsc->rfpwr_state = ERFON;
1117
1118 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1119 _rtl88ee_enable_aspm_back_door(hw);
1120 rtlpriv->intf_ops->enable_aspm(hw);
1121
1122 if (ppsc->rfpwr_state == ERFON) {
1123 if ((rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) ||
1124 ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) &&
1125 (rtlhal->oem_id == RT_CID_819X_HP))) {
1126 rtl88e_phy_set_rfpath_switch(hw, true);
1127 rtlpriv->dm.fat_table.rx_idle_ant = MAIN_ANT;
1128 } else {
1129 rtl88e_phy_set_rfpath_switch(hw, false);
1130 rtlpriv->dm.fat_table.rx_idle_ant = AUX_ANT;
1131 }
1132 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "rx idle ant %s\n",
1133 (rtlpriv->dm.fat_table.rx_idle_ant == MAIN_ANT) ?
1134 ("MAIN_ANT") : ("AUX_ANT"));
1135
1136 if (rtlphy->iqk_initialized) {
1137 rtl88e_phy_iq_calibrate(hw, true);
1138 } else {
1139 rtl88e_phy_iq_calibrate(hw, false);
1140 rtlphy->iqk_initialized = true;
1141 }
1142
1143 rtl88e_dm_check_txpower_tracking(hw);
1144 rtl88e_phy_lc_calibrate(hw);
1145 }
1146
1147 tmp_u1b = efuse_read_1byte(hw, 0x1FA);
1148 if (!(tmp_u1b & BIT(0))) {
1149 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1150 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path A\n");
1151 }
1152
1153 if (!(tmp_u1b & BIT(4))) {
1154 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1155 tmp_u1b &= 0x0F;
1156 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1157 udelay(10);
1158 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1159 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "under 1.5V\n");
1160 }
1161 rtl_write_byte(rtlpriv, REG_NAV_CTRL+2, ((30000+127)/128));
1162 rtl88e_dm_init(hw);
1163 exit:
1164 local_irq_restore(flags);
1165 rtlpriv->rtlhal.being_init_adapter = false;
1166 return err;
1167 }
1168
_rtl88ee_read_chip_version(struct ieee80211_hw * hw)1169 static enum version_8188e _rtl88ee_read_chip_version(struct ieee80211_hw *hw)
1170 {
1171 struct rtl_priv *rtlpriv = rtl_priv(hw);
1172 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1173 enum version_8188e version = VERSION_UNKNOWN;
1174 u32 value32;
1175
1176 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1177 if (value32 & TRP_VAUX_EN) {
1178 version = (enum version_8188e) VERSION_TEST_CHIP_88E;
1179 } else {
1180 version = NORMAL_CHIP;
1181 version = version | ((value32 & TYPE_ID) ? RF_TYPE_2T2R : 0);
1182 version = version | ((value32 & VENDOR_ID) ?
1183 CHIP_VENDOR_UMC : 0);
1184 }
1185
1186 rtlphy->rf_type = RF_1T1R;
1187 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1188 "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1189 "RF_2T2R" : "RF_1T1R");
1190
1191 return version;
1192 }
1193
_rtl88ee_set_media_status(struct ieee80211_hw * hw,enum nl80211_iftype type)1194 static int _rtl88ee_set_media_status(struct ieee80211_hw *hw,
1195 enum nl80211_iftype type)
1196 {
1197 struct rtl_priv *rtlpriv = rtl_priv(hw);
1198 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1199 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1200 u8 mode = MSR_NOLINK;
1201
1202 switch (type) {
1203 case NL80211_IFTYPE_UNSPECIFIED:
1204 mode = MSR_NOLINK;
1205 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1206 "Set Network type to NO LINK!\n");
1207 break;
1208 case NL80211_IFTYPE_ADHOC:
1209 case NL80211_IFTYPE_MESH_POINT:
1210 mode = MSR_ADHOC;
1211 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1212 "Set Network type to Ad Hoc!\n");
1213 break;
1214 case NL80211_IFTYPE_STATION:
1215 mode = MSR_INFRA;
1216 ledaction = LED_CTL_LINK;
1217 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1218 "Set Network type to STA!\n");
1219 break;
1220 case NL80211_IFTYPE_AP:
1221 mode = MSR_AP;
1222 ledaction = LED_CTL_LINK;
1223 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1224 "Set Network type to AP!\n");
1225 break;
1226 default:
1227 pr_err("Network type %d not support!\n", type);
1228 return 1;
1229 break;
1230 }
1231
1232 /* MSR_INFRA == Link in infrastructure network;
1233 * MSR_ADHOC == Link in ad hoc network;
1234 * Therefore, check link state is necessary.
1235 *
1236 * MSR_AP == AP mode; link state is not cared here.
1237 */
1238 if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1239 mode = MSR_NOLINK;
1240 ledaction = LED_CTL_NO_LINK;
1241 }
1242
1243 if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1244 _rtl88ee_stop_tx_beacon(hw);
1245 _rtl88ee_enable_bcn_sub_func(hw);
1246 } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1247 _rtl88ee_resume_tx_beacon(hw);
1248 _rtl88ee_disable_bcn_sub_func(hw);
1249 } else {
1250 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1251 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1252 mode);
1253 }
1254
1255 rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1256 rtlpriv->cfg->ops->led_control(hw, ledaction);
1257 if (mode == MSR_AP)
1258 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1259 else
1260 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1261 return 0;
1262 }
1263
rtl88ee_set_check_bssid(struct ieee80211_hw * hw,bool check_bssid)1264 void rtl88ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1265 {
1266 struct rtl_priv *rtlpriv = rtl_priv(hw);
1267 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1268 u32 reg_rcr = rtlpci->receive_config;
1269
1270 if (rtlpriv->psc.rfpwr_state != ERFON)
1271 return;
1272
1273 if (check_bssid == true) {
1274 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1275 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1276 (u8 *)(®_rcr));
1277 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
1278 } else if (check_bssid == false) {
1279 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1280 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
1281 rtlpriv->cfg->ops->set_hw_reg(hw,
1282 HW_VAR_RCR, (u8 *)(®_rcr));
1283 }
1284
1285 }
1286
rtl88ee_set_network_type(struct ieee80211_hw * hw,enum nl80211_iftype type)1287 int rtl88ee_set_network_type(struct ieee80211_hw *hw,
1288 enum nl80211_iftype type)
1289 {
1290 struct rtl_priv *rtlpriv = rtl_priv(hw);
1291
1292 if (_rtl88ee_set_media_status(hw, type))
1293 return -EOPNOTSUPP;
1294
1295 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1296 if (type != NL80211_IFTYPE_AP &&
1297 type != NL80211_IFTYPE_MESH_POINT)
1298 rtl88ee_set_check_bssid(hw, true);
1299 } else {
1300 rtl88ee_set_check_bssid(hw, false);
1301 }
1302
1303 return 0;
1304 }
1305
1306 /* don't set REG_EDCA_BE_PARAM here
1307 * because mac80211 will send pkt when scan
1308 */
rtl88ee_set_qos(struct ieee80211_hw * hw,int aci)1309 void rtl88ee_set_qos(struct ieee80211_hw *hw, int aci)
1310 {
1311 struct rtl_priv *rtlpriv = rtl_priv(hw);
1312 rtl88e_dm_init_edca_turbo(hw);
1313 switch (aci) {
1314 case AC1_BK:
1315 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1316 break;
1317 case AC0_BE:
1318 break;
1319 case AC2_VI:
1320 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1321 break;
1322 case AC3_VO:
1323 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1324 break;
1325 default:
1326 WARN_ONCE(true, "rtl8188ee: invalid aci: %d !\n", aci);
1327 break;
1328 }
1329 }
1330
rtl88ee_enable_interrupt(struct ieee80211_hw * hw)1331 void rtl88ee_enable_interrupt(struct ieee80211_hw *hw)
1332 {
1333 struct rtl_priv *rtlpriv = rtl_priv(hw);
1334 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1335
1336 rtl_write_dword(rtlpriv, REG_HIMR,
1337 rtlpci->irq_mask[0] & 0xFFFFFFFF);
1338 rtl_write_dword(rtlpriv, REG_HIMRE,
1339 rtlpci->irq_mask[1] & 0xFFFFFFFF);
1340 rtlpci->irq_enabled = true;
1341 /* there are some C2H CMDs have been sent
1342 * before system interrupt is enabled, e.g., C2H, CPWM.
1343 * So we need to clear all C2H events that FW has notified,
1344 * otherwise FW won't schedule any commands anymore.
1345 */
1346 rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0);
1347 /*enable system interrupt*/
1348 rtl_write_dword(rtlpriv, REG_HSIMR,
1349 rtlpci->sys_irq_mask & 0xFFFFFFFF);
1350 }
1351
rtl88ee_disable_interrupt(struct ieee80211_hw * hw)1352 void rtl88ee_disable_interrupt(struct ieee80211_hw *hw)
1353 {
1354 struct rtl_priv *rtlpriv = rtl_priv(hw);
1355 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1356
1357 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1358 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1359 rtlpci->irq_enabled = false;
1360 /*synchronize_irq(rtlpci->pdev->irq);*/
1361 }
1362
_rtl88ee_poweroff_adapter(struct ieee80211_hw * hw)1363 static void _rtl88ee_poweroff_adapter(struct ieee80211_hw *hw)
1364 {
1365 struct rtl_priv *rtlpriv = rtl_priv(hw);
1366 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1367 u8 u1b_tmp;
1368 u32 count = 0;
1369 rtlhal->mac_func_enable = false;
1370 rtlpriv->intf_ops->enable_aspm(hw);
1371
1372 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "POWER OFF adapter\n");
1373 u1b_tmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL);
1374 rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, u1b_tmp & (~BIT(1)));
1375
1376 u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1377 while (!(u1b_tmp & BIT(1)) && (count++ < 100)) {
1378 udelay(10);
1379 u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1380 count++;
1381 }
1382 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0xFF);
1383
1384 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1385 PWR_INTF_PCI_MSK,
1386 RTL8188EE_NIC_LPS_ENTER_FLOW);
1387
1388 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1389
1390 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1391 rtl88e_firmware_selfreset(hw);
1392
1393 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1394 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1395 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1396
1397 u1b_tmp = rtl_read_byte(rtlpriv, REG_32K_CTRL);
1398 rtl_write_byte(rtlpriv, REG_32K_CTRL, (u1b_tmp & (~BIT(0))));
1399
1400 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1401 PWR_INTF_PCI_MSK, RTL8188EE_NIC_DISABLE_FLOW);
1402
1403 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
1404 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp & (~BIT(3))));
1405 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
1406 rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp | BIT(3)));
1407
1408 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1409
1410 u1b_tmp = rtl_read_byte(rtlpriv, GPIO_IN);
1411 rtl_write_byte(rtlpriv, GPIO_OUT, u1b_tmp);
1412 rtl_write_byte(rtlpriv, GPIO_IO_SEL, 0x7F);
1413
1414 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
1415 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL, (u1b_tmp << 4) | u1b_tmp);
1416 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL+1);
1417 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL+1, u1b_tmp | 0x0F);
1418
1419 rtl_write_dword(rtlpriv, REG_GPIO_IO_SEL_2+2, 0x00080808);
1420 }
1421
rtl88ee_card_disable(struct ieee80211_hw * hw)1422 void rtl88ee_card_disable(struct ieee80211_hw *hw)
1423 {
1424 struct rtl_priv *rtlpriv = rtl_priv(hw);
1425 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1426 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1427 enum nl80211_iftype opmode;
1428
1429 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8188ee card disable\n");
1430
1431 mac->link_state = MAC80211_NOLINK;
1432 opmode = NL80211_IFTYPE_UNSPECIFIED;
1433
1434 _rtl88ee_set_media_status(hw, opmode);
1435
1436 if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1437 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1438 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1439
1440 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1441 _rtl88ee_poweroff_adapter(hw);
1442
1443 /* after power off we should do iqk again */
1444 rtlpriv->phy.iqk_initialized = false;
1445 }
1446
rtl88ee_interrupt_recognized(struct ieee80211_hw * hw,struct rtl_int * intvec)1447 void rtl88ee_interrupt_recognized(struct ieee80211_hw *hw,
1448 struct rtl_int *intvec)
1449 {
1450 struct rtl_priv *rtlpriv = rtl_priv(hw);
1451 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1452
1453 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1454 rtl_write_dword(rtlpriv, ISR, intvec->inta);
1455
1456 intvec->intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1457 rtl_write_dword(rtlpriv, REG_HISRE, intvec->intb);
1458
1459 }
1460
rtl88ee_set_beacon_related_registers(struct ieee80211_hw * hw)1461 void rtl88ee_set_beacon_related_registers(struct ieee80211_hw *hw)
1462 {
1463 struct rtl_priv *rtlpriv = rtl_priv(hw);
1464 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1465 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1466 u16 bcn_interval, atim_window;
1467
1468 bcn_interval = mac->beacon_interval;
1469 atim_window = 2; /*FIX MERGE */
1470 rtl88ee_disable_interrupt(hw);
1471 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1472 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1473 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1474 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1475 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1476 rtl_write_byte(rtlpriv, 0x606, 0x30);
1477 rtlpci->reg_bcn_ctrl_val |= BIT(3);
1478 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
1479 /*rtl88ee_enable_interrupt(hw);*/
1480 }
1481
rtl88ee_set_beacon_interval(struct ieee80211_hw * hw)1482 void rtl88ee_set_beacon_interval(struct ieee80211_hw *hw)
1483 {
1484 struct rtl_priv *rtlpriv = rtl_priv(hw);
1485 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1486 u16 bcn_interval = mac->beacon_interval;
1487
1488 rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG,
1489 "beacon_interval:%d\n", bcn_interval);
1490 /*rtl88ee_disable_interrupt(hw);*/
1491 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1492 /*rtl88ee_enable_interrupt(hw);*/
1493 }
1494
rtl88ee_update_interrupt_mask(struct ieee80211_hw * hw,u32 add_msr,u32 rm_msr)1495 void rtl88ee_update_interrupt_mask(struct ieee80211_hw *hw,
1496 u32 add_msr, u32 rm_msr)
1497 {
1498 struct rtl_priv *rtlpriv = rtl_priv(hw);
1499 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1500
1501 rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD,
1502 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1503
1504 if (add_msr)
1505 rtlpci->irq_mask[0] |= add_msr;
1506 if (rm_msr)
1507 rtlpci->irq_mask[0] &= (~rm_msr);
1508 rtl88ee_disable_interrupt(hw);
1509 rtl88ee_enable_interrupt(hw);
1510 }
1511
_rtl88e_get_chnl_group(u8 chnl)1512 static u8 _rtl88e_get_chnl_group(u8 chnl)
1513 {
1514 u8 group = 0;
1515
1516 if (chnl < 3)
1517 group = 0;
1518 else if (chnl < 6)
1519 group = 1;
1520 else if (chnl < 9)
1521 group = 2;
1522 else if (chnl < 12)
1523 group = 3;
1524 else if (chnl < 14)
1525 group = 4;
1526 else if (chnl == 14)
1527 group = 5;
1528
1529 return group;
1530 }
1531
set_24g_base(struct txpower_info_2g * pwrinfo24g,u32 rfpath)1532 static void set_24g_base(struct txpower_info_2g *pwrinfo24g, u32 rfpath)
1533 {
1534 int group, txcnt;
1535
1536 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1537 pwrinfo24g->index_cck_base[rfpath][group] = 0x2D;
1538 pwrinfo24g->index_bw40_base[rfpath][group] = 0x2D;
1539 }
1540 for (txcnt = 0; txcnt < MAX_TX_COUNT; txcnt++) {
1541 if (txcnt == 0) {
1542 pwrinfo24g->bw20_diff[rfpath][0] = 0x02;
1543 pwrinfo24g->ofdm_diff[rfpath][0] = 0x04;
1544 } else {
1545 pwrinfo24g->bw20_diff[rfpath][txcnt] = 0xFE;
1546 pwrinfo24g->bw40_diff[rfpath][txcnt] = 0xFE;
1547 pwrinfo24g->cck_diff[rfpath][txcnt] = 0xFE;
1548 pwrinfo24g->ofdm_diff[rfpath][txcnt] = 0xFE;
1549 }
1550 }
1551 }
1552
read_power_value_fromprom(struct ieee80211_hw * hw,struct txpower_info_2g * pwrinfo24g,struct txpower_info_5g * pwrinfo5g,bool autoload_fail,u8 * hwinfo)1553 static void read_power_value_fromprom(struct ieee80211_hw *hw,
1554 struct txpower_info_2g *pwrinfo24g,
1555 struct txpower_info_5g *pwrinfo5g,
1556 bool autoload_fail, u8 *hwinfo)
1557 {
1558 struct rtl_priv *rtlpriv = rtl_priv(hw);
1559 u32 rfpath, eeaddr = EEPROM_TX_PWR_INX, group, txcnt = 0;
1560
1561 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1562 "hal_ReadPowerValueFromPROM88E():PROMContent[0x%x]=0x%x\n",
1563 (eeaddr + 1), hwinfo[eeaddr + 1]);
1564 if (0xFF == hwinfo[eeaddr+1]) /*YJ,add,120316*/
1565 autoload_fail = true;
1566
1567 if (autoload_fail) {
1568 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1569 "auto load fail : Use Default value!\n");
1570 for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
1571 /* 2.4G default value */
1572 set_24g_base(pwrinfo24g, rfpath);
1573 }
1574 return;
1575 }
1576
1577 for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
1578 /*2.4G default value*/
1579 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1580 pwrinfo24g->index_cck_base[rfpath][group] =
1581 hwinfo[eeaddr++];
1582 if (pwrinfo24g->index_cck_base[rfpath][group] == 0xFF)
1583 pwrinfo24g->index_cck_base[rfpath][group] =
1584 0x2D;
1585 }
1586 for (group = 0 ; group < MAX_CHNL_GROUP_24G-1; group++) {
1587 pwrinfo24g->index_bw40_base[rfpath][group] =
1588 hwinfo[eeaddr++];
1589 if (pwrinfo24g->index_bw40_base[rfpath][group] == 0xFF)
1590 pwrinfo24g->index_bw40_base[rfpath][group] =
1591 0x2D;
1592 }
1593 pwrinfo24g->bw40_diff[rfpath][0] = 0;
1594 if (hwinfo[eeaddr] == 0xFF) {
1595 pwrinfo24g->bw20_diff[rfpath][0] = 0x02;
1596 } else {
1597 pwrinfo24g->bw20_diff[rfpath][0] =
1598 (hwinfo[eeaddr]&0xf0)>>4;
1599 /*bit sign number to 8 bit sign number*/
1600 if (pwrinfo24g->bw20_diff[rfpath][0] & BIT(3))
1601 pwrinfo24g->bw20_diff[rfpath][0] |= 0xF0;
1602 }
1603
1604 if (hwinfo[eeaddr] == 0xFF) {
1605 pwrinfo24g->ofdm_diff[rfpath][0] = 0x04;
1606 } else {
1607 pwrinfo24g->ofdm_diff[rfpath][0] =
1608 (hwinfo[eeaddr]&0x0f);
1609 /*bit sign number to 8 bit sign number*/
1610 if (pwrinfo24g->ofdm_diff[rfpath][0] & BIT(3))
1611 pwrinfo24g->ofdm_diff[rfpath][0] |= 0xF0;
1612 }
1613 pwrinfo24g->cck_diff[rfpath][0] = 0;
1614 eeaddr++;
1615 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1616 if (hwinfo[eeaddr] == 0xFF) {
1617 pwrinfo24g->bw40_diff[rfpath][txcnt] = 0xFE;
1618 } else {
1619 pwrinfo24g->bw40_diff[rfpath][txcnt] =
1620 (hwinfo[eeaddr]&0xf0)>>4;
1621 if (pwrinfo24g->bw40_diff[rfpath][txcnt] &
1622 BIT(3))
1623 pwrinfo24g->bw40_diff[rfpath][txcnt] |=
1624 0xF0;
1625 }
1626
1627 if (hwinfo[eeaddr] == 0xFF) {
1628 pwrinfo24g->bw20_diff[rfpath][txcnt] =
1629 0xFE;
1630 } else {
1631 pwrinfo24g->bw20_diff[rfpath][txcnt] =
1632 (hwinfo[eeaddr]&0x0f);
1633 if (pwrinfo24g->bw20_diff[rfpath][txcnt] &
1634 BIT(3))
1635 pwrinfo24g->bw20_diff[rfpath][txcnt] |=
1636 0xF0;
1637 }
1638 eeaddr++;
1639
1640 if (hwinfo[eeaddr] == 0xFF) {
1641 pwrinfo24g->ofdm_diff[rfpath][txcnt] = 0xFE;
1642 } else {
1643 pwrinfo24g->ofdm_diff[rfpath][txcnt] =
1644 (hwinfo[eeaddr]&0xf0)>>4;
1645 if (pwrinfo24g->ofdm_diff[rfpath][txcnt] &
1646 BIT(3))
1647 pwrinfo24g->ofdm_diff[rfpath][txcnt] |=
1648 0xF0;
1649 }
1650
1651 if (hwinfo[eeaddr] == 0xFF) {
1652 pwrinfo24g->cck_diff[rfpath][txcnt] = 0xFE;
1653 } else {
1654 pwrinfo24g->cck_diff[rfpath][txcnt] =
1655 (hwinfo[eeaddr]&0x0f);
1656 if (pwrinfo24g->cck_diff[rfpath][txcnt] &
1657 BIT(3))
1658 pwrinfo24g->cck_diff[rfpath][txcnt] |=
1659 0xF0;
1660 }
1661 eeaddr++;
1662 }
1663
1664 /*5G default value*/
1665 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
1666 pwrinfo5g->index_bw40_base[rfpath][group] =
1667 hwinfo[eeaddr++];
1668 if (pwrinfo5g->index_bw40_base[rfpath][group] == 0xFF)
1669 pwrinfo5g->index_bw40_base[rfpath][group] =
1670 0xFE;
1671 }
1672
1673 pwrinfo5g->bw40_diff[rfpath][0] = 0;
1674
1675 if (hwinfo[eeaddr] == 0xFF) {
1676 pwrinfo5g->bw20_diff[rfpath][0] = 0;
1677 } else {
1678 pwrinfo5g->bw20_diff[rfpath][0] =
1679 (hwinfo[eeaddr]&0xf0)>>4;
1680 if (pwrinfo5g->bw20_diff[rfpath][0] & BIT(3))
1681 pwrinfo5g->bw20_diff[rfpath][0] |= 0xF0;
1682 }
1683
1684 if (hwinfo[eeaddr] == 0xFF) {
1685 pwrinfo5g->ofdm_diff[rfpath][0] = 0x04;
1686 } else {
1687 pwrinfo5g->ofdm_diff[rfpath][0] = (hwinfo[eeaddr]&0x0f);
1688 if (pwrinfo5g->ofdm_diff[rfpath][0] & BIT(3))
1689 pwrinfo5g->ofdm_diff[rfpath][0] |= 0xF0;
1690 }
1691 eeaddr++;
1692 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1693 if (hwinfo[eeaddr] == 0xFF) {
1694 pwrinfo5g->bw40_diff[rfpath][txcnt] = 0xFE;
1695 } else {
1696 pwrinfo5g->bw40_diff[rfpath][txcnt] =
1697 (hwinfo[eeaddr]&0xf0)>>4;
1698 if (pwrinfo5g->bw40_diff[rfpath][txcnt] &
1699 BIT(3))
1700 pwrinfo5g->bw40_diff[rfpath][txcnt] |=
1701 0xF0;
1702 }
1703
1704 if (hwinfo[eeaddr] == 0xFF) {
1705 pwrinfo5g->bw20_diff[rfpath][txcnt] = 0xFE;
1706 } else {
1707 pwrinfo5g->bw20_diff[rfpath][txcnt] =
1708 (hwinfo[eeaddr]&0x0f);
1709 if (pwrinfo5g->bw20_diff[rfpath][txcnt] &
1710 BIT(3))
1711 pwrinfo5g->bw20_diff[rfpath][txcnt] |=
1712 0xF0;
1713 }
1714 eeaddr++;
1715 }
1716
1717 if (hwinfo[eeaddr] == 0xFF) {
1718 pwrinfo5g->ofdm_diff[rfpath][1] = 0xFE;
1719 pwrinfo5g->ofdm_diff[rfpath][2] = 0xFE;
1720 } else {
1721 pwrinfo5g->ofdm_diff[rfpath][1] =
1722 (hwinfo[eeaddr]&0xf0)>>4;
1723 pwrinfo5g->ofdm_diff[rfpath][2] =
1724 (hwinfo[eeaddr]&0x0f);
1725 }
1726 eeaddr++;
1727
1728 if (hwinfo[eeaddr] == 0xFF)
1729 pwrinfo5g->ofdm_diff[rfpath][3] = 0xFE;
1730 else
1731 pwrinfo5g->ofdm_diff[rfpath][3] = (hwinfo[eeaddr]&0x0f);
1732 eeaddr++;
1733
1734 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1735 if (pwrinfo5g->ofdm_diff[rfpath][txcnt] == 0xFF)
1736 pwrinfo5g->ofdm_diff[rfpath][txcnt] = 0xFE;
1737 else if (pwrinfo5g->ofdm_diff[rfpath][txcnt] & BIT(3))
1738 pwrinfo5g->ofdm_diff[rfpath][txcnt] |= 0xF0;
1739 }
1740 }
1741 }
1742
_rtl88ee_read_txpower_info_from_hwpg(struct ieee80211_hw * hw,bool autoload_fail,u8 * hwinfo)1743 static void _rtl88ee_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1744 bool autoload_fail,
1745 u8 *hwinfo)
1746 {
1747 struct rtl_priv *rtlpriv = rtl_priv(hw);
1748 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1749 struct txpower_info_2g pwrinfo24g;
1750 struct txpower_info_5g pwrinfo5g;
1751 u8 rf_path, index;
1752 u8 i;
1753
1754 read_power_value_fromprom(hw, &pwrinfo24g,
1755 &pwrinfo5g, autoload_fail, hwinfo);
1756
1757 for (rf_path = 0; rf_path < 2; rf_path++) {
1758 for (i = 0; i < 14; i++) {
1759 index = _rtl88e_get_chnl_group(i+1);
1760
1761 rtlefuse->txpwrlevel_cck[rf_path][i] =
1762 pwrinfo24g.index_cck_base[rf_path][index];
1763 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1764 pwrinfo24g.index_bw40_base[rf_path][index];
1765 rtlefuse->txpwr_ht20diff[rf_path][i] =
1766 pwrinfo24g.bw20_diff[rf_path][0];
1767 rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
1768 pwrinfo24g.ofdm_diff[rf_path][0];
1769 }
1770
1771 for (i = 0; i < 14; i++) {
1772 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1773 "RF(%d)-Ch(%d) [CCK / HT40_1S ] = [0x%x / 0x%x ]\n",
1774 rf_path, i,
1775 rtlefuse->txpwrlevel_cck[rf_path][i],
1776 rtlefuse->txpwrlevel_ht40_1s[rf_path][i]);
1777 }
1778 }
1779
1780 if (!autoload_fail)
1781 rtlefuse->eeprom_thermalmeter =
1782 hwinfo[EEPROM_THERMAL_METER_88E];
1783 else
1784 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1785
1786 if (rtlefuse->eeprom_thermalmeter == 0xff || autoload_fail) {
1787 rtlefuse->apk_thermalmeterignore = true;
1788 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1789 }
1790
1791 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1792 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1793 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1794
1795 if (!autoload_fail) {
1796 rtlefuse->eeprom_regulatory =
1797 hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x07;/*bit0~2*/
1798 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
1799 rtlefuse->eeprom_regulatory = 0;
1800 } else {
1801 rtlefuse->eeprom_regulatory = 0;
1802 }
1803 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1804 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1805 }
1806
_rtl88ee_read_adapter_info(struct ieee80211_hw * hw)1807 static void _rtl88ee_read_adapter_info(struct ieee80211_hw *hw)
1808 {
1809 struct rtl_priv *rtlpriv = rtl_priv(hw);
1810 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1811 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1812 int params[] = {RTL8188E_EEPROM_ID, EEPROM_VID, EEPROM_DID,
1813 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
1814 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
1815 COUNTRY_CODE_WORLD_WIDE_13};
1816 u8 *hwinfo;
1817
1818 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
1819 if (!hwinfo)
1820 return;
1821
1822 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
1823 goto exit;
1824
1825 if (rtlefuse->eeprom_oemid == 0xFF)
1826 rtlefuse->eeprom_oemid = 0;
1827
1828 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
1829 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
1830 /* set channel plan from efuse */
1831 rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
1832 /*tx power*/
1833 _rtl88ee_read_txpower_info_from_hwpg(hw,
1834 rtlefuse->autoload_failflag,
1835 hwinfo);
1836 rtlefuse->txpwr_fromeprom = true;
1837
1838 rtl8188ee_read_bt_coexist_info_from_hwpg(hw,
1839 rtlefuse->autoload_failflag,
1840 hwinfo);
1841
1842 /*board type*/
1843 rtlefuse->board_type =
1844 ((hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0xE0) >> 5);
1845 rtlhal->board_type = rtlefuse->board_type;
1846 /*Wake on wlan*/
1847 rtlefuse->wowlan_enable =
1848 ((hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & 0x40) >> 6);
1849 /*parse xtal*/
1850 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_88E];
1851 if (hwinfo[EEPROM_XTAL_88E])
1852 rtlefuse->crystalcap = 0x20;
1853 /*antenna diversity*/
1854 rtlefuse->antenna_div_cfg =
1855 (hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x18) >> 3;
1856 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
1857 rtlefuse->antenna_div_cfg = 0;
1858 if (rtlpriv->btcoexist.eeprom_bt_coexist != 0 &&
1859 rtlpriv->btcoexist.eeprom_bt_ant_num == ANT_X1)
1860 rtlefuse->antenna_div_cfg = 0;
1861
1862 rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
1863 if (rtlefuse->antenna_div_type == 0xFF)
1864 rtlefuse->antenna_div_type = 0x01;
1865 if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV ||
1866 rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
1867 rtlefuse->antenna_div_cfg = 1;
1868
1869 if (rtlhal->oem_id == RT_CID_DEFAULT) {
1870 switch (rtlefuse->eeprom_oemid) {
1871 case EEPROM_CID_DEFAULT:
1872 if (rtlefuse->eeprom_did == 0x8179) {
1873 if (rtlefuse->eeprom_svid == 0x1025) {
1874 rtlhal->oem_id = RT_CID_819X_ACER;
1875 } else if ((rtlefuse->eeprom_svid == 0x10EC &&
1876 rtlefuse->eeprom_smid == 0x0179) ||
1877 (rtlefuse->eeprom_svid == 0x17AA &&
1878 rtlefuse->eeprom_smid == 0x0179)) {
1879 rtlhal->oem_id = RT_CID_819X_LENOVO;
1880 } else if (rtlefuse->eeprom_svid == 0x103c &&
1881 rtlefuse->eeprom_smid == 0x197d) {
1882 rtlhal->oem_id = RT_CID_819X_HP;
1883 } else {
1884 rtlhal->oem_id = RT_CID_DEFAULT;
1885 }
1886 } else {
1887 rtlhal->oem_id = RT_CID_DEFAULT;
1888 }
1889 break;
1890 case EEPROM_CID_TOSHIBA:
1891 rtlhal->oem_id = RT_CID_TOSHIBA;
1892 break;
1893 case EEPROM_CID_QMI:
1894 rtlhal->oem_id = RT_CID_819X_QMI;
1895 break;
1896 case EEPROM_CID_WHQL:
1897 default:
1898 rtlhal->oem_id = RT_CID_DEFAULT;
1899 break;
1900
1901 }
1902 }
1903 exit:
1904 kfree(hwinfo);
1905 }
1906
_rtl88ee_hal_customized_behavior(struct ieee80211_hw * hw)1907 static void _rtl88ee_hal_customized_behavior(struct ieee80211_hw *hw)
1908 {
1909 struct rtl_priv *rtlpriv = rtl_priv(hw);
1910 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1911
1912 rtlpriv->ledctl.led_opendrain = true;
1913
1914 switch (rtlhal->oem_id) {
1915 case RT_CID_819X_HP:
1916 rtlpriv->ledctl.led_opendrain = true;
1917 break;
1918 case RT_CID_819X_LENOVO:
1919 case RT_CID_DEFAULT:
1920 case RT_CID_TOSHIBA:
1921 case RT_CID_CCX:
1922 case RT_CID_819X_ACER:
1923 case RT_CID_WHQL:
1924 default:
1925 break;
1926 }
1927 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1928 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1929 }
1930
rtl88ee_read_eeprom_info(struct ieee80211_hw * hw)1931 void rtl88ee_read_eeprom_info(struct ieee80211_hw *hw)
1932 {
1933 struct rtl_priv *rtlpriv = rtl_priv(hw);
1934 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1935 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1936 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1937 u8 tmp_u1b;
1938
1939 rtlhal->version = _rtl88ee_read_chip_version(hw);
1940 if (get_rf_type(rtlphy) == RF_1T1R)
1941 rtlpriv->dm.rfpath_rxenable[0] = true;
1942 else
1943 rtlpriv->dm.rfpath_rxenable[0] =
1944 rtlpriv->dm.rfpath_rxenable[1] = true;
1945 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1946 rtlhal->version);
1947 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1948 if (tmp_u1b & BIT(4)) {
1949 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1950 rtlefuse->epromtype = EEPROM_93C46;
1951 } else {
1952 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1953 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1954 }
1955 if (tmp_u1b & BIT(5)) {
1956 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1957 rtlefuse->autoload_failflag = false;
1958 _rtl88ee_read_adapter_info(hw);
1959 } else {
1960 pr_err("Autoload ERR!!\n");
1961 }
1962 _rtl88ee_hal_customized_behavior(hw);
1963 }
1964
rtl88ee_update_hal_rate_table(struct ieee80211_hw * hw,struct ieee80211_sta * sta)1965 static void rtl88ee_update_hal_rate_table(struct ieee80211_hw *hw,
1966 struct ieee80211_sta *sta)
1967 {
1968 struct rtl_priv *rtlpriv = rtl_priv(hw);
1969 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1970 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1971 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1972 u32 ratr_value;
1973 u8 ratr_index = 0;
1974 u8 b_nmode = mac->ht_enable;
1975 /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
1976 u16 shortgi_rate;
1977 u32 tmp_ratr_value;
1978 u8 curtxbw_40mhz = mac->bw_40;
1979 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1980 1 : 0;
1981 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1982 1 : 0;
1983 enum wireless_mode wirelessmode = mac->mode;
1984 u32 ratr_mask;
1985
1986 if (rtlhal->current_bandtype == BAND_ON_5G)
1987 ratr_value = sta->supp_rates[1] << 4;
1988 else
1989 ratr_value = sta->supp_rates[0];
1990 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1991 ratr_value = 0xfff;
1992 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1993 sta->ht_cap.mcs.rx_mask[0] << 12);
1994 switch (wirelessmode) {
1995 case WIRELESS_MODE_B:
1996 if (ratr_value & 0x0000000c)
1997 ratr_value &= 0x0000000d;
1998 else
1999 ratr_value &= 0x0000000f;
2000 break;
2001 case WIRELESS_MODE_G:
2002 ratr_value &= 0x00000FF5;
2003 break;
2004 case WIRELESS_MODE_N_24G:
2005 case WIRELESS_MODE_N_5G:
2006 b_nmode = 1;
2007 if (get_rf_type(rtlphy) == RF_1T2R ||
2008 get_rf_type(rtlphy) == RF_1T1R)
2009 ratr_mask = 0x000ff005;
2010 else
2011 ratr_mask = 0x0f0ff005;
2012
2013 ratr_value &= ratr_mask;
2014 break;
2015 default:
2016 if (rtlphy->rf_type == RF_1T2R)
2017 ratr_value &= 0x000ff0ff;
2018 else
2019 ratr_value &= 0x0f0ff0ff;
2020
2021 break;
2022 }
2023
2024 if ((rtlpriv->btcoexist.bt_coexistence) &&
2025 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
2026 (rtlpriv->btcoexist.bt_cur_state) &&
2027 (rtlpriv->btcoexist.bt_ant_isolation) &&
2028 ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
2029 (rtlpriv->btcoexist.bt_service == BT_BUSY)))
2030 ratr_value &= 0x0fffcfc0;
2031 else
2032 ratr_value &= 0x0FFFFFFF;
2033
2034 if (b_nmode &&
2035 ((curtxbw_40mhz && curshortgi_40mhz) ||
2036 (!curtxbw_40mhz && curshortgi_20mhz))) {
2037 ratr_value |= 0x10000000;
2038 tmp_ratr_value = (ratr_value >> 12);
2039
2040 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2041 if ((1 << shortgi_rate) & tmp_ratr_value)
2042 break;
2043 }
2044
2045 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2046 (shortgi_rate << 4) | (shortgi_rate);
2047 }
2048
2049 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2050
2051 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
2052 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
2053 }
2054
rtl88ee_update_hal_rate_mask(struct ieee80211_hw * hw,struct ieee80211_sta * sta,u8 rssi_level,bool update_bw)2055 static void rtl88ee_update_hal_rate_mask(struct ieee80211_hw *hw,
2056 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
2057 {
2058 struct rtl_priv *rtlpriv = rtl_priv(hw);
2059 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2060 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2061 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2062 struct rtl_sta_info *sta_entry = NULL;
2063 u32 ratr_bitmap;
2064 u8 ratr_index;
2065 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
2066 ? 1 : 0;
2067 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2068 1 : 0;
2069 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2070 1 : 0;
2071 enum wireless_mode wirelessmode = 0;
2072 bool b_shortgi = false;
2073 u8 rate_mask[5];
2074 u8 macid = 0;
2075 /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
2076
2077 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2078 wirelessmode = sta_entry->wireless_mode;
2079 if (mac->opmode == NL80211_IFTYPE_STATION ||
2080 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2081 curtxbw_40mhz = mac->bw_40;
2082 else if (mac->opmode == NL80211_IFTYPE_AP ||
2083 mac->opmode == NL80211_IFTYPE_ADHOC)
2084 macid = sta->aid + 1;
2085
2086 if (rtlhal->current_bandtype == BAND_ON_5G)
2087 ratr_bitmap = sta->supp_rates[1] << 4;
2088 else
2089 ratr_bitmap = sta->supp_rates[0];
2090 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2091 ratr_bitmap = 0xfff;
2092 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2093 sta->ht_cap.mcs.rx_mask[0] << 12);
2094 switch (wirelessmode) {
2095 case WIRELESS_MODE_B:
2096 ratr_index = RATR_INX_WIRELESS_B;
2097 if (ratr_bitmap & 0x0000000c)
2098 ratr_bitmap &= 0x0000000d;
2099 else
2100 ratr_bitmap &= 0x0000000f;
2101 break;
2102 case WIRELESS_MODE_G:
2103 ratr_index = RATR_INX_WIRELESS_GB;
2104
2105 if (rssi_level == 1)
2106 ratr_bitmap &= 0x00000f00;
2107 else if (rssi_level == 2)
2108 ratr_bitmap &= 0x00000ff0;
2109 else
2110 ratr_bitmap &= 0x00000ff5;
2111 break;
2112 case WIRELESS_MODE_N_24G:
2113 case WIRELESS_MODE_N_5G:
2114 ratr_index = RATR_INX_WIRELESS_NGB;
2115 if (rtlphy->rf_type == RF_1T2R ||
2116 rtlphy->rf_type == RF_1T1R) {
2117 if (curtxbw_40mhz) {
2118 if (rssi_level == 1)
2119 ratr_bitmap &= 0x000f0000;
2120 else if (rssi_level == 2)
2121 ratr_bitmap &= 0x000ff000;
2122 else
2123 ratr_bitmap &= 0x000ff015;
2124 } else {
2125 if (rssi_level == 1)
2126 ratr_bitmap &= 0x000f0000;
2127 else if (rssi_level == 2)
2128 ratr_bitmap &= 0x000ff000;
2129 else
2130 ratr_bitmap &= 0x000ff005;
2131 }
2132 } else {
2133 if (curtxbw_40mhz) {
2134 if (rssi_level == 1)
2135 ratr_bitmap &= 0x0f8f0000;
2136 else if (rssi_level == 2)
2137 ratr_bitmap &= 0x0f8ff000;
2138 else
2139 ratr_bitmap &= 0x0f8ff015;
2140 } else {
2141 if (rssi_level == 1)
2142 ratr_bitmap &= 0x0f8f0000;
2143 else if (rssi_level == 2)
2144 ratr_bitmap &= 0x0f8ff000;
2145 else
2146 ratr_bitmap &= 0x0f8ff005;
2147 }
2148 }
2149 /*}*/
2150
2151 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2152 (!curtxbw_40mhz && curshortgi_20mhz)) {
2153
2154 if (macid == 0)
2155 b_shortgi = true;
2156 else if (macid == 1)
2157 b_shortgi = false;
2158 }
2159 break;
2160 default:
2161 ratr_index = RATR_INX_WIRELESS_NGB;
2162
2163 if (rtlphy->rf_type == RF_1T2R)
2164 ratr_bitmap &= 0x000ff0ff;
2165 else
2166 ratr_bitmap &= 0x0f0ff0ff;
2167 break;
2168 }
2169 sta_entry->ratr_index = ratr_index;
2170
2171 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
2172 "ratr_bitmap :%x\n", ratr_bitmap);
2173 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2174 (ratr_index << 28);
2175 rate_mask[4] = macid | (b_shortgi ? 0x20 : 0x00) | 0x80;
2176 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
2177 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n",
2178 ratr_index, ratr_bitmap,
2179 rate_mask[0], rate_mask[1],
2180 rate_mask[2], rate_mask[3],
2181 rate_mask[4]);
2182 rtl88e_fill_h2c_cmd(hw, H2C_88E_RA_MASK, 5, rate_mask);
2183 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
2184 }
2185
rtl88ee_update_hal_rate_tbl(struct ieee80211_hw * hw,struct ieee80211_sta * sta,u8 rssi_level,bool update_bw)2186 void rtl88ee_update_hal_rate_tbl(struct ieee80211_hw *hw,
2187 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
2188 {
2189 struct rtl_priv *rtlpriv = rtl_priv(hw);
2190
2191 if (rtlpriv->dm.useramask)
2192 rtl88ee_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
2193 else
2194 rtl88ee_update_hal_rate_table(hw, sta);
2195 }
2196
rtl88ee_update_channel_access_setting(struct ieee80211_hw * hw)2197 void rtl88ee_update_channel_access_setting(struct ieee80211_hw *hw)
2198 {
2199 struct rtl_priv *rtlpriv = rtl_priv(hw);
2200 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2201 u16 sifs_timer;
2202
2203 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time);
2204 if (!mac->ht_enable)
2205 sifs_timer = 0x0a0a;
2206 else
2207 sifs_timer = 0x0e0e;
2208 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2209 }
2210
rtl88ee_gpio_radio_on_off_checking(struct ieee80211_hw * hw,u8 * valid)2211 bool rtl88ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2212 {
2213 struct rtl_priv *rtlpriv = rtl_priv(hw);
2214 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2215 enum rf_pwrstate e_rfpowerstate_toset;
2216 u32 u4tmp;
2217 bool b_actuallyset = false;
2218
2219 if (rtlpriv->rtlhal.being_init_adapter)
2220 return false;
2221
2222 if (ppsc->swrf_processing)
2223 return false;
2224
2225 spin_lock(&rtlpriv->locks.rf_ps_lock);
2226 if (ppsc->rfchange_inprogress) {
2227 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2228 return false;
2229 } else {
2230 ppsc->rfchange_inprogress = true;
2231 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2232 }
2233
2234 u4tmp = rtl_read_dword(rtlpriv, REG_GPIO_OUTPUT);
2235 e_rfpowerstate_toset = (u4tmp & BIT(31)) ? ERFON : ERFOFF;
2236
2237 if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) {
2238 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2239 "GPIOChangeRF - HW Radio ON, RF ON\n");
2240
2241 e_rfpowerstate_toset = ERFON;
2242 ppsc->hwradiooff = false;
2243 b_actuallyset = true;
2244 } else if ((!ppsc->hwradiooff) &&
2245 (e_rfpowerstate_toset == ERFOFF)) {
2246 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2247 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
2248
2249 e_rfpowerstate_toset = ERFOFF;
2250 ppsc->hwradiooff = true;
2251 b_actuallyset = true;
2252 }
2253
2254 if (b_actuallyset) {
2255 spin_lock(&rtlpriv->locks.rf_ps_lock);
2256 ppsc->rfchange_inprogress = false;
2257 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2258 } else {
2259 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2260 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2261
2262 spin_lock(&rtlpriv->locks.rf_ps_lock);
2263 ppsc->rfchange_inprogress = false;
2264 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2265 }
2266
2267 *valid = 1;
2268 return !ppsc->hwradiooff;
2269
2270 }
2271
rtl88ee_set_key(struct ieee80211_hw * hw,u32 key_index,u8 * p_macaddr,bool is_group,u8 enc_algo,bool is_wepkey,bool clear_all)2272 void rtl88ee_set_key(struct ieee80211_hw *hw, u32 key_index,
2273 u8 *p_macaddr, bool is_group, u8 enc_algo,
2274 bool is_wepkey, bool clear_all)
2275 {
2276 struct rtl_priv *rtlpriv = rtl_priv(hw);
2277 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2278 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2279 u8 *macaddr = p_macaddr;
2280 u32 entry_id = 0;
2281 bool is_pairwise = false;
2282 static u8 cam_const_addr[4][6] = {
2283 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2284 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2285 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2286 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2287 };
2288 static u8 cam_const_broad[] = {
2289 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2290 };
2291
2292 if (clear_all) {
2293 u8 idx = 0;
2294 u8 cam_offset = 0;
2295 u8 clear_number = 5;
2296
2297 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2298
2299 for (idx = 0; idx < clear_number; idx++) {
2300 rtl_cam_mark_invalid(hw, cam_offset + idx);
2301 rtl_cam_empty_entry(hw, cam_offset + idx);
2302
2303 if (idx < 5) {
2304 memset(rtlpriv->sec.key_buf[idx], 0,
2305 MAX_KEY_LEN);
2306 rtlpriv->sec.key_len[idx] = 0;
2307 }
2308 }
2309
2310 } else {
2311 switch (enc_algo) {
2312 case WEP40_ENCRYPTION:
2313 enc_algo = CAM_WEP40;
2314 break;
2315 case WEP104_ENCRYPTION:
2316 enc_algo = CAM_WEP104;
2317 break;
2318 case TKIP_ENCRYPTION:
2319 enc_algo = CAM_TKIP;
2320 break;
2321 case AESCCMP_ENCRYPTION:
2322 enc_algo = CAM_AES;
2323 break;
2324 default:
2325 pr_err("switch case %#x not processed\n",
2326 enc_algo);
2327 enc_algo = CAM_TKIP;
2328 break;
2329 }
2330
2331 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2332 macaddr = cam_const_addr[key_index];
2333 entry_id = key_index;
2334 } else {
2335 if (is_group) {
2336 macaddr = cam_const_broad;
2337 entry_id = key_index;
2338 } else {
2339 if (mac->opmode == NL80211_IFTYPE_AP ||
2340 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2341 entry_id =
2342 rtl_cam_get_free_entry(hw, p_macaddr);
2343 if (entry_id >= TOTAL_CAM_ENTRY) {
2344 pr_err("Can not find free hw security cam entry\n");
2345 return;
2346 }
2347 } else {
2348 entry_id = CAM_PAIRWISE_KEY_POSITION;
2349 }
2350 key_index = PAIRWISE_KEYIDX;
2351 is_pairwise = true;
2352 }
2353 }
2354
2355 if (rtlpriv->sec.key_len[key_index] == 0) {
2356 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2357 "delete one entry, entry_id is %d\n",
2358 entry_id);
2359 if (mac->opmode == NL80211_IFTYPE_AP ||
2360 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2361 rtl_cam_del_entry(hw, p_macaddr);
2362 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2363 } else {
2364 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2365 "add one entry\n");
2366 if (is_pairwise) {
2367 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2368 "set Pairwise key\n");
2369
2370 rtl_cam_add_one_entry(hw, macaddr, key_index,
2371 entry_id, enc_algo,
2372 CAM_CONFIG_NO_USEDK,
2373 rtlpriv->sec.key_buf[key_index]);
2374 } else {
2375 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2376 "set group key\n");
2377
2378 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2379 rtl_cam_add_one_entry(hw,
2380 rtlefuse->dev_addr,
2381 PAIRWISE_KEYIDX,
2382 CAM_PAIRWISE_KEY_POSITION,
2383 enc_algo,
2384 CAM_CONFIG_NO_USEDK,
2385 rtlpriv->sec.key_buf
2386 [entry_id]);
2387 }
2388
2389 rtl_cam_add_one_entry(hw, macaddr, key_index,
2390 entry_id, enc_algo,
2391 CAM_CONFIG_NO_USEDK,
2392 rtlpriv->sec.key_buf[entry_id]);
2393 }
2394
2395 }
2396 }
2397 }
2398
rtl8188ee_bt_var_init(struct ieee80211_hw * hw)2399 static void rtl8188ee_bt_var_init(struct ieee80211_hw *hw)
2400 {
2401 struct rtl_priv *rtlpriv = rtl_priv(hw);
2402
2403 rtlpriv->btcoexist.bt_coexistence =
2404 rtlpriv->btcoexist.eeprom_bt_coexist;
2405 rtlpriv->btcoexist.bt_ant_num = rtlpriv->btcoexist.eeprom_bt_ant_num;
2406 rtlpriv->btcoexist.bt_coexist_type = rtlpriv->btcoexist.eeprom_bt_type;
2407
2408 if (rtlpriv->btcoexist.reg_bt_iso == 2)
2409 rtlpriv->btcoexist.bt_ant_isolation =
2410 rtlpriv->btcoexist.eeprom_bt_ant_isol;
2411 else
2412 rtlpriv->btcoexist.bt_ant_isolation =
2413 rtlpriv->btcoexist.reg_bt_iso;
2414
2415 rtlpriv->btcoexist.bt_radio_shared_type =
2416 rtlpriv->btcoexist.eeprom_bt_radio_shared;
2417
2418 if (rtlpriv->btcoexist.bt_coexistence) {
2419 if (rtlpriv->btcoexist.reg_bt_sco == 1)
2420 rtlpriv->btcoexist.bt_service = BT_OTHER_ACTION;
2421 else if (rtlpriv->btcoexist.reg_bt_sco == 2)
2422 rtlpriv->btcoexist.bt_service = BT_SCO;
2423 else if (rtlpriv->btcoexist.reg_bt_sco == 4)
2424 rtlpriv->btcoexist.bt_service = BT_BUSY;
2425 else if (rtlpriv->btcoexist.reg_bt_sco == 5)
2426 rtlpriv->btcoexist.bt_service = BT_OTHERBUSY;
2427 else
2428 rtlpriv->btcoexist.bt_service = BT_IDLE;
2429
2430 rtlpriv->btcoexist.bt_edca_ul = 0;
2431 rtlpriv->btcoexist.bt_edca_dl = 0;
2432 rtlpriv->btcoexist.bt_rssi_state = 0xff;
2433 }
2434 }
2435
rtl8188ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw * hw,bool auto_load_fail,u8 * hwinfo)2436 void rtl8188ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2437 bool auto_load_fail, u8 *hwinfo)
2438 {
2439 struct rtl_priv *rtlpriv = rtl_priv(hw);
2440 u8 value;
2441
2442 if (!auto_load_fail) {
2443 rtlpriv->btcoexist.eeprom_bt_coexist =
2444 ((hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & 0xe0) >> 5);
2445 if (hwinfo[EEPROM_RF_FEATURE_OPTION_88E] == 0xFF)
2446 rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2447 value = hwinfo[EEPROM_RF_BT_SETTING_88E];
2448 rtlpriv->btcoexist.eeprom_bt_type = ((value & 0xe) >> 1);
2449 rtlpriv->btcoexist.eeprom_bt_ant_num = (value & 0x1);
2450 rtlpriv->btcoexist.eeprom_bt_ant_isol = ((value & 0x10) >> 4);
2451 rtlpriv->btcoexist.eeprom_bt_radio_shared =
2452 ((value & 0x20) >> 5);
2453 } else {
2454 rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2455 rtlpriv->btcoexist.eeprom_bt_type = BT_2WIRE;
2456 rtlpriv->btcoexist.eeprom_bt_ant_num = ANT_X2;
2457 rtlpriv->btcoexist.eeprom_bt_ant_isol = 0;
2458 rtlpriv->btcoexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2459 }
2460
2461 rtl8188ee_bt_var_init(hw);
2462 }
2463
rtl8188ee_bt_reg_init(struct ieee80211_hw * hw)2464 void rtl8188ee_bt_reg_init(struct ieee80211_hw *hw)
2465 {
2466 struct rtl_priv *rtlpriv = rtl_priv(hw);
2467
2468 /* 0:Low, 1:High, 2:From Efuse. */
2469 rtlpriv->btcoexist.reg_bt_iso = 2;
2470 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2471 rtlpriv->btcoexist.reg_bt_sco = 3;
2472 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2473 rtlpriv->btcoexist.reg_bt_sco = 0;
2474 }
2475
rtl8188ee_bt_hw_init(struct ieee80211_hw * hw)2476 void rtl8188ee_bt_hw_init(struct ieee80211_hw *hw)
2477 {
2478 struct rtl_priv *rtlpriv = rtl_priv(hw);
2479 struct rtl_phy *rtlphy = &rtlpriv->phy;
2480 u8 u1_tmp;
2481
2482 if (rtlpriv->btcoexist.bt_coexistence &&
2483 ((rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) ||
2484 rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC8)) {
2485 if (rtlpriv->btcoexist.bt_ant_isolation)
2486 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2487
2488 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) & BIT(0);
2489 u1_tmp = u1_tmp |
2490 ((rtlpriv->btcoexist.bt_ant_isolation == 1) ?
2491 0 : BIT((1)) |
2492 ((rtlpriv->btcoexist.bt_service == BT_SCO) ?
2493 0 : BIT(2)));
2494 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2495
2496 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2497 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2498 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2499
2500 /* Config to 1T1R. */
2501 if (rtlphy->rf_type == RF_1T1R) {
2502 u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2503 u1_tmp &= ~(BIT(1));
2504 rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2505
2506 u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2507 u1_tmp &= ~(BIT(1));
2508 rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2509 }
2510 }
2511 }
2512
rtl88ee_suspend(struct ieee80211_hw * hw)2513 void rtl88ee_suspend(struct ieee80211_hw *hw)
2514 {
2515 }
2516
rtl88ee_resume(struct ieee80211_hw * hw)2517 void rtl88ee_resume(struct ieee80211_hw *hw)
2518 {
2519 }
2520
