1 // SPDX-License-Identifier: GPL-2.0
2 /******************************************************************************
3 *
4 * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
5 *
6 ******************************************************************************/
7 #define _SDIO_HALINIT_C_
8
9 #include <drv_types.h>
10 #include <rtw_debug.h>
11 #include <rtl8723b_hal.h>
12
13 #include "hal_com_h2c.h"
14 /*
15 * Description:
16 *Call power on sequence to enable card
17 *
18 * Return:
19 *_SUCCESS enable success
20 *_FAIL enable fail
21 */
CardEnable(struct adapter * padapter)22 static u8 CardEnable(struct adapter *padapter)
23 {
24 u8 bMacPwrCtrlOn;
25 u8 ret = _FAIL;
26
27
28 rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
29 if (bMacPwrCtrlOn == false) {
30 /* RSV_CTRL 0x1C[7:0] = 0x00 */
31 /* unlock ISO/CLK/Power control register */
32 rtw_write8(padapter, REG_RSV_CTRL, 0x0);
33
34 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_card_enable_flow);
35 if (ret == _SUCCESS) {
36 u8 bMacPwrCtrlOn = true;
37 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
38 }
39 } else
40 ret = _SUCCESS;
41
42 return ret;
43 }
44
45 #ifdef CONFIG_GPIO_WAKEUP
46 /* we set it high under init and fw will */
47 /* give us Low Pulse when host wake up */
HostWakeUpGpioClear(struct adapter * Adapter)48 void HostWakeUpGpioClear(struct adapter *Adapter)
49 {
50 u32 value32;
51
52 value32 = rtw_read32(Adapter, REG_GPIO_PIN_CTRL_2);
53
54 /* set GPIO 12 1 */
55 value32 |= BIT(12);/* 4+8 */
56 /* GPIO 12 out put */
57 value32 |= BIT(20);/* 4+16 */
58
59 rtw_write32(Adapter, REG_GPIO_PIN_CTRL_2, value32);
60 } /* HostWakeUpGpioClear */
61
HalSetOutPutGPIO(struct adapter * padapter,u8 index,u8 OutPutValue)62 void HalSetOutPutGPIO(struct adapter *padapter, u8 index, u8 OutPutValue)
63 {
64 if (index <= 7) {
65 /* config GPIO mode */
66 rtw_write8(padapter, REG_GPIO_PIN_CTRL + 3, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 3) & ~BIT(index));
67
68 /* config GPIO Sel */
69 /* 0: input */
70 /* 1: output */
71 rtw_write8(padapter, REG_GPIO_PIN_CTRL + 2, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 2) | BIT(index));
72
73 /* set output value */
74 if (OutPutValue)
75 rtw_write8(padapter, REG_GPIO_PIN_CTRL + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) | BIT(index));
76 else
77 rtw_write8(padapter, REG_GPIO_PIN_CTRL + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) & ~BIT(index));
78 } else {
79 /* 88C Series: */
80 /* index: 11~8 transform to 3~0 */
81 /* 8723 Series: */
82 /* index: 12~8 transform to 4~0 */
83 index -= 8;
84
85 /* config GPIO mode */
86 rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 3, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 3) & ~BIT(index));
87
88 /* config GPIO Sel */
89 /* 0: input */
90 /* 1: output */
91 rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 2, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 2) | BIT(index));
92
93 /* set output value */
94 if (OutPutValue)
95 rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) | BIT(index));
96 else
97 rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) & ~BIT(index));
98 }
99 }
100 #endif
101
102 static
_InitPowerOn_8723BS(struct adapter * padapter)103 u8 _InitPowerOn_8723BS(struct adapter *padapter)
104 {
105 u8 value8;
106 u16 value16;
107 u32 value32;
108 u8 ret;
109 /* u8 bMacPwrCtrlOn; */
110
111
112 /* all of these MUST be configured before power on */
113 #ifdef CONFIG_EXT_CLK
114 /* Use external crystal(XTAL) */
115 value8 = rtw_read8(padapter, REG_PAD_CTRL1_8723B+2);
116 value8 |= BIT(7);
117 rtw_write8(padapter, REG_PAD_CTRL1_8723B+2, value8);
118
119 /* CLK_REQ High active or Low Active */
120 /* Request GPIO polarity: */
121 /* 0: low active */
122 /* 1: high active */
123 value8 = rtw_read8(padapter, REG_MULTI_FUNC_CTRL+1);
124 value8 |= BIT(5);
125 rtw_write8(padapter, REG_MULTI_FUNC_CTRL+1, value8);
126 #endif /* CONFIG_EXT_CLK */
127
128 /* only cmd52 can be used before power on(card enable) */
129 ret = CardEnable(padapter);
130 if (ret == false) {
131 RT_TRACE(
132 _module_hci_hal_init_c_,
133 _drv_emerg_,
134 ("%s: run power on flow fail\n", __func__)
135 );
136 return _FAIL;
137 }
138
139 /* Radio-Off Pin Trigger */
140 value8 = rtw_read8(padapter, REG_GPIO_INTM+1);
141 value8 |= BIT(1); /* Enable falling edge triggering interrupt */
142 rtw_write8(padapter, REG_GPIO_INTM+1, value8);
143 value8 = rtw_read8(padapter, REG_GPIO_IO_SEL_2+1);
144 value8 |= BIT(1);
145 rtw_write8(padapter, REG_GPIO_IO_SEL_2+1, value8);
146
147 /* Enable power down and GPIO interrupt */
148 value16 = rtw_read16(padapter, REG_APS_FSMCO);
149 value16 |= EnPDN; /* Enable HW power down and RF on */
150 rtw_write16(padapter, REG_APS_FSMCO, value16);
151
152 /* Enable CMD53 R/W Operation */
153 /* bMacPwrCtrlOn = true; */
154 /* rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); */
155
156 rtw_write8(padapter, REG_CR, 0x00);
157 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
158 value16 = rtw_read16(padapter, REG_CR);
159 value16 |= (
160 HCI_TXDMA_EN |
161 HCI_RXDMA_EN |
162 TXDMA_EN |
163 RXDMA_EN |
164 PROTOCOL_EN |
165 SCHEDULE_EN |
166 ENSEC |
167 CALTMR_EN
168 );
169 rtw_write16(padapter, REG_CR, value16);
170
171 rtw_btcoex_PowerOnSetting(padapter);
172
173 /* external switch to S1 */
174 /* 0x38[11] = 0x1 */
175 /* 0x4c[23] = 0x1 */
176 /* 0x64[0] = 0 */
177 value16 = rtw_read16(padapter, REG_PWR_DATA);
178 /* Switch the control of EESK, EECS to RFC for DPDT or Antenna switch */
179 value16 |= BIT(11); /* BIT_EEPRPAD_RFE_CTRL_EN */
180 rtw_write16(padapter, REG_PWR_DATA, value16);
181 /* DBG_8192C("%s: REG_PWR_DATA(0x%x) = 0x%04X\n", __func__, REG_PWR_DATA, rtw_read16(padapter, REG_PWR_DATA)); */
182
183 value32 = rtw_read32(padapter, REG_LEDCFG0);
184 value32 |= BIT(23); /* DPDT_SEL_EN, 1 for SW control */
185 rtw_write32(padapter, REG_LEDCFG0, value32);
186 /* DBG_8192C("%s: REG_LEDCFG0(0x%x) = 0x%08X\n", __func__, REG_LEDCFG0, rtw_read32(padapter, REG_LEDCFG0)); */
187
188 value8 = rtw_read8(padapter, REG_PAD_CTRL1_8723B);
189 value8 &= ~BIT(0); /* BIT_SW_DPDT_SEL_DATA, DPDT_SEL default configuration */
190 rtw_write8(padapter, REG_PAD_CTRL1_8723B, value8);
191 /* DBG_8192C("%s: REG_PAD_CTRL1(0x%x) = 0x%02X\n", __func__, REG_PAD_CTRL1_8723B, rtw_read8(padapter, REG_PAD_CTRL1_8723B)); */
192
193 #ifdef CONFIG_GPIO_WAKEUP
194 HostWakeUpGpioClear(padapter);
195 #endif
196
197 return _SUCCESS;
198 }
199
200 /* Tx Page FIFO threshold */
_init_available_page_threshold(struct adapter * padapter,u8 numHQ,u8 numNQ,u8 numLQ,u8 numPubQ)201 static void _init_available_page_threshold(struct adapter *padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ)
202 {
203 u16 HQ_threshold, NQ_threshold, LQ_threshold;
204
205 HQ_threshold = (numPubQ + numHQ + 1) >> 1;
206 HQ_threshold |= (HQ_threshold<<8);
207
208 NQ_threshold = (numPubQ + numNQ + 1) >> 1;
209 NQ_threshold |= (NQ_threshold<<8);
210
211 LQ_threshold = (numPubQ + numLQ + 1) >> 1;
212 LQ_threshold |= (LQ_threshold<<8);
213
214 rtw_write16(padapter, 0x218, HQ_threshold);
215 rtw_write16(padapter, 0x21A, NQ_threshold);
216 rtw_write16(padapter, 0x21C, LQ_threshold);
217 DBG_8192C("%s(): Enable Tx FIFO Page Threshold H:0x%x, N:0x%x, L:0x%x\n", __func__, HQ_threshold, NQ_threshold, LQ_threshold);
218 }
219
_InitQueueReservedPage(struct adapter * padapter)220 static void _InitQueueReservedPage(struct adapter *padapter)
221 {
222 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
223 struct registry_priv *pregistrypriv = &padapter->registrypriv;
224 u32 numHQ = 0;
225 u32 numLQ = 0;
226 u32 numNQ = 0;
227 u32 numPubQ;
228 u32 value32;
229 u8 value8;
230 bool bWiFiConfig = pregistrypriv->wifi_spec;
231
232 if (pHalData->OutEpQueueSel & TX_SELE_HQ)
233 numHQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_HPQ_8723B : NORMAL_PAGE_NUM_HPQ_8723B;
234
235 if (pHalData->OutEpQueueSel & TX_SELE_LQ)
236 numLQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_LPQ_8723B : NORMAL_PAGE_NUM_LPQ_8723B;
237
238 /* NOTE: This step shall be proceed before writting REG_RQPN. */
239 if (pHalData->OutEpQueueSel & TX_SELE_NQ)
240 numNQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_NPQ_8723B : NORMAL_PAGE_NUM_NPQ_8723B;
241
242 numPubQ = TX_TOTAL_PAGE_NUMBER_8723B - numHQ - numLQ - numNQ;
243
244 value8 = (u8)_NPQ(numNQ);
245 rtw_write8(padapter, REG_RQPN_NPQ, value8);
246
247 /* TX DMA */
248 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
249 rtw_write32(padapter, REG_RQPN, value32);
250
251 rtw_hal_set_sdio_tx_max_length(padapter, numHQ, numNQ, numLQ, numPubQ);
252
253 _init_available_page_threshold(padapter, numHQ, numNQ, numLQ, numPubQ);
254 }
255
_InitTxBufferBoundary(struct adapter * padapter)256 static void _InitTxBufferBoundary(struct adapter *padapter)
257 {
258 struct registry_priv *pregistrypriv = &padapter->registrypriv;
259
260 /* u16 txdmactrl; */
261 u8 txpktbuf_bndy;
262
263 if (!pregistrypriv->wifi_spec) {
264 txpktbuf_bndy = TX_PAGE_BOUNDARY_8723B;
265 } else {
266 /* for WMM */
267 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_8723B;
268 }
269
270 rtw_write8(padapter, REG_TXPKTBUF_BCNQ_BDNY_8723B, txpktbuf_bndy);
271 rtw_write8(padapter, REG_TXPKTBUF_MGQ_BDNY_8723B, txpktbuf_bndy);
272 rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B, txpktbuf_bndy);
273 rtw_write8(padapter, REG_TRXFF_BNDY, txpktbuf_bndy);
274 rtw_write8(padapter, REG_TDECTRL+1, txpktbuf_bndy);
275 }
276
_InitNormalChipRegPriority(struct adapter * Adapter,u16 beQ,u16 bkQ,u16 viQ,u16 voQ,u16 mgtQ,u16 hiQ)277 static void _InitNormalChipRegPriority(
278 struct adapter *Adapter,
279 u16 beQ,
280 u16 bkQ,
281 u16 viQ,
282 u16 voQ,
283 u16 mgtQ,
284 u16 hiQ
285 )
286 {
287 u16 value16 = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
288
289 value16 |=
290 _TXDMA_BEQ_MAP(beQ) |
291 _TXDMA_BKQ_MAP(bkQ) |
292 _TXDMA_VIQ_MAP(viQ) |
293 _TXDMA_VOQ_MAP(voQ) |
294 _TXDMA_MGQ_MAP(mgtQ) |
295 _TXDMA_HIQ_MAP(hiQ);
296
297 rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
298 }
299
_InitNormalChipOneOutEpPriority(struct adapter * Adapter)300 static void _InitNormalChipOneOutEpPriority(struct adapter *Adapter)
301 {
302 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
303
304 u16 value = 0;
305 switch (pHalData->OutEpQueueSel) {
306 case TX_SELE_HQ:
307 value = QUEUE_HIGH;
308 break;
309 case TX_SELE_LQ:
310 value = QUEUE_LOW;
311 break;
312 case TX_SELE_NQ:
313 value = QUEUE_NORMAL;
314 break;
315 default:
316 /* RT_ASSERT(false, ("Shall not reach here!\n")); */
317 break;
318 }
319
320 _InitNormalChipRegPriority(
321 Adapter, value, value, value, value, value, value
322 );
323
324 }
325
_InitNormalChipTwoOutEpPriority(struct adapter * Adapter)326 static void _InitNormalChipTwoOutEpPriority(struct adapter *Adapter)
327 {
328 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
329 struct registry_priv *pregistrypriv = &Adapter->registrypriv;
330 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
331
332
333 u16 valueHi = 0;
334 u16 valueLow = 0;
335
336 switch (pHalData->OutEpQueueSel) {
337 case (TX_SELE_HQ | TX_SELE_LQ):
338 valueHi = QUEUE_HIGH;
339 valueLow = QUEUE_LOW;
340 break;
341 case (TX_SELE_NQ | TX_SELE_LQ):
342 valueHi = QUEUE_NORMAL;
343 valueLow = QUEUE_LOW;
344 break;
345 case (TX_SELE_HQ | TX_SELE_NQ):
346 valueHi = QUEUE_HIGH;
347 valueLow = QUEUE_NORMAL;
348 break;
349 default:
350 /* RT_ASSERT(false, ("Shall not reach here!\n")); */
351 break;
352 }
353
354 if (!pregistrypriv->wifi_spec) {
355 beQ = valueLow;
356 bkQ = valueLow;
357 viQ = valueHi;
358 voQ = valueHi;
359 mgtQ = valueHi;
360 hiQ = valueHi;
361 } else {
362 /* for WMM , CONFIG_OUT_EP_WIFI_MODE */
363 beQ = valueLow;
364 bkQ = valueHi;
365 viQ = valueHi;
366 voQ = valueLow;
367 mgtQ = valueHi;
368 hiQ = valueHi;
369 }
370
371 _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
372
373 }
374
_InitNormalChipThreeOutEpPriority(struct adapter * padapter)375 static void _InitNormalChipThreeOutEpPriority(struct adapter *padapter)
376 {
377 struct registry_priv *pregistrypriv = &padapter->registrypriv;
378 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
379
380 if (!pregistrypriv->wifi_spec) {
381 /* typical setting */
382 beQ = QUEUE_LOW;
383 bkQ = QUEUE_LOW;
384 viQ = QUEUE_NORMAL;
385 voQ = QUEUE_HIGH;
386 mgtQ = QUEUE_HIGH;
387 hiQ = QUEUE_HIGH;
388 } else {
389 /* for WMM */
390 beQ = QUEUE_LOW;
391 bkQ = QUEUE_NORMAL;
392 viQ = QUEUE_NORMAL;
393 voQ = QUEUE_HIGH;
394 mgtQ = QUEUE_HIGH;
395 hiQ = QUEUE_HIGH;
396 }
397 _InitNormalChipRegPriority(padapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
398 }
399
_InitNormalChipQueuePriority(struct adapter * Adapter)400 static void _InitNormalChipQueuePriority(struct adapter *Adapter)
401 {
402 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
403
404 switch (pHalData->OutEpNumber) {
405 case 1:
406 _InitNormalChipOneOutEpPriority(Adapter);
407 break;
408 case 2:
409 _InitNormalChipTwoOutEpPriority(Adapter);
410 break;
411 case 3:
412 _InitNormalChipThreeOutEpPriority(Adapter);
413 break;
414 default:
415 /* RT_ASSERT(false, ("Shall not reach here!\n")); */
416 break;
417 }
418
419
420 }
421
_InitQueuePriority(struct adapter * padapter)422 static void _InitQueuePriority(struct adapter *padapter)
423 {
424 _InitNormalChipQueuePriority(padapter);
425 }
426
_InitPageBoundary(struct adapter * padapter)427 static void _InitPageBoundary(struct adapter *padapter)
428 {
429 /* RX Page Boundary */
430 u16 rxff_bndy = RX_DMA_BOUNDARY_8723B;
431
432 rtw_write16(padapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
433 }
434
_InitTransferPageSize(struct adapter * padapter)435 static void _InitTransferPageSize(struct adapter *padapter)
436 {
437 /* Tx page size is always 128. */
438
439 u8 value8;
440 value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
441 rtw_write8(padapter, REG_PBP, value8);
442 }
443
_InitDriverInfoSize(struct adapter * padapter,u8 drvInfoSize)444 static void _InitDriverInfoSize(struct adapter *padapter, u8 drvInfoSize)
445 {
446 rtw_write8(padapter, REG_RX_DRVINFO_SZ, drvInfoSize);
447 }
448
_InitNetworkType(struct adapter * padapter)449 static void _InitNetworkType(struct adapter *padapter)
450 {
451 u32 value32;
452
453 value32 = rtw_read32(padapter, REG_CR);
454
455 /* TODO: use the other function to set network type */
456 /* value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AD_HOC); */
457 value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
458
459 rtw_write32(padapter, REG_CR, value32);
460 }
461
_InitWMACSetting(struct adapter * padapter)462 static void _InitWMACSetting(struct adapter *padapter)
463 {
464 struct hal_com_data *pHalData;
465 u16 value16;
466
467
468 pHalData = GET_HAL_DATA(padapter);
469
470 pHalData->ReceiveConfig = 0;
471 pHalData->ReceiveConfig |= RCR_APM | RCR_AM | RCR_AB;
472 pHalData->ReceiveConfig |= RCR_CBSSID_DATA | RCR_CBSSID_BCN | RCR_AMF;
473 pHalData->ReceiveConfig |= RCR_HTC_LOC_CTRL;
474 pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC;
475 rtw_write32(padapter, REG_RCR, pHalData->ReceiveConfig);
476
477 /* Accept all multicast address */
478 rtw_write32(padapter, REG_MAR, 0xFFFFFFFF);
479 rtw_write32(padapter, REG_MAR + 4, 0xFFFFFFFF);
480
481 /* Accept all data frames */
482 value16 = 0xFFFF;
483 rtw_write16(padapter, REG_RXFLTMAP2, value16);
484
485 /* 2010.09.08 hpfan */
486 /* Since ADF is removed from RCR, ps-poll will not be indicate to driver, */
487 /* RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. */
488 value16 = 0x400;
489 rtw_write16(padapter, REG_RXFLTMAP1, value16);
490
491 /* Accept all management frames */
492 value16 = 0xFFFF;
493 rtw_write16(padapter, REG_RXFLTMAP0, value16);
494 }
495
_InitAdaptiveCtrl(struct adapter * padapter)496 static void _InitAdaptiveCtrl(struct adapter *padapter)
497 {
498 u16 value16;
499 u32 value32;
500
501 /* Response Rate Set */
502 value32 = rtw_read32(padapter, REG_RRSR);
503 value32 &= ~RATE_BITMAP_ALL;
504 value32 |= RATE_RRSR_CCK_ONLY_1M;
505 rtw_write32(padapter, REG_RRSR, value32);
506
507 /* CF-END Threshold */
508 /* m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1); */
509
510 /* SIFS (used in NAV) */
511 value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
512 rtw_write16(padapter, REG_SPEC_SIFS, value16);
513
514 /* Retry Limit */
515 value16 = _LRL(0x30) | _SRL(0x30);
516 rtw_write16(padapter, REG_RL, value16);
517 }
518
_InitEDCA(struct adapter * padapter)519 static void _InitEDCA(struct adapter *padapter)
520 {
521 /* Set Spec SIFS (used in NAV) */
522 rtw_write16(padapter, REG_SPEC_SIFS, 0x100a);
523 rtw_write16(padapter, REG_MAC_SPEC_SIFS, 0x100a);
524
525 /* Set SIFS for CCK */
526 rtw_write16(padapter, REG_SIFS_CTX, 0x100a);
527
528 /* Set SIFS for OFDM */
529 rtw_write16(padapter, REG_SIFS_TRX, 0x100a);
530
531 /* TXOP */
532 rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x005EA42B);
533 rtw_write32(padapter, REG_EDCA_BK_PARAM, 0x0000A44F);
534 rtw_write32(padapter, REG_EDCA_VI_PARAM, 0x005EA324);
535 rtw_write32(padapter, REG_EDCA_VO_PARAM, 0x002FA226);
536 }
537
_InitRetryFunction(struct adapter * padapter)538 static void _InitRetryFunction(struct adapter *padapter)
539 {
540 u8 value8;
541
542 value8 = rtw_read8(padapter, REG_FWHW_TXQ_CTRL);
543 value8 |= EN_AMPDU_RTY_NEW;
544 rtw_write8(padapter, REG_FWHW_TXQ_CTRL, value8);
545
546 /* Set ACK timeout */
547 rtw_write8(padapter, REG_ACKTO, 0x40);
548 }
549
HalRxAggr8723BSdio(struct adapter * padapter)550 static void HalRxAggr8723BSdio(struct adapter *padapter)
551 {
552 struct registry_priv *pregistrypriv;
553 u8 valueDMATimeout;
554 u8 valueDMAPageCount;
555
556
557 pregistrypriv = &padapter->registrypriv;
558
559 if (pregistrypriv->wifi_spec) {
560 /* 2010.04.27 hpfan */
561 /* Adjust RxAggrTimeout to close to zero disable RxAggr, suggested by designer */
562 /* Timeout value is calculated by 34 / (2^n) */
563 valueDMATimeout = 0x06;
564 valueDMAPageCount = 0x06;
565 } else {
566 /* 20130530, Isaac@SD1 suggest 3 kinds of parameter */
567 /* TX/RX Balance */
568 valueDMATimeout = 0x06;
569 valueDMAPageCount = 0x06;
570 }
571
572 rtw_write8(padapter, REG_RXDMA_AGG_PG_TH+1, valueDMATimeout);
573 rtw_write8(padapter, REG_RXDMA_AGG_PG_TH, valueDMAPageCount);
574 }
575
sdio_AggSettingRxUpdate(struct adapter * padapter)576 static void sdio_AggSettingRxUpdate(struct adapter *padapter)
577 {
578 struct hal_com_data *pHalData;
579 u8 valueDMA;
580 u8 valueRxAggCtrl = 0;
581 u8 aggBurstNum = 3; /* 0:1, 1:2, 2:3, 3:4 */
582 u8 aggBurstSize = 0; /* 0:1K, 1:512Byte, 2:256Byte... */
583
584 pHalData = GET_HAL_DATA(padapter);
585
586 valueDMA = rtw_read8(padapter, REG_TRXDMA_CTRL);
587 valueDMA |= RXDMA_AGG_EN;
588 rtw_write8(padapter, REG_TRXDMA_CTRL, valueDMA);
589
590 valueRxAggCtrl |= RXDMA_AGG_MODE_EN;
591 valueRxAggCtrl |= ((aggBurstNum<<2) & 0x0C);
592 valueRxAggCtrl |= ((aggBurstSize<<4) & 0x30);
593 rtw_write8(padapter, REG_RXDMA_MODE_CTRL_8723B, valueRxAggCtrl);/* RxAggLowThresh = 4*1K */
594 }
595
_initSdioAggregationSetting(struct adapter * padapter)596 static void _initSdioAggregationSetting(struct adapter *padapter)
597 {
598 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
599
600 /* Tx aggregation setting */
601 /* sdio_AggSettingTxUpdate(padapter); */
602
603 /* Rx aggregation setting */
604 HalRxAggr8723BSdio(padapter);
605
606 sdio_AggSettingRxUpdate(padapter);
607
608 /* 201/12/10 MH Add for USB agg mode dynamic switch. */
609 pHalData->UsbRxHighSpeedMode = false;
610 }
611
_InitOperationMode(struct adapter * padapter)612 static void _InitOperationMode(struct adapter *padapter)
613 {
614 struct hal_com_data *pHalData;
615 struct mlme_ext_priv *pmlmeext;
616 u8 regBwOpMode = 0;
617 u32 regRATR = 0, regRRSR = 0;
618
619 pHalData = GET_HAL_DATA(padapter);
620 pmlmeext = &padapter->mlmeextpriv;
621
622 /* 1 This part need to modified according to the rate set we filtered!! */
623 /* */
624 /* Set RRSR, RATR, and REG_BWOPMODE registers */
625 /* */
626 switch (pmlmeext->cur_wireless_mode) {
627 case WIRELESS_MODE_B:
628 regBwOpMode = BW_OPMODE_20MHZ;
629 regRATR = RATE_ALL_CCK;
630 regRRSR = RATE_ALL_CCK;
631 break;
632 case WIRELESS_MODE_A:
633 /* RT_ASSERT(false, ("Error wireless a mode\n")); */
634 break;
635 case WIRELESS_MODE_G:
636 regBwOpMode = BW_OPMODE_20MHZ;
637 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
638 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
639 break;
640 case WIRELESS_MODE_AUTO:
641 regBwOpMode = BW_OPMODE_20MHZ;
642 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
643 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
644 break;
645 case WIRELESS_MODE_N_24G:
646 /* It support CCK rate by default. */
647 /* CCK rate will be filtered out only when associated AP does not support it. */
648 regBwOpMode = BW_OPMODE_20MHZ;
649 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
650 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
651 break;
652 case WIRELESS_MODE_N_5G:
653 /* RT_ASSERT(false, ("Error wireless mode")); */
654 regBwOpMode = BW_OPMODE_5G;
655 regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
656 regRRSR = RATE_ALL_OFDM_AG;
657 break;
658
659 default: /* for MacOSX compiler warning. */
660 break;
661 }
662
663 rtw_write8(padapter, REG_BWOPMODE, regBwOpMode);
664
665 }
666
_InitInterrupt(struct adapter * padapter)667 static void _InitInterrupt(struct adapter *padapter)
668 {
669 /* HISR - turn all off */
670 rtw_write32(padapter, REG_HISR, 0);
671
672 /* HIMR - turn all off */
673 rtw_write32(padapter, REG_HIMR, 0);
674
675 /* */
676 /* Initialize and enable SDIO Host Interrupt. */
677 /* */
678 InitInterrupt8723BSdio(padapter);
679
680 /* */
681 /* Initialize system Host Interrupt. */
682 /* */
683 InitSysInterrupt8723BSdio(padapter);
684 }
685
_InitRFType(struct adapter * padapter)686 static void _InitRFType(struct adapter *padapter)
687 {
688 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
689
690 #if DISABLE_BB_RF
691 pHalData->rf_chip = RF_PSEUDO_11N;
692 return;
693 #endif
694
695 pHalData->rf_chip = RF_6052;
696
697 pHalData->rf_type = RF_1T1R;
698 DBG_8192C("Set RF Chip ID to RF_6052 and RF type to 1T1R.\n");
699 }
700
_RfPowerSave(struct adapter * padapter)701 static void _RfPowerSave(struct adapter *padapter)
702 {
703 /* YJ, TODO */
704 }
705
706 /* */
707 /* 2010/08/09 MH Add for power down check. */
708 /* */
HalDetectPwrDownMode(struct adapter * Adapter)709 static bool HalDetectPwrDownMode(struct adapter *Adapter)
710 {
711 u8 tmpvalue;
712 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
713 struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter);
714
715
716 EFUSE_ShadowRead(Adapter, 1, 0x7B/*EEPROM_RF_OPT3_92C*/, (u32 *)&tmpvalue);
717
718 /* 2010/08/25 MH INF priority > PDN Efuse value. */
719 if (tmpvalue & BIT4 && pwrctrlpriv->reg_pdnmode)
720 pHalData->pwrdown = true;
721 else
722 pHalData->pwrdown = false;
723
724 DBG_8192C("HalDetectPwrDownMode(): PDN =%d\n", pHalData->pwrdown);
725
726 return pHalData->pwrdown;
727 } /* HalDetectPwrDownMode */
728
rtl8723bs_hal_init(struct adapter * padapter)729 static u32 rtl8723bs_hal_init(struct adapter *padapter)
730 {
731 s32 ret;
732 struct hal_com_data *pHalData;
733 struct pwrctrl_priv *pwrctrlpriv;
734 struct registry_priv *pregistrypriv;
735 u32 NavUpper = WiFiNavUpperUs;
736 u8 u1bTmp;
737
738 pHalData = GET_HAL_DATA(padapter);
739 pwrctrlpriv = adapter_to_pwrctl(padapter);
740 pregistrypriv = &padapter->registrypriv;
741
742 if (
743 adapter_to_pwrctl(padapter)->bips_processing == true &&
744 adapter_to_pwrctl(padapter)->pre_ips_type == 0
745 ) {
746 unsigned long start_time;
747 u8 cpwm_orig, cpwm_now;
748 u8 val8, bMacPwrCtrlOn = true;
749
750 DBG_871X("%s: Leaving IPS in FWLPS state\n", __func__);
751
752 /* for polling cpwm */
753 cpwm_orig = 0;
754 rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig);
755
756 /* ser rpwm */
757 val8 = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1);
758 val8 &= 0x80;
759 val8 += 0x80;
760 val8 |= BIT(6);
761 rtw_write8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1, val8);
762 DBG_871X("%s: write rpwm =%02x\n", __func__, val8);
763 adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
764
765 /* do polling cpwm */
766 start_time = jiffies;
767 do {
768
769 mdelay(1);
770
771 rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now);
772 if ((cpwm_orig ^ cpwm_now) & 0x80)
773 break;
774
775 if (jiffies_to_msecs(jiffies - start_time) > 100) {
776 DBG_871X("%s: polling cpwm timeout when leaving IPS in FWLPS state\n", __func__);
777 break;
778 }
779 } while (1);
780
781 rtl8723b_set_FwPwrModeInIPS_cmd(padapter, 0);
782
783 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
784
785 rtw_btcoex_HAL_Initialize(padapter, false);
786
787 return _SUCCESS;
788 }
789
790 #ifdef CONFIG_WOWLAN
791 if (rtw_read8(padapter, REG_MCUFWDL)&BIT7) {
792 u8 reg_val = 0;
793 DBG_871X("+Reset Entry+\n");
794 rtw_write8(padapter, REG_MCUFWDL, 0x00);
795 _8051Reset8723(padapter);
796 /* reset BB */
797 reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN);
798 reg_val &= ~(BIT(0) | BIT(1));
799 rtw_write8(padapter, REG_SYS_FUNC_EN, reg_val);
800 /* reset RF */
801 rtw_write8(padapter, REG_RF_CTRL, 0);
802 /* reset TRX path */
803 rtw_write16(padapter, REG_CR, 0);
804 /* reset MAC, Digital Core */
805 reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
806 reg_val &= ~(BIT(4) | BIT(7));
807 rtw_write8(padapter, REG_SYS_FUNC_EN+1, reg_val);
808 reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
809 reg_val |= BIT(4) | BIT(7);
810 rtw_write8(padapter, REG_SYS_FUNC_EN+1, reg_val);
811 DBG_871X("-Reset Entry-\n");
812 }
813 #endif /* CONFIG_WOWLAN */
814 /* Disable Interrupt first. */
815 /* rtw_hal_disable_interrupt(padapter); */
816
817 ret = _InitPowerOn_8723BS(padapter);
818 if (_FAIL == ret) {
819 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init Power On!\n"));
820 return _FAIL;
821 }
822
823 rtw_write8(padapter, REG_EARLY_MODE_CONTROL, 0);
824
825 ret = rtl8723b_FirmwareDownload(padapter, false);
826 if (ret != _SUCCESS) {
827 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("%s: Download Firmware failed!!\n", __func__));
828 padapter->bFWReady = false;
829 pHalData->fw_ractrl = false;
830 return ret;
831 } else {
832 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("rtl8723bs_hal_init(): Download Firmware Success!!\n"));
833 padapter->bFWReady = true;
834 pHalData->fw_ractrl = true;
835 }
836
837 rtl8723b_InitializeFirmwareVars(padapter);
838
839 /* SIC_Init(padapter); */
840
841 if (pwrctrlpriv->reg_rfoff == true)
842 pwrctrlpriv->rf_pwrstate = rf_off;
843
844 /* 2010/08/09 MH We need to check if we need to turnon or off RF after detecting */
845 /* HW GPIO pin. Before PHY_RFConfig8192C. */
846 HalDetectPwrDownMode(padapter);
847
848 /* Set RF type for BB/RF configuration */
849 _InitRFType(padapter);
850
851 /* Save target channel */
852 /* <Roger_Notes> Current Channel will be updated again later. */
853 pHalData->CurrentChannel = 6;
854
855 #if (HAL_MAC_ENABLE == 1)
856 ret = PHY_MACConfig8723B(padapter);
857 if (ret != _SUCCESS) {
858 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter8192CSdio(): Fail to configure MAC!!\n"));
859 return ret;
860 }
861 #endif
862 /* */
863 /* d. Initialize BB related configurations. */
864 /* */
865 #if (HAL_BB_ENABLE == 1)
866 ret = PHY_BBConfig8723B(padapter);
867 if (ret != _SUCCESS) {
868 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter8192CSdio(): Fail to configure BB!!\n"));
869 return ret;
870 }
871 #endif
872
873 /* If RF is on, we need to init RF. Otherwise, skip the procedure. */
874 /* We need to follow SU method to change the RF cfg.txt. Default disable RF TX/RX mode. */
875 /* if (pHalData->eRFPowerState == eRfOn) */
876 {
877 #if (HAL_RF_ENABLE == 1)
878 ret = PHY_RFConfig8723B(padapter);
879 if (ret != _SUCCESS) {
880 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter8192CSdio(): Fail to configure RF!!\n"));
881 return ret;
882 }
883 #endif
884 }
885
886 /* */
887 /* Joseph Note: Keep RfRegChnlVal for later use. */
888 /* */
889 pHalData->RfRegChnlVal[0] =
890 PHY_QueryRFReg(padapter, (enum RF_PATH)0, RF_CHNLBW, bRFRegOffsetMask);
891 pHalData->RfRegChnlVal[1] =
892 PHY_QueryRFReg(padapter, (enum RF_PATH)1, RF_CHNLBW, bRFRegOffsetMask);
893
894
895 /* if (!pHalData->bMACFuncEnable) { */
896 _InitQueueReservedPage(padapter);
897 _InitTxBufferBoundary(padapter);
898
899 /* init LLT after tx buffer boundary is defined */
900 ret = rtl8723b_InitLLTTable(padapter);
901 if (_SUCCESS != ret) {
902 DBG_8192C("%s: Failed to init LLT Table!\n", __func__);
903 return _FAIL;
904 }
905 /* */
906 _InitQueuePriority(padapter);
907 _InitPageBoundary(padapter);
908 _InitTransferPageSize(padapter);
909
910 /* Get Rx PHY status in order to report RSSI and others. */
911 _InitDriverInfoSize(padapter, DRVINFO_SZ);
912 hal_init_macaddr(padapter);
913 _InitNetworkType(padapter);
914 _InitWMACSetting(padapter);
915 _InitAdaptiveCtrl(padapter);
916 _InitEDCA(padapter);
917 _InitRetryFunction(padapter);
918 _initSdioAggregationSetting(padapter);
919 _InitOperationMode(padapter);
920 rtl8723b_InitBeaconParameters(padapter);
921 _InitInterrupt(padapter);
922 _InitBurstPktLen_8723BS(padapter);
923
924 /* YJ, TODO */
925 rtw_write8(padapter, REG_SECONDARY_CCA_CTRL_8723B, 0x3); /* CCA */
926 rtw_write8(padapter, 0x976, 0); /* hpfan_todo: 2nd CCA related */
927
928 rtw_write16(padapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
929 rtw_write16(padapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
930
931 invalidate_cam_all(padapter);
932
933 rtw_hal_set_chnl_bw(padapter, padapter->registrypriv.channel,
934 CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HAL_PRIME_CHNL_OFFSET_DONT_CARE);
935
936 /* Record original value for template. This is arough data, we can only use the data */
937 /* for power adjust. The value can not be adjustde according to different power!!! */
938 /* pHalData->OriginalCckTxPwrIdx = pHalData->CurrentCckTxPwrIdx; */
939 /* pHalData->OriginalOfdm24GTxPwrIdx = pHalData->CurrentOfdm24GTxPwrIdx; */
940
941 rtl8723b_InitAntenna_Selection(padapter);
942
943 /* */
944 /* Disable BAR, suggested by Scott */
945 /* 2010.04.09 add by hpfan */
946 /* */
947 rtw_write32(padapter, REG_BAR_MODE_CTRL, 0x0201ffff);
948
949 /* HW SEQ CTRL */
950 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
951 rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF);
952
953
954 /* */
955 /* Configure SDIO TxRx Control to enable Rx DMA timer masking. */
956 /* 2010.02.24. */
957 /* */
958 rtw_write32(padapter, SDIO_LOCAL_BASE|SDIO_REG_TX_CTRL, 0);
959
960 _RfPowerSave(padapter);
961
962
963 rtl8723b_InitHalDm(padapter);
964
965 /* DbgPrint("pHalData->DefaultTxPwrDbm = %d\n", pHalData->DefaultTxPwrDbm); */
966
967 /* */
968 /* Update current Tx FIFO page status. */
969 /* */
970 HalQueryTxBufferStatus8723BSdio(padapter);
971 HalQueryTxOQTBufferStatus8723BSdio(padapter);
972 pHalData->SdioTxOQTMaxFreeSpace = pHalData->SdioTxOQTFreeSpace;
973
974 /* Enable MACTXEN/MACRXEN block */
975 u1bTmp = rtw_read8(padapter, REG_CR);
976 u1bTmp |= (MACTXEN | MACRXEN);
977 rtw_write8(padapter, REG_CR, u1bTmp);
978
979 rtw_hal_set_hwreg(padapter, HW_VAR_NAV_UPPER, (u8 *)&NavUpper);
980
981 /* ack for xmit mgmt frames. */
982 rtw_write32(padapter, REG_FWHW_TXQ_CTRL, rtw_read32(padapter, REG_FWHW_TXQ_CTRL)|BIT(12));
983
984 /* pHalData->PreRpwmVal = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_HRPWM1) & 0x80; */
985
986 {
987 pwrctrlpriv->rf_pwrstate = rf_on;
988
989 if (pwrctrlpriv->rf_pwrstate == rf_on) {
990 struct pwrctrl_priv *pwrpriv;
991 unsigned long start_time;
992 u8 restore_iqk_rst;
993 u8 b2Ant;
994 u8 h2cCmdBuf;
995
996 pwrpriv = adapter_to_pwrctl(padapter);
997
998 PHY_LCCalibrate_8723B(&pHalData->odmpriv);
999
1000 /* Inform WiFi FW that it is the beginning of IQK */
1001 h2cCmdBuf = 1;
1002 FillH2CCmd8723B(padapter, H2C_8723B_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf);
1003
1004 start_time = jiffies;
1005 do {
1006 if (rtw_read8(padapter, 0x1e7) & 0x01)
1007 break;
1008
1009 msleep(50);
1010 } while (jiffies_to_msecs(jiffies - start_time) <= 400);
1011
1012 rtw_btcoex_IQKNotify(padapter, true);
1013
1014 restore_iqk_rst = pwrpriv->bips_processing;
1015 b2Ant = pHalData->EEPROMBluetoothAntNum == Ant_x2;
1016 PHY_IQCalibrate_8723B(padapter, false, restore_iqk_rst, b2Ant, pHalData->ant_path);
1017 pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = true;
1018
1019 rtw_btcoex_IQKNotify(padapter, false);
1020
1021 /* Inform WiFi FW that it is the finish of IQK */
1022 h2cCmdBuf = 0;
1023 FillH2CCmd8723B(padapter, H2C_8723B_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf);
1024
1025 ODM_TXPowerTrackingCheck(&pHalData->odmpriv);
1026 }
1027 }
1028
1029 /* Init BT hw config. */
1030 rtw_btcoex_HAL_Initialize(padapter, false);
1031
1032 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("-%s\n", __func__));
1033
1034 return _SUCCESS;
1035 }
1036
1037 /* */
1038 /* Description: */
1039 /* RTL8723e card disable power sequence v003 which suggested by Scott. */
1040 /* */
1041 /* First created by tynli. 2011.01.28. */
1042 /* */
CardDisableRTL8723BSdio(struct adapter * padapter)1043 static void CardDisableRTL8723BSdio(struct adapter *padapter)
1044 {
1045 u8 u1bTmp;
1046 u8 bMacPwrCtrlOn;
1047 u8 ret = _FAIL;
1048
1049 /* Run LPS WL RFOFF flow */
1050 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_enter_lps_flow);
1051 if (ret == _FAIL) {
1052 DBG_8192C(KERN_ERR "%s: run RF OFF flow fail!\n", __func__);
1053 }
1054
1055 /* ==== Reset digital sequence ====== */
1056
1057 u1bTmp = rtw_read8(padapter, REG_MCUFWDL);
1058 if ((u1bTmp & RAM_DL_SEL) && padapter->bFWReady) /* 8051 RAM code */
1059 rtl8723b_FirmwareSelfReset(padapter);
1060
1061 /* Reset MCU 0x2[10]= 0. Suggested by Filen. 2011.01.26. by tynli. */
1062 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
1063 u1bTmp &= ~BIT(2); /* 0x2[10], FEN_CPUEN */
1064 rtw_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp);
1065
1066 /* MCUFWDL 0x80[1:0]= 0 */
1067 /* reset MCU ready status */
1068 rtw_write8(padapter, REG_MCUFWDL, 0);
1069
1070 /* Reset MCU IO Wrapper, added by Roger, 2011.08.30 */
1071 u1bTmp = rtw_read8(padapter, REG_RSV_CTRL+1);
1072 u1bTmp &= ~BIT(0);
1073 rtw_write8(padapter, REG_RSV_CTRL+1, u1bTmp);
1074 u1bTmp = rtw_read8(padapter, REG_RSV_CTRL+1);
1075 u1bTmp |= BIT(0);
1076 rtw_write8(padapter, REG_RSV_CTRL+1, u1bTmp);
1077
1078 /* ==== Reset digital sequence end ====== */
1079
1080 bMacPwrCtrlOn = false; /* Disable CMD53 R/W */
1081 ret = false;
1082 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
1083 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_card_disable_flow);
1084 if (ret == false) {
1085 DBG_8192C(KERN_ERR "%s: run CARD DISABLE flow fail!\n", __func__);
1086 }
1087 }
1088
rtl8723bs_hal_deinit(struct adapter * padapter)1089 static u32 rtl8723bs_hal_deinit(struct adapter *padapter)
1090 {
1091 struct dvobj_priv *psdpriv = padapter->dvobj;
1092 struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
1093
1094 if (padapter->hw_init_completed == true) {
1095 if (adapter_to_pwrctl(padapter)->bips_processing == true) {
1096 if (padapter->netif_up == true) {
1097 int cnt = 0;
1098 u8 val8 = 0;
1099
1100 DBG_871X("%s: issue H2C to FW when entering IPS\n", __func__);
1101
1102 rtl8723b_set_FwPwrModeInIPS_cmd(padapter, 0x3);
1103 /* poll 0x1cc to make sure H2C command already finished by FW; MAC_0x1cc = 0 means H2C done by FW. */
1104 do {
1105 val8 = rtw_read8(padapter, REG_HMETFR);
1106 cnt++;
1107 DBG_871X("%s polling REG_HMETFR = 0x%x, cnt =%d\n", __func__, val8, cnt);
1108 mdelay(10);
1109 } while (cnt < 100 && (val8 != 0));
1110 /* H2C done, enter 32k */
1111 if (val8 == 0) {
1112 /* ser rpwm to enter 32k */
1113 val8 = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1);
1114 val8 += 0x80;
1115 val8 |= BIT(0);
1116 rtw_write8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1, val8);
1117 DBG_871X("%s: write rpwm =%02x\n", __func__, val8);
1118 adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
1119 cnt = val8 = 0;
1120 do {
1121 val8 = rtw_read8(padapter, REG_CR);
1122 cnt++;
1123 DBG_871X("%s polling 0x100 = 0x%x, cnt =%d\n", __func__, val8, cnt);
1124 mdelay(10);
1125 } while (cnt < 100 && (val8 != 0xEA));
1126 } else {
1127 DBG_871X(
1128 "MAC_1C0 =%08x, MAC_1C4 =%08x, MAC_1C8 =%08x, MAC_1CC =%08x\n",
1129 rtw_read32(padapter, 0x1c0),
1130 rtw_read32(padapter, 0x1c4),
1131 rtw_read32(padapter, 0x1c8),
1132 rtw_read32(padapter, 0x1cc)
1133 );
1134 }
1135
1136 DBG_871X(
1137 "polling done when entering IPS, check result : 0x100 = 0x%x, cnt =%d, MAC_1cc = 0x%02x\n",
1138 rtw_read8(padapter, REG_CR),
1139 cnt,
1140 rtw_read8(padapter, REG_HMETFR)
1141 );
1142
1143 adapter_to_pwrctl(padapter)->pre_ips_type = 0;
1144
1145 } else {
1146 pdbgpriv->dbg_carddisable_cnt++;
1147 CardDisableRTL8723BSdio(padapter);
1148
1149 adapter_to_pwrctl(padapter)->pre_ips_type = 1;
1150 }
1151
1152 } else {
1153 pdbgpriv->dbg_carddisable_cnt++;
1154 CardDisableRTL8723BSdio(padapter);
1155 }
1156 } else
1157 pdbgpriv->dbg_deinit_fail_cnt++;
1158
1159 return _SUCCESS;
1160 }
1161
rtl8723bs_inirp_init(struct adapter * padapter)1162 static u32 rtl8723bs_inirp_init(struct adapter *padapter)
1163 {
1164 return _SUCCESS;
1165 }
1166
rtl8723bs_inirp_deinit(struct adapter * padapter)1167 static u32 rtl8723bs_inirp_deinit(struct adapter *padapter)
1168 {
1169 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+rtl8723bs_inirp_deinit\n"));
1170
1171 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("-rtl8723bs_inirp_deinit\n"));
1172
1173 return _SUCCESS;
1174 }
1175
rtl8723bs_init_default_value(struct adapter * padapter)1176 static void rtl8723bs_init_default_value(struct adapter *padapter)
1177 {
1178 struct hal_com_data *pHalData;
1179
1180
1181 pHalData = GET_HAL_DATA(padapter);
1182
1183 rtl8723b_init_default_value(padapter);
1184
1185 /* interface related variable */
1186 pHalData->SdioRxFIFOCnt = 0;
1187 }
1188
rtl8723bs_interface_configure(struct adapter * padapter)1189 static void rtl8723bs_interface_configure(struct adapter *padapter)
1190 {
1191 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1192 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
1193 struct registry_priv *pregistrypriv = &padapter->registrypriv;
1194 bool bWiFiConfig = pregistrypriv->wifi_spec;
1195
1196
1197 pdvobjpriv->RtOutPipe[0] = WLAN_TX_HIQ_DEVICE_ID;
1198 pdvobjpriv->RtOutPipe[1] = WLAN_TX_MIQ_DEVICE_ID;
1199 pdvobjpriv->RtOutPipe[2] = WLAN_TX_LOQ_DEVICE_ID;
1200
1201 if (bWiFiConfig)
1202 pHalData->OutEpNumber = 2;
1203 else
1204 pHalData->OutEpNumber = SDIO_MAX_TX_QUEUE;
1205
1206 switch (pHalData->OutEpNumber) {
1207 case 3:
1208 pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ|TX_SELE_NQ;
1209 break;
1210 case 2:
1211 pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_NQ;
1212 break;
1213 case 1:
1214 pHalData->OutEpQueueSel = TX_SELE_HQ;
1215 break;
1216 default:
1217 break;
1218 }
1219
1220 Hal_MappingOutPipe(padapter, pHalData->OutEpNumber);
1221 }
1222
1223 /* */
1224 /* Description: */
1225 /* We should set Efuse cell selection to WiFi cell in default. */
1226 /* */
1227 /* Assumption: */
1228 /* PASSIVE_LEVEL */
1229 /* */
1230 /* Added by Roger, 2010.11.23. */
1231 /* */
_EfuseCellSel(struct adapter * padapter)1232 static void _EfuseCellSel(struct adapter *padapter)
1233 {
1234 u32 value32;
1235
1236 value32 = rtw_read32(padapter, EFUSE_TEST);
1237 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1238 rtw_write32(padapter, EFUSE_TEST, value32);
1239 }
1240
_ReadRFType(struct adapter * Adapter)1241 static void _ReadRFType(struct adapter *Adapter)
1242 {
1243 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
1244
1245 #if DISABLE_BB_RF
1246 pHalData->rf_chip = RF_PSEUDO_11N;
1247 #else
1248 pHalData->rf_chip = RF_6052;
1249 #endif
1250 }
1251
1252
Hal_EfuseParseMACAddr_8723BS(struct adapter * padapter,u8 * hwinfo,bool AutoLoadFail)1253 static void Hal_EfuseParseMACAddr_8723BS(
1254 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
1255 )
1256 {
1257 u16 i;
1258 u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0xb7, 0x23, 0x00};
1259 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1260
1261 if (AutoLoadFail) {
1262 /* sMacAddr[5] = (u8)GetRandomNumber(1, 254); */
1263 for (i = 0; i < 6; i++)
1264 pEEPROM->mac_addr[i] = sMacAddr[i];
1265 } else {
1266 /* Read Permanent MAC address */
1267 memcpy(pEEPROM->mac_addr, &hwinfo[EEPROM_MAC_ADDR_8723BS], ETH_ALEN);
1268 }
1269 /* NicIFSetMacAddress(padapter, padapter->PermanentAddress); */
1270
1271 RT_TRACE(
1272 _module_hci_hal_init_c_,
1273 _drv_notice_,
1274 (
1275 "Hal_EfuseParseMACAddr_8723BS: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
1276 pEEPROM->mac_addr[0],
1277 pEEPROM->mac_addr[1],
1278 pEEPROM->mac_addr[2],
1279 pEEPROM->mac_addr[3],
1280 pEEPROM->mac_addr[4],
1281 pEEPROM->mac_addr[5]
1282 )
1283 );
1284 }
1285
Hal_EfuseParseBoardType_8723BS(struct adapter * padapter,u8 * hwinfo,bool AutoLoadFail)1286 static void Hal_EfuseParseBoardType_8723BS(
1287 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
1288 )
1289 {
1290 struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1291
1292 if (!AutoLoadFail) {
1293 pHalData->BoardType = (hwinfo[EEPROM_RF_BOARD_OPTION_8723B] & 0xE0) >> 5;
1294 if (pHalData->BoardType == 0xFF)
1295 pHalData->BoardType = (EEPROM_DEFAULT_BOARD_OPTION&0xE0)>>5;
1296 } else
1297 pHalData->BoardType = 0;
1298 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Board Type: 0x%2x\n", pHalData->BoardType));
1299 }
1300
_ReadEfuseInfo8723BS(struct adapter * padapter)1301 static void _ReadEfuseInfo8723BS(struct adapter *padapter)
1302 {
1303 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1304 u8 *hwinfo = NULL;
1305
1306 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("====>_ReadEfuseInfo8723BS()\n"));
1307
1308 /* */
1309 /* This part read and parse the eeprom/efuse content */
1310 /* */
1311
1312 if (sizeof(pEEPROM->efuse_eeprom_data) < HWSET_MAX_SIZE_8723B)
1313 DBG_871X("[WARNING] size of efuse_eeprom_data is less than HWSET_MAX_SIZE_8723B!\n");
1314
1315 hwinfo = pEEPROM->efuse_eeprom_data;
1316
1317 Hal_InitPGData(padapter, hwinfo);
1318
1319 Hal_EfuseParseIDCode(padapter, hwinfo);
1320 Hal_EfuseParseEEPROMVer_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1321
1322 Hal_EfuseParseMACAddr_8723BS(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1323
1324 Hal_EfuseParseTxPowerInfo_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1325 Hal_EfuseParseBoardType_8723BS(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1326
1327 /* */
1328 /* Read Bluetooth co-exist and initialize */
1329 /* */
1330 Hal_EfuseParsePackageType_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1331 Hal_EfuseParseBTCoexistInfo_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1332 Hal_EfuseParseChnlPlan_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1333 Hal_EfuseParseXtal_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1334 Hal_EfuseParseThermalMeter_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1335 Hal_EfuseParseAntennaDiversity_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1336 Hal_EfuseParseCustomerID_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1337
1338 Hal_EfuseParseVoltage_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1339
1340 #ifdef CONFIG_WOWLAN
1341 Hal_DetectWoWMode(padapter);
1342 #endif
1343
1344 Hal_ReadRFGainOffset(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1345
1346 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("<==== _ReadEfuseInfo8723BS()\n"));
1347 }
1348
_ReadPROMContent(struct adapter * padapter)1349 static void _ReadPROMContent(struct adapter *padapter)
1350 {
1351 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1352 u8 eeValue;
1353
1354 eeValue = rtw_read8(padapter, REG_9346CR);
1355 /* To check system boot selection. */
1356 pEEPROM->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? true : false;
1357 pEEPROM->bautoload_fail_flag = (eeValue & EEPROM_EN) ? false : true;
1358
1359 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1360 ("%s: 9346CR = 0x%02X, Boot from %s, Autoload %s\n",
1361 __func__, eeValue,
1362 (pEEPROM->EepromOrEfuse ? "EEPROM" : "EFUSE"),
1363 (pEEPROM->bautoload_fail_flag ? "Fail" : "OK")));
1364
1365 /* pHalData->EEType = IS_BOOT_FROM_EEPROM(Adapter) ? EEPROM_93C46 : EEPROM_BOOT_EFUSE; */
1366
1367 _ReadEfuseInfo8723BS(padapter);
1368 }
1369
_InitOtherVariable(struct adapter * Adapter)1370 static void _InitOtherVariable(struct adapter *Adapter)
1371 {
1372 }
1373
1374 /* */
1375 /* Description: */
1376 /* Read HW adapter information by E-Fuse or EEPROM according CR9346 reported. */
1377 /* */
1378 /* Assumption: */
1379 /* PASSIVE_LEVEL (SDIO interface) */
1380 /* */
1381 /* */
_ReadAdapterInfo8723BS(struct adapter * padapter)1382 static s32 _ReadAdapterInfo8723BS(struct adapter *padapter)
1383 {
1384 u8 val8;
1385 unsigned long start;
1386
1387 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+_ReadAdapterInfo8723BS\n"));
1388
1389 /* before access eFuse, make sure card enable has been called */
1390 if (padapter->hw_init_completed == false)
1391 _InitPowerOn_8723BS(padapter);
1392
1393
1394 val8 = rtw_read8(padapter, 0x4e);
1395 MSG_8192C("%s, 0x4e = 0x%x\n", __func__, val8);
1396 val8 |= BIT(6);
1397 rtw_write8(padapter, 0x4e, val8);
1398
1399
1400 start = jiffies;
1401
1402 _EfuseCellSel(padapter);
1403 _ReadRFType(padapter);
1404 _ReadPROMContent(padapter);
1405 _InitOtherVariable(padapter);
1406
1407 if (padapter->hw_init_completed == false) {
1408 rtw_write8(padapter, 0x67, 0x00); /* for BT, Switch Ant control to BT */
1409 CardDisableRTL8723BSdio(padapter);/* for the power consumption issue, wifi ko module is loaded during booting, but wifi GUI is off */
1410 }
1411
1412
1413 MSG_8192C("<==== _ReadAdapterInfo8723BS in %d ms\n", jiffies_to_msecs(jiffies - start));
1414
1415 return _SUCCESS;
1416 }
1417
ReadAdapterInfo8723BS(struct adapter * padapter)1418 static void ReadAdapterInfo8723BS(struct adapter *padapter)
1419 {
1420 /* Read EEPROM size before call any EEPROM function */
1421 padapter->EepromAddressSize = GetEEPROMSize8723B(padapter);
1422
1423 _ReadAdapterInfo8723BS(padapter);
1424 }
1425
1426 /*
1427 * If variable not handled here,
1428 * some variables will be processed in SetHwReg8723B()
1429 */
SetHwReg8723BS(struct adapter * padapter,u8 variable,u8 * val)1430 static void SetHwReg8723BS(struct adapter *padapter, u8 variable, u8 *val)
1431 {
1432 struct hal_com_data *pHalData;
1433 u8 val8;
1434
1435 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
1436 struct wowlan_ioctl_param *poidparam;
1437 struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
1438 int res;
1439 u32 tmp;
1440 u16 len = 0;
1441 u8 trycnt = 100;
1442 u32 himr = 0;
1443 #if defined(CONFIG_WOWLAN)
1444 struct security_priv *psecuritypriv = &padapter->securitypriv;
1445 struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
1446 struct sta_info *psta = NULL;
1447 u64 iv_low = 0, iv_high = 0;
1448 u8 mstatus = (*(u8 *)val);
1449 #endif
1450 #endif
1451
1452 pHalData = GET_HAL_DATA(padapter);
1453
1454 switch (variable) {
1455 case HW_VAR_SET_RPWM:
1456 /* rpwm value only use BIT0(clock bit) , BIT6(Ack bit), and BIT7(Toggle bit) */
1457 /* BIT0 value - 1: 32k, 0:40MHz. */
1458 /* BIT6 value - 1: report cpwm value after success set, 0:do not report. */
1459 /* BIT7 value - Toggle bit change. */
1460 {
1461 val8 = *val;
1462 val8 &= 0xC1;
1463 rtw_write8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1, val8);
1464 }
1465 break;
1466 case HW_VAR_SET_REQ_FW_PS:
1467 {
1468 u8 req_fw_ps = 0;
1469 req_fw_ps = rtw_read8(padapter, 0x8f);
1470 req_fw_ps |= 0x10;
1471 rtw_write8(padapter, 0x8f, req_fw_ps);
1472 }
1473 break;
1474 case HW_VAR_RXDMA_AGG_PG_TH:
1475 val8 = *val;
1476 break;
1477
1478 #ifdef CONFIG_WOWLAN
1479 case HW_VAR_WOWLAN:
1480 {
1481 poidparam = (struct wowlan_ioctl_param *)val;
1482 switch (poidparam->subcode) {
1483 case WOWLAN_ENABLE:
1484 DBG_871X_LEVEL(_drv_always_, "WOWLAN_ENABLE\n");
1485
1486 /* backup data rate to register 0x8b for wowlan FW */
1487 rtw_write8(padapter, 0x8d, 1);
1488 rtw_write8(padapter, 0x8c, 0);
1489 rtw_write8(padapter, 0x8f, 0x40);
1490 rtw_write8(padapter, 0x8b,
1491 rtw_read8(padapter, 0x2f0));
1492
1493 /* 1. Download WOWLAN FW */
1494 DBG_871X_LEVEL(_drv_always_, "Re-download WoWlan FW!\n");
1495 SetFwRelatedForWoWLAN8723b(padapter, true);
1496
1497 /* 2. RX DMA stop */
1498 DBG_871X_LEVEL(_drv_always_, "Pause DMA\n");
1499 rtw_write32(padapter, REG_RXPKT_NUM, (rtw_read32(padapter, REG_RXPKT_NUM)|RW_RELEASE_EN));
1500 do {
1501 if ((rtw_read32(padapter, REG_RXPKT_NUM)&RXDMA_IDLE)) {
1502 DBG_871X_LEVEL(_drv_always_, "RX_DMA_IDLE is true\n");
1503 break;
1504 } else {
1505 /* If RX_DMA is not idle, receive one pkt from DMA */
1506 res = sdio_local_read(padapter, SDIO_REG_RX0_REQ_LEN, 4, (u8 *)&tmp);
1507 len = le16_to_cpu(tmp);
1508 DBG_871X_LEVEL(_drv_always_, "RX len:%d\n", len);
1509 if (len > 0)
1510 res = RecvOnePkt(padapter, len);
1511 else
1512 DBG_871X_LEVEL(_drv_always_, "read length fail %d\n", len);
1513
1514 DBG_871X_LEVEL(_drv_always_, "RecvOnePkt Result: %d\n", res);
1515 }
1516 } while (trycnt--);
1517 if (trycnt == 0)
1518 DBG_871X_LEVEL(_drv_always_, "Stop RX DMA failed......\n");
1519
1520 /* 3. Clear IMR and ISR */
1521 DBG_871X_LEVEL(_drv_always_, "Clear IMR and ISR\n");
1522 tmp = 0;
1523 sdio_local_write(padapter, SDIO_REG_HIMR_ON, 4, (u8 *)&tmp);
1524 sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
1525 sdio_local_read(padapter, SDIO_REG_HISR, 4, (u8 *)&tmp);
1526 sdio_local_write(padapter, SDIO_REG_HISR, 4, (u8 *)&tmp);
1527
1528 /* 4. Enable CPWM2 only */
1529 DBG_871X_LEVEL(_drv_always_, "Enable only CPWM2\n");
1530 sdio_local_read(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
1531 DBG_871X("DisableInterruptButCpwm28723BSdio(): Read SDIO_REG_HIMR: 0x%08x\n", tmp);
1532
1533 himr = cpu_to_le32(SDIO_HIMR_DISABLED)|SDIO_HIMR_CPWM2_MSK;
1534 sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8 *)&himr);
1535
1536 sdio_local_read(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
1537 DBG_871X("DisableInterruptButCpwm28723BSdio(): Read again SDIO_REG_HIMR: 0x%08x\n", tmp);
1538
1539 /* 5. Set Enable WOWLAN H2C command. */
1540 DBG_871X_LEVEL(_drv_always_, "Set Enable WOWLan cmd\n");
1541 rtl8723b_set_wowlan_cmd(padapter, 1);
1542
1543 /* 6. Check EnableWoWlan CMD is ready */
1544 if (!pwrctl->wowlan_pno_enable) {
1545 DBG_871X_LEVEL(_drv_always_, "Check EnableWoWlan CMD is ready\n");
1546 mstatus = rtw_read8(padapter, REG_WOW_CTRL);
1547 trycnt = 10;
1548 while (!(mstatus&BIT1) && trycnt > 1) {
1549 mstatus = rtw_read8(padapter, REG_WOW_CTRL);
1550 DBG_871X("Loop index: %d :0x%02x\n", trycnt, mstatus);
1551 trycnt--;
1552 msleep(2);
1553 }
1554 }
1555 break;
1556
1557 case WOWLAN_DISABLE:
1558 DBG_871X_LEVEL(_drv_always_, "WOWLAN_DISABLE\n");
1559
1560 psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(pmlmepriv));
1561 if (psta != NULL)
1562 rtl8723b_set_FwMediaStatusRpt_cmd(padapter, RT_MEDIA_DISCONNECT, psta->mac_id);
1563 else
1564 DBG_871X("psta is null\n");
1565
1566 /* 1. Read wakeup reason */
1567 pwrctl->wowlan_wake_reason = rtw_read8(padapter, REG_WOWLAN_WAKE_REASON);
1568 DBG_871X_LEVEL(
1569 _drv_always_,
1570 "wakeup_reason: 0x%02x, mac_630 = 0x%08x, mac_634 = 0x%08x, mac_1c0 = 0x%08x, mac_1c4 = 0x%08x"
1571 ", mac_494 = 0x%08x, , mac_498 = 0x%08x, mac_49c = 0x%08x, mac_608 = 0x%08x, mac_4a0 = 0x%08x, mac_4a4 = 0x%08x\n"
1572 ", mac_1cc = 0x%08x, mac_2f0 = 0x%08x, mac_2f4 = 0x%08x, mac_2f8 = 0x%08x, mac_2fc = 0x%08x, mac_8c = 0x%08x",
1573 pwrctl->wowlan_wake_reason,
1574 rtw_read32(padapter, REG_WOWLAN_GTK_DBG1),
1575 rtw_read32(padapter, REG_WOWLAN_GTK_DBG2),
1576 rtw_read32(padapter, 0x1c0),
1577 rtw_read32(padapter, 0x1c4),
1578 rtw_read32(padapter, 0x494),
1579 rtw_read32(padapter, 0x498),
1580 rtw_read32(padapter, 0x49c),
1581 rtw_read32(padapter, 0x608),
1582 rtw_read32(padapter, 0x4a0),
1583 rtw_read32(padapter, 0x4a4),
1584 rtw_read32(padapter, 0x1cc),
1585 rtw_read32(padapter, 0x2f0),
1586 rtw_read32(padapter, 0x2f4),
1587 rtw_read32(padapter, 0x2f8),
1588 rtw_read32(padapter, 0x2fc),
1589 rtw_read32(padapter, 0x8c)
1590 );
1591 #ifdef CONFIG_PNO_SET_DEBUG
1592 DBG_871X("0x1b9: 0x%02x, 0x632: 0x%02x\n", rtw_read8(padapter, 0x1b9), rtw_read8(padapter, 0x632));
1593 DBG_871X("0x4fc: 0x%02x, 0x4fd: 0x%02x\n", rtw_read8(padapter, 0x4fc), rtw_read8(padapter, 0x4fd));
1594 DBG_871X("TXDMA STATUS: 0x%08x\n", rtw_read32(padapter, REG_TXDMA_STATUS));
1595 #endif
1596
1597 {
1598 /* 2. Set Disable WOWLAN H2C command. */
1599 DBG_871X_LEVEL(_drv_always_, "Set Disable WOWLan cmd\n");
1600 rtl8723b_set_wowlan_cmd(padapter, 0);
1601
1602 /* 3. Check Disable WoWlan CMD ready. */
1603 DBG_871X_LEVEL(_drv_always_, "Check DisableWoWlan CMD is ready\n");
1604 mstatus = rtw_read8(padapter, REG_WOW_CTRL);
1605 trycnt = 50;
1606 while (mstatus&BIT1 && trycnt > 1) {
1607 mstatus = rtw_read8(padapter, REG_WOW_CTRL);
1608 DBG_871X_LEVEL(_drv_always_, "Loop index: %d :0x%02x\n", trycnt, mstatus);
1609 trycnt--;
1610 msleep(10);
1611 }
1612
1613 if (mstatus & BIT1) {
1614 DBG_871X_LEVEL(_drv_always_, "Disable WOW mode fail!!\n");
1615 DBG_871X("Set 0x690 = 0x00\n");
1616 rtw_write8(padapter, REG_WOW_CTRL, (rtw_read8(padapter, REG_WOW_CTRL)&0xf0));
1617 DBG_871X_LEVEL(_drv_always_, "Release RXDMA\n");
1618 rtw_write32(padapter, REG_RXPKT_NUM, (rtw_read32(padapter, REG_RXPKT_NUM)&(~RW_RELEASE_EN)));
1619 }
1620
1621 /* 3.1 read fw iv */
1622 iv_low = rtw_read32(padapter, REG_TXPKTBUF_IV_LOW);
1623 /* only low two bytes is PN, check AES_IV macro for detail */
1624 iv_low &= 0xffff;
1625 iv_high = rtw_read32(padapter, REG_TXPKTBUF_IV_HIGH);
1626 /* get the real packet number */
1627 pwrctl->wowlan_fw_iv = iv_high << 16 | iv_low;
1628 DBG_871X_LEVEL(_drv_always_, "fw_iv: 0x%016llx\n", pwrctl->wowlan_fw_iv);
1629 /* Update TX iv data. */
1630 rtw_set_sec_pn(padapter);
1631
1632 /* 3.2 read GTK index and key */
1633 if (
1634 psecuritypriv->binstallKCK_KEK == true &&
1635 psecuritypriv->dot11PrivacyAlgrthm == _AES_
1636 ) {
1637 u8 gtk_keyindex = 0;
1638 u8 get_key[16];
1639 /* read gtk key index */
1640 gtk_keyindex = rtw_read8(padapter, 0x48c);
1641
1642 if (gtk_keyindex < 4) {
1643 psecuritypriv->dot118021XGrpKeyid = gtk_keyindex;
1644 read_cam(padapter, gtk_keyindex, get_key);
1645 memcpy(psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey, get_key, 16);
1646 DBG_871X_LEVEL(
1647 _drv_always_,
1648 "GTK (%d) = 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
1649 gtk_keyindex,
1650 psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].lkey[0],
1651 psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].lkey[1],
1652 psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].lkey[2],
1653 psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].lkey[3]
1654 );
1655 } else
1656 DBG_871X_LEVEL(_drv_always_, "GTK index =%d\n", gtk_keyindex);
1657 }
1658
1659 /* 4. Re-download Normal FW. */
1660 DBG_871X_LEVEL(_drv_always_, "Re-download Normal FW!\n");
1661 SetFwRelatedForWoWLAN8723b(padapter, false);
1662 }
1663 #ifdef CONFIG_GPIO_WAKEUP
1664 DBG_871X_LEVEL(_drv_always_, "Set Wake GPIO to high for default.\n");
1665 HalSetOutPutGPIO(padapter, WAKEUP_GPIO_IDX, 1);
1666 #endif
1667
1668 /* 5. Download reserved pages and report media status if needed. */
1669 if (
1670 (pwrctl->wowlan_wake_reason != FWDecisionDisconnect) &&
1671 (pwrctl->wowlan_wake_reason != Rx_Pairwisekey) &&
1672 (pwrctl->wowlan_wake_reason != Rx_DisAssoc) &&
1673 (pwrctl->wowlan_wake_reason != Rx_DeAuth)
1674 ) {
1675 rtl8723b_set_FwJoinBssRpt_cmd(padapter, RT_MEDIA_CONNECT);
1676 if (psta != NULL)
1677 rtl8723b_set_FwMediaStatusRpt_cmd(padapter, RT_MEDIA_CONNECT, psta->mac_id);
1678 }
1679 #ifdef CONFIG_PNO_SUPPORT
1680 rtw_write8(padapter, 0x1b8, 0);
1681 DBG_871X("reset 0x1b8: %d\n", rtw_read8(padapter, 0x1b8));
1682 rtw_write8(padapter, 0x1b9, 0);
1683 DBG_871X("reset 0x1b9: %d\n", rtw_read8(padapter, 0x1b9));
1684 rtw_write8(padapter, REG_PNO_STATUS, 0);
1685 DBG_871X("reset REG_PNO_STATUS: %d\n", rtw_read8(padapter, REG_PNO_STATUS));
1686 #endif
1687 break;
1688
1689 default:
1690 break;
1691 }
1692 }
1693 break;
1694 #endif /* CONFIG_WOWLAN */
1695 #ifdef CONFIG_AP_WOWLAN
1696 case HW_VAR_AP_WOWLAN:
1697 {
1698 poidparam = (struct wowlan_ioctl_param *)val;
1699 switch (poidparam->subcode) {
1700 case WOWLAN_AP_ENABLE:
1701 DBG_871X("%s, WOWLAN_AP_ENABLE\n", __func__);
1702 /* 1. Download WOWLAN FW */
1703 DBG_871X_LEVEL(_drv_always_, "Re-download WoWlan FW!\n");
1704 SetFwRelatedForWoWLAN8723b(padapter, true);
1705
1706 /* 2. RX DMA stop */
1707 DBG_871X_LEVEL(_drv_always_, "Pause DMA\n");
1708 rtw_write32(padapter, REG_RXPKT_NUM,
1709 (rtw_read32(padapter, REG_RXPKT_NUM)|RW_RELEASE_EN));
1710 do {
1711 if ((rtw_read32(padapter, REG_RXPKT_NUM)&RXDMA_IDLE)) {
1712 DBG_871X_LEVEL(_drv_always_, "RX_DMA_IDLE is true\n");
1713 break;
1714 } else {
1715 /* If RX_DMA is not idle, receive one pkt from DMA */
1716 res = sdio_local_read(padapter, SDIO_REG_RX0_REQ_LEN, 4, (u8 *)&tmp);
1717 len = le16_to_cpu(tmp);
1718
1719 DBG_871X_LEVEL(_drv_always_, "RX len:%d\n", len);
1720 if (len > 0)
1721 res = RecvOnePkt(padapter, len);
1722 else
1723 DBG_871X_LEVEL(_drv_always_, "read length fail %d\n", len);
1724
1725 DBG_871X_LEVEL(_drv_always_, "RecvOnePkt Result: %d\n", res);
1726 }
1727 } while (trycnt--);
1728
1729 if (trycnt == 0)
1730 DBG_871X_LEVEL(_drv_always_, "Stop RX DMA failed......\n");
1731
1732 /* 3. Clear IMR and ISR */
1733 DBG_871X_LEVEL(_drv_always_, "Clear IMR and ISR\n");
1734 tmp = 0;
1735 sdio_local_write(padapter, SDIO_REG_HIMR_ON, 4, (u8 *)&tmp);
1736 sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
1737 sdio_local_read(padapter, SDIO_REG_HISR, 4, (u8 *)&tmp);
1738 sdio_local_write(padapter, SDIO_REG_HISR, 4, (u8 *)&tmp);
1739
1740 /* 4. Enable CPWM2 only */
1741 DBG_871X_LEVEL(_drv_always_, "Enable only CPWM2\n");
1742 sdio_local_read(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
1743 DBG_871X("DisableInterruptButCpwm28723BSdio(): Read SDIO_REG_HIMR: 0x%08x\n", tmp);
1744
1745 himr = cpu_to_le32(SDIO_HIMR_DISABLED)|SDIO_HIMR_CPWM2_MSK;
1746 sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8 *)&himr);
1747
1748 sdio_local_read(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
1749 DBG_871X("DisableInterruptButCpwm28723BSdio(): Read again SDIO_REG_HIMR: 0x%08x\n", tmp);
1750
1751 /* 5. Set Enable WOWLAN H2C command. */
1752 DBG_871X_LEVEL(_drv_always_, "Set Enable AP WOWLan cmd\n");
1753 rtl8723b_set_ap_wowlan_cmd(padapter, 1);
1754 /* 6. add some delay for H2C cmd ready */
1755 msleep(10);
1756
1757 rtw_write8(padapter, REG_WOWLAN_WAKE_REASON, 0);
1758 break;
1759 case WOWLAN_AP_DISABLE:
1760 DBG_871X("%s, WOWLAN_AP_DISABLE\n", __func__);
1761 /* 1. Read wakeup reason */
1762 pwrctl->wowlan_wake_reason =
1763 rtw_read8(padapter, REG_WOWLAN_WAKE_REASON);
1764
1765 DBG_871X_LEVEL(_drv_always_, "wakeup_reason: 0x%02x\n",
1766 pwrctl->wowlan_wake_reason);
1767
1768 /* 2. Set Disable WOWLAN H2C command. */
1769 DBG_871X_LEVEL(_drv_always_, "Set Disable WOWLan cmd\n");
1770 rtl8723b_set_ap_wowlan_cmd(padapter, 0);
1771 /* 6. add some delay for H2C cmd ready */
1772 msleep(2);
1773
1774 DBG_871X_LEVEL(_drv_always_, "Release RXDMA\n");
1775
1776 rtw_write32(padapter, REG_RXPKT_NUM,
1777 (rtw_read32(padapter, REG_RXPKT_NUM) & (~RW_RELEASE_EN)));
1778
1779 SetFwRelatedForWoWLAN8723b(padapter, false);
1780
1781 #ifdef CONFIG_GPIO_WAKEUP
1782 DBG_871X_LEVEL(_drv_always_, "Set Wake GPIO to high for default.\n");
1783 HalSetOutPutGPIO(padapter, WAKEUP_GPIO_IDX, 1);
1784 #endif /* CONFIG_GPIO_WAKEUP */
1785 rtl8723b_set_FwJoinBssRpt_cmd(padapter, RT_MEDIA_CONNECT);
1786 issue_beacon(padapter, 0);
1787 break;
1788 default:
1789 break;
1790 }
1791 }
1792 break;
1793 #endif /* CONFIG_AP_WOWLAN */
1794 case HW_VAR_DM_IN_LPS:
1795 rtl8723b_hal_dm_in_lps(padapter);
1796 break;
1797 default:
1798 SetHwReg8723B(padapter, variable, val);
1799 break;
1800 }
1801 }
1802
1803 /*
1804 * If variable not handled here,
1805 * some variables will be processed in GetHwReg8723B()
1806 */
GetHwReg8723BS(struct adapter * padapter,u8 variable,u8 * val)1807 static void GetHwReg8723BS(struct adapter *padapter, u8 variable, u8 *val)
1808 {
1809 switch (variable) {
1810 case HW_VAR_CPWM:
1811 *val = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HCPWM1_8723B);
1812 break;
1813
1814 case HW_VAR_FW_PS_STATE:
1815 {
1816 /* 3. read dword 0x88 driver read fw ps state */
1817 *((u16 *)val) = rtw_read16(padapter, 0x88);
1818 }
1819 break;
1820 default:
1821 GetHwReg8723B(padapter, variable, val);
1822 break;
1823 }
1824 }
1825
SetHwRegWithBuf8723B(struct adapter * padapter,u8 variable,u8 * pbuf,int len)1826 static void SetHwRegWithBuf8723B(struct adapter *padapter, u8 variable, u8 *pbuf, int len)
1827 {
1828 switch (variable) {
1829 case HW_VAR_C2H_HANDLE:
1830 /* DBG_8192C("%s len =%d\n", __func__, len); */
1831 C2HPacketHandler_8723B(padapter, pbuf, len);
1832 break;
1833 default:
1834 break;
1835 }
1836 }
1837
1838 /* */
1839 /* Description: */
1840 /* Query setting of specified variable. */
1841 /* */
GetHalDefVar8723BSDIO(struct adapter * Adapter,enum HAL_DEF_VARIABLE eVariable,void * pValue)1842 static u8 GetHalDefVar8723BSDIO(
1843 struct adapter *Adapter, enum HAL_DEF_VARIABLE eVariable, void *pValue
1844 )
1845 {
1846 u8 bResult = _SUCCESS;
1847
1848 switch (eVariable) {
1849 case HAL_DEF_IS_SUPPORT_ANT_DIV:
1850 break;
1851 case HAL_DEF_CURRENT_ANTENNA:
1852 break;
1853 case HW_VAR_MAX_RX_AMPDU_FACTOR:
1854 /* Stanley@BB.SD3 suggests 16K can get stable performance */
1855 /* coding by Lucas@20130730 */
1856 *(u32 *)pValue = MAX_AMPDU_FACTOR_16K;
1857 break;
1858 default:
1859 bResult = GetHalDefVar8723B(Adapter, eVariable, pValue);
1860 break;
1861 }
1862
1863 return bResult;
1864 }
1865
1866 /* */
1867 /* Description: */
1868 /* Change default setting of specified variable. */
1869 /* */
SetHalDefVar8723BSDIO(struct adapter * Adapter,enum HAL_DEF_VARIABLE eVariable,void * pValue)1870 static u8 SetHalDefVar8723BSDIO(struct adapter *Adapter,
1871 enum HAL_DEF_VARIABLE eVariable, void *pValue)
1872 {
1873 return SetHalDefVar8723B(Adapter, eVariable, pValue);
1874 }
1875
rtl8723bs_set_hal_ops(struct adapter * padapter)1876 void rtl8723bs_set_hal_ops(struct adapter *padapter)
1877 {
1878 struct hal_ops *pHalFunc = &padapter->HalFunc;
1879
1880 rtl8723b_set_hal_ops(pHalFunc);
1881
1882 pHalFunc->hal_init = &rtl8723bs_hal_init;
1883 pHalFunc->hal_deinit = &rtl8723bs_hal_deinit;
1884
1885 pHalFunc->inirp_init = &rtl8723bs_inirp_init;
1886 pHalFunc->inirp_deinit = &rtl8723bs_inirp_deinit;
1887
1888 pHalFunc->init_xmit_priv = &rtl8723bs_init_xmit_priv;
1889 pHalFunc->free_xmit_priv = &rtl8723bs_free_xmit_priv;
1890
1891 pHalFunc->init_recv_priv = &rtl8723bs_init_recv_priv;
1892 pHalFunc->free_recv_priv = &rtl8723bs_free_recv_priv;
1893
1894 pHalFunc->init_default_value = &rtl8723bs_init_default_value;
1895 pHalFunc->intf_chip_configure = &rtl8723bs_interface_configure;
1896 pHalFunc->read_adapter_info = &ReadAdapterInfo8723BS;
1897
1898 pHalFunc->enable_interrupt = &EnableInterrupt8723BSdio;
1899 pHalFunc->disable_interrupt = &DisableInterrupt8723BSdio;
1900 pHalFunc->check_ips_status = &CheckIPSStatus;
1901 #ifdef CONFIG_WOWLAN
1902 pHalFunc->clear_interrupt = &ClearInterrupt8723BSdio;
1903 #endif
1904 pHalFunc->SetHwRegHandler = &SetHwReg8723BS;
1905 pHalFunc->GetHwRegHandler = &GetHwReg8723BS;
1906 pHalFunc->SetHwRegHandlerWithBuf = &SetHwRegWithBuf8723B;
1907 pHalFunc->GetHalDefVarHandler = &GetHalDefVar8723BSDIO;
1908 pHalFunc->SetHalDefVarHandler = &SetHalDefVar8723BSDIO;
1909
1910 pHalFunc->hal_xmit = &rtl8723bs_hal_xmit;
1911 pHalFunc->mgnt_xmit = &rtl8723bs_mgnt_xmit;
1912 pHalFunc->hal_xmitframe_enqueue = &rtl8723bs_hal_xmitframe_enqueue;
1913
1914 #if defined(CONFIG_CHECK_BT_HANG)
1915 pHalFunc->hal_init_checkbthang_workqueue = &rtl8723bs_init_checkbthang_workqueue;
1916 pHalFunc->hal_free_checkbthang_workqueue = &rtl8723bs_free_checkbthang_workqueue;
1917 pHalFunc->hal_cancle_checkbthang_workqueue = &rtl8723bs_cancle_checkbthang_workqueue;
1918 pHalFunc->hal_checke_bt_hang = &rtl8723bs_hal_check_bt_hang;
1919 #endif
1920 }
1921
