1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // rt5682.c -- RT5682 ALSA SoC audio component driver
4 //
5 // Copyright 2018 Realtek Semiconductor Corp.
6 // Author: Bard Liao <bardliao@realtek.com>
7 //
8
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/pm.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/platform_device.h>
16 #include <linux/spi/spi.h>
17 #include <linux/acpi.h>
18 #include <linux/gpio.h>
19 #include <linux/of_gpio.h>
20 #include <linux/mutex.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/jack.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29 #include <sound/rt5682.h>
30
31 #include "rl6231.h"
32 #include "rt5682.h"
33
34 const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = {
35 "AVDD",
36 "MICVDD",
37 "VBAT",
38 };
39 EXPORT_SYMBOL_GPL(rt5682_supply_names);
40
41 static const struct reg_sequence patch_list[] = {
42 {RT5682_HP_IMP_SENS_CTRL_19, 0x1000},
43 {RT5682_DAC_ADC_DIG_VOL1, 0xa020},
44 {RT5682_I2C_CTRL, 0x000f},
45 {RT5682_PLL2_INTERNAL, 0x8266},
46 {RT5682_SAR_IL_CMD_3, 0x8365},
47 };
48
rt5682_apply_patch_list(struct rt5682_priv * rt5682,struct device * dev)49 void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev)
50 {
51 int ret;
52
53 ret = regmap_multi_reg_write(rt5682->regmap, patch_list,
54 ARRAY_SIZE(patch_list));
55 if (ret)
56 dev_warn(dev, "Failed to apply regmap patch: %d\n", ret);
57 }
58 EXPORT_SYMBOL_GPL(rt5682_apply_patch_list);
59
60 const struct reg_default rt5682_reg[RT5682_REG_NUM] = {
61 {0x0002, 0x8080},
62 {0x0003, 0x8000},
63 {0x0005, 0x0000},
64 {0x0006, 0x0000},
65 {0x0008, 0x800f},
66 {0x000b, 0x0000},
67 {0x0010, 0x4040},
68 {0x0011, 0x0000},
69 {0x0012, 0x1404},
70 {0x0013, 0x1000},
71 {0x0014, 0xa00a},
72 {0x0015, 0x0404},
73 {0x0016, 0x0404},
74 {0x0019, 0xafaf},
75 {0x001c, 0x2f2f},
76 {0x001f, 0x0000},
77 {0x0022, 0x5757},
78 {0x0023, 0x0039},
79 {0x0024, 0x000b},
80 {0x0026, 0xc0c4},
81 {0x0029, 0x8080},
82 {0x002a, 0xa0a0},
83 {0x002b, 0x0300},
84 {0x0030, 0x0000},
85 {0x003c, 0x0080},
86 {0x0044, 0x0c0c},
87 {0x0049, 0x0000},
88 {0x0061, 0x0000},
89 {0x0062, 0x0000},
90 {0x0063, 0x003f},
91 {0x0064, 0x0000},
92 {0x0065, 0x0000},
93 {0x0066, 0x0030},
94 {0x0067, 0x0000},
95 {0x006b, 0x0000},
96 {0x006c, 0x0000},
97 {0x006d, 0x2200},
98 {0x006e, 0x0a10},
99 {0x0070, 0x8000},
100 {0x0071, 0x8000},
101 {0x0073, 0x0000},
102 {0x0074, 0x0000},
103 {0x0075, 0x0002},
104 {0x0076, 0x0001},
105 {0x0079, 0x0000},
106 {0x007a, 0x0000},
107 {0x007b, 0x0000},
108 {0x007c, 0x0100},
109 {0x007e, 0x0000},
110 {0x0080, 0x0000},
111 {0x0081, 0x0000},
112 {0x0082, 0x0000},
113 {0x0083, 0x0000},
114 {0x0084, 0x0000},
115 {0x0085, 0x0000},
116 {0x0086, 0x0005},
117 {0x0087, 0x0000},
118 {0x0088, 0x0000},
119 {0x008c, 0x0003},
120 {0x008d, 0x0000},
121 {0x008e, 0x0060},
122 {0x008f, 0x1000},
123 {0x0091, 0x0c26},
124 {0x0092, 0x0073},
125 {0x0093, 0x0000},
126 {0x0094, 0x0080},
127 {0x0098, 0x0000},
128 {0x009a, 0x0000},
129 {0x009b, 0x0000},
130 {0x009c, 0x0000},
131 {0x009d, 0x0000},
132 {0x009e, 0x100c},
133 {0x009f, 0x0000},
134 {0x00a0, 0x0000},
135 {0x00a3, 0x0002},
136 {0x00a4, 0x0001},
137 {0x00ae, 0x2040},
138 {0x00af, 0x0000},
139 {0x00b6, 0x0000},
140 {0x00b7, 0x0000},
141 {0x00b8, 0x0000},
142 {0x00b9, 0x0002},
143 {0x00be, 0x0000},
144 {0x00c0, 0x0160},
145 {0x00c1, 0x82a0},
146 {0x00c2, 0x0000},
147 {0x00d0, 0x0000},
148 {0x00d1, 0x2244},
149 {0x00d2, 0x3300},
150 {0x00d3, 0x2200},
151 {0x00d4, 0x0000},
152 {0x00d9, 0x0009},
153 {0x00da, 0x0000},
154 {0x00db, 0x0000},
155 {0x00dc, 0x00c0},
156 {0x00dd, 0x2220},
157 {0x00de, 0x3131},
158 {0x00df, 0x3131},
159 {0x00e0, 0x3131},
160 {0x00e2, 0x0000},
161 {0x00e3, 0x4000},
162 {0x00e4, 0x0aa0},
163 {0x00e5, 0x3131},
164 {0x00e6, 0x3131},
165 {0x00e7, 0x3131},
166 {0x00e8, 0x3131},
167 {0x00ea, 0xb320},
168 {0x00eb, 0x0000},
169 {0x00f0, 0x0000},
170 {0x00f1, 0x00d0},
171 {0x00f2, 0x00d0},
172 {0x00f6, 0x0000},
173 {0x00fa, 0x0000},
174 {0x00fb, 0x0000},
175 {0x00fc, 0x0000},
176 {0x00fd, 0x0000},
177 {0x00fe, 0x10ec},
178 {0x00ff, 0x6530},
179 {0x0100, 0xa0a0},
180 {0x010b, 0x0000},
181 {0x010c, 0xae00},
182 {0x010d, 0xaaa0},
183 {0x010e, 0x8aa2},
184 {0x010f, 0x02a2},
185 {0x0110, 0xc000},
186 {0x0111, 0x04a2},
187 {0x0112, 0x2800},
188 {0x0113, 0x0000},
189 {0x0117, 0x0100},
190 {0x0125, 0x0410},
191 {0x0132, 0x6026},
192 {0x0136, 0x5555},
193 {0x0138, 0x3700},
194 {0x013a, 0x2000},
195 {0x013b, 0x2000},
196 {0x013c, 0x2005},
197 {0x013f, 0x0000},
198 {0x0142, 0x0000},
199 {0x0145, 0x0002},
200 {0x0146, 0x0000},
201 {0x0147, 0x0000},
202 {0x0148, 0x0000},
203 {0x0149, 0x0000},
204 {0x0150, 0x79a1},
205 {0x0156, 0xaaaa},
206 {0x0160, 0x4ec0},
207 {0x0161, 0x0080},
208 {0x0162, 0x0200},
209 {0x0163, 0x0800},
210 {0x0164, 0x0000},
211 {0x0165, 0x0000},
212 {0x0166, 0x0000},
213 {0x0167, 0x000f},
214 {0x0168, 0x000f},
215 {0x0169, 0x0021},
216 {0x0190, 0x413d},
217 {0x0194, 0x0000},
218 {0x0195, 0x0000},
219 {0x0197, 0x0022},
220 {0x0198, 0x0000},
221 {0x0199, 0x0000},
222 {0x01af, 0x0000},
223 {0x01b0, 0x0400},
224 {0x01b1, 0x0000},
225 {0x01b2, 0x0000},
226 {0x01b3, 0x0000},
227 {0x01b4, 0x0000},
228 {0x01b5, 0x0000},
229 {0x01b6, 0x01c3},
230 {0x01b7, 0x02a0},
231 {0x01b8, 0x03e9},
232 {0x01b9, 0x1389},
233 {0x01ba, 0xc351},
234 {0x01bb, 0x0009},
235 {0x01bc, 0x0018},
236 {0x01bd, 0x002a},
237 {0x01be, 0x004c},
238 {0x01bf, 0x0097},
239 {0x01c0, 0x433d},
240 {0x01c2, 0x0000},
241 {0x01c3, 0x0000},
242 {0x01c4, 0x0000},
243 {0x01c5, 0x0000},
244 {0x01c6, 0x0000},
245 {0x01c7, 0x0000},
246 {0x01c8, 0x40af},
247 {0x01c9, 0x0702},
248 {0x01ca, 0x0000},
249 {0x01cb, 0x0000},
250 {0x01cc, 0x5757},
251 {0x01cd, 0x5757},
252 {0x01ce, 0x5757},
253 {0x01cf, 0x5757},
254 {0x01d0, 0x5757},
255 {0x01d1, 0x5757},
256 {0x01d2, 0x5757},
257 {0x01d3, 0x5757},
258 {0x01d4, 0x5757},
259 {0x01d5, 0x5757},
260 {0x01d6, 0x0000},
261 {0x01d7, 0x0008},
262 {0x01d8, 0x0029},
263 {0x01d9, 0x3333},
264 {0x01da, 0x0000},
265 {0x01db, 0x0004},
266 {0x01dc, 0x0000},
267 {0x01de, 0x7c00},
268 {0x01df, 0x0320},
269 {0x01e0, 0x06a1},
270 {0x01e1, 0x0000},
271 {0x01e2, 0x0000},
272 {0x01e3, 0x0000},
273 {0x01e4, 0x0000},
274 {0x01e6, 0x0001},
275 {0x01e7, 0x0000},
276 {0x01e8, 0x0000},
277 {0x01ea, 0x0000},
278 {0x01eb, 0x0000},
279 {0x01ec, 0x0000},
280 {0x01ed, 0x0000},
281 {0x01ee, 0x0000},
282 {0x01ef, 0x0000},
283 {0x01f0, 0x0000},
284 {0x01f1, 0x0000},
285 {0x01f2, 0x0000},
286 {0x01f3, 0x0000},
287 {0x01f4, 0x0000},
288 {0x0210, 0x6297},
289 {0x0211, 0xa005},
290 {0x0212, 0x824c},
291 {0x0213, 0xf7ff},
292 {0x0214, 0xf24c},
293 {0x0215, 0x0102},
294 {0x0216, 0x00a3},
295 {0x0217, 0x0048},
296 {0x0218, 0xa2c0},
297 {0x0219, 0x0400},
298 {0x021a, 0x00c8},
299 {0x021b, 0x00c0},
300 {0x021c, 0x0000},
301 {0x0250, 0x4500},
302 {0x0251, 0x40b3},
303 {0x0252, 0x0000},
304 {0x0253, 0x0000},
305 {0x0254, 0x0000},
306 {0x0255, 0x0000},
307 {0x0256, 0x0000},
308 {0x0257, 0x0000},
309 {0x0258, 0x0000},
310 {0x0259, 0x0000},
311 {0x025a, 0x0005},
312 {0x0270, 0x0000},
313 {0x02ff, 0x0110},
314 {0x0300, 0x001f},
315 {0x0301, 0x032c},
316 {0x0302, 0x5f21},
317 {0x0303, 0x4000},
318 {0x0304, 0x4000},
319 {0x0305, 0x06d5},
320 {0x0306, 0x8000},
321 {0x0307, 0x0700},
322 {0x0310, 0x4560},
323 {0x0311, 0xa4a8},
324 {0x0312, 0x7418},
325 {0x0313, 0x0000},
326 {0x0314, 0x0006},
327 {0x0315, 0xffff},
328 {0x0316, 0xc400},
329 {0x0317, 0x0000},
330 {0x03c0, 0x7e00},
331 {0x03c1, 0x8000},
332 {0x03c2, 0x8000},
333 {0x03c3, 0x8000},
334 {0x03c4, 0x8000},
335 {0x03c5, 0x8000},
336 {0x03c6, 0x8000},
337 {0x03c7, 0x8000},
338 {0x03c8, 0x8000},
339 {0x03c9, 0x8000},
340 {0x03ca, 0x8000},
341 {0x03cb, 0x8000},
342 {0x03cc, 0x8000},
343 {0x03d0, 0x0000},
344 {0x03d1, 0x0000},
345 {0x03d2, 0x0000},
346 {0x03d3, 0x0000},
347 {0x03d4, 0x2000},
348 {0x03d5, 0x2000},
349 {0x03d6, 0x0000},
350 {0x03d7, 0x0000},
351 {0x03d8, 0x2000},
352 {0x03d9, 0x2000},
353 {0x03da, 0x2000},
354 {0x03db, 0x2000},
355 {0x03dc, 0x0000},
356 {0x03dd, 0x0000},
357 {0x03de, 0x0000},
358 {0x03df, 0x2000},
359 {0x03e0, 0x0000},
360 {0x03e1, 0x0000},
361 {0x03e2, 0x0000},
362 {0x03e3, 0x0000},
363 {0x03e4, 0x0000},
364 {0x03e5, 0x0000},
365 {0x03e6, 0x0000},
366 {0x03e7, 0x0000},
367 {0x03e8, 0x0000},
368 {0x03e9, 0x0000},
369 {0x03ea, 0x0000},
370 {0x03eb, 0x0000},
371 {0x03ec, 0x0000},
372 {0x03ed, 0x0000},
373 {0x03ee, 0x0000},
374 {0x03ef, 0x0000},
375 {0x03f0, 0x0800},
376 {0x03f1, 0x0800},
377 {0x03f2, 0x0800},
378 {0x03f3, 0x0800},
379 };
380 EXPORT_SYMBOL_GPL(rt5682_reg);
381
rt5682_volatile_register(struct device * dev,unsigned int reg)382 bool rt5682_volatile_register(struct device *dev, unsigned int reg)
383 {
384 switch (reg) {
385 case RT5682_RESET:
386 case RT5682_CBJ_CTRL_2:
387 case RT5682_INT_ST_1:
388 case RT5682_4BTN_IL_CMD_1:
389 case RT5682_AJD1_CTRL:
390 case RT5682_HP_CALIB_CTRL_1:
391 case RT5682_DEVICE_ID:
392 case RT5682_I2C_MODE:
393 case RT5682_HP_CALIB_CTRL_10:
394 case RT5682_EFUSE_CTRL_2:
395 case RT5682_JD_TOP_VC_VTRL:
396 case RT5682_HP_IMP_SENS_CTRL_19:
397 case RT5682_IL_CMD_1:
398 case RT5682_SAR_IL_CMD_2:
399 case RT5682_SAR_IL_CMD_4:
400 case RT5682_SAR_IL_CMD_10:
401 case RT5682_SAR_IL_CMD_11:
402 case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11:
403 case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11:
404 return true;
405 default:
406 return false;
407 }
408 }
409 EXPORT_SYMBOL_GPL(rt5682_volatile_register);
410
rt5682_readable_register(struct device * dev,unsigned int reg)411 bool rt5682_readable_register(struct device *dev, unsigned int reg)
412 {
413 switch (reg) {
414 case RT5682_RESET:
415 case RT5682_VERSION_ID:
416 case RT5682_VENDOR_ID:
417 case RT5682_DEVICE_ID:
418 case RT5682_HP_CTRL_1:
419 case RT5682_HP_CTRL_2:
420 case RT5682_HPL_GAIN:
421 case RT5682_HPR_GAIN:
422 case RT5682_I2C_CTRL:
423 case RT5682_CBJ_BST_CTRL:
424 case RT5682_CBJ_CTRL_1:
425 case RT5682_CBJ_CTRL_2:
426 case RT5682_CBJ_CTRL_3:
427 case RT5682_CBJ_CTRL_4:
428 case RT5682_CBJ_CTRL_5:
429 case RT5682_CBJ_CTRL_6:
430 case RT5682_CBJ_CTRL_7:
431 case RT5682_DAC1_DIG_VOL:
432 case RT5682_STO1_ADC_DIG_VOL:
433 case RT5682_STO1_ADC_BOOST:
434 case RT5682_HP_IMP_GAIN_1:
435 case RT5682_HP_IMP_GAIN_2:
436 case RT5682_SIDETONE_CTRL:
437 case RT5682_STO1_ADC_MIXER:
438 case RT5682_AD_DA_MIXER:
439 case RT5682_STO1_DAC_MIXER:
440 case RT5682_A_DAC1_MUX:
441 case RT5682_DIG_INF2_DATA:
442 case RT5682_REC_MIXER:
443 case RT5682_CAL_REC:
444 case RT5682_ALC_BACK_GAIN:
445 case RT5682_PWR_DIG_1:
446 case RT5682_PWR_DIG_2:
447 case RT5682_PWR_ANLG_1:
448 case RT5682_PWR_ANLG_2:
449 case RT5682_PWR_ANLG_3:
450 case RT5682_PWR_MIXER:
451 case RT5682_PWR_VOL:
452 case RT5682_CLK_DET:
453 case RT5682_RESET_LPF_CTRL:
454 case RT5682_RESET_HPF_CTRL:
455 case RT5682_DMIC_CTRL_1:
456 case RT5682_I2S1_SDP:
457 case RT5682_I2S2_SDP:
458 case RT5682_ADDA_CLK_1:
459 case RT5682_ADDA_CLK_2:
460 case RT5682_I2S1_F_DIV_CTRL_1:
461 case RT5682_I2S1_F_DIV_CTRL_2:
462 case RT5682_TDM_CTRL:
463 case RT5682_TDM_ADDA_CTRL_1:
464 case RT5682_TDM_ADDA_CTRL_2:
465 case RT5682_DATA_SEL_CTRL_1:
466 case RT5682_TDM_TCON_CTRL:
467 case RT5682_GLB_CLK:
468 case RT5682_PLL_CTRL_1:
469 case RT5682_PLL_CTRL_2:
470 case RT5682_PLL_TRACK_1:
471 case RT5682_PLL_TRACK_2:
472 case RT5682_PLL_TRACK_3:
473 case RT5682_PLL_TRACK_4:
474 case RT5682_PLL_TRACK_5:
475 case RT5682_PLL_TRACK_6:
476 case RT5682_PLL_TRACK_11:
477 case RT5682_SDW_REF_CLK:
478 case RT5682_DEPOP_1:
479 case RT5682_DEPOP_2:
480 case RT5682_HP_CHARGE_PUMP_1:
481 case RT5682_HP_CHARGE_PUMP_2:
482 case RT5682_MICBIAS_1:
483 case RT5682_MICBIAS_2:
484 case RT5682_PLL_TRACK_12:
485 case RT5682_PLL_TRACK_14:
486 case RT5682_PLL2_CTRL_1:
487 case RT5682_PLL2_CTRL_2:
488 case RT5682_PLL2_CTRL_3:
489 case RT5682_PLL2_CTRL_4:
490 case RT5682_RC_CLK_CTRL:
491 case RT5682_I2S_M_CLK_CTRL_1:
492 case RT5682_I2S2_F_DIV_CTRL_1:
493 case RT5682_I2S2_F_DIV_CTRL_2:
494 case RT5682_EQ_CTRL_1:
495 case RT5682_EQ_CTRL_2:
496 case RT5682_IRQ_CTRL_1:
497 case RT5682_IRQ_CTRL_2:
498 case RT5682_IRQ_CTRL_3:
499 case RT5682_IRQ_CTRL_4:
500 case RT5682_INT_ST_1:
501 case RT5682_GPIO_CTRL_1:
502 case RT5682_GPIO_CTRL_2:
503 case RT5682_GPIO_CTRL_3:
504 case RT5682_HP_AMP_DET_CTRL_1:
505 case RT5682_HP_AMP_DET_CTRL_2:
506 case RT5682_MID_HP_AMP_DET:
507 case RT5682_LOW_HP_AMP_DET:
508 case RT5682_DELAY_BUF_CTRL:
509 case RT5682_SV_ZCD_1:
510 case RT5682_SV_ZCD_2:
511 case RT5682_IL_CMD_1:
512 case RT5682_IL_CMD_2:
513 case RT5682_IL_CMD_3:
514 case RT5682_IL_CMD_4:
515 case RT5682_IL_CMD_5:
516 case RT5682_IL_CMD_6:
517 case RT5682_4BTN_IL_CMD_1:
518 case RT5682_4BTN_IL_CMD_2:
519 case RT5682_4BTN_IL_CMD_3:
520 case RT5682_4BTN_IL_CMD_4:
521 case RT5682_4BTN_IL_CMD_5:
522 case RT5682_4BTN_IL_CMD_6:
523 case RT5682_4BTN_IL_CMD_7:
524 case RT5682_ADC_STO1_HP_CTRL_1:
525 case RT5682_ADC_STO1_HP_CTRL_2:
526 case RT5682_AJD1_CTRL:
527 case RT5682_JD1_THD:
528 case RT5682_JD2_THD:
529 case RT5682_JD_CTRL_1:
530 case RT5682_DUMMY_1:
531 case RT5682_DUMMY_2:
532 case RT5682_DUMMY_3:
533 case RT5682_DAC_ADC_DIG_VOL1:
534 case RT5682_BIAS_CUR_CTRL_2:
535 case RT5682_BIAS_CUR_CTRL_3:
536 case RT5682_BIAS_CUR_CTRL_4:
537 case RT5682_BIAS_CUR_CTRL_5:
538 case RT5682_BIAS_CUR_CTRL_6:
539 case RT5682_BIAS_CUR_CTRL_7:
540 case RT5682_BIAS_CUR_CTRL_8:
541 case RT5682_BIAS_CUR_CTRL_9:
542 case RT5682_BIAS_CUR_CTRL_10:
543 case RT5682_VREF_REC_OP_FB_CAP_CTRL:
544 case RT5682_CHARGE_PUMP_1:
545 case RT5682_DIG_IN_CTRL_1:
546 case RT5682_PAD_DRIVING_CTRL:
547 case RT5682_SOFT_RAMP_DEPOP:
548 case RT5682_CHOP_DAC:
549 case RT5682_CHOP_ADC:
550 case RT5682_CALIB_ADC_CTRL:
551 case RT5682_VOL_TEST:
552 case RT5682_SPKVDD_DET_STA:
553 case RT5682_TEST_MODE_CTRL_1:
554 case RT5682_TEST_MODE_CTRL_2:
555 case RT5682_TEST_MODE_CTRL_3:
556 case RT5682_TEST_MODE_CTRL_4:
557 case RT5682_TEST_MODE_CTRL_5:
558 case RT5682_PLL1_INTERNAL:
559 case RT5682_PLL2_INTERNAL:
560 case RT5682_STO_NG2_CTRL_1:
561 case RT5682_STO_NG2_CTRL_2:
562 case RT5682_STO_NG2_CTRL_3:
563 case RT5682_STO_NG2_CTRL_4:
564 case RT5682_STO_NG2_CTRL_5:
565 case RT5682_STO_NG2_CTRL_6:
566 case RT5682_STO_NG2_CTRL_7:
567 case RT5682_STO_NG2_CTRL_8:
568 case RT5682_STO_NG2_CTRL_9:
569 case RT5682_STO_NG2_CTRL_10:
570 case RT5682_STO1_DAC_SIL_DET:
571 case RT5682_SIL_PSV_CTRL1:
572 case RT5682_SIL_PSV_CTRL2:
573 case RT5682_SIL_PSV_CTRL3:
574 case RT5682_SIL_PSV_CTRL4:
575 case RT5682_SIL_PSV_CTRL5:
576 case RT5682_HP_IMP_SENS_CTRL_01:
577 case RT5682_HP_IMP_SENS_CTRL_02:
578 case RT5682_HP_IMP_SENS_CTRL_03:
579 case RT5682_HP_IMP_SENS_CTRL_04:
580 case RT5682_HP_IMP_SENS_CTRL_05:
581 case RT5682_HP_IMP_SENS_CTRL_06:
582 case RT5682_HP_IMP_SENS_CTRL_07:
583 case RT5682_HP_IMP_SENS_CTRL_08:
584 case RT5682_HP_IMP_SENS_CTRL_09:
585 case RT5682_HP_IMP_SENS_CTRL_10:
586 case RT5682_HP_IMP_SENS_CTRL_11:
587 case RT5682_HP_IMP_SENS_CTRL_12:
588 case RT5682_HP_IMP_SENS_CTRL_13:
589 case RT5682_HP_IMP_SENS_CTRL_14:
590 case RT5682_HP_IMP_SENS_CTRL_15:
591 case RT5682_HP_IMP_SENS_CTRL_16:
592 case RT5682_HP_IMP_SENS_CTRL_17:
593 case RT5682_HP_IMP_SENS_CTRL_18:
594 case RT5682_HP_IMP_SENS_CTRL_19:
595 case RT5682_HP_IMP_SENS_CTRL_20:
596 case RT5682_HP_IMP_SENS_CTRL_21:
597 case RT5682_HP_IMP_SENS_CTRL_22:
598 case RT5682_HP_IMP_SENS_CTRL_23:
599 case RT5682_HP_IMP_SENS_CTRL_24:
600 case RT5682_HP_IMP_SENS_CTRL_25:
601 case RT5682_HP_IMP_SENS_CTRL_26:
602 case RT5682_HP_IMP_SENS_CTRL_27:
603 case RT5682_HP_IMP_SENS_CTRL_28:
604 case RT5682_HP_IMP_SENS_CTRL_29:
605 case RT5682_HP_IMP_SENS_CTRL_30:
606 case RT5682_HP_IMP_SENS_CTRL_31:
607 case RT5682_HP_IMP_SENS_CTRL_32:
608 case RT5682_HP_IMP_SENS_CTRL_33:
609 case RT5682_HP_IMP_SENS_CTRL_34:
610 case RT5682_HP_IMP_SENS_CTRL_35:
611 case RT5682_HP_IMP_SENS_CTRL_36:
612 case RT5682_HP_IMP_SENS_CTRL_37:
613 case RT5682_HP_IMP_SENS_CTRL_38:
614 case RT5682_HP_IMP_SENS_CTRL_39:
615 case RT5682_HP_IMP_SENS_CTRL_40:
616 case RT5682_HP_IMP_SENS_CTRL_41:
617 case RT5682_HP_IMP_SENS_CTRL_42:
618 case RT5682_HP_IMP_SENS_CTRL_43:
619 case RT5682_HP_LOGIC_CTRL_1:
620 case RT5682_HP_LOGIC_CTRL_2:
621 case RT5682_HP_LOGIC_CTRL_3:
622 case RT5682_HP_CALIB_CTRL_1:
623 case RT5682_HP_CALIB_CTRL_2:
624 case RT5682_HP_CALIB_CTRL_3:
625 case RT5682_HP_CALIB_CTRL_4:
626 case RT5682_HP_CALIB_CTRL_5:
627 case RT5682_HP_CALIB_CTRL_6:
628 case RT5682_HP_CALIB_CTRL_7:
629 case RT5682_HP_CALIB_CTRL_9:
630 case RT5682_HP_CALIB_CTRL_10:
631 case RT5682_HP_CALIB_CTRL_11:
632 case RT5682_HP_CALIB_STA_1:
633 case RT5682_HP_CALIB_STA_2:
634 case RT5682_HP_CALIB_STA_3:
635 case RT5682_HP_CALIB_STA_4:
636 case RT5682_HP_CALIB_STA_5:
637 case RT5682_HP_CALIB_STA_6:
638 case RT5682_HP_CALIB_STA_7:
639 case RT5682_HP_CALIB_STA_8:
640 case RT5682_HP_CALIB_STA_9:
641 case RT5682_HP_CALIB_STA_10:
642 case RT5682_HP_CALIB_STA_11:
643 case RT5682_SAR_IL_CMD_1:
644 case RT5682_SAR_IL_CMD_2:
645 case RT5682_SAR_IL_CMD_3:
646 case RT5682_SAR_IL_CMD_4:
647 case RT5682_SAR_IL_CMD_5:
648 case RT5682_SAR_IL_CMD_6:
649 case RT5682_SAR_IL_CMD_7:
650 case RT5682_SAR_IL_CMD_8:
651 case RT5682_SAR_IL_CMD_9:
652 case RT5682_SAR_IL_CMD_10:
653 case RT5682_SAR_IL_CMD_11:
654 case RT5682_SAR_IL_CMD_12:
655 case RT5682_SAR_IL_CMD_13:
656 case RT5682_EFUSE_CTRL_1:
657 case RT5682_EFUSE_CTRL_2:
658 case RT5682_EFUSE_CTRL_3:
659 case RT5682_EFUSE_CTRL_4:
660 case RT5682_EFUSE_CTRL_5:
661 case RT5682_EFUSE_CTRL_6:
662 case RT5682_EFUSE_CTRL_7:
663 case RT5682_EFUSE_CTRL_8:
664 case RT5682_EFUSE_CTRL_9:
665 case RT5682_EFUSE_CTRL_10:
666 case RT5682_EFUSE_CTRL_11:
667 case RT5682_JD_TOP_VC_VTRL:
668 case RT5682_DRC1_CTRL_0:
669 case RT5682_DRC1_CTRL_1:
670 case RT5682_DRC1_CTRL_2:
671 case RT5682_DRC1_CTRL_3:
672 case RT5682_DRC1_CTRL_4:
673 case RT5682_DRC1_CTRL_5:
674 case RT5682_DRC1_CTRL_6:
675 case RT5682_DRC1_HARD_LMT_CTRL_1:
676 case RT5682_DRC1_HARD_LMT_CTRL_2:
677 case RT5682_DRC1_PRIV_1:
678 case RT5682_DRC1_PRIV_2:
679 case RT5682_DRC1_PRIV_3:
680 case RT5682_DRC1_PRIV_4:
681 case RT5682_DRC1_PRIV_5:
682 case RT5682_DRC1_PRIV_6:
683 case RT5682_DRC1_PRIV_7:
684 case RT5682_DRC1_PRIV_8:
685 case RT5682_EQ_AUTO_RCV_CTRL1:
686 case RT5682_EQ_AUTO_RCV_CTRL2:
687 case RT5682_EQ_AUTO_RCV_CTRL3:
688 case RT5682_EQ_AUTO_RCV_CTRL4:
689 case RT5682_EQ_AUTO_RCV_CTRL5:
690 case RT5682_EQ_AUTO_RCV_CTRL6:
691 case RT5682_EQ_AUTO_RCV_CTRL7:
692 case RT5682_EQ_AUTO_RCV_CTRL8:
693 case RT5682_EQ_AUTO_RCV_CTRL9:
694 case RT5682_EQ_AUTO_RCV_CTRL10:
695 case RT5682_EQ_AUTO_RCV_CTRL11:
696 case RT5682_EQ_AUTO_RCV_CTRL12:
697 case RT5682_EQ_AUTO_RCV_CTRL13:
698 case RT5682_ADC_L_EQ_LPF1_A1:
699 case RT5682_R_EQ_LPF1_A1:
700 case RT5682_L_EQ_LPF1_H0:
701 case RT5682_R_EQ_LPF1_H0:
702 case RT5682_L_EQ_BPF1_A1:
703 case RT5682_R_EQ_BPF1_A1:
704 case RT5682_L_EQ_BPF1_A2:
705 case RT5682_R_EQ_BPF1_A2:
706 case RT5682_L_EQ_BPF1_H0:
707 case RT5682_R_EQ_BPF1_H0:
708 case RT5682_L_EQ_BPF2_A1:
709 case RT5682_R_EQ_BPF2_A1:
710 case RT5682_L_EQ_BPF2_A2:
711 case RT5682_R_EQ_BPF2_A2:
712 case RT5682_L_EQ_BPF2_H0:
713 case RT5682_R_EQ_BPF2_H0:
714 case RT5682_L_EQ_BPF3_A1:
715 case RT5682_R_EQ_BPF3_A1:
716 case RT5682_L_EQ_BPF3_A2:
717 case RT5682_R_EQ_BPF3_A2:
718 case RT5682_L_EQ_BPF3_H0:
719 case RT5682_R_EQ_BPF3_H0:
720 case RT5682_L_EQ_BPF4_A1:
721 case RT5682_R_EQ_BPF4_A1:
722 case RT5682_L_EQ_BPF4_A2:
723 case RT5682_R_EQ_BPF4_A2:
724 case RT5682_L_EQ_BPF4_H0:
725 case RT5682_R_EQ_BPF4_H0:
726 case RT5682_L_EQ_HPF1_A1:
727 case RT5682_R_EQ_HPF1_A1:
728 case RT5682_L_EQ_HPF1_H0:
729 case RT5682_R_EQ_HPF1_H0:
730 case RT5682_L_EQ_PRE_VOL:
731 case RT5682_R_EQ_PRE_VOL:
732 case RT5682_L_EQ_POST_VOL:
733 case RT5682_R_EQ_POST_VOL:
734 case RT5682_I2C_MODE:
735 return true;
736 default:
737 return false;
738 }
739 }
740 EXPORT_SYMBOL_GPL(rt5682_readable_register);
741
742 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
743 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
744 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
745
746 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
747 static const DECLARE_TLV_DB_RANGE(bst_tlv,
748 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
749 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
750 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
751 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
752 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
753 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
754 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
755 );
756
757 /* Interface data select */
758 static const char * const rt5682_data_select[] = {
759 "L/R", "R/L", "L/L", "R/R"
760 };
761
762 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum,
763 RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select);
764
765 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum,
766 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select);
767
768 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum,
769 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select);
770
771 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum,
772 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select);
773
774 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum,
775 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select);
776
777 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux =
778 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
779
780 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux =
781 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
782
783 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux =
784 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
785
786 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux =
787 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
788
789 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux =
790 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
791
792 static const char * const rt5682_dac_select[] = {
793 "IF1", "SOUND"
794 };
795
796 static SOC_ENUM_SINGLE_DECL(rt5682_dacl_enum,
797 RT5682_AD_DA_MIXER, RT5682_DAC1_L_SEL_SFT, rt5682_dac_select);
798
799 static const struct snd_kcontrol_new rt5682_dac_l_mux =
800 SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum);
801
802 static SOC_ENUM_SINGLE_DECL(rt5682_dacr_enum,
803 RT5682_AD_DA_MIXER, RT5682_DAC1_R_SEL_SFT, rt5682_dac_select);
804
805 static const struct snd_kcontrol_new rt5682_dac_r_mux =
806 SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum);
807
rt5682_reset(struct rt5682_priv * rt5682)808 void rt5682_reset(struct rt5682_priv *rt5682)
809 {
810 regmap_write(rt5682->regmap, RT5682_RESET, 0);
811 if (!rt5682->is_sdw)
812 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1);
813 }
814 EXPORT_SYMBOL_GPL(rt5682_reset);
815
816 /**
817 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
818 * @component: SoC audio component device.
819 * @filter_mask: mask of filters.
820 * @clk_src: clock source
821 *
822 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can
823 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
824 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
825 * ASRC function will track i2s clock and generate a corresponding system clock
826 * for codec. This function provides an API to select the clock source for a
827 * set of filters specified by the mask. And the component driver will turn on
828 * ASRC for these filters if ASRC is selected as their clock source.
829 */
rt5682_sel_asrc_clk_src(struct snd_soc_component * component,unsigned int filter_mask,unsigned int clk_src)830 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
831 unsigned int filter_mask, unsigned int clk_src)
832 {
833 switch (clk_src) {
834 case RT5682_CLK_SEL_SYS:
835 case RT5682_CLK_SEL_I2S1_ASRC:
836 case RT5682_CLK_SEL_I2S2_ASRC:
837 break;
838
839 default:
840 return -EINVAL;
841 }
842
843 if (filter_mask & RT5682_DA_STEREO1_FILTER) {
844 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2,
845 RT5682_FILTER_CLK_SEL_MASK,
846 clk_src << RT5682_FILTER_CLK_SEL_SFT);
847 }
848
849 if (filter_mask & RT5682_AD_STEREO1_FILTER) {
850 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3,
851 RT5682_FILTER_CLK_SEL_MASK,
852 clk_src << RT5682_FILTER_CLK_SEL_SFT);
853 }
854
855 return 0;
856 }
857 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src);
858
rt5682_button_detect(struct snd_soc_component * component)859 static int rt5682_button_detect(struct snd_soc_component *component)
860 {
861 int btn_type, val;
862
863 val = snd_soc_component_read(component, RT5682_4BTN_IL_CMD_1);
864 btn_type = val & 0xfff0;
865 snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val);
866 dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type);
867 snd_soc_component_update_bits(component,
868 RT5682_SAR_IL_CMD_2, 0x10, 0x10);
869
870 return btn_type;
871 }
872
rt5682_enable_push_button_irq(struct snd_soc_component * component,bool enable)873 static void rt5682_enable_push_button_irq(struct snd_soc_component *component,
874 bool enable)
875 {
876 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
877
878 if (enable) {
879 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
880 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN);
881 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
882 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN);
883 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040);
884 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
885 RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK,
886 RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR);
887 if (rt5682->is_sdw)
888 snd_soc_component_update_bits(component,
889 RT5682_IRQ_CTRL_3,
890 RT5682_IL_IRQ_MASK | RT5682_IL_IRQ_TYPE_MASK,
891 RT5682_IL_IRQ_EN | RT5682_IL_IRQ_PUL);
892 else
893 snd_soc_component_update_bits(component,
894 RT5682_IRQ_CTRL_3, RT5682_IL_IRQ_MASK,
895 RT5682_IL_IRQ_EN);
896 } else {
897 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
898 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS);
899 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
900 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS);
901 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
902 RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS);
903 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
904 RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST);
905 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
906 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE);
907 }
908 }
909
910 /**
911 * rt5682_headset_detect - Detect headset.
912 * @component: SoC audio component device.
913 * @jack_insert: Jack insert or not.
914 *
915 * Detect whether is headset or not when jack inserted.
916 *
917 * Returns detect status.
918 */
rt5682_headset_detect(struct snd_soc_component * component,int jack_insert)919 int rt5682_headset_detect(struct snd_soc_component *component, int jack_insert)
920 {
921 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
922 struct snd_soc_dapm_context *dapm = &component->dapm;
923 unsigned int val, count;
924
925 if (jack_insert) {
926 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
927 RT5682_PWR_VREF2 | RT5682_PWR_MB,
928 RT5682_PWR_VREF2 | RT5682_PWR_MB);
929 snd_soc_component_update_bits(component,
930 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
931 usleep_range(15000, 20000);
932 snd_soc_component_update_bits(component,
933 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2);
934 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
935 RT5682_PWR_CBJ, RT5682_PWR_CBJ);
936 snd_soc_component_update_bits(component,
937 RT5682_HP_CHARGE_PUMP_1,
938 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0);
939 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
940 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH);
941
942 count = 0;
943 val = snd_soc_component_read(component, RT5682_CBJ_CTRL_2)
944 & RT5682_JACK_TYPE_MASK;
945 while (val == 0 && count < 50) {
946 usleep_range(10000, 15000);
947 val = snd_soc_component_read(component,
948 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
949 count++;
950 }
951
952 switch (val) {
953 case 0x1:
954 case 0x2:
955 rt5682->jack_type = SND_JACK_HEADSET;
956 rt5682_enable_push_button_irq(component, true);
957 break;
958 default:
959 rt5682->jack_type = SND_JACK_HEADPHONE;
960 break;
961 }
962
963 snd_soc_component_update_bits(component,
964 RT5682_HP_CHARGE_PUMP_1,
965 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK,
966 RT5682_OSW_L_EN | RT5682_OSW_R_EN);
967 snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
968 RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
969 RT5682_PWR_CLK25M_PU | RT5682_PWR_CLK1M_PU);
970 } else {
971 rt5682_enable_push_button_irq(component, false);
972 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
973 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
974 if (!snd_soc_dapm_get_pin_status(dapm, "MICBIAS"))
975 snd_soc_component_update_bits(component,
976 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
977 if (!snd_soc_dapm_get_pin_status(dapm, "Vref2"))
978 snd_soc_component_update_bits(component,
979 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
980 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
981 RT5682_PWR_CBJ, 0);
982 snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
983 RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
984 RT5682_PWR_CLK25M_PD | RT5682_PWR_CLK1M_PD);
985
986 rt5682->jack_type = 0;
987 }
988
989 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type);
990 return rt5682->jack_type;
991 }
992 EXPORT_SYMBOL_GPL(rt5682_headset_detect);
993
rt5682_set_jack_detect(struct snd_soc_component * component,struct snd_soc_jack * hs_jack,void * data)994 static int rt5682_set_jack_detect(struct snd_soc_component *component,
995 struct snd_soc_jack *hs_jack, void *data)
996 {
997 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
998
999 rt5682->hs_jack = hs_jack;
1000
1001 if (!hs_jack) {
1002 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1003 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1004 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1005 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1006 cancel_delayed_work_sync(&rt5682->jack_detect_work);
1007
1008 return 0;
1009 }
1010
1011 if (!rt5682->is_sdw) {
1012 switch (rt5682->pdata.jd_src) {
1013 case RT5682_JD1:
1014 snd_soc_component_update_bits(component,
1015 RT5682_CBJ_CTRL_2, RT5682_EXT_JD_SRC,
1016 RT5682_EXT_JD_SRC_MANUAL);
1017 snd_soc_component_write(component, RT5682_CBJ_CTRL_1,
1018 0xd042);
1019 snd_soc_component_update_bits(component,
1020 RT5682_CBJ_CTRL_3, RT5682_CBJ_IN_BUF_EN,
1021 RT5682_CBJ_IN_BUF_EN);
1022 snd_soc_component_update_bits(component,
1023 RT5682_SAR_IL_CMD_1, RT5682_SAR_POW_MASK,
1024 RT5682_SAR_POW_EN);
1025 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
1026 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ);
1027 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1028 RT5682_POW_IRQ | RT5682_POW_JDH |
1029 RT5682_POW_ANA, RT5682_POW_IRQ |
1030 RT5682_POW_JDH | RT5682_POW_ANA);
1031 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
1032 RT5682_PWR_JDH, RT5682_PWR_JDH);
1033 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1034 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK,
1035 RT5682_JD1_EN | RT5682_JD1_POL_NOR);
1036 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4,
1037 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1038 rt5682->pdata.btndet_delay));
1039 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5,
1040 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1041 rt5682->pdata.btndet_delay));
1042 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6,
1043 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1044 rt5682->pdata.btndet_delay));
1045 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7,
1046 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1047 rt5682->pdata.btndet_delay));
1048 mod_delayed_work(system_power_efficient_wq,
1049 &rt5682->jack_detect_work,
1050 msecs_to_jiffies(250));
1051 break;
1052
1053 case RT5682_JD_NULL:
1054 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1055 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1056 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1057 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1058 break;
1059
1060 default:
1061 dev_warn(component->dev, "Wrong JD source\n");
1062 break;
1063 }
1064 }
1065
1066 return 0;
1067 }
1068
rt5682_jack_detect_handler(struct work_struct * work)1069 void rt5682_jack_detect_handler(struct work_struct *work)
1070 {
1071 struct rt5682_priv *rt5682 =
1072 container_of(work, struct rt5682_priv, jack_detect_work.work);
1073 int val, btn_type;
1074
1075 while (!rt5682->component)
1076 usleep_range(10000, 15000);
1077
1078 while (!rt5682->component->card->instantiated)
1079 usleep_range(10000, 15000);
1080
1081 mutex_lock(&rt5682->calibrate_mutex);
1082
1083 val = snd_soc_component_read(rt5682->component, RT5682_AJD1_CTRL)
1084 & RT5682_JDH_RS_MASK;
1085 if (!val) {
1086 /* jack in */
1087 if (rt5682->jack_type == 0) {
1088 /* jack was out, report jack type */
1089 rt5682->jack_type =
1090 rt5682_headset_detect(rt5682->component, 1);
1091 } else if ((rt5682->jack_type & SND_JACK_HEADSET) ==
1092 SND_JACK_HEADSET) {
1093 /* jack is already in, report button event */
1094 rt5682->jack_type = SND_JACK_HEADSET;
1095 btn_type = rt5682_button_detect(rt5682->component);
1096 /**
1097 * rt5682 can report three kinds of button behavior,
1098 * one click, double click and hold. However,
1099 * currently we will report button pressed/released
1100 * event. So all the three button behaviors are
1101 * treated as button pressed.
1102 */
1103 switch (btn_type) {
1104 case 0x8000:
1105 case 0x4000:
1106 case 0x2000:
1107 rt5682->jack_type |= SND_JACK_BTN_0;
1108 break;
1109 case 0x1000:
1110 case 0x0800:
1111 case 0x0400:
1112 rt5682->jack_type |= SND_JACK_BTN_1;
1113 break;
1114 case 0x0200:
1115 case 0x0100:
1116 case 0x0080:
1117 rt5682->jack_type |= SND_JACK_BTN_2;
1118 break;
1119 case 0x0040:
1120 case 0x0020:
1121 case 0x0010:
1122 rt5682->jack_type |= SND_JACK_BTN_3;
1123 break;
1124 case 0x0000: /* unpressed */
1125 break;
1126 default:
1127 dev_err(rt5682->component->dev,
1128 "Unexpected button code 0x%04x\n",
1129 btn_type);
1130 break;
1131 }
1132 }
1133 } else {
1134 /* jack out */
1135 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
1136 }
1137
1138 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
1139 SND_JACK_HEADSET |
1140 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1141 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1142
1143 if (!rt5682->is_sdw) {
1144 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1145 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1146 schedule_delayed_work(&rt5682->jd_check_work, 0);
1147 else
1148 cancel_delayed_work_sync(&rt5682->jd_check_work);
1149 }
1150
1151 mutex_unlock(&rt5682->calibrate_mutex);
1152 }
1153 EXPORT_SYMBOL_GPL(rt5682_jack_detect_handler);
1154
1155 static const struct snd_kcontrol_new rt5682_snd_controls[] = {
1156 /* DAC Digital Volume */
1157 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL,
1158 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
1159
1160 /* IN Boost Volume */
1161 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL,
1162 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv),
1163
1164 /* ADC Digital Volume Control */
1165 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
1166 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1),
1167 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
1168 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1169
1170 /* ADC Boost Volume Control */
1171 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
1172 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT,
1173 3, 0, adc_bst_tlv),
1174 };
1175
rt5682_div_sel(struct rt5682_priv * rt5682,int target,const int div[],int size)1176 static int rt5682_div_sel(struct rt5682_priv *rt5682,
1177 int target, const int div[], int size)
1178 {
1179 int i;
1180
1181 if (rt5682->sysclk < target) {
1182 dev_err(rt5682->component->dev,
1183 "sysclk rate %d is too low\n", rt5682->sysclk);
1184 return 0;
1185 }
1186
1187 for (i = 0; i < size - 1; i++) {
1188 dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]);
1189 if (target * div[i] == rt5682->sysclk)
1190 return i;
1191 if (target * div[i + 1] > rt5682->sysclk) {
1192 dev_dbg(rt5682->component->dev,
1193 "can't find div for sysclk %d\n",
1194 rt5682->sysclk);
1195 return i;
1196 }
1197 }
1198
1199 if (target * div[i] < rt5682->sysclk)
1200 dev_err(rt5682->component->dev,
1201 "sysclk rate %d is too high\n", rt5682->sysclk);
1202
1203 return size - 1;
1204 }
1205
1206 /**
1207 * set_dmic_clk - Set parameter of dmic.
1208 *
1209 * @w: DAPM widget.
1210 * @kcontrol: The kcontrol of this widget.
1211 * @event: Event id.
1212 *
1213 * Choose dmic clock between 1MHz and 3MHz.
1214 * It is better for clock to approximate 3MHz.
1215 */
set_dmic_clk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1216 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1217 struct snd_kcontrol *kcontrol, int event)
1218 {
1219 struct snd_soc_component *component =
1220 snd_soc_dapm_to_component(w->dapm);
1221 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1222 int idx = -EINVAL, dmic_clk_rate = 3072000;
1223 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1224
1225 if (rt5682->pdata.dmic_clk_rate)
1226 dmic_clk_rate = rt5682->pdata.dmic_clk_rate;
1227
1228 idx = rt5682_div_sel(rt5682, dmic_clk_rate, div, ARRAY_SIZE(div));
1229
1230 snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1,
1231 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT);
1232
1233 return 0;
1234 }
1235
set_filter_clk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1236 static int set_filter_clk(struct snd_soc_dapm_widget *w,
1237 struct snd_kcontrol *kcontrol, int event)
1238 {
1239 struct snd_soc_component *component =
1240 snd_soc_dapm_to_component(w->dapm);
1241 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1242 int ref, val, reg, idx = -EINVAL;
1243 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1244 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1245
1246 if (rt5682->is_sdw)
1247 return 0;
1248
1249 val = snd_soc_component_read(component, RT5682_GPIO_CTRL_1) &
1250 RT5682_GP4_PIN_MASK;
1251 if (w->shift == RT5682_PWR_ADC_S1F_BIT &&
1252 val == RT5682_GP4_PIN_ADCDAT2)
1253 ref = 256 * rt5682->lrck[RT5682_AIF2];
1254 else
1255 ref = 256 * rt5682->lrck[RT5682_AIF1];
1256
1257 idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f));
1258
1259 if (w->shift == RT5682_PWR_ADC_S1F_BIT)
1260 reg = RT5682_PLL_TRACK_3;
1261 else
1262 reg = RT5682_PLL_TRACK_2;
1263
1264 snd_soc_component_update_bits(component, reg,
1265 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT);
1266
1267 /* select over sample rate */
1268 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
1269 if (rt5682->sysclk <= 12288000 * div_o[idx])
1270 break;
1271 }
1272
1273 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
1274 RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK,
1275 (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT));
1276
1277 return 0;
1278 }
1279
is_sys_clk_from_pll1(struct snd_soc_dapm_widget * w,struct snd_soc_dapm_widget * sink)1280 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
1281 struct snd_soc_dapm_widget *sink)
1282 {
1283 unsigned int val;
1284 struct snd_soc_component *component =
1285 snd_soc_dapm_to_component(w->dapm);
1286
1287 val = snd_soc_component_read(component, RT5682_GLB_CLK);
1288 val &= RT5682_SCLK_SRC_MASK;
1289 if (val == RT5682_SCLK_SRC_PLL1)
1290 return 1;
1291 else
1292 return 0;
1293 }
1294
is_sys_clk_from_pll2(struct snd_soc_dapm_widget * w,struct snd_soc_dapm_widget * sink)1295 static int is_sys_clk_from_pll2(struct snd_soc_dapm_widget *w,
1296 struct snd_soc_dapm_widget *sink)
1297 {
1298 unsigned int val;
1299 struct snd_soc_component *component =
1300 snd_soc_dapm_to_component(w->dapm);
1301
1302 val = snd_soc_component_read(component, RT5682_GLB_CLK);
1303 val &= RT5682_SCLK_SRC_MASK;
1304 if (val == RT5682_SCLK_SRC_PLL2)
1305 return 1;
1306 else
1307 return 0;
1308 }
1309
is_using_asrc(struct snd_soc_dapm_widget * w,struct snd_soc_dapm_widget * sink)1310 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1311 struct snd_soc_dapm_widget *sink)
1312 {
1313 unsigned int reg, shift, val;
1314 struct snd_soc_component *component =
1315 snd_soc_dapm_to_component(w->dapm);
1316
1317 switch (w->shift) {
1318 case RT5682_ADC_STO1_ASRC_SFT:
1319 reg = RT5682_PLL_TRACK_3;
1320 shift = RT5682_FILTER_CLK_SEL_SFT;
1321 break;
1322 case RT5682_DAC_STO1_ASRC_SFT:
1323 reg = RT5682_PLL_TRACK_2;
1324 shift = RT5682_FILTER_CLK_SEL_SFT;
1325 break;
1326 default:
1327 return 0;
1328 }
1329
1330 val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
1331 switch (val) {
1332 case RT5682_CLK_SEL_I2S1_ASRC:
1333 case RT5682_CLK_SEL_I2S2_ASRC:
1334 return 1;
1335 default:
1336 return 0;
1337 }
1338 }
1339
1340 /* Digital Mixer */
1341 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = {
1342 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1343 RT5682_M_STO1_ADC_L1_SFT, 1, 1),
1344 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1345 RT5682_M_STO1_ADC_L2_SFT, 1, 1),
1346 };
1347
1348 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = {
1349 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1350 RT5682_M_STO1_ADC_R1_SFT, 1, 1),
1351 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1352 RT5682_M_STO1_ADC_R2_SFT, 1, 1),
1353 };
1354
1355 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = {
1356 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1357 RT5682_M_ADCMIX_L_SFT, 1, 1),
1358 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1359 RT5682_M_DAC1_L_SFT, 1, 1),
1360 };
1361
1362 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = {
1363 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1364 RT5682_M_ADCMIX_R_SFT, 1, 1),
1365 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1366 RT5682_M_DAC1_R_SFT, 1, 1),
1367 };
1368
1369 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = {
1370 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1371 RT5682_M_DAC_L1_STO_L_SFT, 1, 1),
1372 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1373 RT5682_M_DAC_R1_STO_L_SFT, 1, 1),
1374 };
1375
1376 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = {
1377 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1378 RT5682_M_DAC_L1_STO_R_SFT, 1, 1),
1379 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1380 RT5682_M_DAC_R1_STO_R_SFT, 1, 1),
1381 };
1382
1383 /* Analog Input Mixer */
1384 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = {
1385 SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER,
1386 RT5682_M_CBJ_RM1_L_SFT, 1, 1),
1387 };
1388
1389 /* STO1 ADC1 Source */
1390 /* MX-26 [13] [5] */
1391 static const char * const rt5682_sto1_adc1_src[] = {
1392 "DAC MIX", "ADC"
1393 };
1394
1395 static SOC_ENUM_SINGLE_DECL(
1396 rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER,
1397 RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src);
1398
1399 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux =
1400 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum);
1401
1402 static SOC_ENUM_SINGLE_DECL(
1403 rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER,
1404 RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src);
1405
1406 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux =
1407 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum);
1408
1409 /* STO1 ADC Source */
1410 /* MX-26 [11:10] [3:2] */
1411 static const char * const rt5682_sto1_adc_src[] = {
1412 "ADC1 L", "ADC1 R"
1413 };
1414
1415 static SOC_ENUM_SINGLE_DECL(
1416 rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER,
1417 RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src);
1418
1419 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux =
1420 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum);
1421
1422 static SOC_ENUM_SINGLE_DECL(
1423 rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER,
1424 RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src);
1425
1426 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux =
1427 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum);
1428
1429 /* STO1 ADC2 Source */
1430 /* MX-26 [12] [4] */
1431 static const char * const rt5682_sto1_adc2_src[] = {
1432 "DAC MIX", "DMIC"
1433 };
1434
1435 static SOC_ENUM_SINGLE_DECL(
1436 rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER,
1437 RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src);
1438
1439 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux =
1440 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum);
1441
1442 static SOC_ENUM_SINGLE_DECL(
1443 rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER,
1444 RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src);
1445
1446 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux =
1447 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum);
1448
1449 /* MX-79 [6:4] I2S1 ADC data location */
1450 static const unsigned int rt5682_if1_adc_slot_values[] = {
1451 0,
1452 2,
1453 4,
1454 6,
1455 };
1456
1457 static const char * const rt5682_if1_adc_slot_src[] = {
1458 "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1459 };
1460
1461 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum,
1462 RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK,
1463 rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values);
1464
1465 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux =
1466 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
1467
1468 /* Analog DAC L1 Source, Analog DAC R1 Source*/
1469 /* MX-2B [4], MX-2B [0]*/
1470 static const char * const rt5682_alg_dac1_src[] = {
1471 "Stereo1 DAC Mixer", "DAC1"
1472 };
1473
1474 static SOC_ENUM_SINGLE_DECL(
1475 rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX,
1476 RT5682_A_DACL1_SFT, rt5682_alg_dac1_src);
1477
1478 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux =
1479 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum);
1480
1481 static SOC_ENUM_SINGLE_DECL(
1482 rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX,
1483 RT5682_A_DACR1_SFT, rt5682_alg_dac1_src);
1484
1485 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux =
1486 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum);
1487
1488 /* Out Switch */
1489 static const struct snd_kcontrol_new hpol_switch =
1490 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1491 RT5682_L_MUTE_SFT, 1, 1);
1492 static const struct snd_kcontrol_new hpor_switch =
1493 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1494 RT5682_R_MUTE_SFT, 1, 1);
1495
rt5682_hp_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1496 static int rt5682_hp_event(struct snd_soc_dapm_widget *w,
1497 struct snd_kcontrol *kcontrol, int event)
1498 {
1499 struct snd_soc_component *component =
1500 snd_soc_dapm_to_component(w->dapm);
1501
1502 switch (event) {
1503 case SND_SOC_DAPM_PRE_PMU:
1504 snd_soc_component_write(component,
1505 RT5682_HP_LOGIC_CTRL_2, 0x0012);
1506 snd_soc_component_write(component,
1507 RT5682_HP_CTRL_2, 0x6000);
1508 snd_soc_component_update_bits(component,
1509 RT5682_DEPOP_1, 0x60, 0x60);
1510 snd_soc_component_update_bits(component,
1511 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080);
1512 break;
1513
1514 case SND_SOC_DAPM_POST_PMD:
1515 snd_soc_component_update_bits(component,
1516 RT5682_DEPOP_1, 0x60, 0x0);
1517 snd_soc_component_write(component,
1518 RT5682_HP_CTRL_2, 0x0000);
1519 snd_soc_component_update_bits(component,
1520 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000);
1521 break;
1522 }
1523
1524 return 0;
1525 }
1526
set_dmic_power(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1527 static int set_dmic_power(struct snd_soc_dapm_widget *w,
1528 struct snd_kcontrol *kcontrol, int event)
1529 {
1530 struct snd_soc_component *component =
1531 snd_soc_dapm_to_component(w->dapm);
1532 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1533 unsigned int delay = 50, val;
1534
1535 if (rt5682->pdata.dmic_delay)
1536 delay = rt5682->pdata.dmic_delay;
1537
1538 switch (event) {
1539 case SND_SOC_DAPM_POST_PMU:
1540 val = snd_soc_component_read(component, RT5682_GLB_CLK);
1541 val &= RT5682_SCLK_SRC_MASK;
1542 if (val == RT5682_SCLK_SRC_PLL1 || val == RT5682_SCLK_SRC_PLL2)
1543 snd_soc_component_update_bits(component,
1544 RT5682_PWR_ANLG_1,
1545 RT5682_PWR_VREF2 | RT5682_PWR_MB,
1546 RT5682_PWR_VREF2 | RT5682_PWR_MB);
1547
1548 /*Add delay to avoid pop noise*/
1549 msleep(delay);
1550 break;
1551
1552 case SND_SOC_DAPM_POST_PMD:
1553 if (!rt5682->jack_type) {
1554 if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS"))
1555 snd_soc_component_update_bits(component,
1556 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
1557 if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2"))
1558 snd_soc_component_update_bits(component,
1559 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
1560 }
1561 break;
1562 }
1563
1564 return 0;
1565 }
1566
rt5682_set_verf(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1567 static int rt5682_set_verf(struct snd_soc_dapm_widget *w,
1568 struct snd_kcontrol *kcontrol, int event)
1569 {
1570 struct snd_soc_component *component =
1571 snd_soc_dapm_to_component(w->dapm);
1572
1573 switch (event) {
1574 case SND_SOC_DAPM_PRE_PMU:
1575 switch (w->shift) {
1576 case RT5682_PWR_VREF1_BIT:
1577 snd_soc_component_update_bits(component,
1578 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0);
1579 break;
1580
1581 case RT5682_PWR_VREF2_BIT:
1582 snd_soc_component_update_bits(component,
1583 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
1584 break;
1585 }
1586 break;
1587
1588 case SND_SOC_DAPM_POST_PMU:
1589 usleep_range(15000, 20000);
1590 switch (w->shift) {
1591 case RT5682_PWR_VREF1_BIT:
1592 snd_soc_component_update_bits(component,
1593 RT5682_PWR_ANLG_1, RT5682_PWR_FV1,
1594 RT5682_PWR_FV1);
1595 break;
1596
1597 case RT5682_PWR_VREF2_BIT:
1598 snd_soc_component_update_bits(component,
1599 RT5682_PWR_ANLG_1, RT5682_PWR_FV2,
1600 RT5682_PWR_FV2);
1601 break;
1602 }
1603 break;
1604 }
1605
1606 return 0;
1607 }
1608
1609 static const unsigned int rt5682_adcdat_pin_values[] = {
1610 1,
1611 3,
1612 };
1613
1614 static const char * const rt5682_adcdat_pin_select[] = {
1615 "ADCDAT1",
1616 "ADCDAT2",
1617 };
1618
1619 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum,
1620 RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK,
1621 rt5682_adcdat_pin_select, rt5682_adcdat_pin_values);
1622
1623 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl =
1624 SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum);
1625
1626 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {
1627 SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT,
1628 0, NULL, 0),
1629 SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT,
1630 0, NULL, 0),
1631 SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT,
1632 0, NULL, 0),
1633 SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT,
1634 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1635 SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0,
1636 rt5682_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1637 SND_SOC_DAPM_SUPPLY("Vref2", SND_SOC_NOPM, 0, 0, NULL, 0),
1638 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0),
1639
1640 /* ASRC */
1641 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1642 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1643 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1644 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1645 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1,
1646 RT5682_AD_ASRC_SFT, 0, NULL, 0),
1647 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1,
1648 RT5682_DA_ASRC_SFT, 0, NULL, 0),
1649 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1,
1650 RT5682_DMIC_ASRC_SFT, 0, NULL, 0),
1651
1652 /* Input Side */
1653 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT,
1654 0, NULL, 0),
1655 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT,
1656 0, NULL, 0),
1657
1658 /* Input Lines */
1659 SND_SOC_DAPM_INPUT("DMIC L1"),
1660 SND_SOC_DAPM_INPUT("DMIC R1"),
1661
1662 SND_SOC_DAPM_INPUT("IN1P"),
1663
1664 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1665 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1666 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1,
1667 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power,
1668 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1669
1670 /* Boost */
1671 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
1672 0, 0, NULL, 0),
1673
1674 /* REC Mixer */
1675 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix,
1676 ARRAY_SIZE(rt5682_rec1_l_mix)),
1677 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2,
1678 RT5682_PWR_RM1_L_BIT, 0, NULL, 0),
1679
1680 /* ADCs */
1681 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1682 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1683
1684 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1,
1685 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0),
1686 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1,
1687 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0),
1688 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC,
1689 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0),
1690
1691 /* ADC Mux */
1692 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1693 &rt5682_sto1_adc1l_mux),
1694 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1695 &rt5682_sto1_adc1r_mux),
1696 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1697 &rt5682_sto1_adc2l_mux),
1698 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1699 &rt5682_sto1_adc2r_mux),
1700 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1701 &rt5682_sto1_adcl_mux),
1702 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1703 &rt5682_sto1_adcr_mux),
1704 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1705 &rt5682_if1_adc_slot_mux),
1706
1707 /* ADC Mixer */
1708 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
1709 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk,
1710 SND_SOC_DAPM_PRE_PMU),
1711 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
1712 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix,
1713 ARRAY_SIZE(rt5682_sto1_adc_l_mix)),
1714 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
1715 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,
1716 ARRAY_SIZE(rt5682_sto1_adc_r_mix)),
1717 SND_SOC_DAPM_SUPPLY("BTN Detection Mode", RT5682_SAR_IL_CMD_1,
1718 14, 1, NULL, 0),
1719
1720 /* ADC PGA */
1721 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1722
1723 /* Digital Interface */
1724 SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT,
1725 0, NULL, 0),
1726 SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT,
1727 0, NULL, 0),
1728 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1729 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1730 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1731 SND_SOC_DAPM_PGA("SOUND DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1732 SND_SOC_DAPM_PGA("SOUND DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1733
1734 /* Digital Interface Select */
1735 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1736 &rt5682_if1_01_adc_swap_mux),
1737 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1738 &rt5682_if1_23_adc_swap_mux),
1739 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1740 &rt5682_if1_45_adc_swap_mux),
1741 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1742 &rt5682_if1_67_adc_swap_mux),
1743 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1744 &rt5682_if2_adc_swap_mux),
1745
1746 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
1747 &rt5682_adcdat_pin_ctrl),
1748
1749 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0,
1750 &rt5682_dac_l_mux),
1751 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0,
1752 &rt5682_dac_r_mux),
1753
1754 /* Audio Interface */
1755 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
1756 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1),
1757 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1758 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1),
1759 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1760 SND_SOC_DAPM_AIF_IN("SDWRX", "SDW Playback", 0, SND_SOC_NOPM, 0, 0),
1761 SND_SOC_DAPM_AIF_OUT("SDWTX", "SDW Capture", 0, SND_SOC_NOPM, 0, 0),
1762
1763 /* Output Side */
1764 /* DAC mixer before sound effect */
1765 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1766 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)),
1767 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1768 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)),
1769
1770 /* DAC channel Mux */
1771 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
1772 &rt5682_alg_dac_l1_mux),
1773 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
1774 &rt5682_alg_dac_r1_mux),
1775
1776 /* DAC Mixer */
1777 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2,
1778 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk,
1779 SND_SOC_DAPM_PRE_PMU),
1780 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1781 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)),
1782 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1783 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)),
1784
1785 /* DACs */
1786 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1,
1787 RT5682_PWR_DAC_L1_BIT, 0),
1788 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1,
1789 RT5682_PWR_DAC_R1_BIT, 0),
1790 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC,
1791 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0),
1792
1793 /* HPO */
1794 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event,
1795 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
1796
1797 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1,
1798 RT5682_PWR_HA_L_BIT, 0, NULL, 0),
1799 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1,
1800 RT5682_PWR_HA_R_BIT, 0, NULL, 0),
1801 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1,
1802 RT5682_PUMP_EN_SFT, 0, NULL, 0),
1803 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1,
1804 RT5682_CAPLESS_EN_SFT, 0, NULL, 0),
1805
1806 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
1807 &hpol_switch),
1808 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
1809 &hpor_switch),
1810
1811 /* CLK DET */
1812 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET,
1813 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0),
1814 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET,
1815 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0),
1816 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET,
1817 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0),
1818 SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET,
1819 RT5682_POW_CLK_DET_SFT, 0, NULL, 0),
1820
1821 /* Output Lines */
1822 SND_SOC_DAPM_OUTPUT("HPOL"),
1823 SND_SOC_DAPM_OUTPUT("HPOR"),
1824 };
1825
1826 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = {
1827 /*PLL*/
1828 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1829 {"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1830 {"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1831 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1832 {"DAC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1833 {"DAC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1834
1835 /*ASRC*/
1836 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1837 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1838 {"ADC STO1 ASRC", NULL, "AD ASRC"},
1839 {"ADC STO1 ASRC", NULL, "DA ASRC"},
1840 {"ADC STO1 ASRC", NULL, "CLKDET"},
1841 {"DAC STO1 ASRC", NULL, "AD ASRC"},
1842 {"DAC STO1 ASRC", NULL, "DA ASRC"},
1843 {"DAC STO1 ASRC", NULL, "CLKDET"},
1844
1845 /*Vref*/
1846 {"MICBIAS1", NULL, "Vref1"},
1847 {"MICBIAS2", NULL, "Vref1"},
1848
1849 {"CLKDET SYS", NULL, "CLKDET"},
1850
1851 {"IN1P", NULL, "LDO2"},
1852
1853 {"BST1 CBJ", NULL, "IN1P"},
1854
1855 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1856 {"RECMIX1L", NULL, "RECMIX1L Power"},
1857
1858 {"ADC1 L", NULL, "RECMIX1L"},
1859 {"ADC1 L", NULL, "ADC1 L Power"},
1860 {"ADC1 L", NULL, "ADC1 clock"},
1861
1862 {"DMIC L1", NULL, "DMIC CLK"},
1863 {"DMIC L1", NULL, "DMIC1 Power"},
1864 {"DMIC R1", NULL, "DMIC CLK"},
1865 {"DMIC R1", NULL, "DMIC1 Power"},
1866 {"DMIC CLK", NULL, "DMIC ASRC"},
1867
1868 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1869 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1870 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1871 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1872
1873 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1874 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1875 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1876 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1877
1878 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1879 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1880 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1881 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1882
1883 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1884 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1885 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1886
1887 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1888 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1889 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1890
1891 {"ADC Stereo1 Filter", NULL, "BTN Detection Mode"},
1892
1893 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1894 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1895
1896 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1897 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1898 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1899 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1900 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1901 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1902 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1903 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1904 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1905 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1906 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1907 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1908 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1909 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1910 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1911 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1912
1913 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1914 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1915 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1916 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1917 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1918 {"AIF1TX", NULL, "I2S1"},
1919 {"AIF1TX", NULL, "ADCDAT Mux"},
1920 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1921 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1922 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1923 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1924 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1925 {"AIF2TX", NULL, "ADCDAT Mux"},
1926
1927 {"SDWTX", NULL, "PLL2B"},
1928 {"SDWTX", NULL, "PLL2F"},
1929 {"SDWTX", NULL, "ADCDAT Mux"},
1930
1931 {"IF1 DAC1 L", NULL, "AIF1RX"},
1932 {"IF1 DAC1 L", NULL, "I2S1"},
1933 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1934 {"IF1 DAC1 R", NULL, "AIF1RX"},
1935 {"IF1 DAC1 R", NULL, "I2S1"},
1936 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1937
1938 {"SOUND DAC L", NULL, "SDWRX"},
1939 {"SOUND DAC L", NULL, "DAC Stereo1 Filter"},
1940 {"SOUND DAC L", NULL, "PLL2B"},
1941 {"SOUND DAC L", NULL, "PLL2F"},
1942 {"SOUND DAC R", NULL, "SDWRX"},
1943 {"SOUND DAC R", NULL, "DAC Stereo1 Filter"},
1944 {"SOUND DAC R", NULL, "PLL2B"},
1945 {"SOUND DAC R", NULL, "PLL2F"},
1946
1947 {"DAC L Mux", "IF1", "IF1 DAC1 L"},
1948 {"DAC L Mux", "SOUND", "SOUND DAC L"},
1949 {"DAC R Mux", "IF1", "IF1 DAC1 R"},
1950 {"DAC R Mux", "SOUND", "SOUND DAC R"},
1951
1952 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1953 {"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"},
1954 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1955 {"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"},
1956
1957 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
1958 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
1959
1960 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
1961 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
1962
1963 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
1964 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
1965 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
1966 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
1967
1968 {"DAC L1", NULL, "DAC L1 Source"},
1969 {"DAC R1", NULL, "DAC R1 Source"},
1970
1971 {"DAC L1", NULL, "DAC 1 Clock"},
1972 {"DAC R1", NULL, "DAC 1 Clock"},
1973
1974 {"HP Amp", NULL, "DAC L1"},
1975 {"HP Amp", NULL, "DAC R1"},
1976 {"HP Amp", NULL, "HP Amp L"},
1977 {"HP Amp", NULL, "HP Amp R"},
1978 {"HP Amp", NULL, "Capless"},
1979 {"HP Amp", NULL, "Charge Pump"},
1980 {"HP Amp", NULL, "CLKDET SYS"},
1981 {"HP Amp", NULL, "Vref1"},
1982 {"HPOL Playback", "Switch", "HP Amp"},
1983 {"HPOR Playback", "Switch", "HP Amp"},
1984 {"HPOL", NULL, "HPOL Playback"},
1985 {"HPOR", NULL, "HPOR Playback"},
1986 };
1987
rt5682_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)1988 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1989 unsigned int rx_mask, int slots, int slot_width)
1990 {
1991 struct snd_soc_component *component = dai->component;
1992 unsigned int cl, val = 0;
1993
1994 if (tx_mask || rx_mask)
1995 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
1996 RT5682_TDM_EN, RT5682_TDM_EN);
1997 else
1998 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
1999 RT5682_TDM_EN, 0);
2000
2001 switch (slots) {
2002 case 4:
2003 val |= RT5682_TDM_TX_CH_4;
2004 val |= RT5682_TDM_RX_CH_4;
2005 break;
2006 case 6:
2007 val |= RT5682_TDM_TX_CH_6;
2008 val |= RT5682_TDM_RX_CH_6;
2009 break;
2010 case 8:
2011 val |= RT5682_TDM_TX_CH_8;
2012 val |= RT5682_TDM_RX_CH_8;
2013 break;
2014 case 2:
2015 break;
2016 default:
2017 return -EINVAL;
2018 }
2019
2020 snd_soc_component_update_bits(component, RT5682_TDM_CTRL,
2021 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val);
2022
2023 switch (slot_width) {
2024 case 8:
2025 if (tx_mask || rx_mask)
2026 return -EINVAL;
2027 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8;
2028 break;
2029 case 16:
2030 val = RT5682_TDM_CL_16;
2031 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16;
2032 break;
2033 case 20:
2034 val = RT5682_TDM_CL_20;
2035 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20;
2036 break;
2037 case 24:
2038 val = RT5682_TDM_CL_24;
2039 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24;
2040 break;
2041 case 32:
2042 val = RT5682_TDM_CL_32;
2043 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32;
2044 break;
2045 default:
2046 return -EINVAL;
2047 }
2048
2049 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2050 RT5682_TDM_CL_MASK, val);
2051 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2052 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl);
2053
2054 return 0;
2055 }
2056
rt5682_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)2057 static int rt5682_hw_params(struct snd_pcm_substream *substream,
2058 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2059 {
2060 struct snd_soc_component *component = dai->component;
2061 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2062 unsigned int len_1 = 0, len_2 = 0;
2063 int pre_div, frame_size;
2064
2065 rt5682->lrck[dai->id] = params_rate(params);
2066 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]);
2067
2068 frame_size = snd_soc_params_to_frame_size(params);
2069 if (frame_size < 0) {
2070 dev_err(component->dev, "Unsupported frame size: %d\n",
2071 frame_size);
2072 return -EINVAL;
2073 }
2074
2075 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
2076 rt5682->lrck[dai->id], pre_div, dai->id);
2077
2078 switch (params_width(params)) {
2079 case 16:
2080 break;
2081 case 20:
2082 len_1 |= RT5682_I2S1_DL_20;
2083 len_2 |= RT5682_I2S2_DL_20;
2084 break;
2085 case 24:
2086 len_1 |= RT5682_I2S1_DL_24;
2087 len_2 |= RT5682_I2S2_DL_24;
2088 break;
2089 case 32:
2090 len_1 |= RT5682_I2S1_DL_32;
2091 len_2 |= RT5682_I2S2_DL_24;
2092 break;
2093 case 8:
2094 len_1 |= RT5682_I2S2_DL_8;
2095 len_2 |= RT5682_I2S2_DL_8;
2096 break;
2097 default:
2098 return -EINVAL;
2099 }
2100
2101 switch (dai->id) {
2102 case RT5682_AIF1:
2103 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2104 RT5682_I2S1_DL_MASK, len_1);
2105 if (rt5682->master[RT5682_AIF1]) {
2106 snd_soc_component_update_bits(component,
2107 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK |
2108 RT5682_I2S_CLK_SRC_MASK,
2109 pre_div << RT5682_I2S_M_DIV_SFT |
2110 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2111 }
2112 if (params_channels(params) == 1) /* mono mode */
2113 snd_soc_component_update_bits(component,
2114 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2115 RT5682_I2S1_MONO_EN);
2116 else
2117 snd_soc_component_update_bits(component,
2118 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2119 RT5682_I2S1_MONO_DIS);
2120 break;
2121 case RT5682_AIF2:
2122 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2123 RT5682_I2S2_DL_MASK, len_2);
2124 if (rt5682->master[RT5682_AIF2]) {
2125 snd_soc_component_update_bits(component,
2126 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK,
2127 pre_div << RT5682_I2S2_M_PD_SFT);
2128 }
2129 if (params_channels(params) == 1) /* mono mode */
2130 snd_soc_component_update_bits(component,
2131 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2132 RT5682_I2S2_MONO_EN);
2133 else
2134 snd_soc_component_update_bits(component,
2135 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2136 RT5682_I2S2_MONO_DIS);
2137 break;
2138 default:
2139 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2140 return -EINVAL;
2141 }
2142
2143 return 0;
2144 }
2145
rt5682_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)2146 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2147 {
2148 struct snd_soc_component *component = dai->component;
2149 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2150 unsigned int reg_val = 0, tdm_ctrl = 0;
2151
2152 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2153 case SND_SOC_DAIFMT_CBM_CFM:
2154 rt5682->master[dai->id] = 1;
2155 break;
2156 case SND_SOC_DAIFMT_CBS_CFS:
2157 rt5682->master[dai->id] = 0;
2158 break;
2159 default:
2160 return -EINVAL;
2161 }
2162
2163 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2164 case SND_SOC_DAIFMT_NB_NF:
2165 break;
2166 case SND_SOC_DAIFMT_IB_NF:
2167 reg_val |= RT5682_I2S_BP_INV;
2168 tdm_ctrl |= RT5682_TDM_S_BP_INV;
2169 break;
2170 case SND_SOC_DAIFMT_NB_IF:
2171 if (dai->id == RT5682_AIF1)
2172 tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV;
2173 else
2174 return -EINVAL;
2175 break;
2176 case SND_SOC_DAIFMT_IB_IF:
2177 if (dai->id == RT5682_AIF1)
2178 tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV |
2179 RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV;
2180 else
2181 return -EINVAL;
2182 break;
2183 default:
2184 return -EINVAL;
2185 }
2186
2187 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2188 case SND_SOC_DAIFMT_I2S:
2189 break;
2190 case SND_SOC_DAIFMT_LEFT_J:
2191 reg_val |= RT5682_I2S_DF_LEFT;
2192 tdm_ctrl |= RT5682_TDM_DF_LEFT;
2193 break;
2194 case SND_SOC_DAIFMT_DSP_A:
2195 reg_val |= RT5682_I2S_DF_PCM_A;
2196 tdm_ctrl |= RT5682_TDM_DF_PCM_A;
2197 break;
2198 case SND_SOC_DAIFMT_DSP_B:
2199 reg_val |= RT5682_I2S_DF_PCM_B;
2200 tdm_ctrl |= RT5682_TDM_DF_PCM_B;
2201 break;
2202 default:
2203 return -EINVAL;
2204 }
2205
2206 switch (dai->id) {
2207 case RT5682_AIF1:
2208 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2209 RT5682_I2S_DF_MASK, reg_val);
2210 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2211 RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK |
2212 RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK |
2213 RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK,
2214 tdm_ctrl | rt5682->master[dai->id]);
2215 break;
2216 case RT5682_AIF2:
2217 if (rt5682->master[dai->id] == 0)
2218 reg_val |= RT5682_I2S2_MS_S;
2219 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2220 RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK |
2221 RT5682_I2S_DF_MASK, reg_val);
2222 break;
2223 default:
2224 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2225 return -EINVAL;
2226 }
2227 return 0;
2228 }
2229
rt5682_set_component_sysclk(struct snd_soc_component * component,int clk_id,int source,unsigned int freq,int dir)2230 static int rt5682_set_component_sysclk(struct snd_soc_component *component,
2231 int clk_id, int source, unsigned int freq, int dir)
2232 {
2233 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2234 unsigned int reg_val = 0, src = 0;
2235
2236 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src)
2237 return 0;
2238
2239 switch (clk_id) {
2240 case RT5682_SCLK_S_MCLK:
2241 reg_val |= RT5682_SCLK_SRC_MCLK;
2242 src = RT5682_CLK_SRC_MCLK;
2243 break;
2244 case RT5682_SCLK_S_PLL1:
2245 reg_val |= RT5682_SCLK_SRC_PLL1;
2246 src = RT5682_CLK_SRC_PLL1;
2247 break;
2248 case RT5682_SCLK_S_PLL2:
2249 reg_val |= RT5682_SCLK_SRC_PLL2;
2250 src = RT5682_CLK_SRC_PLL2;
2251 break;
2252 case RT5682_SCLK_S_RCCLK:
2253 reg_val |= RT5682_SCLK_SRC_RCCLK;
2254 src = RT5682_CLK_SRC_RCCLK;
2255 break;
2256 default:
2257 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2258 return -EINVAL;
2259 }
2260 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2261 RT5682_SCLK_SRC_MASK, reg_val);
2262
2263 if (rt5682->master[RT5682_AIF2]) {
2264 snd_soc_component_update_bits(component,
2265 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK,
2266 src << RT5682_I2S2_SRC_SFT);
2267 }
2268
2269 rt5682->sysclk = freq;
2270 rt5682->sysclk_src = clk_id;
2271
2272 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2273 freq, clk_id);
2274
2275 return 0;
2276 }
2277
rt5682_set_component_pll(struct snd_soc_component * component,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)2278 static int rt5682_set_component_pll(struct snd_soc_component *component,
2279 int pll_id, int source, unsigned int freq_in,
2280 unsigned int freq_out)
2281 {
2282 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2283 struct rl6231_pll_code pll_code, pll2f_code, pll2b_code;
2284 unsigned int pll2_fout1, pll2_ps_val;
2285 int ret;
2286
2287 if (source == rt5682->pll_src[pll_id] &&
2288 freq_in == rt5682->pll_in[pll_id] &&
2289 freq_out == rt5682->pll_out[pll_id])
2290 return 0;
2291
2292 if (!freq_in || !freq_out) {
2293 dev_dbg(component->dev, "PLL disabled\n");
2294
2295 rt5682->pll_in[pll_id] = 0;
2296 rt5682->pll_out[pll_id] = 0;
2297 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2298 RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK);
2299 return 0;
2300 }
2301
2302 if (pll_id == RT5682_PLL2) {
2303 switch (source) {
2304 case RT5682_PLL2_S_MCLK:
2305 snd_soc_component_update_bits(component,
2306 RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK,
2307 RT5682_PLL2_SRC_MCLK);
2308 break;
2309 default:
2310 dev_err(component->dev, "Unknown PLL2 Source %d\n",
2311 source);
2312 return -EINVAL;
2313 }
2314
2315 /**
2316 * PLL2 concatenates 2 PLL units.
2317 * We suggest the Fout of the front PLL is 3.84MHz.
2318 */
2319 pll2_fout1 = 3840000;
2320 ret = rl6231_pll_calc(freq_in, pll2_fout1, &pll2f_code);
2321 if (ret < 0) {
2322 dev_err(component->dev, "Unsupport input clock %d\n",
2323 freq_in);
2324 return ret;
2325 }
2326 dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2327 freq_in, pll2_fout1,
2328 pll2f_code.m_bp,
2329 (pll2f_code.m_bp ? 0 : pll2f_code.m_code),
2330 pll2f_code.n_code, pll2f_code.k_code);
2331
2332 ret = rl6231_pll_calc(pll2_fout1, freq_out, &pll2b_code);
2333 if (ret < 0) {
2334 dev_err(component->dev, "Unsupport input clock %d\n",
2335 pll2_fout1);
2336 return ret;
2337 }
2338 dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2339 pll2_fout1, freq_out,
2340 pll2b_code.m_bp,
2341 (pll2b_code.m_bp ? 0 : pll2b_code.m_code),
2342 pll2b_code.n_code, pll2b_code.k_code);
2343
2344 snd_soc_component_write(component, RT5682_PLL2_CTRL_1,
2345 pll2f_code.k_code << RT5682_PLL2F_K_SFT |
2346 pll2b_code.k_code << RT5682_PLL2B_K_SFT |
2347 pll2b_code.m_code);
2348 snd_soc_component_write(component, RT5682_PLL2_CTRL_2,
2349 pll2f_code.m_code << RT5682_PLL2F_M_SFT |
2350 pll2b_code.n_code);
2351 snd_soc_component_write(component, RT5682_PLL2_CTRL_3,
2352 pll2f_code.n_code << RT5682_PLL2F_N_SFT);
2353
2354 if (freq_out == 22579200)
2355 pll2_ps_val = 1 << RT5682_PLL2B_SEL_PS_SFT;
2356 else
2357 pll2_ps_val = 1 << RT5682_PLL2B_PS_BYP_SFT;
2358 snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4,
2359 RT5682_PLL2B_SEL_PS_MASK | RT5682_PLL2B_PS_BYP_MASK |
2360 RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf,
2361 pll2_ps_val |
2362 (pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT |
2363 (pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT |
2364 0xf);
2365 } else {
2366 switch (source) {
2367 case RT5682_PLL1_S_MCLK:
2368 snd_soc_component_update_bits(component,
2369 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2370 RT5682_PLL1_SRC_MCLK);
2371 break;
2372 case RT5682_PLL1_S_BCLK1:
2373 snd_soc_component_update_bits(component,
2374 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2375 RT5682_PLL1_SRC_BCLK1);
2376 break;
2377 default:
2378 dev_err(component->dev, "Unknown PLL1 Source %d\n",
2379 source);
2380 return -EINVAL;
2381 }
2382
2383 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2384 if (ret < 0) {
2385 dev_err(component->dev, "Unsupport input clock %d\n",
2386 freq_in);
2387 return ret;
2388 }
2389
2390 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2391 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2392 pll_code.n_code, pll_code.k_code);
2393
2394 snd_soc_component_write(component, RT5682_PLL_CTRL_1,
2395 pll_code.n_code << RT5682_PLL_N_SFT | pll_code.k_code);
2396 snd_soc_component_write(component, RT5682_PLL_CTRL_2,
2397 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT |
2398 pll_code.m_bp << RT5682_PLL_M_BP_SFT | RT5682_PLL_RST);
2399 }
2400
2401 rt5682->pll_in[pll_id] = freq_in;
2402 rt5682->pll_out[pll_id] = freq_out;
2403 rt5682->pll_src[pll_id] = source;
2404
2405 return 0;
2406 }
2407
rt5682_set_bclk1_ratio(struct snd_soc_dai * dai,unsigned int ratio)2408 static int rt5682_set_bclk1_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2409 {
2410 struct snd_soc_component *component = dai->component;
2411 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2412
2413 rt5682->bclk[dai->id] = ratio;
2414
2415 switch (ratio) {
2416 case 256:
2417 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2418 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_256);
2419 break;
2420 case 128:
2421 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2422 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_128);
2423 break;
2424 case 64:
2425 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2426 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_64);
2427 break;
2428 case 32:
2429 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2430 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_32);
2431 break;
2432 default:
2433 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio);
2434 return -EINVAL;
2435 }
2436
2437 return 0;
2438 }
2439
rt5682_set_bclk2_ratio(struct snd_soc_dai * dai,unsigned int ratio)2440 static int rt5682_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2441 {
2442 struct snd_soc_component *component = dai->component;
2443 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2444
2445 rt5682->bclk[dai->id] = ratio;
2446
2447 switch (ratio) {
2448 case 64:
2449 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2450 RT5682_I2S2_BCLK_MS2_MASK,
2451 RT5682_I2S2_BCLK_MS2_64);
2452 break;
2453 case 32:
2454 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2455 RT5682_I2S2_BCLK_MS2_MASK,
2456 RT5682_I2S2_BCLK_MS2_32);
2457 break;
2458 default:
2459 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio);
2460 return -EINVAL;
2461 }
2462
2463 return 0;
2464 }
2465
rt5682_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)2466 static int rt5682_set_bias_level(struct snd_soc_component *component,
2467 enum snd_soc_bias_level level)
2468 {
2469 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2470
2471 switch (level) {
2472 case SND_SOC_BIAS_PREPARE:
2473 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2474 RT5682_PWR_BG, RT5682_PWR_BG);
2475 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2476 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO,
2477 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO);
2478 break;
2479
2480 case SND_SOC_BIAS_STANDBY:
2481 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2482 RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL);
2483 break;
2484 case SND_SOC_BIAS_OFF:
2485 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2486 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0);
2487 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2488 RT5682_PWR_BG, 0);
2489 break;
2490 case SND_SOC_BIAS_ON:
2491 break;
2492 }
2493
2494 return 0;
2495 }
2496
2497 #ifdef CONFIG_COMMON_CLK
2498 #define CLK_PLL2_FIN 48000000
2499 #define CLK_48 48000
2500 #define CLK_44 44100
2501
rt5682_clk_check(struct rt5682_priv * rt5682)2502 static bool rt5682_clk_check(struct rt5682_priv *rt5682)
2503 {
2504 if (!rt5682->master[RT5682_AIF1]) {
2505 dev_dbg(rt5682->component->dev, "sysclk/dai not set correctly\n");
2506 return false;
2507 }
2508 return true;
2509 }
2510
rt5682_wclk_prepare(struct clk_hw * hw)2511 static int rt5682_wclk_prepare(struct clk_hw *hw)
2512 {
2513 struct rt5682_priv *rt5682 =
2514 container_of(hw, struct rt5682_priv,
2515 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2516 struct snd_soc_component *component = rt5682->component;
2517 struct snd_soc_dapm_context *dapm =
2518 snd_soc_component_get_dapm(component);
2519
2520 if (!rt5682_clk_check(rt5682))
2521 return -EINVAL;
2522
2523 snd_soc_dapm_mutex_lock(dapm);
2524
2525 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");
2526 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2527 RT5682_PWR_MB, RT5682_PWR_MB);
2528
2529 snd_soc_dapm_force_enable_pin_unlocked(dapm, "Vref2");
2530 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2531 RT5682_PWR_VREF2 | RT5682_PWR_FV2,
2532 RT5682_PWR_VREF2);
2533 usleep_range(55000, 60000);
2534 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2535 RT5682_PWR_FV2, RT5682_PWR_FV2);
2536
2537 snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1");
2538 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2F");
2539 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2B");
2540 snd_soc_dapm_sync_unlocked(dapm);
2541
2542 snd_soc_dapm_mutex_unlock(dapm);
2543
2544 return 0;
2545 }
2546
rt5682_wclk_unprepare(struct clk_hw * hw)2547 static void rt5682_wclk_unprepare(struct clk_hw *hw)
2548 {
2549 struct rt5682_priv *rt5682 =
2550 container_of(hw, struct rt5682_priv,
2551 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2552 struct snd_soc_component *component = rt5682->component;
2553 struct snd_soc_dapm_context *dapm =
2554 snd_soc_component_get_dapm(component);
2555
2556 if (!rt5682_clk_check(rt5682))
2557 return;
2558
2559 snd_soc_dapm_mutex_lock(dapm);
2560
2561 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");
2562 snd_soc_dapm_disable_pin_unlocked(dapm, "Vref2");
2563 if (!rt5682->jack_type)
2564 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2565 RT5682_PWR_VREF2 | RT5682_PWR_FV2 |
2566 RT5682_PWR_MB, 0);
2567
2568 snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1");
2569 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2F");
2570 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2B");
2571 snd_soc_dapm_sync_unlocked(dapm);
2572
2573 snd_soc_dapm_mutex_unlock(dapm);
2574 }
2575
rt5682_wclk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2576 static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw,
2577 unsigned long parent_rate)
2578 {
2579 struct rt5682_priv *rt5682 =
2580 container_of(hw, struct rt5682_priv,
2581 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2582 struct snd_soc_component *component = rt5682->component;
2583 const char * const clk_name = clk_hw_get_name(hw);
2584
2585 if (!rt5682_clk_check(rt5682))
2586 return 0;
2587 /*
2588 * Only accept to set wclk rate to 44.1k or 48kHz.
2589 */
2590 if (rt5682->lrck[RT5682_AIF1] != CLK_48 &&
2591 rt5682->lrck[RT5682_AIF1] != CLK_44) {
2592 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
2593 __func__, clk_name, CLK_44, CLK_48);
2594 return 0;
2595 }
2596
2597 return rt5682->lrck[RT5682_AIF1];
2598 }
2599
rt5682_wclk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)2600 static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
2601 unsigned long *parent_rate)
2602 {
2603 struct rt5682_priv *rt5682 =
2604 container_of(hw, struct rt5682_priv,
2605 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2606 struct snd_soc_component *component = rt5682->component;
2607 const char * const clk_name = clk_hw_get_name(hw);
2608
2609 if (!rt5682_clk_check(rt5682))
2610 return -EINVAL;
2611 /*
2612 * Only accept to set wclk rate to 44.1k or 48kHz.
2613 * It will force to 48kHz if not both.
2614 */
2615 if (rate != CLK_48 && rate != CLK_44) {
2616 dev_warn(component->dev, "%s: clk %s only support %d or %d Hz output\n",
2617 __func__, clk_name, CLK_44, CLK_48);
2618 rate = CLK_48;
2619 }
2620
2621 return rate;
2622 }
2623
rt5682_wclk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)2624 static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
2625 unsigned long parent_rate)
2626 {
2627 struct rt5682_priv *rt5682 =
2628 container_of(hw, struct rt5682_priv,
2629 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2630 struct snd_soc_component *component = rt5682->component;
2631 struct clk *parent_clk;
2632 const char * const clk_name = clk_hw_get_name(hw);
2633 int pre_div;
2634 unsigned int clk_pll2_out;
2635
2636 if (!rt5682_clk_check(rt5682))
2637 return -EINVAL;
2638
2639 /*
2640 * Whether the wclk's parent clk (mclk) exists or not, please ensure
2641 * it is fixed or set to 48MHz before setting wclk rate. It's a
2642 * temporary limitation. Only accept 48MHz clk as the clk provider.
2643 *
2644 * It will set the codec anyway by assuming mclk is 48MHz.
2645 */
2646 parent_clk = clk_get_parent(hw->clk);
2647 if (!parent_clk)
2648 dev_warn(component->dev,
2649 "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",
2650 CLK_PLL2_FIN);
2651
2652 if (parent_rate != CLK_PLL2_FIN)
2653 dev_warn(component->dev, "clk %s only support %d Hz input\n",
2654 clk_name, CLK_PLL2_FIN);
2655
2656 /*
2657 * To achieve the rate conversion from 48MHz to 44.1k or 48kHz,
2658 * PLL2 is needed.
2659 */
2660 clk_pll2_out = rate * 512;
2661 rt5682_set_component_pll(component, RT5682_PLL2, RT5682_PLL2_S_MCLK,
2662 CLK_PLL2_FIN, clk_pll2_out);
2663
2664 rt5682_set_component_sysclk(component, RT5682_SCLK_S_PLL2, 0,
2665 clk_pll2_out, SND_SOC_CLOCK_IN);
2666
2667 rt5682->lrck[RT5682_AIF1] = rate;
2668
2669 pre_div = rl6231_get_clk_info(rt5682->sysclk, rate);
2670
2671 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
2672 RT5682_I2S_M_DIV_MASK | RT5682_I2S_CLK_SRC_MASK,
2673 pre_div << RT5682_I2S_M_DIV_SFT |
2674 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2675
2676 return 0;
2677 }
2678
rt5682_bclk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2679 static unsigned long rt5682_bclk_recalc_rate(struct clk_hw *hw,
2680 unsigned long parent_rate)
2681 {
2682 struct rt5682_priv *rt5682 =
2683 container_of(hw, struct rt5682_priv,
2684 dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2685 struct snd_soc_component *component = rt5682->component;
2686 unsigned int bclks_per_wclk;
2687
2688 bclks_per_wclk = snd_soc_component_read(component, RT5682_TDM_TCON_CTRL);
2689
2690 switch (bclks_per_wclk & RT5682_TDM_BCLK_MS1_MASK) {
2691 case RT5682_TDM_BCLK_MS1_256:
2692 return parent_rate * 256;
2693 case RT5682_TDM_BCLK_MS1_128:
2694 return parent_rate * 128;
2695 case RT5682_TDM_BCLK_MS1_64:
2696 return parent_rate * 64;
2697 case RT5682_TDM_BCLK_MS1_32:
2698 return parent_rate * 32;
2699 default:
2700 return 0;
2701 }
2702 }
2703
rt5682_bclk_get_factor(unsigned long rate,unsigned long parent_rate)2704 static unsigned long rt5682_bclk_get_factor(unsigned long rate,
2705 unsigned long parent_rate)
2706 {
2707 unsigned long factor;
2708
2709 factor = rate / parent_rate;
2710 if (factor < 64)
2711 return 32;
2712 else if (factor < 128)
2713 return 64;
2714 else if (factor < 256)
2715 return 128;
2716 else
2717 return 256;
2718 }
2719
rt5682_bclk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)2720 static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
2721 unsigned long *parent_rate)
2722 {
2723 struct rt5682_priv *rt5682 =
2724 container_of(hw, struct rt5682_priv,
2725 dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2726 unsigned long factor;
2727
2728 if (!*parent_rate || !rt5682_clk_check(rt5682))
2729 return -EINVAL;
2730
2731 /*
2732 * BCLK rates are set as a multiplier of WCLK in HW.
2733 * We don't allow changing the parent WCLK. We just do
2734 * some rounding down based on the parent WCLK rate
2735 * and find the appropriate multiplier of BCLK to
2736 * get the rounded down BCLK value.
2737 */
2738 factor = rt5682_bclk_get_factor(rate, *parent_rate);
2739
2740 return *parent_rate * factor;
2741 }
2742
rt5682_bclk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)2743 static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
2744 unsigned long parent_rate)
2745 {
2746 struct rt5682_priv *rt5682 =
2747 container_of(hw, struct rt5682_priv,
2748 dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2749 struct snd_soc_component *component = rt5682->component;
2750 struct snd_soc_dai *dai = NULL;
2751 unsigned long factor;
2752
2753 if (!rt5682_clk_check(rt5682))
2754 return -EINVAL;
2755
2756 factor = rt5682_bclk_get_factor(rate, parent_rate);
2757
2758 for_each_component_dais(component, dai)
2759 if (dai->id == RT5682_AIF1)
2760 break;
2761 if (!dai) {
2762 dev_err(component->dev, "dai %d not found in component\n",
2763 RT5682_AIF1);
2764 return -ENODEV;
2765 }
2766
2767 return rt5682_set_bclk1_ratio(dai, factor);
2768 }
2769
2770 static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = {
2771 [RT5682_DAI_WCLK_IDX] = {
2772 .prepare = rt5682_wclk_prepare,
2773 .unprepare = rt5682_wclk_unprepare,
2774 .recalc_rate = rt5682_wclk_recalc_rate,
2775 .round_rate = rt5682_wclk_round_rate,
2776 .set_rate = rt5682_wclk_set_rate,
2777 },
2778 [RT5682_DAI_BCLK_IDX] = {
2779 .recalc_rate = rt5682_bclk_recalc_rate,
2780 .round_rate = rt5682_bclk_round_rate,
2781 .set_rate = rt5682_bclk_set_rate,
2782 },
2783 };
2784
rt5682_register_dai_clks(struct snd_soc_component * component)2785 static int rt5682_register_dai_clks(struct snd_soc_component *component)
2786 {
2787 struct device *dev = component->dev;
2788 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2789 struct rt5682_platform_data *pdata = &rt5682->pdata;
2790 struct clk_hw *dai_clk_hw;
2791 int i, ret;
2792
2793 for (i = 0; i < RT5682_DAI_NUM_CLKS; ++i) {
2794 struct clk_init_data init = { };
2795
2796 dai_clk_hw = &rt5682->dai_clks_hw[i];
2797
2798 switch (i) {
2799 case RT5682_DAI_WCLK_IDX:
2800 /* Make MCLK the parent of WCLK */
2801 if (rt5682->mclk) {
2802 init.parent_data = &(struct clk_parent_data){
2803 .fw_name = "mclk",
2804 };
2805 init.num_parents = 1;
2806 }
2807 break;
2808 case RT5682_DAI_BCLK_IDX:
2809 /* Make WCLK the parent of BCLK */
2810 init.parent_hws = &(const struct clk_hw *){
2811 &rt5682->dai_clks_hw[RT5682_DAI_WCLK_IDX]
2812 };
2813 init.num_parents = 1;
2814 break;
2815 default:
2816 dev_err(dev, "Invalid clock index\n");
2817 return -EINVAL;
2818 }
2819
2820 init.name = pdata->dai_clk_names[i];
2821 init.ops = &rt5682_dai_clk_ops[i];
2822 init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
2823 dai_clk_hw->init = &init;
2824
2825 ret = devm_clk_hw_register(dev, dai_clk_hw);
2826 if (ret) {
2827 dev_warn(dev, "Failed to register %s: %d\n",
2828 init.name, ret);
2829 return ret;
2830 }
2831
2832 if (dev->of_node) {
2833 devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
2834 dai_clk_hw);
2835 } else {
2836 ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw,
2837 init.name,
2838 dev_name(dev));
2839 if (ret)
2840 return ret;
2841 }
2842 }
2843
2844 return 0;
2845 }
2846 #endif /* CONFIG_COMMON_CLK */
2847
rt5682_probe(struct snd_soc_component * component)2848 static int rt5682_probe(struct snd_soc_component *component)
2849 {
2850 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2851 struct sdw_slave *slave;
2852 unsigned long time;
2853 struct snd_soc_dapm_context *dapm = &component->dapm;
2854
2855 #ifdef CONFIG_COMMON_CLK
2856 int ret;
2857 #endif
2858 rt5682->component = component;
2859
2860 if (rt5682->is_sdw) {
2861 slave = rt5682->slave;
2862 time = wait_for_completion_timeout(
2863 &slave->initialization_complete,
2864 msecs_to_jiffies(RT5682_PROBE_TIMEOUT));
2865 if (!time) {
2866 dev_err(&slave->dev, "Initialization not complete, timed out\n");
2867 return -ETIMEDOUT;
2868 }
2869 } else {
2870 #ifdef CONFIG_COMMON_CLK
2871 /* Check if MCLK provided */
2872 rt5682->mclk = devm_clk_get(component->dev, "mclk");
2873 if (IS_ERR(rt5682->mclk)) {
2874 if (PTR_ERR(rt5682->mclk) != -ENOENT) {
2875 ret = PTR_ERR(rt5682->mclk);
2876 return ret;
2877 }
2878 rt5682->mclk = NULL;
2879 }
2880
2881 /* Register CCF DAI clock control */
2882 ret = rt5682_register_dai_clks(component);
2883 if (ret)
2884 return ret;
2885
2886 /* Initial setup for CCF */
2887 rt5682->lrck[RT5682_AIF1] = CLK_48;
2888 #endif
2889 }
2890
2891 snd_soc_dapm_disable_pin(dapm, "MICBIAS");
2892 snd_soc_dapm_disable_pin(dapm, "Vref2");
2893 snd_soc_dapm_sync(dapm);
2894 return 0;
2895 }
2896
rt5682_remove(struct snd_soc_component * component)2897 static void rt5682_remove(struct snd_soc_component *component)
2898 {
2899 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2900
2901 rt5682_reset(rt5682);
2902 }
2903
2904 #ifdef CONFIG_PM
rt5682_suspend(struct snd_soc_component * component)2905 static int rt5682_suspend(struct snd_soc_component *component)
2906 {
2907 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2908
2909 regcache_cache_only(rt5682->regmap, true);
2910 regcache_mark_dirty(rt5682->regmap);
2911 return 0;
2912 }
2913
rt5682_resume(struct snd_soc_component * component)2914 static int rt5682_resume(struct snd_soc_component *component)
2915 {
2916 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2917
2918 regcache_cache_only(rt5682->regmap, false);
2919 regcache_sync(rt5682->regmap);
2920
2921 mod_delayed_work(system_power_efficient_wq,
2922 &rt5682->jack_detect_work, msecs_to_jiffies(250));
2923
2924 return 0;
2925 }
2926 #else
2927 #define rt5682_suspend NULL
2928 #define rt5682_resume NULL
2929 #endif
2930
2931 const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {
2932 .hw_params = rt5682_hw_params,
2933 .set_fmt = rt5682_set_dai_fmt,
2934 .set_tdm_slot = rt5682_set_tdm_slot,
2935 .set_bclk_ratio = rt5682_set_bclk1_ratio,
2936 };
2937 EXPORT_SYMBOL_GPL(rt5682_aif1_dai_ops);
2938
2939 const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {
2940 .hw_params = rt5682_hw_params,
2941 .set_fmt = rt5682_set_dai_fmt,
2942 .set_bclk_ratio = rt5682_set_bclk2_ratio,
2943 };
2944 EXPORT_SYMBOL_GPL(rt5682_aif2_dai_ops);
2945
2946 const struct snd_soc_component_driver rt5682_soc_component_dev = {
2947 .probe = rt5682_probe,
2948 .remove = rt5682_remove,
2949 .suspend = rt5682_suspend,
2950 .resume = rt5682_resume,
2951 .set_bias_level = rt5682_set_bias_level,
2952 .controls = rt5682_snd_controls,
2953 .num_controls = ARRAY_SIZE(rt5682_snd_controls),
2954 .dapm_widgets = rt5682_dapm_widgets,
2955 .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets),
2956 .dapm_routes = rt5682_dapm_routes,
2957 .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes),
2958 .set_sysclk = rt5682_set_component_sysclk,
2959 .set_pll = rt5682_set_component_pll,
2960 .set_jack = rt5682_set_jack_detect,
2961 .use_pmdown_time = 1,
2962 .endianness = 1,
2963 .non_legacy_dai_naming = 1,
2964 };
2965 EXPORT_SYMBOL_GPL(rt5682_soc_component_dev);
2966
rt5682_parse_dt(struct rt5682_priv * rt5682,struct device * dev)2967 int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
2968 {
2969
2970 device_property_read_u32(dev, "realtek,dmic1-data-pin",
2971 &rt5682->pdata.dmic1_data_pin);
2972 device_property_read_u32(dev, "realtek,dmic1-clk-pin",
2973 &rt5682->pdata.dmic1_clk_pin);
2974 device_property_read_u32(dev, "realtek,jd-src",
2975 &rt5682->pdata.jd_src);
2976 device_property_read_u32(dev, "realtek,btndet-delay",
2977 &rt5682->pdata.btndet_delay);
2978 device_property_read_u32(dev, "realtek,dmic-clk-rate-hz",
2979 &rt5682->pdata.dmic_clk_rate);
2980 device_property_read_u32(dev, "realtek,dmic-delay-ms",
2981 &rt5682->pdata.dmic_delay);
2982
2983 rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
2984 "realtek,ldo1-en-gpios", 0);
2985
2986 if (device_property_read_string_array(dev, "clock-output-names",
2987 rt5682->pdata.dai_clk_names,
2988 RT5682_DAI_NUM_CLKS) < 0)
2989 dev_warn(dev, "Using default DAI clk names: %s, %s\n",
2990 rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX],
2991 rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]);
2992
2993 return 0;
2994 }
2995 EXPORT_SYMBOL_GPL(rt5682_parse_dt);
2996
rt5682_calibrate(struct rt5682_priv * rt5682)2997 void rt5682_calibrate(struct rt5682_priv *rt5682)
2998 {
2999 int value, count;
3000
3001 mutex_lock(&rt5682->calibrate_mutex);
3002
3003 rt5682_reset(rt5682);
3004 regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f);
3005 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af);
3006 usleep_range(15000, 20000);
3007 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af);
3008 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300);
3009 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000);
3010 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100);
3011 regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800);
3012 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000);
3013 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005);
3014 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c);
3015 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d);
3016 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321);
3017 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004);
3018 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
3019 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1);
3020 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311);
3021 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
3022
3023 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00);
3024
3025 for (count = 0; count < 60; count++) {
3026 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value);
3027 if (!(value & 0x8000))
3028 break;
3029
3030 usleep_range(10000, 10005);
3031 }
3032
3033 if (count >= 60)
3034 dev_err(rt5682->component->dev, "HP Calibration Failure\n");
3035
3036 /* restore settings */
3037 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x002f);
3038 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080);
3039 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000);
3040 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000);
3041 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000);
3042 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005);
3043 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4);
3044 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0c0c);
3045
3046 mutex_unlock(&rt5682->calibrate_mutex);
3047 }
3048 EXPORT_SYMBOL_GPL(rt5682_calibrate);
3049
3050 MODULE_DESCRIPTION("ASoC RT5682 driver");
3051 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
3052 MODULE_LICENSE("GPL v2");
3053
