1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/err.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 #include <soc/qcom/cmd-db.h>
14 #include <soc/qcom/rpmh.h>
15 #include <soc/qcom/tcs.h>
16
17 #include <dt-bindings/clock/qcom,rpmh.h>
18
19 #define CLK_RPMH_ARC_EN_OFFSET 0
20 #define CLK_RPMH_VRM_EN_OFFSET 4
21
22 /**
23 * struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager(BCM)
24 * @unit: divisor used to convert Hz value to an RPMh msg
25 * @width: multiplier used to convert Hz value to an RPMh msg
26 * @vcd: virtual clock domain that this bcm belongs to
27 * @reserved: reserved to pad the struct
28 */
29 struct bcm_db {
30 __le32 unit;
31 __le16 width;
32 u8 vcd;
33 u8 reserved;
34 };
35
36 /**
37 * struct clk_rpmh - individual rpmh clock data structure
38 * @hw: handle between common and hardware-specific interfaces
39 * @res_name: resource name for the rpmh clock
40 * @div: clock divider to compute the clock rate
41 * @res_addr: base address of the rpmh resource within the RPMh
42 * @res_on_val: rpmh clock enable value
43 * @state: rpmh clock requested state
44 * @aggr_state: rpmh clock aggregated state
45 * @last_sent_aggr_state: rpmh clock last aggr state sent to RPMh
46 * @valid_state_mask: mask to determine the state of the rpmh clock
47 * @unit: divisor to convert rate to rpmh msg in magnitudes of Khz
48 * @dev: device to which it is attached
49 * @peer: pointer to the clock rpmh sibling
50 */
51 struct clk_rpmh {
52 struct clk_hw hw;
53 const char *res_name;
54 u8 div;
55 u32 res_addr;
56 u32 res_on_val;
57 u32 state;
58 u32 aggr_state;
59 u32 last_sent_aggr_state;
60 u32 valid_state_mask;
61 u32 unit;
62 struct device *dev;
63 struct clk_rpmh *peer;
64 };
65
66 struct clk_rpmh_desc {
67 struct clk_hw **clks;
68 size_t num_clks;
69 };
70
71 static DEFINE_MUTEX(rpmh_clk_lock);
72
73 #define __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \
74 _res_en_offset, _res_on, _div) \
75 static struct clk_rpmh _platform##_##_name_active; \
76 static struct clk_rpmh _platform##_##_name = { \
77 .res_name = _res_name, \
78 .res_addr = _res_en_offset, \
79 .res_on_val = _res_on, \
80 .div = _div, \
81 .peer = &_platform##_##_name_active, \
82 .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \
83 BIT(RPMH_ACTIVE_ONLY_STATE) | \
84 BIT(RPMH_SLEEP_STATE)), \
85 .hw.init = &(struct clk_init_data){ \
86 .ops = &clk_rpmh_ops, \
87 .name = #_name, \
88 .parent_data = &(const struct clk_parent_data){ \
89 .fw_name = "xo", \
90 .name = "xo_board", \
91 }, \
92 .num_parents = 1, \
93 }, \
94 }; \
95 static struct clk_rpmh _platform##_##_name_active = { \
96 .res_name = _res_name, \
97 .res_addr = _res_en_offset, \
98 .res_on_val = _res_on, \
99 .div = _div, \
100 .peer = &_platform##_##_name, \
101 .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) | \
102 BIT(RPMH_ACTIVE_ONLY_STATE)), \
103 .hw.init = &(struct clk_init_data){ \
104 .ops = &clk_rpmh_ops, \
105 .name = #_name_active, \
106 .parent_data = &(const struct clk_parent_data){ \
107 .fw_name = "xo", \
108 .name = "xo_board", \
109 }, \
110 .num_parents = 1, \
111 }, \
112 }
113
114 #define DEFINE_CLK_RPMH_ARC(_platform, _name, _name_active, _res_name, \
115 _res_on, _div) \
116 __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \
117 CLK_RPMH_ARC_EN_OFFSET, _res_on, _div)
118
119 #define DEFINE_CLK_RPMH_VRM(_platform, _name, _name_active, _res_name, \
120 _div) \
121 __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name, \
122 CLK_RPMH_VRM_EN_OFFSET, 1, _div)
123
124 #define DEFINE_CLK_RPMH_BCM(_platform, _name, _res_name) \
125 static struct clk_rpmh _platform##_##_name = { \
126 .res_name = _res_name, \
127 .valid_state_mask = BIT(RPMH_ACTIVE_ONLY_STATE), \
128 .div = 1, \
129 .hw.init = &(struct clk_init_data){ \
130 .ops = &clk_rpmh_bcm_ops, \
131 .name = #_name, \
132 }, \
133 }
134
to_clk_rpmh(struct clk_hw * _hw)135 static inline struct clk_rpmh *to_clk_rpmh(struct clk_hw *_hw)
136 {
137 return container_of(_hw, struct clk_rpmh, hw);
138 }
139
has_state_changed(struct clk_rpmh * c,u32 state)140 static inline bool has_state_changed(struct clk_rpmh *c, u32 state)
141 {
142 return (c->last_sent_aggr_state & BIT(state))
143 != (c->aggr_state & BIT(state));
144 }
145
clk_rpmh_send_aggregate_command(struct clk_rpmh * c)146 static int clk_rpmh_send_aggregate_command(struct clk_rpmh *c)
147 {
148 struct tcs_cmd cmd = { 0 };
149 u32 cmd_state, on_val;
150 enum rpmh_state state = RPMH_SLEEP_STATE;
151 int ret;
152
153 cmd.addr = c->res_addr;
154 cmd_state = c->aggr_state;
155 on_val = c->res_on_val;
156
157 for (; state <= RPMH_ACTIVE_ONLY_STATE; state++) {
158 if (has_state_changed(c, state)) {
159 if (cmd_state & BIT(state))
160 cmd.data = on_val;
161
162 ret = rpmh_write_async(c->dev, state, &cmd, 1);
163 if (ret) {
164 dev_err(c->dev, "set %s state of %s failed: (%d)\n",
165 !state ? "sleep" :
166 state == RPMH_WAKE_ONLY_STATE ?
167 "wake" : "active", c->res_name, ret);
168 return ret;
169 }
170 }
171 }
172
173 c->last_sent_aggr_state = c->aggr_state;
174 c->peer->last_sent_aggr_state = c->last_sent_aggr_state;
175
176 return 0;
177 }
178
179 /*
180 * Update state and aggregate state values based on enable value.
181 */
clk_rpmh_aggregate_state_send_command(struct clk_rpmh * c,bool enable)182 static int clk_rpmh_aggregate_state_send_command(struct clk_rpmh *c,
183 bool enable)
184 {
185 int ret;
186
187 /* Nothing required to be done if already off or on */
188 if (enable == c->state)
189 return 0;
190
191 c->state = enable ? c->valid_state_mask : 0;
192 c->aggr_state = c->state | c->peer->state;
193 c->peer->aggr_state = c->aggr_state;
194
195 ret = clk_rpmh_send_aggregate_command(c);
196 if (!ret)
197 return 0;
198
199 if (ret && enable)
200 c->state = 0;
201 else if (ret)
202 c->state = c->valid_state_mask;
203
204 WARN(1, "clk: %s failed to %s\n", c->res_name,
205 enable ? "enable" : "disable");
206 return ret;
207 }
208
clk_rpmh_prepare(struct clk_hw * hw)209 static int clk_rpmh_prepare(struct clk_hw *hw)
210 {
211 struct clk_rpmh *c = to_clk_rpmh(hw);
212 int ret = 0;
213
214 mutex_lock(&rpmh_clk_lock);
215 ret = clk_rpmh_aggregate_state_send_command(c, true);
216 mutex_unlock(&rpmh_clk_lock);
217
218 return ret;
219 };
220
clk_rpmh_unprepare(struct clk_hw * hw)221 static void clk_rpmh_unprepare(struct clk_hw *hw)
222 {
223 struct clk_rpmh *c = to_clk_rpmh(hw);
224
225 mutex_lock(&rpmh_clk_lock);
226 clk_rpmh_aggregate_state_send_command(c, false);
227 mutex_unlock(&rpmh_clk_lock);
228 };
229
clk_rpmh_recalc_rate(struct clk_hw * hw,unsigned long prate)230 static unsigned long clk_rpmh_recalc_rate(struct clk_hw *hw,
231 unsigned long prate)
232 {
233 struct clk_rpmh *r = to_clk_rpmh(hw);
234
235 /*
236 * RPMh clocks have a fixed rate. Return static rate.
237 */
238 return prate / r->div;
239 }
240
241 static const struct clk_ops clk_rpmh_ops = {
242 .prepare = clk_rpmh_prepare,
243 .unprepare = clk_rpmh_unprepare,
244 .recalc_rate = clk_rpmh_recalc_rate,
245 };
246
clk_rpmh_bcm_send_cmd(struct clk_rpmh * c,bool enable)247 static int clk_rpmh_bcm_send_cmd(struct clk_rpmh *c, bool enable)
248 {
249 struct tcs_cmd cmd = { 0 };
250 u32 cmd_state;
251 int ret;
252
253 mutex_lock(&rpmh_clk_lock);
254
255 cmd_state = 0;
256 if (enable) {
257 cmd_state = 1;
258 if (c->aggr_state)
259 cmd_state = c->aggr_state;
260 }
261
262 if (c->last_sent_aggr_state == cmd_state) {
263 mutex_unlock(&rpmh_clk_lock);
264 return 0;
265 }
266
267 cmd.addr = c->res_addr;
268 cmd.data = BCM_TCS_CMD(1, enable, 0, cmd_state);
269
270 ret = rpmh_write_async(c->dev, RPMH_ACTIVE_ONLY_STATE, &cmd, 1);
271 if (ret) {
272 dev_err(c->dev, "set active state of %s failed: (%d)\n",
273 c->res_name, ret);
274 mutex_unlock(&rpmh_clk_lock);
275 return ret;
276 }
277
278 c->last_sent_aggr_state = cmd_state;
279
280 mutex_unlock(&rpmh_clk_lock);
281
282 return 0;
283 }
284
clk_rpmh_bcm_prepare(struct clk_hw * hw)285 static int clk_rpmh_bcm_prepare(struct clk_hw *hw)
286 {
287 struct clk_rpmh *c = to_clk_rpmh(hw);
288
289 return clk_rpmh_bcm_send_cmd(c, true);
290 };
291
clk_rpmh_bcm_unprepare(struct clk_hw * hw)292 static void clk_rpmh_bcm_unprepare(struct clk_hw *hw)
293 {
294 struct clk_rpmh *c = to_clk_rpmh(hw);
295
296 clk_rpmh_bcm_send_cmd(c, false);
297 };
298
clk_rpmh_bcm_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)299 static int clk_rpmh_bcm_set_rate(struct clk_hw *hw, unsigned long rate,
300 unsigned long parent_rate)
301 {
302 struct clk_rpmh *c = to_clk_rpmh(hw);
303
304 c->aggr_state = rate / c->unit;
305 /*
306 * Since any non-zero value sent to hw would result in enabling the
307 * clock, only send the value if the clock has already been prepared.
308 */
309 if (clk_hw_is_prepared(hw))
310 clk_rpmh_bcm_send_cmd(c, true);
311
312 return 0;
313 };
314
clk_rpmh_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)315 static long clk_rpmh_round_rate(struct clk_hw *hw, unsigned long rate,
316 unsigned long *parent_rate)
317 {
318 return rate;
319 }
320
clk_rpmh_bcm_recalc_rate(struct clk_hw * hw,unsigned long prate)321 static unsigned long clk_rpmh_bcm_recalc_rate(struct clk_hw *hw,
322 unsigned long prate)
323 {
324 struct clk_rpmh *c = to_clk_rpmh(hw);
325
326 return c->aggr_state * c->unit;
327 }
328
329 static const struct clk_ops clk_rpmh_bcm_ops = {
330 .prepare = clk_rpmh_bcm_prepare,
331 .unprepare = clk_rpmh_bcm_unprepare,
332 .set_rate = clk_rpmh_bcm_set_rate,
333 .round_rate = clk_rpmh_round_rate,
334 .recalc_rate = clk_rpmh_bcm_recalc_rate,
335 };
336
337 /* Resource name must match resource id present in cmd-db. */
338 DEFINE_CLK_RPMH_ARC(sdm845, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2);
339 DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2);
340 DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);
341 DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, rf_clk1_ao, "rfclka1", 1);
342 DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, rf_clk2_ao, "rfclka2", 1);
343 DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, rf_clk3_ao, "rfclka3", 1);
344 DEFINE_CLK_RPMH_BCM(sdm845, ipa, "IP0");
345
346 static struct clk_hw *sdm845_rpmh_clocks[] = {
347 [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
348 [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
349 [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
350 [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
351 [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
352 [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
353 [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
354 [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
355 [RPMH_RF_CLK2] = &sdm845_rf_clk2.hw,
356 [RPMH_RF_CLK2_A] = &sdm845_rf_clk2_ao.hw,
357 [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
358 [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
359 [RPMH_IPA_CLK] = &sdm845_ipa.hw,
360 };
361
362 static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
363 .clks = sdm845_rpmh_clocks,
364 .num_clks = ARRAY_SIZE(sdm845_rpmh_clocks),
365 };
366
367 DEFINE_CLK_RPMH_ARC(sm8150, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2);
368 DEFINE_CLK_RPMH_VRM(sm8150, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2);
369 DEFINE_CLK_RPMH_VRM(sm8150, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);
370 DEFINE_CLK_RPMH_VRM(sm8150, rf_clk1, rf_clk1_ao, "rfclka1", 1);
371 DEFINE_CLK_RPMH_VRM(sm8150, rf_clk2, rf_clk2_ao, "rfclka2", 1);
372 DEFINE_CLK_RPMH_VRM(sm8150, rf_clk3, rf_clk3_ao, "rfclka3", 1);
373
374 static struct clk_hw *sm8150_rpmh_clocks[] = {
375 [RPMH_CXO_CLK] = &sm8150_bi_tcxo.hw,
376 [RPMH_CXO_CLK_A] = &sm8150_bi_tcxo_ao.hw,
377 [RPMH_LN_BB_CLK2] = &sm8150_ln_bb_clk2.hw,
378 [RPMH_LN_BB_CLK2_A] = &sm8150_ln_bb_clk2_ao.hw,
379 [RPMH_LN_BB_CLK3] = &sm8150_ln_bb_clk3.hw,
380 [RPMH_LN_BB_CLK3_A] = &sm8150_ln_bb_clk3_ao.hw,
381 [RPMH_RF_CLK1] = &sm8150_rf_clk1.hw,
382 [RPMH_RF_CLK1_A] = &sm8150_rf_clk1_ao.hw,
383 [RPMH_RF_CLK2] = &sm8150_rf_clk2.hw,
384 [RPMH_RF_CLK2_A] = &sm8150_rf_clk2_ao.hw,
385 [RPMH_RF_CLK3] = &sm8150_rf_clk3.hw,
386 [RPMH_RF_CLK3_A] = &sm8150_rf_clk3_ao.hw,
387 };
388
389 static const struct clk_rpmh_desc clk_rpmh_sm8150 = {
390 .clks = sm8150_rpmh_clocks,
391 .num_clks = ARRAY_SIZE(sm8150_rpmh_clocks),
392 };
393
of_clk_rpmh_hw_get(struct of_phandle_args * clkspec,void * data)394 static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
395 void *data)
396 {
397 struct clk_rpmh_desc *rpmh = data;
398 unsigned int idx = clkspec->args[0];
399
400 if (idx >= rpmh->num_clks) {
401 pr_err("%s: invalid index %u\n", __func__, idx);
402 return ERR_PTR(-EINVAL);
403 }
404
405 return rpmh->clks[idx];
406 }
407
clk_rpmh_probe(struct platform_device * pdev)408 static int clk_rpmh_probe(struct platform_device *pdev)
409 {
410 struct clk_hw **hw_clks;
411 struct clk_rpmh *rpmh_clk;
412 const struct clk_rpmh_desc *desc;
413 int ret, i;
414
415 desc = of_device_get_match_data(&pdev->dev);
416 if (!desc)
417 return -ENODEV;
418
419 hw_clks = desc->clks;
420
421 for (i = 0; i < desc->num_clks; i++) {
422 const char *name = hw_clks[i]->init->name;
423 u32 res_addr;
424 size_t aux_data_len;
425 const struct bcm_db *data;
426
427 rpmh_clk = to_clk_rpmh(hw_clks[i]);
428 res_addr = cmd_db_read_addr(rpmh_clk->res_name);
429 if (!res_addr) {
430 dev_err(&pdev->dev, "missing RPMh resource address for %s\n",
431 rpmh_clk->res_name);
432 return -ENODEV;
433 }
434
435 data = cmd_db_read_aux_data(rpmh_clk->res_name, &aux_data_len);
436 if (IS_ERR(data)) {
437 ret = PTR_ERR(data);
438 dev_err(&pdev->dev,
439 "error reading RPMh aux data for %s (%d)\n",
440 rpmh_clk->res_name, ret);
441 return ret;
442 }
443
444 /* Convert unit from Khz to Hz */
445 if (aux_data_len == sizeof(*data))
446 rpmh_clk->unit = le32_to_cpu(data->unit) * 1000ULL;
447
448 rpmh_clk->res_addr += res_addr;
449 rpmh_clk->dev = &pdev->dev;
450
451 ret = devm_clk_hw_register(&pdev->dev, hw_clks[i]);
452 if (ret) {
453 dev_err(&pdev->dev, "failed to register %s\n", name);
454 return ret;
455 }
456 }
457
458 /* typecast to silence compiler warning */
459 ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_rpmh_hw_get,
460 (void *)desc);
461 if (ret) {
462 dev_err(&pdev->dev, "Failed to add clock provider\n");
463 return ret;
464 }
465
466 dev_dbg(&pdev->dev, "Registered RPMh clocks\n");
467
468 return 0;
469 }
470
471 static const struct of_device_id clk_rpmh_match_table[] = {
472 { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
473 { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
474 { }
475 };
476 MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);
477
478 static struct platform_driver clk_rpmh_driver = {
479 .probe = clk_rpmh_probe,
480 .driver = {
481 .name = "clk-rpmh",
482 .of_match_table = clk_rpmh_match_table,
483 },
484 };
485
clk_rpmh_init(void)486 static int __init clk_rpmh_init(void)
487 {
488 return platform_driver_register(&clk_rpmh_driver);
489 }
490 subsys_initcall(clk_rpmh_init);
491
clk_rpmh_exit(void)492 static void __exit clk_rpmh_exit(void)
493 {
494 platform_driver_unregister(&clk_rpmh_driver);
495 }
496 module_exit(clk_rpmh_exit);
497
498 MODULE_DESCRIPTION("QCOM RPMh Clock Driver");
499 MODULE_LICENSE("GPL v2");
500
