1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Hantro VPU codec driver
4 *
5 * Copyright (C) 2018 Rockchip Electronics Co., Ltd.
6 * Jeffy Chen <jeffy.chen@rock-chips.com>
7 */
8
9 #include <linux/clk.h>
10
11 #include "hantro.h"
12 #include "hantro_jpeg.h"
13 #include "rk3399_vpu_regs.h"
14
15 #define RK3399_ACLK_MAX_FREQ (400 * 1000 * 1000)
16
17 /*
18 * Supported formats.
19 */
20
21 static const struct hantro_fmt rk3399_vpu_enc_fmts[] = {
22 {
23 .fourcc = V4L2_PIX_FMT_YUV420M,
24 .codec_mode = HANTRO_MODE_NONE,
25 .enc_fmt = RK3288_VPU_ENC_FMT_YUV420P,
26 },
27 {
28 .fourcc = V4L2_PIX_FMT_NV12M,
29 .codec_mode = HANTRO_MODE_NONE,
30 .enc_fmt = RK3288_VPU_ENC_FMT_YUV420SP,
31 },
32 {
33 .fourcc = V4L2_PIX_FMT_YUYV,
34 .codec_mode = HANTRO_MODE_NONE,
35 .enc_fmt = RK3288_VPU_ENC_FMT_YUYV422,
36 },
37 {
38 .fourcc = V4L2_PIX_FMT_UYVY,
39 .codec_mode = HANTRO_MODE_NONE,
40 .enc_fmt = RK3288_VPU_ENC_FMT_UYVY422,
41 },
42 {
43 .fourcc = V4L2_PIX_FMT_JPEG,
44 .codec_mode = HANTRO_MODE_JPEG_ENC,
45 .max_depth = 2,
46 .header_size = JPEG_HEADER_SIZE,
47 .frmsize = {
48 .min_width = 96,
49 .max_width = 8192,
50 .step_width = JPEG_MB_DIM,
51 .min_height = 32,
52 .max_height = 8192,
53 .step_height = JPEG_MB_DIM,
54 },
55 },
56 };
57
58 static const struct hantro_fmt rk3399_vpu_dec_fmts[] = {
59 {
60 .fourcc = V4L2_PIX_FMT_NV12,
61 .codec_mode = HANTRO_MODE_NONE,
62 },
63 {
64 .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
65 .codec_mode = HANTRO_MODE_MPEG2_DEC,
66 .max_depth = 2,
67 .frmsize = {
68 .min_width = 48,
69 .max_width = 1920,
70 .step_width = MPEG2_MB_DIM,
71 .min_height = 48,
72 .max_height = 1088,
73 .step_height = MPEG2_MB_DIM,
74 },
75 },
76 {
77 .fourcc = V4L2_PIX_FMT_VP8_FRAME,
78 .codec_mode = HANTRO_MODE_VP8_DEC,
79 .max_depth = 2,
80 .frmsize = {
81 .min_width = 48,
82 .max_width = 3840,
83 .step_width = VP8_MB_DIM,
84 .min_height = 48,
85 .max_height = 2160,
86 .step_height = VP8_MB_DIM,
87 },
88 },
89 };
90
rk3399_vepu_irq(int irq,void * dev_id)91 static irqreturn_t rk3399_vepu_irq(int irq, void *dev_id)
92 {
93 struct hantro_dev *vpu = dev_id;
94 enum vb2_buffer_state state;
95 u32 status, bytesused;
96
97 status = vepu_read(vpu, VEPU_REG_INTERRUPT);
98 bytesused = vepu_read(vpu, VEPU_REG_STR_BUF_LIMIT) / 8;
99 state = (status & VEPU_REG_INTERRUPT_FRAME_READY) ?
100 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
101
102 vepu_write(vpu, 0, VEPU_REG_INTERRUPT);
103 vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
104
105 hantro_irq_done(vpu, bytesused, state);
106
107 return IRQ_HANDLED;
108 }
109
rk3399_vdpu_irq(int irq,void * dev_id)110 static irqreturn_t rk3399_vdpu_irq(int irq, void *dev_id)
111 {
112 struct hantro_dev *vpu = dev_id;
113 enum vb2_buffer_state state;
114 u32 status;
115
116 status = vdpu_read(vpu, VDPU_REG_INTERRUPT);
117 state = (status & VDPU_REG_INTERRUPT_DEC_IRQ) ?
118 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
119
120 vdpu_write(vpu, 0, VDPU_REG_INTERRUPT);
121 vdpu_write(vpu, 0, VDPU_REG_AXI_CTRL);
122
123 hantro_irq_done(vpu, 0, state);
124
125 return IRQ_HANDLED;
126 }
127
rk3399_vpu_hw_init(struct hantro_dev * vpu)128 static int rk3399_vpu_hw_init(struct hantro_dev *vpu)
129 {
130 /* Bump ACLK to max. possible freq. to improve performance. */
131 clk_set_rate(vpu->clocks[0].clk, RK3399_ACLK_MAX_FREQ);
132 return 0;
133 }
134
rk3399_vpu_enc_reset(struct hantro_ctx * ctx)135 static void rk3399_vpu_enc_reset(struct hantro_ctx *ctx)
136 {
137 struct hantro_dev *vpu = ctx->dev;
138
139 vepu_write(vpu, VEPU_REG_INTERRUPT_DIS_BIT, VEPU_REG_INTERRUPT);
140 vepu_write(vpu, 0, VEPU_REG_ENCODE_START);
141 vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
142 }
143
rk3399_vpu_dec_reset(struct hantro_ctx * ctx)144 static void rk3399_vpu_dec_reset(struct hantro_ctx *ctx)
145 {
146 struct hantro_dev *vpu = ctx->dev;
147
148 vdpu_write(vpu, VDPU_REG_INTERRUPT_DEC_IRQ_DIS, VDPU_REG_INTERRUPT);
149 vdpu_write(vpu, 0, VDPU_REG_EN_FLAGS);
150 vdpu_write(vpu, 1, VDPU_REG_SOFT_RESET);
151 }
152
153 /*
154 * Supported codec ops.
155 */
156
157 static const struct hantro_codec_ops rk3399_vpu_codec_ops[] = {
158 [HANTRO_MODE_JPEG_ENC] = {
159 .run = rk3399_vpu_jpeg_enc_run,
160 .reset = rk3399_vpu_enc_reset,
161 .init = hantro_jpeg_enc_init,
162 .exit = hantro_jpeg_enc_exit,
163 },
164 [HANTRO_MODE_MPEG2_DEC] = {
165 .run = rk3399_vpu_mpeg2_dec_run,
166 .reset = rk3399_vpu_dec_reset,
167 .init = hantro_mpeg2_dec_init,
168 .exit = hantro_mpeg2_dec_exit,
169 },
170 [HANTRO_MODE_VP8_DEC] = {
171 .run = rk3399_vpu_vp8_dec_run,
172 .reset = rk3399_vpu_dec_reset,
173 .init = hantro_vp8_dec_init,
174 .exit = hantro_vp8_dec_exit,
175 },
176 };
177
178 /*
179 * VPU variant.
180 */
181
182 static const struct hantro_irq rk3399_irqs[] = {
183 { "vepu", rk3399_vepu_irq },
184 { "vdpu", rk3399_vdpu_irq },
185 };
186
187 static const char * const rk3399_clk_names[] = {
188 "aclk", "hclk"
189 };
190
191 const struct hantro_variant rk3399_vpu_variant = {
192 .enc_offset = 0x0,
193 .enc_fmts = rk3399_vpu_enc_fmts,
194 .num_enc_fmts = ARRAY_SIZE(rk3399_vpu_enc_fmts),
195 .dec_offset = 0x400,
196 .dec_fmts = rk3399_vpu_dec_fmts,
197 .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
198 .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
199 HANTRO_VP8_DECODER,
200 .codec_ops = rk3399_vpu_codec_ops,
201 .irqs = rk3399_irqs,
202 .num_irqs = ARRAY_SIZE(rk3399_irqs),
203 .init = rk3399_vpu_hw_init,
204 .clk_names = rk3399_clk_names,
205 .num_clocks = ARRAY_SIZE(rk3399_clk_names)
206 };
207
208 static const struct hantro_irq rk3328_irqs[] = {
209 { "vdpu", rk3399_vdpu_irq },
210 };
211
212 const struct hantro_variant rk3328_vpu_variant = {
213 .dec_offset = 0x400,
214 .dec_fmts = rk3399_vpu_dec_fmts,
215 .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
216 .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER,
217 .codec_ops = rk3399_vpu_codec_ops,
218 .irqs = rk3328_irqs,
219 .num_irqs = ARRAY_SIZE(rk3328_irqs),
220 .init = rk3399_vpu_hw_init,
221 .clk_names = rk3399_clk_names,
222 .num_clocks = ARRAY_SIZE(rk3399_clk_names),
223 };
224
