1 /*
2 * Copyright(c) 2015 - 2019 Intel Corporation.
3 *
4 * This file is provided under a dual BSD/GPLv2 license. When using or
5 * redistributing this file, you may do so under either license.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * BSD LICENSE
19 *
20 * Redistribution and use in source and binary forms, with or without
21 * modification, are permitted provided that the following conditions
22 * are met:
23 *
24 * - Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * - Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in
28 * the documentation and/or other materials provided with the
29 * distribution.
30 * - Neither the name of Intel Corporation nor the names of its
31 * contributors may be used to endorse or promote products derived
32 * from this software without specific prior written permission.
33 *
34 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 */
47
48 #include <linux/pci.h>
49 #include <linux/io.h>
50 #include <linux/delay.h>
51 #include <linux/vmalloc.h>
52 #include <linux/aer.h>
53 #include <linux/module.h>
54
55 #include "hfi.h"
56 #include "chip_registers.h"
57 #include "aspm.h"
58
59 /*
60 * This file contains PCIe utility routines.
61 */
62
63 /*
64 * Do all the common PCIe setup and initialization.
65 */
hfi1_pcie_init(struct hfi1_devdata * dd)66 int hfi1_pcie_init(struct hfi1_devdata *dd)
67 {
68 int ret;
69 struct pci_dev *pdev = dd->pcidev;
70
71 ret = pci_enable_device(pdev);
72 if (ret) {
73 /*
74 * This can happen (in theory) iff:
75 * We did a chip reset, and then failed to reprogram the
76 * BAR, or the chip reset due to an internal error. We then
77 * unloaded the driver and reloaded it.
78 *
79 * Both reset cases set the BAR back to initial state. For
80 * the latter case, the AER sticky error bit at offset 0x718
81 * should be set, but the Linux kernel doesn't yet know
82 * about that, it appears. If the original BAR was retained
83 * in the kernel data structures, this may be OK.
84 */
85 dd_dev_err(dd, "pci enable failed: error %d\n", -ret);
86 return ret;
87 }
88
89 ret = pci_request_regions(pdev, DRIVER_NAME);
90 if (ret) {
91 dd_dev_err(dd, "pci_request_regions fails: err %d\n", -ret);
92 goto bail;
93 }
94
95 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
96 if (ret) {
97 /*
98 * If the 64 bit setup fails, try 32 bit. Some systems
99 * do not setup 64 bit maps on systems with 2GB or less
100 * memory installed.
101 */
102 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
103 if (ret) {
104 dd_dev_err(dd, "Unable to set DMA mask: %d\n", ret);
105 goto bail;
106 }
107 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
108 } else {
109 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
110 }
111 if (ret) {
112 dd_dev_err(dd, "Unable to set DMA consistent mask: %d\n", ret);
113 goto bail;
114 }
115
116 pci_set_master(pdev);
117 (void)pci_enable_pcie_error_reporting(pdev);
118 return 0;
119
120 bail:
121 hfi1_pcie_cleanup(pdev);
122 return ret;
123 }
124
125 /*
126 * Clean what was done in hfi1_pcie_init()
127 */
hfi1_pcie_cleanup(struct pci_dev * pdev)128 void hfi1_pcie_cleanup(struct pci_dev *pdev)
129 {
130 pci_disable_device(pdev);
131 /*
132 * Release regions should be called after the disable. OK to
133 * call if request regions has not been called or failed.
134 */
135 pci_release_regions(pdev);
136 }
137
138 /*
139 * Do remaining PCIe setup, once dd is allocated, and save away
140 * fields required to re-initialize after a chip reset, or for
141 * various other purposes
142 */
hfi1_pcie_ddinit(struct hfi1_devdata * dd,struct pci_dev * pdev)143 int hfi1_pcie_ddinit(struct hfi1_devdata *dd, struct pci_dev *pdev)
144 {
145 unsigned long len;
146 resource_size_t addr;
147 int ret = 0;
148 u32 rcv_array_count;
149
150 addr = pci_resource_start(pdev, 0);
151 len = pci_resource_len(pdev, 0);
152
153 /*
154 * The TXE PIO buffers are at the tail end of the chip space.
155 * Cut them off and map them separately.
156 */
157
158 /* sanity check vs expectations */
159 if (len != TXE_PIO_SEND + TXE_PIO_SIZE) {
160 dd_dev_err(dd, "chip PIO range does not match\n");
161 return -EINVAL;
162 }
163
164 dd->kregbase1 = ioremap_nocache(addr, RCV_ARRAY);
165 if (!dd->kregbase1) {
166 dd_dev_err(dd, "UC mapping of kregbase1 failed\n");
167 return -ENOMEM;
168 }
169 dd_dev_info(dd, "UC base1: %p for %x\n", dd->kregbase1, RCV_ARRAY);
170
171 /* verify that reads actually work, save revision for reset check */
172 dd->revision = readq(dd->kregbase1 + CCE_REVISION);
173 if (dd->revision == ~(u64)0) {
174 dd_dev_err(dd, "Cannot read chip CSRs\n");
175 goto nomem;
176 }
177
178 rcv_array_count = readq(dd->kregbase1 + RCV_ARRAY_CNT);
179 dd_dev_info(dd, "RcvArray count: %u\n", rcv_array_count);
180 dd->base2_start = RCV_ARRAY + rcv_array_count * 8;
181
182 dd->kregbase2 = ioremap_nocache(
183 addr + dd->base2_start,
184 TXE_PIO_SEND - dd->base2_start);
185 if (!dd->kregbase2) {
186 dd_dev_err(dd, "UC mapping of kregbase2 failed\n");
187 goto nomem;
188 }
189 dd_dev_info(dd, "UC base2: %p for %x\n", dd->kregbase2,
190 TXE_PIO_SEND - dd->base2_start);
191
192 dd->piobase = ioremap_wc(addr + TXE_PIO_SEND, TXE_PIO_SIZE);
193 if (!dd->piobase) {
194 dd_dev_err(dd, "WC mapping of send buffers failed\n");
195 goto nomem;
196 }
197 dd_dev_info(dd, "WC piobase: %p for %x\n", dd->piobase, TXE_PIO_SIZE);
198
199 dd->physaddr = addr; /* used for io_remap, etc. */
200
201 /*
202 * Map the chip's RcvArray as write-combining to allow us
203 * to write an entire cacheline worth of entries in one shot.
204 */
205 dd->rcvarray_wc = ioremap_wc(addr + RCV_ARRAY,
206 rcv_array_count * 8);
207 if (!dd->rcvarray_wc) {
208 dd_dev_err(dd, "WC mapping of receive array failed\n");
209 goto nomem;
210 }
211 dd_dev_info(dd, "WC RcvArray: %p for %x\n",
212 dd->rcvarray_wc, rcv_array_count * 8);
213
214 dd->flags |= HFI1_PRESENT; /* chip.c CSR routines now work */
215 return 0;
216 nomem:
217 ret = -ENOMEM;
218 hfi1_pcie_ddcleanup(dd);
219 return ret;
220 }
221
222 /*
223 * Do PCIe cleanup related to dd, after chip-specific cleanup, etc. Just prior
224 * to releasing the dd memory.
225 * Void because all of the core pcie cleanup functions are void.
226 */
hfi1_pcie_ddcleanup(struct hfi1_devdata * dd)227 void hfi1_pcie_ddcleanup(struct hfi1_devdata *dd)
228 {
229 dd->flags &= ~HFI1_PRESENT;
230 if (dd->kregbase1)
231 iounmap(dd->kregbase1);
232 dd->kregbase1 = NULL;
233 if (dd->kregbase2)
234 iounmap(dd->kregbase2);
235 dd->kregbase2 = NULL;
236 if (dd->rcvarray_wc)
237 iounmap(dd->rcvarray_wc);
238 dd->rcvarray_wc = NULL;
239 if (dd->piobase)
240 iounmap(dd->piobase);
241 dd->piobase = NULL;
242 }
243
244 /* return the PCIe link speed from the given link status */
extract_speed(u16 linkstat)245 static u32 extract_speed(u16 linkstat)
246 {
247 u32 speed;
248
249 switch (linkstat & PCI_EXP_LNKSTA_CLS) {
250 default: /* not defined, assume Gen1 */
251 case PCI_EXP_LNKSTA_CLS_2_5GB:
252 speed = 2500; /* Gen 1, 2.5GHz */
253 break;
254 case PCI_EXP_LNKSTA_CLS_5_0GB:
255 speed = 5000; /* Gen 2, 5GHz */
256 break;
257 case PCI_EXP_LNKSTA_CLS_8_0GB:
258 speed = 8000; /* Gen 3, 8GHz */
259 break;
260 }
261 return speed;
262 }
263
264 /* return the PCIe link speed from the given link status */
extract_width(u16 linkstat)265 static u32 extract_width(u16 linkstat)
266 {
267 return (linkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
268 }
269
270 /* read the link status and set dd->{lbus_width,lbus_speed,lbus_info} */
update_lbus_info(struct hfi1_devdata * dd)271 static void update_lbus_info(struct hfi1_devdata *dd)
272 {
273 u16 linkstat;
274 int ret;
275
276 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat);
277 if (ret) {
278 dd_dev_err(dd, "Unable to read from PCI config\n");
279 return;
280 }
281
282 dd->lbus_width = extract_width(linkstat);
283 dd->lbus_speed = extract_speed(linkstat);
284 snprintf(dd->lbus_info, sizeof(dd->lbus_info),
285 "PCIe,%uMHz,x%u", dd->lbus_speed, dd->lbus_width);
286 }
287
288 /*
289 * Read in the current PCIe link width and speed. Find if the link is
290 * Gen3 capable.
291 */
pcie_speeds(struct hfi1_devdata * dd)292 int pcie_speeds(struct hfi1_devdata *dd)
293 {
294 u32 linkcap;
295 struct pci_dev *parent = dd->pcidev->bus->self;
296 int ret;
297
298 if (!pci_is_pcie(dd->pcidev)) {
299 dd_dev_err(dd, "Can't find PCI Express capability!\n");
300 return -EINVAL;
301 }
302
303 /* find if our max speed is Gen3 and parent supports Gen3 speeds */
304 dd->link_gen3_capable = 1;
305
306 ret = pcie_capability_read_dword(dd->pcidev, PCI_EXP_LNKCAP, &linkcap);
307 if (ret) {
308 dd_dev_err(dd, "Unable to read from PCI config\n");
309 return ret;
310 }
311
312 if ((linkcap & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_8_0GB) {
313 dd_dev_info(dd,
314 "This HFI is not Gen3 capable, max speed 0x%x, need 0x3\n",
315 linkcap & PCI_EXP_LNKCAP_SLS);
316 dd->link_gen3_capable = 0;
317 }
318
319 /*
320 * bus->max_bus_speed is set from the bridge's linkcap Max Link Speed
321 */
322 if (parent &&
323 (dd->pcidev->bus->max_bus_speed == PCIE_SPEED_2_5GT ||
324 dd->pcidev->bus->max_bus_speed == PCIE_SPEED_5_0GT)) {
325 dd_dev_info(dd, "Parent PCIe bridge does not support Gen3\n");
326 dd->link_gen3_capable = 0;
327 }
328
329 /* obtain the link width and current speed */
330 update_lbus_info(dd);
331
332 dd_dev_info(dd, "%s\n", dd->lbus_info);
333
334 return 0;
335 }
336
337 /* restore command and BARs after a reset has wiped them out */
restore_pci_variables(struct hfi1_devdata * dd)338 int restore_pci_variables(struct hfi1_devdata *dd)
339 {
340 int ret = 0;
341
342 ret = pci_write_config_word(dd->pcidev, PCI_COMMAND, dd->pci_command);
343 if (ret)
344 goto error;
345
346 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
347 dd->pcibar0);
348 if (ret)
349 goto error;
350
351 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
352 dd->pcibar1);
353 if (ret)
354 goto error;
355
356 ret = pci_write_config_dword(dd->pcidev, PCI_ROM_ADDRESS, dd->pci_rom);
357 if (ret)
358 goto error;
359
360 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL,
361 dd->pcie_devctl);
362 if (ret)
363 goto error;
364
365 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL,
366 dd->pcie_lnkctl);
367 if (ret)
368 goto error;
369
370 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL2,
371 dd->pcie_devctl2);
372 if (ret)
373 goto error;
374
375 ret = pci_write_config_dword(dd->pcidev, PCI_CFG_MSIX0, dd->pci_msix0);
376 if (ret)
377 goto error;
378
379 if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) {
380 ret = pci_write_config_dword(dd->pcidev, PCIE_CFG_TPH2,
381 dd->pci_tph2);
382 if (ret)
383 goto error;
384 }
385 return 0;
386
387 error:
388 dd_dev_err(dd, "Unable to write to PCI config\n");
389 return ret;
390 }
391
392 /* Save BARs and command to rewrite after device reset */
save_pci_variables(struct hfi1_devdata * dd)393 int save_pci_variables(struct hfi1_devdata *dd)
394 {
395 int ret = 0;
396
397 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
398 &dd->pcibar0);
399 if (ret)
400 goto error;
401
402 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
403 &dd->pcibar1);
404 if (ret)
405 goto error;
406
407 ret = pci_read_config_dword(dd->pcidev, PCI_ROM_ADDRESS, &dd->pci_rom);
408 if (ret)
409 goto error;
410
411 ret = pci_read_config_word(dd->pcidev, PCI_COMMAND, &dd->pci_command);
412 if (ret)
413 goto error;
414
415 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL,
416 &dd->pcie_devctl);
417 if (ret)
418 goto error;
419
420 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL,
421 &dd->pcie_lnkctl);
422 if (ret)
423 goto error;
424
425 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL2,
426 &dd->pcie_devctl2);
427 if (ret)
428 goto error;
429
430 ret = pci_read_config_dword(dd->pcidev, PCI_CFG_MSIX0, &dd->pci_msix0);
431 if (ret)
432 goto error;
433
434 if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) {
435 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_TPH2,
436 &dd->pci_tph2);
437 if (ret)
438 goto error;
439 }
440 return 0;
441
442 error:
443 dd_dev_err(dd, "Unable to read from PCI config\n");
444 return ret;
445 }
446
447 /*
448 * BIOS may not set PCIe bus-utilization parameters for best performance.
449 * Check and optionally adjust them to maximize our throughput.
450 */
451 static int hfi1_pcie_caps;
452 module_param_named(pcie_caps, hfi1_pcie_caps, int, 0444);
453 MODULE_PARM_DESC(pcie_caps, "Max PCIe tuning: Payload (0..3), ReadReq (4..7)");
454
455 /**
456 * tune_pcie_caps() - Code to adjust PCIe capabilities.
457 * @dd: Valid device data structure
458 *
459 */
tune_pcie_caps(struct hfi1_devdata * dd)460 void tune_pcie_caps(struct hfi1_devdata *dd)
461 {
462 struct pci_dev *parent;
463 u16 rc_mpss, rc_mps, ep_mpss, ep_mps;
464 u16 rc_mrrs, ep_mrrs, max_mrrs, ectl;
465 int ret;
466
467 /*
468 * Turn on extended tags in DevCtl in case the BIOS has turned it off
469 * to improve WFR SDMA bandwidth
470 */
471 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &ectl);
472 if ((!ret) && !(ectl & PCI_EXP_DEVCTL_EXT_TAG)) {
473 dd_dev_info(dd, "Enabling PCIe extended tags\n");
474 ectl |= PCI_EXP_DEVCTL_EXT_TAG;
475 ret = pcie_capability_write_word(dd->pcidev,
476 PCI_EXP_DEVCTL, ectl);
477 if (ret)
478 dd_dev_info(dd, "Unable to write to PCI config\n");
479 }
480 /* Find out supported and configured values for parent (root) */
481 parent = dd->pcidev->bus->self;
482 /*
483 * The driver cannot perform the tuning if it does not have
484 * access to the upstream component.
485 */
486 if (!parent) {
487 dd_dev_info(dd, "Parent not found\n");
488 return;
489 }
490 if (!pci_is_root_bus(parent->bus)) {
491 dd_dev_info(dd, "Parent not root\n");
492 return;
493 }
494 if (!pci_is_pcie(parent)) {
495 dd_dev_info(dd, "Parent is not PCI Express capable\n");
496 return;
497 }
498 if (!pci_is_pcie(dd->pcidev)) {
499 dd_dev_info(dd, "PCI device is not PCI Express capable\n");
500 return;
501 }
502 rc_mpss = parent->pcie_mpss;
503 rc_mps = ffs(pcie_get_mps(parent)) - 8;
504 /* Find out supported and configured values for endpoint (us) */
505 ep_mpss = dd->pcidev->pcie_mpss;
506 ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8;
507
508 /* Find max payload supported by root, endpoint */
509 if (rc_mpss > ep_mpss)
510 rc_mpss = ep_mpss;
511
512 /* If Supported greater than limit in module param, limit it */
513 if (rc_mpss > (hfi1_pcie_caps & 7))
514 rc_mpss = hfi1_pcie_caps & 7;
515 /* If less than (allowed, supported), bump root payload */
516 if (rc_mpss > rc_mps) {
517 rc_mps = rc_mpss;
518 pcie_set_mps(parent, 128 << rc_mps);
519 }
520 /* If less than (allowed, supported), bump endpoint payload */
521 if (rc_mpss > ep_mps) {
522 ep_mps = rc_mpss;
523 pcie_set_mps(dd->pcidev, 128 << ep_mps);
524 }
525
526 /*
527 * Now the Read Request size.
528 * No field for max supported, but PCIe spec limits it to 4096,
529 * which is code '5' (log2(4096) - 7)
530 */
531 max_mrrs = 5;
532 if (max_mrrs > ((hfi1_pcie_caps >> 4) & 7))
533 max_mrrs = (hfi1_pcie_caps >> 4) & 7;
534
535 max_mrrs = 128 << max_mrrs;
536 rc_mrrs = pcie_get_readrq(parent);
537 ep_mrrs = pcie_get_readrq(dd->pcidev);
538
539 if (max_mrrs > rc_mrrs) {
540 rc_mrrs = max_mrrs;
541 pcie_set_readrq(parent, rc_mrrs);
542 }
543 if (max_mrrs > ep_mrrs) {
544 ep_mrrs = max_mrrs;
545 pcie_set_readrq(dd->pcidev, ep_mrrs);
546 }
547 }
548
549 /* End of PCIe capability tuning */
550
551 /*
552 * From here through hfi1_pci_err_handler definition is invoked via
553 * PCI error infrastructure, registered via pci
554 */
555 static pci_ers_result_t
pci_error_detected(struct pci_dev * pdev,pci_channel_state_t state)556 pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
557 {
558 struct hfi1_devdata *dd = pci_get_drvdata(pdev);
559 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED;
560
561 switch (state) {
562 case pci_channel_io_normal:
563 dd_dev_info(dd, "State Normal, ignoring\n");
564 break;
565
566 case pci_channel_io_frozen:
567 dd_dev_info(dd, "State Frozen, requesting reset\n");
568 pci_disable_device(pdev);
569 ret = PCI_ERS_RESULT_NEED_RESET;
570 break;
571
572 case pci_channel_io_perm_failure:
573 if (dd) {
574 dd_dev_info(dd, "State Permanent Failure, disabling\n");
575 /* no more register accesses! */
576 dd->flags &= ~HFI1_PRESENT;
577 hfi1_disable_after_error(dd);
578 }
579 /* else early, or other problem */
580 ret = PCI_ERS_RESULT_DISCONNECT;
581 break;
582
583 default: /* shouldn't happen */
584 dd_dev_info(dd, "HFI1 PCI errors detected (state %d)\n",
585 state);
586 break;
587 }
588 return ret;
589 }
590
591 static pci_ers_result_t
pci_mmio_enabled(struct pci_dev * pdev)592 pci_mmio_enabled(struct pci_dev *pdev)
593 {
594 u64 words = 0U;
595 struct hfi1_devdata *dd = pci_get_drvdata(pdev);
596 pci_ers_result_t ret = PCI_ERS_RESULT_RECOVERED;
597
598 if (dd && dd->pport) {
599 words = read_port_cntr(dd->pport, C_RX_WORDS, CNTR_INVALID_VL);
600 if (words == ~0ULL)
601 ret = PCI_ERS_RESULT_NEED_RESET;
602 dd_dev_info(dd,
603 "HFI1 mmio_enabled function called, read wordscntr %llx, returning %d\n",
604 words, ret);
605 }
606 return ret;
607 }
608
609 static pci_ers_result_t
pci_slot_reset(struct pci_dev * pdev)610 pci_slot_reset(struct pci_dev *pdev)
611 {
612 struct hfi1_devdata *dd = pci_get_drvdata(pdev);
613
614 dd_dev_info(dd, "HFI1 slot_reset function called, ignored\n");
615 return PCI_ERS_RESULT_CAN_RECOVER;
616 }
617
618 static void
pci_resume(struct pci_dev * pdev)619 pci_resume(struct pci_dev *pdev)
620 {
621 struct hfi1_devdata *dd = pci_get_drvdata(pdev);
622
623 dd_dev_info(dd, "HFI1 resume function called\n");
624 /*
625 * Running jobs will fail, since it's asynchronous
626 * unlike sysfs-requested reset. Better than
627 * doing nothing.
628 */
629 hfi1_init(dd, 1); /* same as re-init after reset */
630 }
631
632 const struct pci_error_handlers hfi1_pci_err_handler = {
633 .error_detected = pci_error_detected,
634 .mmio_enabled = pci_mmio_enabled,
635 .slot_reset = pci_slot_reset,
636 .resume = pci_resume,
637 };
638
639 /*============================================================================*/
640 /* PCIe Gen3 support */
641
642 /*
643 * This code is separated out because it is expected to be removed in the
644 * final shipping product. If not, then it will be revisited and items
645 * will be moved to more standard locations.
646 */
647
648 /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_STS field values */
649 #define DL_STATUS_HFI0 0x1 /* hfi0 firmware download complete */
650 #define DL_STATUS_HFI1 0x2 /* hfi1 firmware download complete */
651 #define DL_STATUS_BOTH 0x3 /* hfi0 and hfi1 firmware download complete */
652
653 /* ASIC_PCI_SD_HOST_STATUS.FW_DNLD_ERR field values */
654 #define DL_ERR_NONE 0x0 /* no error */
655 #define DL_ERR_SWAP_PARITY 0x1 /* parity error in SerDes interrupt */
656 /* or response data */
657 #define DL_ERR_DISABLED 0x2 /* hfi disabled */
658 #define DL_ERR_SECURITY 0x3 /* security check failed */
659 #define DL_ERR_SBUS 0x4 /* SBus status error */
660 #define DL_ERR_XFR_PARITY 0x5 /* parity error during ROM transfer*/
661
662 /* gasket block secondary bus reset delay */
663 #define SBR_DELAY_US 200000 /* 200ms */
664
665 static uint pcie_target = 3;
666 module_param(pcie_target, uint, S_IRUGO);
667 MODULE_PARM_DESC(pcie_target, "PCIe target speed (0 skip, 1-3 Gen1-3)");
668
669 static uint pcie_force;
670 module_param(pcie_force, uint, S_IRUGO);
671 MODULE_PARM_DESC(pcie_force, "Force driver to do a PCIe firmware download even if already at target speed");
672
673 static uint pcie_retry = 5;
674 module_param(pcie_retry, uint, S_IRUGO);
675 MODULE_PARM_DESC(pcie_retry, "Driver will try this many times to reach requested speed");
676
677 #define UNSET_PSET 255
678 #define DEFAULT_DISCRETE_PSET 2 /* discrete HFI */
679 #define DEFAULT_MCP_PSET 6 /* MCP HFI */
680 static uint pcie_pset = UNSET_PSET;
681 module_param(pcie_pset, uint, S_IRUGO);
682 MODULE_PARM_DESC(pcie_pset, "PCIe Eq Pset value to use, range is 0-10");
683
684 static uint pcie_ctle = 3; /* discrete on, integrated on */
685 module_param(pcie_ctle, uint, S_IRUGO);
686 MODULE_PARM_DESC(pcie_ctle, "PCIe static CTLE mode, bit 0 - discrete on/off, bit 1 - integrated on/off");
687
688 /* equalization columns */
689 #define PREC 0
690 #define ATTN 1
691 #define POST 2
692
693 /* discrete silicon preliminary equalization values */
694 static const u8 discrete_preliminary_eq[11][3] = {
695 /* prec attn post */
696 { 0x00, 0x00, 0x12 }, /* p0 */
697 { 0x00, 0x00, 0x0c }, /* p1 */
698 { 0x00, 0x00, 0x0f }, /* p2 */
699 { 0x00, 0x00, 0x09 }, /* p3 */
700 { 0x00, 0x00, 0x00 }, /* p4 */
701 { 0x06, 0x00, 0x00 }, /* p5 */
702 { 0x09, 0x00, 0x00 }, /* p6 */
703 { 0x06, 0x00, 0x0f }, /* p7 */
704 { 0x09, 0x00, 0x09 }, /* p8 */
705 { 0x0c, 0x00, 0x00 }, /* p9 */
706 { 0x00, 0x00, 0x18 }, /* p10 */
707 };
708
709 /* integrated silicon preliminary equalization values */
710 static const u8 integrated_preliminary_eq[11][3] = {
711 /* prec attn post */
712 { 0x00, 0x1e, 0x07 }, /* p0 */
713 { 0x00, 0x1e, 0x05 }, /* p1 */
714 { 0x00, 0x1e, 0x06 }, /* p2 */
715 { 0x00, 0x1e, 0x04 }, /* p3 */
716 { 0x00, 0x1e, 0x00 }, /* p4 */
717 { 0x03, 0x1e, 0x00 }, /* p5 */
718 { 0x04, 0x1e, 0x00 }, /* p6 */
719 { 0x03, 0x1e, 0x06 }, /* p7 */
720 { 0x03, 0x1e, 0x04 }, /* p8 */
721 { 0x05, 0x1e, 0x00 }, /* p9 */
722 { 0x00, 0x1e, 0x0a }, /* p10 */
723 };
724
725 static const u8 discrete_ctle_tunings[11][4] = {
726 /* DC LF HF BW */
727 { 0x48, 0x0b, 0x04, 0x04 }, /* p0 */
728 { 0x60, 0x05, 0x0f, 0x0a }, /* p1 */
729 { 0x50, 0x09, 0x06, 0x06 }, /* p2 */
730 { 0x68, 0x05, 0x0f, 0x0a }, /* p3 */
731 { 0x80, 0x05, 0x0f, 0x0a }, /* p4 */
732 { 0x70, 0x05, 0x0f, 0x0a }, /* p5 */
733 { 0x68, 0x05, 0x0f, 0x0a }, /* p6 */
734 { 0x38, 0x0f, 0x00, 0x00 }, /* p7 */
735 { 0x48, 0x09, 0x06, 0x06 }, /* p8 */
736 { 0x60, 0x05, 0x0f, 0x0a }, /* p9 */
737 { 0x38, 0x0f, 0x00, 0x00 }, /* p10 */
738 };
739
740 static const u8 integrated_ctle_tunings[11][4] = {
741 /* DC LF HF BW */
742 { 0x38, 0x0f, 0x00, 0x00 }, /* p0 */
743 { 0x38, 0x0f, 0x00, 0x00 }, /* p1 */
744 { 0x38, 0x0f, 0x00, 0x00 }, /* p2 */
745 { 0x38, 0x0f, 0x00, 0x00 }, /* p3 */
746 { 0x58, 0x0a, 0x05, 0x05 }, /* p4 */
747 { 0x48, 0x0a, 0x05, 0x05 }, /* p5 */
748 { 0x40, 0x0a, 0x05, 0x05 }, /* p6 */
749 { 0x38, 0x0f, 0x00, 0x00 }, /* p7 */
750 { 0x38, 0x0f, 0x00, 0x00 }, /* p8 */
751 { 0x38, 0x09, 0x06, 0x06 }, /* p9 */
752 { 0x38, 0x0e, 0x01, 0x01 }, /* p10 */
753 };
754
755 /* helper to format the value to write to hardware */
756 #define eq_value(pre, curr, post) \
757 ((((u32)(pre)) << \
758 PCIE_CFG_REG_PL102_GEN3_EQ_PRE_CURSOR_PSET_SHIFT) \
759 | (((u32)(curr)) << PCIE_CFG_REG_PL102_GEN3_EQ_CURSOR_PSET_SHIFT) \
760 | (((u32)(post)) << \
761 PCIE_CFG_REG_PL102_GEN3_EQ_POST_CURSOR_PSET_SHIFT))
762
763 /*
764 * Load the given EQ preset table into the PCIe hardware.
765 */
load_eq_table(struct hfi1_devdata * dd,const u8 eq[11][3],u8 fs,u8 div)766 static int load_eq_table(struct hfi1_devdata *dd, const u8 eq[11][3], u8 fs,
767 u8 div)
768 {
769 struct pci_dev *pdev = dd->pcidev;
770 u32 hit_error = 0;
771 u32 violation;
772 u32 i;
773 u8 c_minus1, c0, c_plus1;
774 int ret;
775
776 for (i = 0; i < 11; i++) {
777 /* set index */
778 pci_write_config_dword(pdev, PCIE_CFG_REG_PL103, i);
779 /* write the value */
780 c_minus1 = eq[i][PREC] / div;
781 c0 = fs - (eq[i][PREC] / div) - (eq[i][POST] / div);
782 c_plus1 = eq[i][POST] / div;
783 pci_write_config_dword(pdev, PCIE_CFG_REG_PL102,
784 eq_value(c_minus1, c0, c_plus1));
785 /* check if these coefficients violate EQ rules */
786 ret = pci_read_config_dword(dd->pcidev,
787 PCIE_CFG_REG_PL105, &violation);
788 if (ret) {
789 dd_dev_err(dd, "Unable to read from PCI config\n");
790 hit_error = 1;
791 break;
792 }
793
794 if (violation
795 & PCIE_CFG_REG_PL105_GEN3_EQ_VIOLATE_COEF_RULES_SMASK){
796 if (hit_error == 0) {
797 dd_dev_err(dd,
798 "Gen3 EQ Table Coefficient rule violations\n");
799 dd_dev_err(dd, " prec attn post\n");
800 }
801 dd_dev_err(dd, " p%02d: %02x %02x %02x\n",
802 i, (u32)eq[i][0], (u32)eq[i][1],
803 (u32)eq[i][2]);
804 dd_dev_err(dd, " %02x %02x %02x\n",
805 (u32)c_minus1, (u32)c0, (u32)c_plus1);
806 hit_error = 1;
807 }
808 }
809 if (hit_error)
810 return -EINVAL;
811 return 0;
812 }
813
814 /*
815 * Steps to be done after the PCIe firmware is downloaded and
816 * before the SBR for the Pcie Gen3.
817 * The SBus resource is already being held.
818 */
pcie_post_steps(struct hfi1_devdata * dd)819 static void pcie_post_steps(struct hfi1_devdata *dd)
820 {
821 int i;
822
823 set_sbus_fast_mode(dd);
824 /*
825 * Write to the PCIe PCSes to set the G3_LOCKED_NEXT bits to 1.
826 * This avoids a spurious framing error that can otherwise be
827 * generated by the MAC layer.
828 *
829 * Use individual addresses since no broadcast is set up.
830 */
831 for (i = 0; i < NUM_PCIE_SERDES; i++) {
832 sbus_request(dd, pcie_pcs_addrs[dd->hfi1_id][i],
833 0x03, WRITE_SBUS_RECEIVER, 0x00022132);
834 }
835
836 clear_sbus_fast_mode(dd);
837 }
838
839 /*
840 * Trigger a secondary bus reset (SBR) on ourselves using our parent.
841 *
842 * Based on pci_parent_bus_reset() which is not exported by the
843 * kernel core.
844 */
trigger_sbr(struct hfi1_devdata * dd)845 static int trigger_sbr(struct hfi1_devdata *dd)
846 {
847 struct pci_dev *dev = dd->pcidev;
848 struct pci_dev *pdev;
849
850 /* need a parent */
851 if (!dev->bus->self) {
852 dd_dev_err(dd, "%s: no parent device\n", __func__);
853 return -ENOTTY;
854 }
855
856 /* should not be anyone else on the bus */
857 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
858 if (pdev != dev) {
859 dd_dev_err(dd,
860 "%s: another device is on the same bus\n",
861 __func__);
862 return -ENOTTY;
863 }
864
865 /*
866 * This is an end around to do an SBR during probe time. A new API needs
867 * to be implemented to have cleaner interface but this fixes the
868 * current brokenness
869 */
870 return pci_bridge_secondary_bus_reset(dev->bus->self);
871 }
872
873 /*
874 * Write the given gasket interrupt register.
875 */
write_gasket_interrupt(struct hfi1_devdata * dd,int index,u16 code,u16 data)876 static void write_gasket_interrupt(struct hfi1_devdata *dd, int index,
877 u16 code, u16 data)
878 {
879 write_csr(dd, ASIC_PCIE_SD_INTRPT_LIST + (index * 8),
880 (((u64)code << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_CODE_SHIFT) |
881 ((u64)data << ASIC_PCIE_SD_INTRPT_LIST_INTRPT_DATA_SHIFT)));
882 }
883
884 /*
885 * Tell the gasket logic how to react to the reset.
886 */
arm_gasket_logic(struct hfi1_devdata * dd)887 static void arm_gasket_logic(struct hfi1_devdata *dd)
888 {
889 u64 reg;
890
891 reg = (((u64)1 << dd->hfi1_id) <<
892 ASIC_PCIE_SD_HOST_CMD_INTRPT_CMD_SHIFT) |
893 ((u64)pcie_serdes_broadcast[dd->hfi1_id] <<
894 ASIC_PCIE_SD_HOST_CMD_SBUS_RCVR_ADDR_SHIFT |
895 ASIC_PCIE_SD_HOST_CMD_SBR_MODE_SMASK |
896 ((u64)SBR_DELAY_US & ASIC_PCIE_SD_HOST_CMD_TIMER_MASK) <<
897 ASIC_PCIE_SD_HOST_CMD_TIMER_SHIFT);
898 write_csr(dd, ASIC_PCIE_SD_HOST_CMD, reg);
899 /* read back to push the write */
900 read_csr(dd, ASIC_PCIE_SD_HOST_CMD);
901 }
902
903 /*
904 * CCE_PCIE_CTRL long name helpers
905 * We redefine these shorter macros to use in the code while leaving
906 * chip_registers.h to be autogenerated from the hardware spec.
907 */
908 #define LANE_BUNDLE_MASK CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_MASK
909 #define LANE_BUNDLE_SHIFT CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_SHIFT
910 #define LANE_DELAY_MASK CCE_PCIE_CTRL_PCIE_LANE_DELAY_MASK
911 #define LANE_DELAY_SHIFT CCE_PCIE_CTRL_PCIE_LANE_DELAY_SHIFT
912 #define MARGIN_OVERWRITE_ENABLE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_OVERWRITE_ENABLE_SHIFT
913 #define MARGIN_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_SHIFT
914 #define MARGIN_G1_G2_OVERWRITE_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_MASK
915 #define MARGIN_G1_G2_OVERWRITE_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_SHIFT
916 #define MARGIN_GEN1_GEN2_MASK CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_MASK
917 #define MARGIN_GEN1_GEN2_SHIFT CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_SHIFT
918
919 /*
920 * Write xmt_margin for full-swing (WFR-B) or half-swing (WFR-C).
921 */
write_xmt_margin(struct hfi1_devdata * dd,const char * fname)922 static void write_xmt_margin(struct hfi1_devdata *dd, const char *fname)
923 {
924 u64 pcie_ctrl;
925 u64 xmt_margin;
926 u64 xmt_margin_oe;
927 u64 lane_delay;
928 u64 lane_bundle;
929
930 pcie_ctrl = read_csr(dd, CCE_PCIE_CTRL);
931
932 /*
933 * For Discrete, use full-swing.
934 * - PCIe TX defaults to full-swing.
935 * Leave this register as default.
936 * For Integrated, use half-swing
937 * - Copy xmt_margin and xmt_margin_oe
938 * from Gen1/Gen2 to Gen3.
939 */
940 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL1) { /* integrated */
941 /* extract initial fields */
942 xmt_margin = (pcie_ctrl >> MARGIN_GEN1_GEN2_SHIFT)
943 & MARGIN_GEN1_GEN2_MASK;
944 xmt_margin_oe = (pcie_ctrl >> MARGIN_G1_G2_OVERWRITE_SHIFT)
945 & MARGIN_G1_G2_OVERWRITE_MASK;
946 lane_delay = (pcie_ctrl >> LANE_DELAY_SHIFT) & LANE_DELAY_MASK;
947 lane_bundle = (pcie_ctrl >> LANE_BUNDLE_SHIFT)
948 & LANE_BUNDLE_MASK;
949
950 /*
951 * For A0, EFUSE values are not set. Override with the
952 * correct values.
953 */
954 if (is_ax(dd)) {
955 /*
956 * xmt_margin and OverwiteEnabel should be the
957 * same for Gen1/Gen2 and Gen3
958 */
959 xmt_margin = 0x5;
960 xmt_margin_oe = 0x1;
961 lane_delay = 0xF; /* Delay 240ns. */
962 lane_bundle = 0x0; /* Set to 1 lane. */
963 }
964
965 /* overwrite existing values */
966 pcie_ctrl = (xmt_margin << MARGIN_GEN1_GEN2_SHIFT)
967 | (xmt_margin_oe << MARGIN_G1_G2_OVERWRITE_SHIFT)
968 | (xmt_margin << MARGIN_SHIFT)
969 | (xmt_margin_oe << MARGIN_OVERWRITE_ENABLE_SHIFT)
970 | (lane_delay << LANE_DELAY_SHIFT)
971 | (lane_bundle << LANE_BUNDLE_SHIFT);
972
973 write_csr(dd, CCE_PCIE_CTRL, pcie_ctrl);
974 }
975
976 dd_dev_dbg(dd, "%s: program XMT margin, CcePcieCtrl 0x%llx\n",
977 fname, pcie_ctrl);
978 }
979
980 /*
981 * Do all the steps needed to transition the PCIe link to Gen3 speed.
982 */
do_pcie_gen3_transition(struct hfi1_devdata * dd)983 int do_pcie_gen3_transition(struct hfi1_devdata *dd)
984 {
985 struct pci_dev *parent = dd->pcidev->bus->self;
986 u64 fw_ctrl;
987 u64 reg, therm;
988 u32 reg32, fs, lf;
989 u32 status, err;
990 int ret;
991 int do_retry, retry_count = 0;
992 int intnum = 0;
993 uint default_pset;
994 uint pset = pcie_pset;
995 u16 target_vector, target_speed;
996 u16 lnkctl2, vendor;
997 u8 div;
998 const u8 (*eq)[3];
999 const u8 (*ctle_tunings)[4];
1000 uint static_ctle_mode;
1001 int return_error = 0;
1002 u32 target_width;
1003
1004 /* PCIe Gen3 is for the ASIC only */
1005 if (dd->icode != ICODE_RTL_SILICON)
1006 return 0;
1007
1008 if (pcie_target == 1) { /* target Gen1 */
1009 target_vector = PCI_EXP_LNKCTL2_TLS_2_5GT;
1010 target_speed = 2500;
1011 } else if (pcie_target == 2) { /* target Gen2 */
1012 target_vector = PCI_EXP_LNKCTL2_TLS_5_0GT;
1013 target_speed = 5000;
1014 } else if (pcie_target == 3) { /* target Gen3 */
1015 target_vector = PCI_EXP_LNKCTL2_TLS_8_0GT;
1016 target_speed = 8000;
1017 } else {
1018 /* off or invalid target - skip */
1019 dd_dev_info(dd, "%s: Skipping PCIe transition\n", __func__);
1020 return 0;
1021 }
1022
1023 /* if already at target speed, done (unless forced) */
1024 if (dd->lbus_speed == target_speed) {
1025 dd_dev_info(dd, "%s: PCIe already at gen%d, %s\n", __func__,
1026 pcie_target,
1027 pcie_force ? "re-doing anyway" : "skipping");
1028 if (!pcie_force)
1029 return 0;
1030 }
1031
1032 /*
1033 * The driver cannot do the transition if it has no access to the
1034 * upstream component
1035 */
1036 if (!parent) {
1037 dd_dev_info(dd, "%s: No upstream, Can't do gen3 transition\n",
1038 __func__);
1039 return 0;
1040 }
1041
1042 /* Previous Gen1/Gen2 bus width */
1043 target_width = dd->lbus_width;
1044
1045 /*
1046 * Do the Gen3 transition. Steps are those of the PCIe Gen3
1047 * recipe.
1048 */
1049
1050 /* step 1: pcie link working in gen1/gen2 */
1051
1052 /* step 2: if either side is not capable of Gen3, done */
1053 if (pcie_target == 3 && !dd->link_gen3_capable) {
1054 dd_dev_err(dd, "The PCIe link is not Gen3 capable\n");
1055 ret = -ENOSYS;
1056 goto done_no_mutex;
1057 }
1058
1059 /* hold the SBus resource across the firmware download and SBR */
1060 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT);
1061 if (ret) {
1062 dd_dev_err(dd, "%s: unable to acquire SBus resource\n",
1063 __func__);
1064 return ret;
1065 }
1066
1067 /* make sure thermal polling is not causing interrupts */
1068 therm = read_csr(dd, ASIC_CFG_THERM_POLL_EN);
1069 if (therm) {
1070 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0);
1071 msleep(100);
1072 dd_dev_info(dd, "%s: Disabled therm polling\n",
1073 __func__);
1074 }
1075
1076 retry:
1077 /* the SBus download will reset the spico for thermal */
1078
1079 /* step 3: download SBus Master firmware */
1080 /* step 4: download PCIe Gen3 SerDes firmware */
1081 dd_dev_info(dd, "%s: downloading firmware\n", __func__);
1082 ret = load_pcie_firmware(dd);
1083 if (ret) {
1084 /* do not proceed if the firmware cannot be downloaded */
1085 return_error = 1;
1086 goto done;
1087 }
1088
1089 /* step 5: set up device parameter settings */
1090 dd_dev_info(dd, "%s: setting PCIe registers\n", __func__);
1091
1092 /*
1093 * PcieCfgSpcie1 - Link Control 3
1094 * Leave at reset value. No need to set PerfEq - link equalization
1095 * will be performed automatically after the SBR when the target
1096 * speed is 8GT/s.
1097 */
1098
1099 /* clear all 16 per-lane error bits (PCIe: Lane Error Status) */
1100 pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, 0xffff);
1101
1102 /* step 5a: Set Synopsys Port Logic registers */
1103
1104 /*
1105 * PcieCfgRegPl2 - Port Force Link
1106 *
1107 * Set the low power field to 0x10 to avoid unnecessary power
1108 * management messages. All other fields are zero.
1109 */
1110 reg32 = 0x10ul << PCIE_CFG_REG_PL2_LOW_PWR_ENT_CNT_SHIFT;
1111 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL2, reg32);
1112
1113 /*
1114 * PcieCfgRegPl100 - Gen3 Control
1115 *
1116 * turn off PcieCfgRegPl100.Gen3ZRxDcNonCompl
1117 * turn on PcieCfgRegPl100.EqEieosCnt
1118 * Everything else zero.
1119 */
1120 reg32 = PCIE_CFG_REG_PL100_EQ_EIEOS_CNT_SMASK;
1121 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL100, reg32);
1122
1123 /*
1124 * PcieCfgRegPl101 - Gen3 EQ FS and LF
1125 * PcieCfgRegPl102 - Gen3 EQ Presets to Coefficients Mapping
1126 * PcieCfgRegPl103 - Gen3 EQ Preset Index
1127 * PcieCfgRegPl105 - Gen3 EQ Status
1128 *
1129 * Give initial EQ settings.
1130 */
1131 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL0) { /* discrete */
1132 /* 1000mV, FS=24, LF = 8 */
1133 fs = 24;
1134 lf = 8;
1135 div = 3;
1136 eq = discrete_preliminary_eq;
1137 default_pset = DEFAULT_DISCRETE_PSET;
1138 ctle_tunings = discrete_ctle_tunings;
1139 /* bit 0 - discrete on/off */
1140 static_ctle_mode = pcie_ctle & 0x1;
1141 } else {
1142 /* 400mV, FS=29, LF = 9 */
1143 fs = 29;
1144 lf = 9;
1145 div = 1;
1146 eq = integrated_preliminary_eq;
1147 default_pset = DEFAULT_MCP_PSET;
1148 ctle_tunings = integrated_ctle_tunings;
1149 /* bit 1 - integrated on/off */
1150 static_ctle_mode = (pcie_ctle >> 1) & 0x1;
1151 }
1152 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL101,
1153 (fs <<
1154 PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_FS_SHIFT) |
1155 (lf <<
1156 PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_LF_SHIFT));
1157 ret = load_eq_table(dd, eq, fs, div);
1158 if (ret)
1159 goto done;
1160
1161 /*
1162 * PcieCfgRegPl106 - Gen3 EQ Control
1163 *
1164 * Set Gen3EqPsetReqVec, leave other fields 0.
1165 */
1166 if (pset == UNSET_PSET)
1167 pset = default_pset;
1168 if (pset > 10) { /* valid range is 0-10, inclusive */
1169 dd_dev_err(dd, "%s: Invalid Eq Pset %u, setting to %d\n",
1170 __func__, pset, default_pset);
1171 pset = default_pset;
1172 }
1173 dd_dev_info(dd, "%s: using EQ Pset %u\n", __func__, pset);
1174 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL106,
1175 ((1 << pset) <<
1176 PCIE_CFG_REG_PL106_GEN3_EQ_PSET_REQ_VEC_SHIFT) |
1177 PCIE_CFG_REG_PL106_GEN3_EQ_EVAL2MS_DISABLE_SMASK |
1178 PCIE_CFG_REG_PL106_GEN3_EQ_PHASE23_EXIT_MODE_SMASK);
1179
1180 /*
1181 * step 5b: Do post firmware download steps via SBus
1182 */
1183 dd_dev_info(dd, "%s: doing pcie post steps\n", __func__);
1184 pcie_post_steps(dd);
1185
1186 /*
1187 * step 5c: Program gasket interrupts
1188 */
1189 /* set the Rx Bit Rate to REFCLK ratio */
1190 write_gasket_interrupt(dd, intnum++, 0x0006, 0x0050);
1191 /* disable pCal for PCIe Gen3 RX equalization */
1192 /* select adaptive or static CTLE */
1193 write_gasket_interrupt(dd, intnum++, 0x0026,
1194 0x5b01 | (static_ctle_mode << 3));
1195 /*
1196 * Enable iCal for PCIe Gen3 RX equalization, and set which
1197 * evaluation of RX_EQ_EVAL will launch the iCal procedure.
1198 */
1199 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5202);
1200
1201 if (static_ctle_mode) {
1202 /* apply static CTLE tunings */
1203 u8 pcie_dc, pcie_lf, pcie_hf, pcie_bw;
1204
1205 pcie_dc = ctle_tunings[pset][0];
1206 pcie_lf = ctle_tunings[pset][1];
1207 pcie_hf = ctle_tunings[pset][2];
1208 pcie_bw = ctle_tunings[pset][3];
1209 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0200 | pcie_dc);
1210 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0100 | pcie_lf);
1211 write_gasket_interrupt(dd, intnum++, 0x0026, 0x0000 | pcie_hf);
1212 write_gasket_interrupt(dd, intnum++, 0x0026, 0x5500 | pcie_bw);
1213 }
1214
1215 /* terminate list */
1216 write_gasket_interrupt(dd, intnum++, 0x0000, 0x0000);
1217
1218 /*
1219 * step 5d: program XMT margin
1220 */
1221 write_xmt_margin(dd, __func__);
1222
1223 /*
1224 * step 5e: disable active state power management (ASPM). It
1225 * will be enabled if required later
1226 */
1227 dd_dev_info(dd, "%s: clearing ASPM\n", __func__);
1228 aspm_hw_disable_l1(dd);
1229
1230 /*
1231 * step 5f: clear DirectSpeedChange
1232 * PcieCfgRegPl67.DirectSpeedChange must be zero to prevent the
1233 * change in the speed target from starting before we are ready.
1234 * This field defaults to 0 and we are not changing it, so nothing
1235 * needs to be done.
1236 */
1237
1238 /* step 5g: Set target link speed */
1239 /*
1240 * Set target link speed to be target on both device and parent.
1241 * On setting the parent: Some system BIOSs "helpfully" set the
1242 * parent target speed to Gen2 to match the ASIC's initial speed.
1243 * We can set the target Gen3 because we have already checked
1244 * that it is Gen3 capable earlier.
1245 */
1246 dd_dev_info(dd, "%s: setting parent target link speed\n", __func__);
1247 ret = pcie_capability_read_word(parent, PCI_EXP_LNKCTL2, &lnkctl2);
1248 if (ret) {
1249 dd_dev_err(dd, "Unable to read from PCI config\n");
1250 return_error = 1;
1251 goto done;
1252 }
1253
1254 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__,
1255 (u32)lnkctl2);
1256 /* only write to parent if target is not as high as ours */
1257 if ((lnkctl2 & PCI_EXP_LNKCTL2_TLS) < target_vector) {
1258 lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS;
1259 lnkctl2 |= target_vector;
1260 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__,
1261 (u32)lnkctl2);
1262 ret = pcie_capability_write_word(parent,
1263 PCI_EXP_LNKCTL2, lnkctl2);
1264 if (ret) {
1265 dd_dev_err(dd, "Unable to write to PCI config\n");
1266 return_error = 1;
1267 goto done;
1268 }
1269 } else {
1270 dd_dev_info(dd, "%s: ..target speed is OK\n", __func__);
1271 }
1272
1273 dd_dev_info(dd, "%s: setting target link speed\n", __func__);
1274 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL2, &lnkctl2);
1275 if (ret) {
1276 dd_dev_err(dd, "Unable to read from PCI config\n");
1277 return_error = 1;
1278 goto done;
1279 }
1280
1281 dd_dev_info(dd, "%s: ..old link control2: 0x%x\n", __func__,
1282 (u32)lnkctl2);
1283 lnkctl2 &= ~PCI_EXP_LNKCTL2_TLS;
1284 lnkctl2 |= target_vector;
1285 dd_dev_info(dd, "%s: ..new link control2: 0x%x\n", __func__,
1286 (u32)lnkctl2);
1287 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL2, lnkctl2);
1288 if (ret) {
1289 dd_dev_err(dd, "Unable to write to PCI config\n");
1290 return_error = 1;
1291 goto done;
1292 }
1293
1294 /* step 5h: arm gasket logic */
1295 /* hold DC in reset across the SBR */
1296 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK);
1297 (void)read_csr(dd, CCE_DC_CTRL); /* DC reset hold */
1298 /* save firmware control across the SBR */
1299 fw_ctrl = read_csr(dd, MISC_CFG_FW_CTRL);
1300
1301 dd_dev_info(dd, "%s: arming gasket logic\n", __func__);
1302 arm_gasket_logic(dd);
1303
1304 /*
1305 * step 6: quiesce PCIe link
1306 * The chip has already been reset, so there will be no traffic
1307 * from the chip. Linux has no easy way to enforce that it will
1308 * not try to access the device, so we just need to hope it doesn't
1309 * do it while we are doing the reset.
1310 */
1311
1312 /*
1313 * step 7: initiate the secondary bus reset (SBR)
1314 * step 8: hardware brings the links back up
1315 * step 9: wait for link speed transition to be complete
1316 */
1317 dd_dev_info(dd, "%s: calling trigger_sbr\n", __func__);
1318 ret = trigger_sbr(dd);
1319 if (ret)
1320 goto done;
1321
1322 /* step 10: decide what to do next */
1323
1324 /* check if we can read PCI space */
1325 ret = pci_read_config_word(dd->pcidev, PCI_VENDOR_ID, &vendor);
1326 if (ret) {
1327 dd_dev_info(dd,
1328 "%s: read of VendorID failed after SBR, err %d\n",
1329 __func__, ret);
1330 return_error = 1;
1331 goto done;
1332 }
1333 if (vendor == 0xffff) {
1334 dd_dev_info(dd, "%s: VendorID is all 1s after SBR\n", __func__);
1335 return_error = 1;
1336 ret = -EIO;
1337 goto done;
1338 }
1339
1340 /* restore PCI space registers we know were reset */
1341 dd_dev_info(dd, "%s: calling restore_pci_variables\n", __func__);
1342 ret = restore_pci_variables(dd);
1343 if (ret) {
1344 dd_dev_err(dd, "%s: Could not restore PCI variables\n",
1345 __func__);
1346 return_error = 1;
1347 goto done;
1348 }
1349
1350 /* restore firmware control */
1351 write_csr(dd, MISC_CFG_FW_CTRL, fw_ctrl);
1352
1353 /*
1354 * Check the gasket block status.
1355 *
1356 * This is the first CSR read after the SBR. If the read returns
1357 * all 1s (fails), the link did not make it back.
1358 *
1359 * Once we're sure we can read and write, clear the DC reset after
1360 * the SBR. Then check for any per-lane errors. Then look over
1361 * the status.
1362 */
1363 reg = read_csr(dd, ASIC_PCIE_SD_HOST_STATUS);
1364 dd_dev_info(dd, "%s: gasket block status: 0x%llx\n", __func__, reg);
1365 if (reg == ~0ull) { /* PCIe read failed/timeout */
1366 dd_dev_err(dd, "SBR failed - unable to read from device\n");
1367 return_error = 1;
1368 ret = -ENOSYS;
1369 goto done;
1370 }
1371
1372 /* clear the DC reset */
1373 write_csr(dd, CCE_DC_CTRL, 0);
1374
1375 /* Set the LED off */
1376 setextled(dd, 0);
1377
1378 /* check for any per-lane errors */
1379 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, ®32);
1380 if (ret) {
1381 dd_dev_err(dd, "Unable to read from PCI config\n");
1382 return_error = 1;
1383 goto done;
1384 }
1385
1386 dd_dev_info(dd, "%s: per-lane errors: 0x%x\n", __func__, reg32);
1387
1388 /* extract status, look for our HFI */
1389 status = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_SHIFT)
1390 & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_MASK;
1391 if ((status & (1 << dd->hfi1_id)) == 0) {
1392 dd_dev_err(dd,
1393 "%s: gasket status 0x%x, expecting 0x%x\n",
1394 __func__, status, 1 << dd->hfi1_id);
1395 ret = -EIO;
1396 goto done;
1397 }
1398
1399 /* extract error */
1400 err = (reg >> ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_SHIFT)
1401 & ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_MASK;
1402 if (err) {
1403 dd_dev_err(dd, "%s: gasket error %d\n", __func__, err);
1404 ret = -EIO;
1405 goto done;
1406 }
1407
1408 /* update our link information cache */
1409 update_lbus_info(dd);
1410 dd_dev_info(dd, "%s: new speed and width: %s\n", __func__,
1411 dd->lbus_info);
1412
1413 if (dd->lbus_speed != target_speed ||
1414 dd->lbus_width < target_width) { /* not target */
1415 /* maybe retry */
1416 do_retry = retry_count < pcie_retry;
1417 dd_dev_err(dd, "PCIe link speed or width did not match target%s\n",
1418 do_retry ? ", retrying" : "");
1419 retry_count++;
1420 if (do_retry) {
1421 msleep(100); /* allow time to settle */
1422 goto retry;
1423 }
1424 ret = -EIO;
1425 }
1426
1427 done:
1428 if (therm) {
1429 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1);
1430 msleep(100);
1431 dd_dev_info(dd, "%s: Re-enable therm polling\n",
1432 __func__);
1433 }
1434 release_chip_resource(dd, CR_SBUS);
1435 done_no_mutex:
1436 /* return no error if it is OK to be at current speed */
1437 if (ret && !return_error) {
1438 dd_dev_err(dd, "Proceeding at current speed PCIe speed\n");
1439 ret = 0;
1440 }
1441
1442 dd_dev_info(dd, "%s: done\n", __func__);
1443 return ret;
1444 }
1445
