1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
4 * Rewrite, cleanup:
5 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
6 */
7
8 #ifndef _ASM_IOMMU_H
9 #define _ASM_IOMMU_H
10 #ifdef __KERNEL__
11
12 #include <linux/compiler.h>
13 #include <linux/spinlock.h>
14 #include <linux/device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/bitops.h>
17 #include <asm/machdep.h>
18 #include <asm/types.h>
19 #include <asm/pci-bridge.h>
20 #include <asm/asm-const.h>
21
22 #define IOMMU_PAGE_SHIFT_4K 12
23 #define IOMMU_PAGE_SIZE_4K (ASM_CONST(1) << IOMMU_PAGE_SHIFT_4K)
24 #define IOMMU_PAGE_MASK_4K (~((1 << IOMMU_PAGE_SHIFT_4K) - 1))
25 #define IOMMU_PAGE_ALIGN_4K(addr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE_4K)
26
27 #define IOMMU_PAGE_SIZE(tblptr) (ASM_CONST(1) << (tblptr)->it_page_shift)
28 #define IOMMU_PAGE_MASK(tblptr) (~((1 << (tblptr)->it_page_shift) - 1))
29 #define IOMMU_PAGE_ALIGN(addr, tblptr) _ALIGN_UP(addr, IOMMU_PAGE_SIZE(tblptr))
30
31 /* Boot time flags */
32 extern int iommu_is_off;
33 extern int iommu_force_on;
34
35 struct iommu_table_ops {
36 /*
37 * When called with direction==DMA_NONE, it is equal to clear().
38 * uaddr is a linear map address.
39 */
40 int (*set)(struct iommu_table *tbl,
41 long index, long npages,
42 unsigned long uaddr,
43 enum dma_data_direction direction,
44 unsigned long attrs);
45 #ifdef CONFIG_IOMMU_API
46 /*
47 * Exchanges existing TCE with new TCE plus direction bits;
48 * returns old TCE and DMA direction mask.
49 * @tce is a physical address.
50 */
51 int (*xchg_no_kill)(struct iommu_table *tbl,
52 long index,
53 unsigned long *hpa,
54 enum dma_data_direction *direction,
55 bool realmode);
56
57 void (*tce_kill)(struct iommu_table *tbl,
58 unsigned long index,
59 unsigned long pages,
60 bool realmode);
61
62 __be64 *(*useraddrptr)(struct iommu_table *tbl, long index, bool alloc);
63 #endif
64 void (*clear)(struct iommu_table *tbl,
65 long index, long npages);
66 /* get() returns a physical address */
67 unsigned long (*get)(struct iommu_table *tbl, long index);
68 void (*flush)(struct iommu_table *tbl);
69 void (*free)(struct iommu_table *tbl);
70 };
71
72 /* These are used by VIO */
73 extern struct iommu_table_ops iommu_table_lpar_multi_ops;
74 extern struct iommu_table_ops iommu_table_pseries_ops;
75
76 /*
77 * IOMAP_MAX_ORDER defines the largest contiguous block
78 * of dma space we can get. IOMAP_MAX_ORDER = 13
79 * allows up to 2**12 pages (4096 * 4096) = 16 MB
80 */
81 #define IOMAP_MAX_ORDER 13
82
83 #define IOMMU_POOL_HASHBITS 2
84 #define IOMMU_NR_POOLS (1 << IOMMU_POOL_HASHBITS)
85
86 struct iommu_pool {
87 unsigned long start;
88 unsigned long end;
89 unsigned long hint;
90 spinlock_t lock;
91 } ____cacheline_aligned_in_smp;
92
93 struct iommu_table {
94 unsigned long it_busno; /* Bus number this table belongs to */
95 unsigned long it_size; /* Size of iommu table in entries */
96 unsigned long it_indirect_levels;
97 unsigned long it_level_size;
98 unsigned long it_allocated_size;
99 unsigned long it_offset; /* Offset into global table */
100 unsigned long it_base; /* mapped address of tce table */
101 unsigned long it_index; /* which iommu table this is */
102 unsigned long it_type; /* type: PCI or Virtual Bus */
103 unsigned long it_blocksize; /* Entries in each block (cacheline) */
104 unsigned long poolsize;
105 unsigned long nr_pools;
106 struct iommu_pool large_pool;
107 struct iommu_pool pools[IOMMU_NR_POOLS];
108 unsigned long *it_map; /* A simple allocation bitmap for now */
109 unsigned long it_page_shift;/* table iommu page size */
110 struct list_head it_group_list;/* List of iommu_table_group_link */
111 __be64 *it_userspace; /* userspace view of the table */
112 struct iommu_table_ops *it_ops;
113 struct kref it_kref;
114 int it_nid;
115 unsigned long it_reserved_start; /* Start of not-DMA-able (MMIO) area */
116 unsigned long it_reserved_end;
117 };
118
119 #define IOMMU_TABLE_USERSPACE_ENTRY_RO(tbl, entry) \
120 ((tbl)->it_ops->useraddrptr((tbl), (entry), false))
121 #define IOMMU_TABLE_USERSPACE_ENTRY(tbl, entry) \
122 ((tbl)->it_ops->useraddrptr((tbl), (entry), true))
123
124 /* Pure 2^n version of get_order */
125 static inline __attribute_const__
get_iommu_order(unsigned long size,struct iommu_table * tbl)126 int get_iommu_order(unsigned long size, struct iommu_table *tbl)
127 {
128 return __ilog2((size - 1) >> tbl->it_page_shift) + 1;
129 }
130
131
132 struct scatterlist;
133
134 #ifdef CONFIG_PPC64
135
set_iommu_table_base(struct device * dev,struct iommu_table * base)136 static inline void set_iommu_table_base(struct device *dev,
137 struct iommu_table *base)
138 {
139 dev->archdata.iommu_table_base = base;
140 }
141
get_iommu_table_base(struct device * dev)142 static inline void *get_iommu_table_base(struct device *dev)
143 {
144 return dev->archdata.iommu_table_base;
145 }
146
147 extern int dma_iommu_dma_supported(struct device *dev, u64 mask);
148
149 extern struct iommu_table *iommu_tce_table_get(struct iommu_table *tbl);
150 extern int iommu_tce_table_put(struct iommu_table *tbl);
151
152 /* Initializes an iommu_table based in values set in the passed-in
153 * structure
154 */
155 extern struct iommu_table *iommu_init_table(struct iommu_table *tbl,
156 int nid, unsigned long res_start, unsigned long res_end);
157
158 #define IOMMU_TABLE_GROUP_MAX_TABLES 2
159
160 struct iommu_table_group;
161
162 struct iommu_table_group_ops {
163 unsigned long (*get_table_size)(
164 __u32 page_shift,
165 __u64 window_size,
166 __u32 levels);
167 long (*create_table)(struct iommu_table_group *table_group,
168 int num,
169 __u32 page_shift,
170 __u64 window_size,
171 __u32 levels,
172 struct iommu_table **ptbl);
173 long (*set_window)(struct iommu_table_group *table_group,
174 int num,
175 struct iommu_table *tblnew);
176 long (*unset_window)(struct iommu_table_group *table_group,
177 int num);
178 /* Switch ownership from platform code to external user (e.g. VFIO) */
179 void (*take_ownership)(struct iommu_table_group *table_group);
180 /* Switch ownership from external user (e.g. VFIO) back to core */
181 void (*release_ownership)(struct iommu_table_group *table_group);
182 };
183
184 struct iommu_table_group_link {
185 struct list_head next;
186 struct rcu_head rcu;
187 struct iommu_table_group *table_group;
188 };
189
190 struct iommu_table_group {
191 /* IOMMU properties */
192 __u32 tce32_start;
193 __u32 tce32_size;
194 __u64 pgsizes; /* Bitmap of supported page sizes */
195 __u32 max_dynamic_windows_supported;
196 __u32 max_levels;
197
198 struct iommu_group *group;
199 struct iommu_table *tables[IOMMU_TABLE_GROUP_MAX_TABLES];
200 struct iommu_table_group_ops *ops;
201 };
202
203 #ifdef CONFIG_IOMMU_API
204
205 extern void iommu_register_group(struct iommu_table_group *table_group,
206 int pci_domain_number, unsigned long pe_num);
207 extern int iommu_add_device(struct iommu_table_group *table_group,
208 struct device *dev);
209 extern void iommu_del_device(struct device *dev);
210 extern long iommu_tce_xchg(struct mm_struct *mm, struct iommu_table *tbl,
211 unsigned long entry, unsigned long *hpa,
212 enum dma_data_direction *direction);
213 extern long iommu_tce_xchg_no_kill(struct mm_struct *mm,
214 struct iommu_table *tbl,
215 unsigned long entry, unsigned long *hpa,
216 enum dma_data_direction *direction);
217 extern void iommu_tce_kill(struct iommu_table *tbl,
218 unsigned long entry, unsigned long pages);
219 #else
iommu_register_group(struct iommu_table_group * table_group,int pci_domain_number,unsigned long pe_num)220 static inline void iommu_register_group(struct iommu_table_group *table_group,
221 int pci_domain_number,
222 unsigned long pe_num)
223 {
224 }
225
iommu_add_device(struct iommu_table_group * table_group,struct device * dev)226 static inline int iommu_add_device(struct iommu_table_group *table_group,
227 struct device *dev)
228 {
229 return 0;
230 }
231
iommu_del_device(struct device * dev)232 static inline void iommu_del_device(struct device *dev)
233 {
234 }
235 #endif /* !CONFIG_IOMMU_API */
236
237 u64 dma_iommu_get_required_mask(struct device *dev);
238 #else
239
get_iommu_table_base(struct device * dev)240 static inline void *get_iommu_table_base(struct device *dev)
241 {
242 return NULL;
243 }
244
dma_iommu_dma_supported(struct device * dev,u64 mask)245 static inline int dma_iommu_dma_supported(struct device *dev, u64 mask)
246 {
247 return 0;
248 }
249
250 #endif /* CONFIG_PPC64 */
251
252 extern int ppc_iommu_map_sg(struct device *dev, struct iommu_table *tbl,
253 struct scatterlist *sglist, int nelems,
254 unsigned long mask,
255 enum dma_data_direction direction,
256 unsigned long attrs);
257 extern void ppc_iommu_unmap_sg(struct iommu_table *tbl,
258 struct scatterlist *sglist,
259 int nelems,
260 enum dma_data_direction direction,
261 unsigned long attrs);
262
263 extern void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl,
264 size_t size, dma_addr_t *dma_handle,
265 unsigned long mask, gfp_t flag, int node);
266 extern void iommu_free_coherent(struct iommu_table *tbl, size_t size,
267 void *vaddr, dma_addr_t dma_handle);
268 extern dma_addr_t iommu_map_page(struct device *dev, struct iommu_table *tbl,
269 struct page *page, unsigned long offset,
270 size_t size, unsigned long mask,
271 enum dma_data_direction direction,
272 unsigned long attrs);
273 extern void iommu_unmap_page(struct iommu_table *tbl, dma_addr_t dma_handle,
274 size_t size, enum dma_data_direction direction,
275 unsigned long attrs);
276
277 extern void iommu_init_early_pSeries(void);
278 extern void iommu_init_early_dart(struct pci_controller_ops *controller_ops);
279 extern void iommu_init_early_pasemi(void);
280
281 #if defined(CONFIG_PPC64) && defined(CONFIG_PM)
iommu_save(void)282 static inline void iommu_save(void)
283 {
284 if (ppc_md.iommu_save)
285 ppc_md.iommu_save();
286 }
287
iommu_restore(void)288 static inline void iommu_restore(void)
289 {
290 if (ppc_md.iommu_restore)
291 ppc_md.iommu_restore();
292 }
293 #endif
294
295 /* The API to support IOMMU operations for VFIO */
296 extern int iommu_tce_check_ioba(unsigned long page_shift,
297 unsigned long offset, unsigned long size,
298 unsigned long ioba, unsigned long npages);
299 extern int iommu_tce_check_gpa(unsigned long page_shift,
300 unsigned long gpa);
301
302 #define iommu_tce_clear_param_check(tbl, ioba, tce_value, npages) \
303 (iommu_tce_check_ioba((tbl)->it_page_shift, \
304 (tbl)->it_offset, (tbl)->it_size, \
305 (ioba), (npages)) || (tce_value))
306 #define iommu_tce_put_param_check(tbl, ioba, gpa) \
307 (iommu_tce_check_ioba((tbl)->it_page_shift, \
308 (tbl)->it_offset, (tbl)->it_size, \
309 (ioba), 1) || \
310 iommu_tce_check_gpa((tbl)->it_page_shift, (gpa)))
311
312 extern void iommu_flush_tce(struct iommu_table *tbl);
313 extern int iommu_take_ownership(struct iommu_table *tbl);
314 extern void iommu_release_ownership(struct iommu_table *tbl);
315
316 extern enum dma_data_direction iommu_tce_direction(unsigned long tce);
317 extern unsigned long iommu_direction_to_tce_perm(enum dma_data_direction dir);
318
319 #ifdef CONFIG_PPC_CELL_NATIVE
320 extern bool iommu_fixed_is_weak;
321 #else
322 #define iommu_fixed_is_weak false
323 #endif
324
325 extern const struct dma_map_ops dma_iommu_ops;
326
327 #endif /* __KERNEL__ */
328 #endif /* _ASM_IOMMU_H */
329
