1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
4 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
5 */
6
7 #include <linux/delay.h>
8 #include <linux/slab.h>
9 #include <linux/init.h>
10 #include <linux/module.h>
11 #include <linux/mtd/mtd.h>
12 #include <linux/mtd/rawnand.h>
13 #include <linux/mtd/partitions.h>
14 #include <linux/interrupt.h>
15 #include <linux/device.h>
16 #include <linux/platform_device.h>
17 #include <linux/clk.h>
18 #include <linux/err.h>
19 #include <linux/io.h>
20 #include <linux/irq.h>
21 #include <linux/completion.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/platform_data/mtd-mxc_nand.h>
25
26 #define DRIVER_NAME "mxc_nand"
27
28 /* Addresses for NFC registers */
29 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
30 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
31 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
32 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
33 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
34 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
35 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
36 #define NFC_V21_RSLTSPARE_AREA (host->regs + 0x10)
37 #define NFC_V1_V2_WRPROT (host->regs + 0x12)
38 #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
39 #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
40 #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20)
41 #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24)
42 #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28)
43 #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c)
44 #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22)
45 #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26)
46 #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a)
47 #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e)
48 #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
49 #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
50 #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
51
52 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
53 #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
54 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
55 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
56 #define NFC_V1_V2_CONFIG1_BIG (1 << 5)
57 #define NFC_V1_V2_CONFIG1_RST (1 << 6)
58 #define NFC_V1_V2_CONFIG1_CE (1 << 7)
59 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
60 #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
61 #define NFC_V2_CONFIG1_FP_INT (1 << 11)
62
63 #define NFC_V1_V2_CONFIG2_INT (1 << 15)
64
65 /*
66 * Operation modes for the NFC. Valid for v1, v2 and v3
67 * type controllers.
68 */
69 #define NFC_CMD (1 << 0)
70 #define NFC_ADDR (1 << 1)
71 #define NFC_INPUT (1 << 2)
72 #define NFC_OUTPUT (1 << 3)
73 #define NFC_ID (1 << 4)
74 #define NFC_STATUS (1 << 5)
75
76 #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
77 #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
78
79 #define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
80 #define NFC_V3_CONFIG1_SP_EN (1 << 0)
81 #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
82
83 #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
84
85 #define NFC_V3_LAUNCH (host->regs_axi + 0x40)
86
87 #define NFC_V3_WRPROT (host->regs_ip + 0x0)
88 #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
89 #define NFC_V3_WRPROT_LOCK (1 << 1)
90 #define NFC_V3_WRPROT_UNLOCK (1 << 2)
91 #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
92
93 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
94
95 #define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
96 #define NFC_V3_CONFIG2_PS_512 (0 << 0)
97 #define NFC_V3_CONFIG2_PS_2048 (1 << 0)
98 #define NFC_V3_CONFIG2_PS_4096 (2 << 0)
99 #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
100 #define NFC_V3_CONFIG2_ECC_EN (1 << 3)
101 #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
102 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
103 #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
104 #define NFC_V3_CONFIG2_PPB(x, shift) (((x) & 0x3) << shift)
105 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
106 #define NFC_V3_CONFIG2_INT_MSK (1 << 15)
107 #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
108 #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
109
110 #define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
111 #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
112 #define NFC_V3_CONFIG3_FW8 (1 << 3)
113 #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
114 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
115 #define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
116 #define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
117
118 #define NFC_V3_IPC (host->regs_ip + 0x2C)
119 #define NFC_V3_IPC_CREQ (1 << 0)
120 #define NFC_V3_IPC_INT (1 << 31)
121
122 #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
123
124 struct mxc_nand_host;
125
126 struct mxc_nand_devtype_data {
127 void (*preset)(struct mtd_info *);
128 int (*read_page)(struct nand_chip *chip, void *buf, void *oob, bool ecc,
129 int page);
130 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
131 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
132 void (*send_page)(struct mtd_info *, unsigned int);
133 void (*send_read_id)(struct mxc_nand_host *);
134 uint16_t (*get_dev_status)(struct mxc_nand_host *);
135 int (*check_int)(struct mxc_nand_host *);
136 void (*irq_control)(struct mxc_nand_host *, int);
137 u32 (*get_ecc_status)(struct mxc_nand_host *);
138 const struct mtd_ooblayout_ops *ooblayout;
139 void (*select_chip)(struct mtd_info *mtd, int chip);
140 int (*setup_data_interface)(struct mtd_info *mtd, int csline,
141 const struct nand_data_interface *conf);
142 void (*enable_hwecc)(struct nand_chip *chip, bool enable);
143
144 /*
145 * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked
146 * (CONFIG1:INT_MSK is set). To handle this the driver uses
147 * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK
148 */
149 int irqpending_quirk;
150 int needs_ip;
151
152 size_t regs_offset;
153 size_t spare0_offset;
154 size_t axi_offset;
155
156 int spare_len;
157 int eccbytes;
158 int eccsize;
159 int ppb_shift;
160 };
161
162 struct mxc_nand_host {
163 struct nand_chip nand;
164 struct device *dev;
165
166 void __iomem *spare0;
167 void __iomem *main_area0;
168
169 void __iomem *base;
170 void __iomem *regs;
171 void __iomem *regs_axi;
172 void __iomem *regs_ip;
173 int status_request;
174 struct clk *clk;
175 int clk_act;
176 int irq;
177 int eccsize;
178 int used_oobsize;
179 int active_cs;
180
181 struct completion op_completion;
182
183 uint8_t *data_buf;
184 unsigned int buf_start;
185
186 const struct mxc_nand_devtype_data *devtype_data;
187 struct mxc_nand_platform_data pdata;
188 };
189
190 static const char * const part_probes[] = {
191 "cmdlinepart", "RedBoot", "ofpart", NULL };
192
memcpy32_fromio(void * trg,const void __iomem * src,size_t size)193 static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size)
194 {
195 int i;
196 u32 *t = trg;
197 const __iomem u32 *s = src;
198
199 for (i = 0; i < (size >> 2); i++)
200 *t++ = __raw_readl(s++);
201 }
202
memcpy16_fromio(void * trg,const void __iomem * src,size_t size)203 static void memcpy16_fromio(void *trg, const void __iomem *src, size_t size)
204 {
205 int i;
206 u16 *t = trg;
207 const __iomem u16 *s = src;
208
209 /* We assume that src (IO) is always 32bit aligned */
210 if (PTR_ALIGN(trg, 4) == trg && IS_ALIGNED(size, 4)) {
211 memcpy32_fromio(trg, src, size);
212 return;
213 }
214
215 for (i = 0; i < (size >> 1); i++)
216 *t++ = __raw_readw(s++);
217 }
218
memcpy32_toio(void __iomem * trg,const void * src,int size)219 static inline void memcpy32_toio(void __iomem *trg, const void *src, int size)
220 {
221 /* __iowrite32_copy use 32bit size values so divide by 4 */
222 __iowrite32_copy(trg, src, size / 4);
223 }
224
memcpy16_toio(void __iomem * trg,const void * src,int size)225 static void memcpy16_toio(void __iomem *trg, const void *src, int size)
226 {
227 int i;
228 __iomem u16 *t = trg;
229 const u16 *s = src;
230
231 /* We assume that trg (IO) is always 32bit aligned */
232 if (PTR_ALIGN(src, 4) == src && IS_ALIGNED(size, 4)) {
233 memcpy32_toio(trg, src, size);
234 return;
235 }
236
237 for (i = 0; i < (size >> 1); i++)
238 __raw_writew(*s++, t++);
239 }
240
241 /*
242 * The controller splits a page into data chunks of 512 bytes + partial oob.
243 * There are writesize / 512 such chunks, the size of the partial oob parts is
244 * oobsize / #chunks rounded down to a multiple of 2. The last oob chunk then
245 * contains additionally the byte lost by rounding (if any).
246 * This function handles the needed shuffling between host->data_buf (which
247 * holds a page in natural order, i.e. writesize bytes data + oobsize bytes
248 * spare) and the NFC buffer.
249 */
copy_spare(struct mtd_info * mtd,bool bfrom,void * buf)250 static void copy_spare(struct mtd_info *mtd, bool bfrom, void *buf)
251 {
252 struct nand_chip *this = mtd_to_nand(mtd);
253 struct mxc_nand_host *host = nand_get_controller_data(this);
254 u16 i, oob_chunk_size;
255 u16 num_chunks = mtd->writesize / 512;
256
257 u8 *d = buf;
258 u8 __iomem *s = host->spare0;
259 u16 sparebuf_size = host->devtype_data->spare_len;
260
261 /* size of oob chunk for all but possibly the last one */
262 oob_chunk_size = (host->used_oobsize / num_chunks) & ~1;
263
264 if (bfrom) {
265 for (i = 0; i < num_chunks - 1; i++)
266 memcpy16_fromio(d + i * oob_chunk_size,
267 s + i * sparebuf_size,
268 oob_chunk_size);
269
270 /* the last chunk */
271 memcpy16_fromio(d + i * oob_chunk_size,
272 s + i * sparebuf_size,
273 host->used_oobsize - i * oob_chunk_size);
274 } else {
275 for (i = 0; i < num_chunks - 1; i++)
276 memcpy16_toio(&s[i * sparebuf_size],
277 &d[i * oob_chunk_size],
278 oob_chunk_size);
279
280 /* the last chunk */
281 memcpy16_toio(&s[i * sparebuf_size],
282 &d[i * oob_chunk_size],
283 host->used_oobsize - i * oob_chunk_size);
284 }
285 }
286
287 /*
288 * MXC NANDFC can only perform full page+spare or spare-only read/write. When
289 * the upper layers perform a read/write buf operation, the saved column address
290 * is used to index into the full page. So usually this function is called with
291 * column == 0 (unless no column cycle is needed indicated by column == -1)
292 */
mxc_do_addr_cycle(struct mtd_info * mtd,int column,int page_addr)293 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
294 {
295 struct nand_chip *nand_chip = mtd_to_nand(mtd);
296 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
297
298 /* Write out column address, if necessary */
299 if (column != -1) {
300 host->devtype_data->send_addr(host, column & 0xff,
301 page_addr == -1);
302 if (mtd->writesize > 512)
303 /* another col addr cycle for 2k page */
304 host->devtype_data->send_addr(host,
305 (column >> 8) & 0xff,
306 false);
307 }
308
309 /* Write out page address, if necessary */
310 if (page_addr != -1) {
311 /* paddr_0 - p_addr_7 */
312 host->devtype_data->send_addr(host, (page_addr & 0xff), false);
313
314 if (mtd->writesize > 512) {
315 if (mtd->size >= 0x10000000) {
316 /* paddr_8 - paddr_15 */
317 host->devtype_data->send_addr(host,
318 (page_addr >> 8) & 0xff,
319 false);
320 host->devtype_data->send_addr(host,
321 (page_addr >> 16) & 0xff,
322 true);
323 } else
324 /* paddr_8 - paddr_15 */
325 host->devtype_data->send_addr(host,
326 (page_addr >> 8) & 0xff, true);
327 } else {
328 if (nand_chip->options & NAND_ROW_ADDR_3) {
329 /* paddr_8 - paddr_15 */
330 host->devtype_data->send_addr(host,
331 (page_addr >> 8) & 0xff,
332 false);
333 host->devtype_data->send_addr(host,
334 (page_addr >> 16) & 0xff,
335 true);
336 } else
337 /* paddr_8 - paddr_15 */
338 host->devtype_data->send_addr(host,
339 (page_addr >> 8) & 0xff, true);
340 }
341 }
342 }
343
check_int_v3(struct mxc_nand_host * host)344 static int check_int_v3(struct mxc_nand_host *host)
345 {
346 uint32_t tmp;
347
348 tmp = readl(NFC_V3_IPC);
349 if (!(tmp & NFC_V3_IPC_INT))
350 return 0;
351
352 tmp &= ~NFC_V3_IPC_INT;
353 writel(tmp, NFC_V3_IPC);
354
355 return 1;
356 }
357
check_int_v1_v2(struct mxc_nand_host * host)358 static int check_int_v1_v2(struct mxc_nand_host *host)
359 {
360 uint32_t tmp;
361
362 tmp = readw(NFC_V1_V2_CONFIG2);
363 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
364 return 0;
365
366 if (!host->devtype_data->irqpending_quirk)
367 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
368
369 return 1;
370 }
371
irq_control_v1_v2(struct mxc_nand_host * host,int activate)372 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
373 {
374 uint16_t tmp;
375
376 tmp = readw(NFC_V1_V2_CONFIG1);
377
378 if (activate)
379 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
380 else
381 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
382
383 writew(tmp, NFC_V1_V2_CONFIG1);
384 }
385
irq_control_v3(struct mxc_nand_host * host,int activate)386 static void irq_control_v3(struct mxc_nand_host *host, int activate)
387 {
388 uint32_t tmp;
389
390 tmp = readl(NFC_V3_CONFIG2);
391
392 if (activate)
393 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
394 else
395 tmp |= NFC_V3_CONFIG2_INT_MSK;
396
397 writel(tmp, NFC_V3_CONFIG2);
398 }
399
irq_control(struct mxc_nand_host * host,int activate)400 static void irq_control(struct mxc_nand_host *host, int activate)
401 {
402 if (host->devtype_data->irqpending_quirk) {
403 if (activate)
404 enable_irq(host->irq);
405 else
406 disable_irq_nosync(host->irq);
407 } else {
408 host->devtype_data->irq_control(host, activate);
409 }
410 }
411
get_ecc_status_v1(struct mxc_nand_host * host)412 static u32 get_ecc_status_v1(struct mxc_nand_host *host)
413 {
414 return readw(NFC_V1_V2_ECC_STATUS_RESULT);
415 }
416
get_ecc_status_v2(struct mxc_nand_host * host)417 static u32 get_ecc_status_v2(struct mxc_nand_host *host)
418 {
419 return readl(NFC_V1_V2_ECC_STATUS_RESULT);
420 }
421
get_ecc_status_v3(struct mxc_nand_host * host)422 static u32 get_ecc_status_v3(struct mxc_nand_host *host)
423 {
424 return readl(NFC_V3_ECC_STATUS_RESULT);
425 }
426
mxc_nfc_irq(int irq,void * dev_id)427 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
428 {
429 struct mxc_nand_host *host = dev_id;
430
431 if (!host->devtype_data->check_int(host))
432 return IRQ_NONE;
433
434 irq_control(host, 0);
435
436 complete(&host->op_completion);
437
438 return IRQ_HANDLED;
439 }
440
441 /* This function polls the NANDFC to wait for the basic operation to
442 * complete by checking the INT bit of config2 register.
443 */
wait_op_done(struct mxc_nand_host * host,int useirq)444 static int wait_op_done(struct mxc_nand_host *host, int useirq)
445 {
446 int ret = 0;
447
448 /*
449 * If operation is already complete, don't bother to setup an irq or a
450 * loop.
451 */
452 if (host->devtype_data->check_int(host))
453 return 0;
454
455 if (useirq) {
456 unsigned long timeout;
457
458 reinit_completion(&host->op_completion);
459
460 irq_control(host, 1);
461
462 timeout = wait_for_completion_timeout(&host->op_completion, HZ);
463 if (!timeout && !host->devtype_data->check_int(host)) {
464 dev_dbg(host->dev, "timeout waiting for irq\n");
465 ret = -ETIMEDOUT;
466 }
467 } else {
468 int max_retries = 8000;
469 int done;
470
471 do {
472 udelay(1);
473
474 done = host->devtype_data->check_int(host);
475 if (done)
476 break;
477
478 } while (--max_retries);
479
480 if (!done) {
481 dev_dbg(host->dev, "timeout polling for completion\n");
482 ret = -ETIMEDOUT;
483 }
484 }
485
486 WARN_ONCE(ret < 0, "timeout! useirq=%d\n", useirq);
487
488 return ret;
489 }
490
send_cmd_v3(struct mxc_nand_host * host,uint16_t cmd,int useirq)491 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
492 {
493 /* fill command */
494 writel(cmd, NFC_V3_FLASH_CMD);
495
496 /* send out command */
497 writel(NFC_CMD, NFC_V3_LAUNCH);
498
499 /* Wait for operation to complete */
500 wait_op_done(host, useirq);
501 }
502
503 /* This function issues the specified command to the NAND device and
504 * waits for completion. */
send_cmd_v1_v2(struct mxc_nand_host * host,uint16_t cmd,int useirq)505 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
506 {
507 dev_dbg(host->dev, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
508
509 writew(cmd, NFC_V1_V2_FLASH_CMD);
510 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
511
512 if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) {
513 int max_retries = 100;
514 /* Reset completion is indicated by NFC_CONFIG2 */
515 /* being set to 0 */
516 while (max_retries-- > 0) {
517 if (readw(NFC_V1_V2_CONFIG2) == 0) {
518 break;
519 }
520 udelay(1);
521 }
522 if (max_retries < 0)
523 dev_dbg(host->dev, "%s: RESET failed\n", __func__);
524 } else {
525 /* Wait for operation to complete */
526 wait_op_done(host, useirq);
527 }
528 }
529
send_addr_v3(struct mxc_nand_host * host,uint16_t addr,int islast)530 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
531 {
532 /* fill address */
533 writel(addr, NFC_V3_FLASH_ADDR0);
534
535 /* send out address */
536 writel(NFC_ADDR, NFC_V3_LAUNCH);
537
538 wait_op_done(host, 0);
539 }
540
541 /* This function sends an address (or partial address) to the
542 * NAND device. The address is used to select the source/destination for
543 * a NAND command. */
send_addr_v1_v2(struct mxc_nand_host * host,uint16_t addr,int islast)544 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
545 {
546 dev_dbg(host->dev, "send_addr(host, 0x%x %d)\n", addr, islast);
547
548 writew(addr, NFC_V1_V2_FLASH_ADDR);
549 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
550
551 /* Wait for operation to complete */
552 wait_op_done(host, islast);
553 }
554
send_page_v3(struct mtd_info * mtd,unsigned int ops)555 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
556 {
557 struct nand_chip *nand_chip = mtd_to_nand(mtd);
558 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
559 uint32_t tmp;
560
561 tmp = readl(NFC_V3_CONFIG1);
562 tmp &= ~(7 << 4);
563 writel(tmp, NFC_V3_CONFIG1);
564
565 /* transfer data from NFC ram to nand */
566 writel(ops, NFC_V3_LAUNCH);
567
568 wait_op_done(host, false);
569 }
570
send_page_v2(struct mtd_info * mtd,unsigned int ops)571 static void send_page_v2(struct mtd_info *mtd, unsigned int ops)
572 {
573 struct nand_chip *nand_chip = mtd_to_nand(mtd);
574 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
575
576 /* NANDFC buffer 0 is used for page read/write */
577 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
578
579 writew(ops, NFC_V1_V2_CONFIG2);
580
581 /* Wait for operation to complete */
582 wait_op_done(host, true);
583 }
584
send_page_v1(struct mtd_info * mtd,unsigned int ops)585 static void send_page_v1(struct mtd_info *mtd, unsigned int ops)
586 {
587 struct nand_chip *nand_chip = mtd_to_nand(mtd);
588 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
589 int bufs, i;
590
591 if (mtd->writesize > 512)
592 bufs = 4;
593 else
594 bufs = 1;
595
596 for (i = 0; i < bufs; i++) {
597
598 /* NANDFC buffer 0 is used for page read/write */
599 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
600
601 writew(ops, NFC_V1_V2_CONFIG2);
602
603 /* Wait for operation to complete */
604 wait_op_done(host, true);
605 }
606 }
607
send_read_id_v3(struct mxc_nand_host * host)608 static void send_read_id_v3(struct mxc_nand_host *host)
609 {
610 /* Read ID into main buffer */
611 writel(NFC_ID, NFC_V3_LAUNCH);
612
613 wait_op_done(host, true);
614
615 memcpy32_fromio(host->data_buf, host->main_area0, 16);
616 }
617
618 /* Request the NANDFC to perform a read of the NAND device ID. */
send_read_id_v1_v2(struct mxc_nand_host * host)619 static void send_read_id_v1_v2(struct mxc_nand_host *host)
620 {
621 /* NANDFC buffer 0 is used for device ID output */
622 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
623
624 writew(NFC_ID, NFC_V1_V2_CONFIG2);
625
626 /* Wait for operation to complete */
627 wait_op_done(host, true);
628
629 memcpy32_fromio(host->data_buf, host->main_area0, 16);
630 }
631
get_dev_status_v3(struct mxc_nand_host * host)632 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
633 {
634 writew(NFC_STATUS, NFC_V3_LAUNCH);
635 wait_op_done(host, true);
636
637 return readl(NFC_V3_CONFIG1) >> 16;
638 }
639
640 /* This function requests the NANDFC to perform a read of the
641 * NAND device status and returns the current status. */
get_dev_status_v1_v2(struct mxc_nand_host * host)642 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
643 {
644 void __iomem *main_buf = host->main_area0;
645 uint32_t store;
646 uint16_t ret;
647
648 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
649
650 /*
651 * The device status is stored in main_area0. To
652 * prevent corruption of the buffer save the value
653 * and restore it afterwards.
654 */
655 store = readl(main_buf);
656
657 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
658 wait_op_done(host, true);
659
660 ret = readw(main_buf);
661
662 writel(store, main_buf);
663
664 return ret;
665 }
666
mxc_nand_enable_hwecc_v1_v2(struct nand_chip * chip,bool enable)667 static void mxc_nand_enable_hwecc_v1_v2(struct nand_chip *chip, bool enable)
668 {
669 struct mxc_nand_host *host = nand_get_controller_data(chip);
670 uint16_t config1;
671
672 if (chip->ecc.mode != NAND_ECC_HW)
673 return;
674
675 config1 = readw(NFC_V1_V2_CONFIG1);
676
677 if (enable)
678 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
679 else
680 config1 &= ~NFC_V1_V2_CONFIG1_ECC_EN;
681
682 writew(config1, NFC_V1_V2_CONFIG1);
683 }
684
mxc_nand_enable_hwecc_v3(struct nand_chip * chip,bool enable)685 static void mxc_nand_enable_hwecc_v3(struct nand_chip *chip, bool enable)
686 {
687 struct mxc_nand_host *host = nand_get_controller_data(chip);
688 uint32_t config2;
689
690 if (chip->ecc.mode != NAND_ECC_HW)
691 return;
692
693 config2 = readl(NFC_V3_CONFIG2);
694
695 if (enable)
696 config2 |= NFC_V3_CONFIG2_ECC_EN;
697 else
698 config2 &= ~NFC_V3_CONFIG2_ECC_EN;
699
700 writel(config2, NFC_V3_CONFIG2);
701 }
702
703 /* This functions is used by upper layer to checks if device is ready */
mxc_nand_dev_ready(struct mtd_info * mtd)704 static int mxc_nand_dev_ready(struct mtd_info *mtd)
705 {
706 /*
707 * NFC handles R/B internally. Therefore, this function
708 * always returns status as ready.
709 */
710 return 1;
711 }
712
mxc_nand_read_page_v1(struct nand_chip * chip,void * buf,void * oob,bool ecc,int page)713 static int mxc_nand_read_page_v1(struct nand_chip *chip, void *buf, void *oob,
714 bool ecc, int page)
715 {
716 struct mtd_info *mtd = nand_to_mtd(chip);
717 struct mxc_nand_host *host = nand_get_controller_data(chip);
718 unsigned int bitflips_corrected = 0;
719 int no_subpages;
720 int i;
721
722 host->devtype_data->enable_hwecc(chip, ecc);
723
724 host->devtype_data->send_cmd(host, NAND_CMD_READ0, false);
725 mxc_do_addr_cycle(mtd, 0, page);
726
727 if (mtd->writesize > 512)
728 host->devtype_data->send_cmd(host, NAND_CMD_READSTART, true);
729
730 no_subpages = mtd->writesize >> 9;
731
732 for (i = 0; i < no_subpages; i++) {
733 uint16_t ecc_stats;
734
735 /* NANDFC buffer 0 is used for page read/write */
736 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
737
738 writew(NFC_OUTPUT, NFC_V1_V2_CONFIG2);
739
740 /* Wait for operation to complete */
741 wait_op_done(host, true);
742
743 ecc_stats = get_ecc_status_v1(host);
744
745 ecc_stats >>= 2;
746
747 if (buf && ecc) {
748 switch (ecc_stats & 0x3) {
749 case 0:
750 default:
751 break;
752 case 1:
753 mtd->ecc_stats.corrected++;
754 bitflips_corrected = 1;
755 break;
756 case 2:
757 mtd->ecc_stats.failed++;
758 break;
759 }
760 }
761 }
762
763 if (buf)
764 memcpy32_fromio(buf, host->main_area0, mtd->writesize);
765 if (oob)
766 copy_spare(mtd, true, oob);
767
768 return bitflips_corrected;
769 }
770
mxc_nand_read_page_v2_v3(struct nand_chip * chip,void * buf,void * oob,bool ecc,int page)771 static int mxc_nand_read_page_v2_v3(struct nand_chip *chip, void *buf,
772 void *oob, bool ecc, int page)
773 {
774 struct mtd_info *mtd = nand_to_mtd(chip);
775 struct mxc_nand_host *host = nand_get_controller_data(chip);
776 unsigned int max_bitflips = 0;
777 u32 ecc_stat, err;
778 int no_subpages;
779 u8 ecc_bit_mask, err_limit;
780
781 host->devtype_data->enable_hwecc(chip, ecc);
782
783 host->devtype_data->send_cmd(host, NAND_CMD_READ0, false);
784 mxc_do_addr_cycle(mtd, 0, page);
785
786 if (mtd->writesize > 512)
787 host->devtype_data->send_cmd(host,
788 NAND_CMD_READSTART, true);
789
790 host->devtype_data->send_page(mtd, NFC_OUTPUT);
791
792 if (buf)
793 memcpy32_fromio(buf, host->main_area0, mtd->writesize);
794 if (oob)
795 copy_spare(mtd, true, oob);
796
797 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
798 err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
799
800 no_subpages = mtd->writesize >> 9;
801
802 ecc_stat = host->devtype_data->get_ecc_status(host);
803
804 do {
805 err = ecc_stat & ecc_bit_mask;
806 if (err > err_limit) {
807 mtd->ecc_stats.failed++;
808 } else {
809 mtd->ecc_stats.corrected += err;
810 max_bitflips = max_t(unsigned int, max_bitflips, err);
811 }
812
813 ecc_stat >>= 4;
814 } while (--no_subpages);
815
816 return max_bitflips;
817 }
818
mxc_nand_read_page(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)819 static int mxc_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
820 uint8_t *buf, int oob_required, int page)
821 {
822 struct mxc_nand_host *host = nand_get_controller_data(chip);
823 void *oob_buf;
824
825 if (oob_required)
826 oob_buf = chip->oob_poi;
827 else
828 oob_buf = NULL;
829
830 return host->devtype_data->read_page(chip, buf, oob_buf, 1, page);
831 }
832
mxc_nand_read_page_raw(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)833 static int mxc_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
834 uint8_t *buf, int oob_required, int page)
835 {
836 struct mxc_nand_host *host = nand_get_controller_data(chip);
837 void *oob_buf;
838
839 if (oob_required)
840 oob_buf = chip->oob_poi;
841 else
842 oob_buf = NULL;
843
844 return host->devtype_data->read_page(chip, buf, oob_buf, 0, page);
845 }
846
mxc_nand_read_oob(struct mtd_info * mtd,struct nand_chip * chip,int page)847 static int mxc_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
848 int page)
849 {
850 struct mxc_nand_host *host = nand_get_controller_data(chip);
851
852 return host->devtype_data->read_page(chip, NULL, chip->oob_poi, 0,
853 page);
854 }
855
mxc_nand_write_page(struct nand_chip * chip,const uint8_t * buf,bool ecc,int page)856 static int mxc_nand_write_page(struct nand_chip *chip, const uint8_t *buf,
857 bool ecc, int page)
858 {
859 struct mtd_info *mtd = nand_to_mtd(chip);
860 struct mxc_nand_host *host = nand_get_controller_data(chip);
861
862 host->devtype_data->enable_hwecc(chip, ecc);
863
864 host->devtype_data->send_cmd(host, NAND_CMD_SEQIN, false);
865 mxc_do_addr_cycle(mtd, 0, page);
866
867 memcpy32_toio(host->main_area0, buf, mtd->writesize);
868 copy_spare(mtd, false, chip->oob_poi);
869
870 host->devtype_data->send_page(mtd, NFC_INPUT);
871 host->devtype_data->send_cmd(host, NAND_CMD_PAGEPROG, true);
872 mxc_do_addr_cycle(mtd, 0, page);
873
874 return 0;
875 }
876
mxc_nand_write_page_ecc(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)877 static int mxc_nand_write_page_ecc(struct mtd_info *mtd, struct nand_chip *chip,
878 const uint8_t *buf, int oob_required,
879 int page)
880 {
881 return mxc_nand_write_page(chip, buf, true, page);
882 }
883
mxc_nand_write_page_raw(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)884 static int mxc_nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
885 const uint8_t *buf, int oob_required, int page)
886 {
887 return mxc_nand_write_page(chip, buf, false, page);
888 }
889
mxc_nand_write_oob(struct mtd_info * mtd,struct nand_chip * chip,int page)890 static int mxc_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
891 int page)
892 {
893 struct mxc_nand_host *host = nand_get_controller_data(chip);
894
895 memset(host->data_buf, 0xff, mtd->writesize);
896
897 return mxc_nand_write_page(chip, host->data_buf, false, page);
898 }
899
mxc_nand_read_byte(struct mtd_info * mtd)900 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
901 {
902 struct nand_chip *nand_chip = mtd_to_nand(mtd);
903 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
904 uint8_t ret;
905
906 /* Check for status request */
907 if (host->status_request)
908 return host->devtype_data->get_dev_status(host) & 0xFF;
909
910 if (nand_chip->options & NAND_BUSWIDTH_16) {
911 /* only take the lower byte of each word */
912 ret = *(uint16_t *)(host->data_buf + host->buf_start);
913
914 host->buf_start += 2;
915 } else {
916 ret = *(uint8_t *)(host->data_buf + host->buf_start);
917 host->buf_start++;
918 }
919
920 dev_dbg(host->dev, "%s: ret=0x%hhx (start=%u)\n", __func__, ret, host->buf_start);
921 return ret;
922 }
923
mxc_nand_read_word(struct mtd_info * mtd)924 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
925 {
926 struct nand_chip *nand_chip = mtd_to_nand(mtd);
927 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
928 uint16_t ret;
929
930 ret = *(uint16_t *)(host->data_buf + host->buf_start);
931 host->buf_start += 2;
932
933 return ret;
934 }
935
936 /* Write data of length len to buffer buf. The data to be
937 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
938 * Operation by the NFC, the data is written to NAND Flash */
mxc_nand_write_buf(struct mtd_info * mtd,const u_char * buf,int len)939 static void mxc_nand_write_buf(struct mtd_info *mtd,
940 const u_char *buf, int len)
941 {
942 struct nand_chip *nand_chip = mtd_to_nand(mtd);
943 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
944 u16 col = host->buf_start;
945 int n = mtd->oobsize + mtd->writesize - col;
946
947 n = min(n, len);
948
949 memcpy(host->data_buf + col, buf, n);
950
951 host->buf_start += n;
952 }
953
954 /* Read the data buffer from the NAND Flash. To read the data from NAND
955 * Flash first the data output cycle is initiated by the NFC, which copies
956 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
957 */
mxc_nand_read_buf(struct mtd_info * mtd,u_char * buf,int len)958 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
959 {
960 struct nand_chip *nand_chip = mtd_to_nand(mtd);
961 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
962 u16 col = host->buf_start;
963 int n = mtd->oobsize + mtd->writesize - col;
964
965 n = min(n, len);
966
967 memcpy(buf, host->data_buf + col, n);
968
969 host->buf_start += n;
970 }
971
972 /* This function is used by upper layer for select and
973 * deselect of the NAND chip */
mxc_nand_select_chip_v1_v3(struct mtd_info * mtd,int chip)974 static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip)
975 {
976 struct nand_chip *nand_chip = mtd_to_nand(mtd);
977 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
978
979 if (chip == -1) {
980 /* Disable the NFC clock */
981 if (host->clk_act) {
982 clk_disable_unprepare(host->clk);
983 host->clk_act = 0;
984 }
985 return;
986 }
987
988 if (!host->clk_act) {
989 /* Enable the NFC clock */
990 clk_prepare_enable(host->clk);
991 host->clk_act = 1;
992 }
993 }
994
mxc_nand_select_chip_v2(struct mtd_info * mtd,int chip)995 static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip)
996 {
997 struct nand_chip *nand_chip = mtd_to_nand(mtd);
998 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
999
1000 if (chip == -1) {
1001 /* Disable the NFC clock */
1002 if (host->clk_act) {
1003 clk_disable_unprepare(host->clk);
1004 host->clk_act = 0;
1005 }
1006 return;
1007 }
1008
1009 if (!host->clk_act) {
1010 /* Enable the NFC clock */
1011 clk_prepare_enable(host->clk);
1012 host->clk_act = 1;
1013 }
1014
1015 host->active_cs = chip;
1016 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
1017 }
1018
1019 #define MXC_V1_ECCBYTES 5
1020
mxc_v1_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)1021 static int mxc_v1_ooblayout_ecc(struct mtd_info *mtd, int section,
1022 struct mtd_oob_region *oobregion)
1023 {
1024 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1025
1026 if (section >= nand_chip->ecc.steps)
1027 return -ERANGE;
1028
1029 oobregion->offset = (section * 16) + 6;
1030 oobregion->length = MXC_V1_ECCBYTES;
1031
1032 return 0;
1033 }
1034
mxc_v1_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)1035 static int mxc_v1_ooblayout_free(struct mtd_info *mtd, int section,
1036 struct mtd_oob_region *oobregion)
1037 {
1038 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1039
1040 if (section > nand_chip->ecc.steps)
1041 return -ERANGE;
1042
1043 if (!section) {
1044 if (mtd->writesize <= 512) {
1045 oobregion->offset = 0;
1046 oobregion->length = 5;
1047 } else {
1048 oobregion->offset = 2;
1049 oobregion->length = 4;
1050 }
1051 } else {
1052 oobregion->offset = ((section - 1) * 16) + MXC_V1_ECCBYTES + 6;
1053 if (section < nand_chip->ecc.steps)
1054 oobregion->length = (section * 16) + 6 -
1055 oobregion->offset;
1056 else
1057 oobregion->length = mtd->oobsize - oobregion->offset;
1058 }
1059
1060 return 0;
1061 }
1062
1063 static const struct mtd_ooblayout_ops mxc_v1_ooblayout_ops = {
1064 .ecc = mxc_v1_ooblayout_ecc,
1065 .free = mxc_v1_ooblayout_free,
1066 };
1067
mxc_v2_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)1068 static int mxc_v2_ooblayout_ecc(struct mtd_info *mtd, int section,
1069 struct mtd_oob_region *oobregion)
1070 {
1071 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1072 int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26;
1073
1074 if (section >= nand_chip->ecc.steps)
1075 return -ERANGE;
1076
1077 oobregion->offset = (section * stepsize) + 7;
1078 oobregion->length = nand_chip->ecc.bytes;
1079
1080 return 0;
1081 }
1082
mxc_v2_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)1083 static int mxc_v2_ooblayout_free(struct mtd_info *mtd, int section,
1084 struct mtd_oob_region *oobregion)
1085 {
1086 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1087 int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26;
1088
1089 if (section >= nand_chip->ecc.steps)
1090 return -ERANGE;
1091
1092 if (!section) {
1093 if (mtd->writesize <= 512) {
1094 oobregion->offset = 0;
1095 oobregion->length = 5;
1096 } else {
1097 oobregion->offset = 2;
1098 oobregion->length = 4;
1099 }
1100 } else {
1101 oobregion->offset = section * stepsize;
1102 oobregion->length = 7;
1103 }
1104
1105 return 0;
1106 }
1107
1108 static const struct mtd_ooblayout_ops mxc_v2_ooblayout_ops = {
1109 .ecc = mxc_v2_ooblayout_ecc,
1110 .free = mxc_v2_ooblayout_free,
1111 };
1112
1113 /*
1114 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
1115 * on how much oob the nand chip has. For 8bit ecc we need at least
1116 * 26 bytes of oob data per 512 byte block.
1117 */
get_eccsize(struct mtd_info * mtd)1118 static int get_eccsize(struct mtd_info *mtd)
1119 {
1120 int oobbytes_per_512 = 0;
1121
1122 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
1123
1124 if (oobbytes_per_512 < 26)
1125 return 4;
1126 else
1127 return 8;
1128 }
1129
preset_v1(struct mtd_info * mtd)1130 static void preset_v1(struct mtd_info *mtd)
1131 {
1132 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1133 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1134 uint16_t config1 = 0;
1135
1136 if (nand_chip->ecc.mode == NAND_ECC_HW && mtd->writesize)
1137 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
1138
1139 if (!host->devtype_data->irqpending_quirk)
1140 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
1141
1142 host->eccsize = 1;
1143
1144 writew(config1, NFC_V1_V2_CONFIG1);
1145 /* preset operation */
1146
1147 /* Unlock the internal RAM Buffer */
1148 writew(0x2, NFC_V1_V2_CONFIG);
1149
1150 /* Blocks to be unlocked */
1151 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
1152 writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR);
1153
1154 /* Unlock Block Command for given address range */
1155 writew(0x4, NFC_V1_V2_WRPROT);
1156 }
1157
mxc_nand_v2_setup_data_interface(struct mtd_info * mtd,int csline,const struct nand_data_interface * conf)1158 static int mxc_nand_v2_setup_data_interface(struct mtd_info *mtd, int csline,
1159 const struct nand_data_interface *conf)
1160 {
1161 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1162 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1163 int tRC_min_ns, tRC_ps, ret;
1164 unsigned long rate, rate_round;
1165 const struct nand_sdr_timings *timings;
1166 u16 config1;
1167
1168 timings = nand_get_sdr_timings(conf);
1169 if (IS_ERR(timings))
1170 return -ENOTSUPP;
1171
1172 config1 = readw(NFC_V1_V2_CONFIG1);
1173
1174 tRC_min_ns = timings->tRC_min / 1000;
1175 rate = 1000000000 / tRC_min_ns;
1176
1177 /*
1178 * For tRC < 30ns we have to use EDO mode. In this case the controller
1179 * does one access per clock cycle. Otherwise the controller does one
1180 * access in two clock cycles, thus we have to double the rate to the
1181 * controller.
1182 */
1183 if (tRC_min_ns < 30) {
1184 rate_round = clk_round_rate(host->clk, rate);
1185 config1 |= NFC_V2_CONFIG1_ONE_CYCLE;
1186 tRC_ps = 1000000000 / (rate_round / 1000);
1187 } else {
1188 rate *= 2;
1189 rate_round = clk_round_rate(host->clk, rate);
1190 config1 &= ~NFC_V2_CONFIG1_ONE_CYCLE;
1191 tRC_ps = 1000000000 / (rate_round / 1000 / 2);
1192 }
1193
1194 /*
1195 * The timing values compared against are from the i.MX25 Automotive
1196 * datasheet, Table 50. NFC Timing Parameters
1197 */
1198 if (timings->tCLS_min > tRC_ps - 1000 ||
1199 timings->tCLH_min > tRC_ps - 2000 ||
1200 timings->tCS_min > tRC_ps - 1000 ||
1201 timings->tCH_min > tRC_ps - 2000 ||
1202 timings->tWP_min > tRC_ps - 1500 ||
1203 timings->tALS_min > tRC_ps ||
1204 timings->tALH_min > tRC_ps - 3000 ||
1205 timings->tDS_min > tRC_ps ||
1206 timings->tDH_min > tRC_ps - 5000 ||
1207 timings->tWC_min > 2 * tRC_ps ||
1208 timings->tWH_min > tRC_ps - 2500 ||
1209 timings->tRR_min > 6 * tRC_ps ||
1210 timings->tRP_min > 3 * tRC_ps / 2 ||
1211 timings->tRC_min > 2 * tRC_ps ||
1212 timings->tREH_min > (tRC_ps / 2) - 2500) {
1213 dev_dbg(host->dev, "Timing out of bounds\n");
1214 return -EINVAL;
1215 }
1216
1217 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1218 return 0;
1219
1220 ret = clk_set_rate(host->clk, rate);
1221 if (ret)
1222 return ret;
1223
1224 writew(config1, NFC_V1_V2_CONFIG1);
1225
1226 dev_dbg(host->dev, "Setting rate to %ldHz, %s mode\n", rate_round,
1227 config1 & NFC_V2_CONFIG1_ONE_CYCLE ? "One cycle (EDO)" :
1228 "normal");
1229
1230 return 0;
1231 }
1232
preset_v2(struct mtd_info * mtd)1233 static void preset_v2(struct mtd_info *mtd)
1234 {
1235 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1236 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1237 uint16_t config1 = 0;
1238
1239 config1 |= NFC_V2_CONFIG1_FP_INT;
1240
1241 if (!host->devtype_data->irqpending_quirk)
1242 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
1243
1244 if (mtd->writesize) {
1245 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
1246
1247 if (nand_chip->ecc.mode == NAND_ECC_HW)
1248 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
1249
1250 host->eccsize = get_eccsize(mtd);
1251 if (host->eccsize == 4)
1252 config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
1253
1254 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
1255 } else {
1256 host->eccsize = 1;
1257 }
1258
1259 writew(config1, NFC_V1_V2_CONFIG1);
1260 /* preset operation */
1261
1262 /* spare area size in 16-bit half-words */
1263 writew(mtd->oobsize / 2, NFC_V21_RSLTSPARE_AREA);
1264
1265 /* Unlock the internal RAM Buffer */
1266 writew(0x2, NFC_V1_V2_CONFIG);
1267
1268 /* Blocks to be unlocked */
1269 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
1270 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
1271 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
1272 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
1273 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
1274 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
1275 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
1276 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
1277
1278 /* Unlock Block Command for given address range */
1279 writew(0x4, NFC_V1_V2_WRPROT);
1280 }
1281
preset_v3(struct mtd_info * mtd)1282 static void preset_v3(struct mtd_info *mtd)
1283 {
1284 struct nand_chip *chip = mtd_to_nand(mtd);
1285 struct mxc_nand_host *host = nand_get_controller_data(chip);
1286 uint32_t config2, config3;
1287 int i, addr_phases;
1288
1289 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
1290 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
1291
1292 /* Unlock the internal RAM Buffer */
1293 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
1294 NFC_V3_WRPROT);
1295
1296 /* Blocks to be unlocked */
1297 for (i = 0; i < NAND_MAX_CHIPS; i++)
1298 writel(0xffff << 16, NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
1299
1300 writel(0, NFC_V3_IPC);
1301
1302 config2 = NFC_V3_CONFIG2_ONE_CYCLE |
1303 NFC_V3_CONFIG2_2CMD_PHASES |
1304 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
1305 NFC_V3_CONFIG2_ST_CMD(0x70) |
1306 NFC_V3_CONFIG2_INT_MSK |
1307 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
1308
1309 addr_phases = fls(chip->pagemask) >> 3;
1310
1311 if (mtd->writesize == 2048) {
1312 config2 |= NFC_V3_CONFIG2_PS_2048;
1313 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1314 } else if (mtd->writesize == 4096) {
1315 config2 |= NFC_V3_CONFIG2_PS_4096;
1316 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1317 } else {
1318 config2 |= NFC_V3_CONFIG2_PS_512;
1319 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
1320 }
1321
1322 if (mtd->writesize) {
1323 if (chip->ecc.mode == NAND_ECC_HW)
1324 config2 |= NFC_V3_CONFIG2_ECC_EN;
1325
1326 config2 |= NFC_V3_CONFIG2_PPB(
1327 ffs(mtd->erasesize / mtd->writesize) - 6,
1328 host->devtype_data->ppb_shift);
1329 host->eccsize = get_eccsize(mtd);
1330 if (host->eccsize == 8)
1331 config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
1332 }
1333
1334 writel(config2, NFC_V3_CONFIG2);
1335
1336 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
1337 NFC_V3_CONFIG3_NO_SDMA |
1338 NFC_V3_CONFIG3_RBB_MODE |
1339 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1340 NFC_V3_CONFIG3_ADD_OP(0);
1341
1342 if (!(chip->options & NAND_BUSWIDTH_16))
1343 config3 |= NFC_V3_CONFIG3_FW8;
1344
1345 writel(config3, NFC_V3_CONFIG3);
1346
1347 writel(0, NFC_V3_DELAY_LINE);
1348 }
1349
1350 /* Used by the upper layer to write command to NAND Flash for
1351 * different operations to be carried out on NAND Flash */
mxc_nand_command(struct mtd_info * mtd,unsigned command,int column,int page_addr)1352 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
1353 int column, int page_addr)
1354 {
1355 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1356 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1357
1358 dev_dbg(host->dev, "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1359 command, column, page_addr);
1360
1361 /* Reset command state information */
1362 host->status_request = false;
1363
1364 /* Command pre-processing step */
1365 switch (command) {
1366 case NAND_CMD_RESET:
1367 host->devtype_data->preset(mtd);
1368 host->devtype_data->send_cmd(host, command, false);
1369 break;
1370
1371 case NAND_CMD_STATUS:
1372 host->buf_start = 0;
1373 host->status_request = true;
1374
1375 host->devtype_data->send_cmd(host, command, true);
1376 WARN_ONCE(column != -1 || page_addr != -1,
1377 "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1378 command, column, page_addr);
1379 mxc_do_addr_cycle(mtd, column, page_addr);
1380 break;
1381
1382 case NAND_CMD_READID:
1383 host->devtype_data->send_cmd(host, command, true);
1384 mxc_do_addr_cycle(mtd, column, page_addr);
1385 host->devtype_data->send_read_id(host);
1386 host->buf_start = 0;
1387 break;
1388
1389 case NAND_CMD_ERASE1:
1390 case NAND_CMD_ERASE2:
1391 host->devtype_data->send_cmd(host, command, false);
1392 WARN_ONCE(column != -1,
1393 "Unexpected column value (cmd=%u, col=%d)\n",
1394 command, column);
1395 mxc_do_addr_cycle(mtd, column, page_addr);
1396
1397 break;
1398 case NAND_CMD_PARAM:
1399 host->devtype_data->send_cmd(host, command, false);
1400 mxc_do_addr_cycle(mtd, column, page_addr);
1401 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1402 memcpy32_fromio(host->data_buf, host->main_area0, 512);
1403 host->buf_start = 0;
1404 break;
1405 default:
1406 WARN_ONCE(1, "Unimplemented command (cmd=%u)\n",
1407 command);
1408 break;
1409 }
1410 }
1411
mxc_nand_set_features(struct mtd_info * mtd,struct nand_chip * chip,int addr,u8 * subfeature_param)1412 static int mxc_nand_set_features(struct mtd_info *mtd, struct nand_chip *chip,
1413 int addr, u8 *subfeature_param)
1414 {
1415 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1416 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1417 int i;
1418
1419 host->buf_start = 0;
1420
1421 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
1422 chip->write_byte(mtd, subfeature_param[i]);
1423
1424 memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
1425 host->devtype_data->send_cmd(host, NAND_CMD_SET_FEATURES, false);
1426 mxc_do_addr_cycle(mtd, addr, -1);
1427 host->devtype_data->send_page(mtd, NFC_INPUT);
1428
1429 return 0;
1430 }
1431
mxc_nand_get_features(struct mtd_info * mtd,struct nand_chip * chip,int addr,u8 * subfeature_param)1432 static int mxc_nand_get_features(struct mtd_info *mtd, struct nand_chip *chip,
1433 int addr, u8 *subfeature_param)
1434 {
1435 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1436 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1437 int i;
1438
1439 host->devtype_data->send_cmd(host, NAND_CMD_GET_FEATURES, false);
1440 mxc_do_addr_cycle(mtd, addr, -1);
1441 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1442 memcpy32_fromio(host->data_buf, host->main_area0, 512);
1443 host->buf_start = 0;
1444
1445 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
1446 *subfeature_param++ = chip->read_byte(mtd);
1447
1448 return 0;
1449 }
1450
1451 /*
1452 * The generic flash bbt decriptors overlap with our ecc
1453 * hardware, so define some i.MX specific ones.
1454 */
1455 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1456 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1457
1458 static struct nand_bbt_descr bbt_main_descr = {
1459 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1460 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1461 .offs = 0,
1462 .len = 4,
1463 .veroffs = 4,
1464 .maxblocks = 4,
1465 .pattern = bbt_pattern,
1466 };
1467
1468 static struct nand_bbt_descr bbt_mirror_descr = {
1469 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1470 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1471 .offs = 0,
1472 .len = 4,
1473 .veroffs = 4,
1474 .maxblocks = 4,
1475 .pattern = mirror_pattern,
1476 };
1477
1478 /* v1 + irqpending_quirk: i.MX21 */
1479 static const struct mxc_nand_devtype_data imx21_nand_devtype_data = {
1480 .preset = preset_v1,
1481 .read_page = mxc_nand_read_page_v1,
1482 .send_cmd = send_cmd_v1_v2,
1483 .send_addr = send_addr_v1_v2,
1484 .send_page = send_page_v1,
1485 .send_read_id = send_read_id_v1_v2,
1486 .get_dev_status = get_dev_status_v1_v2,
1487 .check_int = check_int_v1_v2,
1488 .irq_control = irq_control_v1_v2,
1489 .get_ecc_status = get_ecc_status_v1,
1490 .ooblayout = &mxc_v1_ooblayout_ops,
1491 .select_chip = mxc_nand_select_chip_v1_v3,
1492 .enable_hwecc = mxc_nand_enable_hwecc_v1_v2,
1493 .irqpending_quirk = 1,
1494 .needs_ip = 0,
1495 .regs_offset = 0xe00,
1496 .spare0_offset = 0x800,
1497 .spare_len = 16,
1498 .eccbytes = 3,
1499 .eccsize = 1,
1500 };
1501
1502 /* v1 + !irqpending_quirk: i.MX27, i.MX31 */
1503 static const struct mxc_nand_devtype_data imx27_nand_devtype_data = {
1504 .preset = preset_v1,
1505 .read_page = mxc_nand_read_page_v1,
1506 .send_cmd = send_cmd_v1_v2,
1507 .send_addr = send_addr_v1_v2,
1508 .send_page = send_page_v1,
1509 .send_read_id = send_read_id_v1_v2,
1510 .get_dev_status = get_dev_status_v1_v2,
1511 .check_int = check_int_v1_v2,
1512 .irq_control = irq_control_v1_v2,
1513 .get_ecc_status = get_ecc_status_v1,
1514 .ooblayout = &mxc_v1_ooblayout_ops,
1515 .select_chip = mxc_nand_select_chip_v1_v3,
1516 .enable_hwecc = mxc_nand_enable_hwecc_v1_v2,
1517 .irqpending_quirk = 0,
1518 .needs_ip = 0,
1519 .regs_offset = 0xe00,
1520 .spare0_offset = 0x800,
1521 .axi_offset = 0,
1522 .spare_len = 16,
1523 .eccbytes = 3,
1524 .eccsize = 1,
1525 };
1526
1527 /* v21: i.MX25, i.MX35 */
1528 static const struct mxc_nand_devtype_data imx25_nand_devtype_data = {
1529 .preset = preset_v2,
1530 .read_page = mxc_nand_read_page_v2_v3,
1531 .send_cmd = send_cmd_v1_v2,
1532 .send_addr = send_addr_v1_v2,
1533 .send_page = send_page_v2,
1534 .send_read_id = send_read_id_v1_v2,
1535 .get_dev_status = get_dev_status_v1_v2,
1536 .check_int = check_int_v1_v2,
1537 .irq_control = irq_control_v1_v2,
1538 .get_ecc_status = get_ecc_status_v2,
1539 .ooblayout = &mxc_v2_ooblayout_ops,
1540 .select_chip = mxc_nand_select_chip_v2,
1541 .setup_data_interface = mxc_nand_v2_setup_data_interface,
1542 .enable_hwecc = mxc_nand_enable_hwecc_v1_v2,
1543 .irqpending_quirk = 0,
1544 .needs_ip = 0,
1545 .regs_offset = 0x1e00,
1546 .spare0_offset = 0x1000,
1547 .axi_offset = 0,
1548 .spare_len = 64,
1549 .eccbytes = 9,
1550 .eccsize = 0,
1551 };
1552
1553 /* v3.2a: i.MX51 */
1554 static const struct mxc_nand_devtype_data imx51_nand_devtype_data = {
1555 .preset = preset_v3,
1556 .read_page = mxc_nand_read_page_v2_v3,
1557 .send_cmd = send_cmd_v3,
1558 .send_addr = send_addr_v3,
1559 .send_page = send_page_v3,
1560 .send_read_id = send_read_id_v3,
1561 .get_dev_status = get_dev_status_v3,
1562 .check_int = check_int_v3,
1563 .irq_control = irq_control_v3,
1564 .get_ecc_status = get_ecc_status_v3,
1565 .ooblayout = &mxc_v2_ooblayout_ops,
1566 .select_chip = mxc_nand_select_chip_v1_v3,
1567 .enable_hwecc = mxc_nand_enable_hwecc_v3,
1568 .irqpending_quirk = 0,
1569 .needs_ip = 1,
1570 .regs_offset = 0,
1571 .spare0_offset = 0x1000,
1572 .axi_offset = 0x1e00,
1573 .spare_len = 64,
1574 .eccbytes = 0,
1575 .eccsize = 0,
1576 .ppb_shift = 7,
1577 };
1578
1579 /* v3.2b: i.MX53 */
1580 static const struct mxc_nand_devtype_data imx53_nand_devtype_data = {
1581 .preset = preset_v3,
1582 .read_page = mxc_nand_read_page_v2_v3,
1583 .send_cmd = send_cmd_v3,
1584 .send_addr = send_addr_v3,
1585 .send_page = send_page_v3,
1586 .send_read_id = send_read_id_v3,
1587 .get_dev_status = get_dev_status_v3,
1588 .check_int = check_int_v3,
1589 .irq_control = irq_control_v3,
1590 .get_ecc_status = get_ecc_status_v3,
1591 .ooblayout = &mxc_v2_ooblayout_ops,
1592 .select_chip = mxc_nand_select_chip_v1_v3,
1593 .enable_hwecc = mxc_nand_enable_hwecc_v3,
1594 .irqpending_quirk = 0,
1595 .needs_ip = 1,
1596 .regs_offset = 0,
1597 .spare0_offset = 0x1000,
1598 .axi_offset = 0x1e00,
1599 .spare_len = 64,
1600 .eccbytes = 0,
1601 .eccsize = 0,
1602 .ppb_shift = 8,
1603 };
1604
is_imx21_nfc(struct mxc_nand_host * host)1605 static inline int is_imx21_nfc(struct mxc_nand_host *host)
1606 {
1607 return host->devtype_data == &imx21_nand_devtype_data;
1608 }
1609
is_imx27_nfc(struct mxc_nand_host * host)1610 static inline int is_imx27_nfc(struct mxc_nand_host *host)
1611 {
1612 return host->devtype_data == &imx27_nand_devtype_data;
1613 }
1614
is_imx25_nfc(struct mxc_nand_host * host)1615 static inline int is_imx25_nfc(struct mxc_nand_host *host)
1616 {
1617 return host->devtype_data == &imx25_nand_devtype_data;
1618 }
1619
is_imx51_nfc(struct mxc_nand_host * host)1620 static inline int is_imx51_nfc(struct mxc_nand_host *host)
1621 {
1622 return host->devtype_data == &imx51_nand_devtype_data;
1623 }
1624
is_imx53_nfc(struct mxc_nand_host * host)1625 static inline int is_imx53_nfc(struct mxc_nand_host *host)
1626 {
1627 return host->devtype_data == &imx53_nand_devtype_data;
1628 }
1629
1630 static const struct platform_device_id mxcnd_devtype[] = {
1631 {
1632 .name = "imx21-nand",
1633 .driver_data = (kernel_ulong_t) &imx21_nand_devtype_data,
1634 }, {
1635 .name = "imx27-nand",
1636 .driver_data = (kernel_ulong_t) &imx27_nand_devtype_data,
1637 }, {
1638 .name = "imx25-nand",
1639 .driver_data = (kernel_ulong_t) &imx25_nand_devtype_data,
1640 }, {
1641 .name = "imx51-nand",
1642 .driver_data = (kernel_ulong_t) &imx51_nand_devtype_data,
1643 }, {
1644 .name = "imx53-nand",
1645 .driver_data = (kernel_ulong_t) &imx53_nand_devtype_data,
1646 }, {
1647 /* sentinel */
1648 }
1649 };
1650 MODULE_DEVICE_TABLE(platform, mxcnd_devtype);
1651
1652 #ifdef CONFIG_OF
1653 static const struct of_device_id mxcnd_dt_ids[] = {
1654 {
1655 .compatible = "fsl,imx21-nand",
1656 .data = &imx21_nand_devtype_data,
1657 }, {
1658 .compatible = "fsl,imx27-nand",
1659 .data = &imx27_nand_devtype_data,
1660 }, {
1661 .compatible = "fsl,imx25-nand",
1662 .data = &imx25_nand_devtype_data,
1663 }, {
1664 .compatible = "fsl,imx51-nand",
1665 .data = &imx51_nand_devtype_data,
1666 }, {
1667 .compatible = "fsl,imx53-nand",
1668 .data = &imx53_nand_devtype_data,
1669 },
1670 { /* sentinel */ }
1671 };
1672 MODULE_DEVICE_TABLE(of, mxcnd_dt_ids);
1673
mxcnd_probe_dt(struct mxc_nand_host * host)1674 static int mxcnd_probe_dt(struct mxc_nand_host *host)
1675 {
1676 struct device_node *np = host->dev->of_node;
1677 const struct of_device_id *of_id =
1678 of_match_device(mxcnd_dt_ids, host->dev);
1679
1680 if (!np)
1681 return 1;
1682
1683 host->devtype_data = of_id->data;
1684
1685 return 0;
1686 }
1687 #else
mxcnd_probe_dt(struct mxc_nand_host * host)1688 static int mxcnd_probe_dt(struct mxc_nand_host *host)
1689 {
1690 return 1;
1691 }
1692 #endif
1693
mxcnd_attach_chip(struct nand_chip * chip)1694 static int mxcnd_attach_chip(struct nand_chip *chip)
1695 {
1696 struct mtd_info *mtd = nand_to_mtd(chip);
1697 struct mxc_nand_host *host = nand_get_controller_data(chip);
1698 struct device *dev = mtd->dev.parent;
1699
1700 switch (chip->ecc.mode) {
1701 case NAND_ECC_HW:
1702 chip->ecc.read_page = mxc_nand_read_page;
1703 chip->ecc.read_page_raw = mxc_nand_read_page_raw;
1704 chip->ecc.read_oob = mxc_nand_read_oob;
1705 chip->ecc.write_page = mxc_nand_write_page_ecc;
1706 chip->ecc.write_page_raw = mxc_nand_write_page_raw;
1707 chip->ecc.write_oob = mxc_nand_write_oob;
1708 break;
1709
1710 case NAND_ECC_SOFT:
1711 break;
1712
1713 default:
1714 return -EINVAL;
1715 }
1716
1717 if (chip->bbt_options & NAND_BBT_USE_FLASH) {
1718 chip->bbt_td = &bbt_main_descr;
1719 chip->bbt_md = &bbt_mirror_descr;
1720 }
1721
1722 /* Allocate the right size buffer now */
1723 devm_kfree(dev, (void *)host->data_buf);
1724 host->data_buf = devm_kzalloc(dev, mtd->writesize + mtd->oobsize,
1725 GFP_KERNEL);
1726 if (!host->data_buf)
1727 return -ENOMEM;
1728
1729 /* Call preset again, with correct writesize chip time */
1730 host->devtype_data->preset(mtd);
1731
1732 if (!chip->ecc.bytes) {
1733 if (host->eccsize == 8)
1734 chip->ecc.bytes = 18;
1735 else if (host->eccsize == 4)
1736 chip->ecc.bytes = 9;
1737 }
1738
1739 /*
1740 * Experimentation shows that i.MX NFC can only handle up to 218 oob
1741 * bytes. Limit used_oobsize to 218 so as to not confuse copy_spare()
1742 * into copying invalid data to/from the spare IO buffer, as this
1743 * might cause ECC data corruption when doing sub-page write to a
1744 * partially written page.
1745 */
1746 host->used_oobsize = min(mtd->oobsize, 218U);
1747
1748 if (chip->ecc.mode == NAND_ECC_HW) {
1749 if (is_imx21_nfc(host) || is_imx27_nfc(host))
1750 chip->ecc.strength = 1;
1751 else
1752 chip->ecc.strength = (host->eccsize == 4) ? 4 : 8;
1753 }
1754
1755 return 0;
1756 }
1757
1758 static const struct nand_controller_ops mxcnd_controller_ops = {
1759 .attach_chip = mxcnd_attach_chip,
1760 };
1761
mxcnd_probe(struct platform_device * pdev)1762 static int mxcnd_probe(struct platform_device *pdev)
1763 {
1764 struct nand_chip *this;
1765 struct mtd_info *mtd;
1766 struct mxc_nand_host *host;
1767 struct resource *res;
1768 int err = 0;
1769
1770 /* Allocate memory for MTD device structure and private data */
1771 host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host),
1772 GFP_KERNEL);
1773 if (!host)
1774 return -ENOMEM;
1775
1776 /* allocate a temporary buffer for the nand_scan_ident() */
1777 host->data_buf = devm_kzalloc(&pdev->dev, PAGE_SIZE, GFP_KERNEL);
1778 if (!host->data_buf)
1779 return -ENOMEM;
1780
1781 host->dev = &pdev->dev;
1782 /* structures must be linked */
1783 this = &host->nand;
1784 mtd = nand_to_mtd(this);
1785 mtd->dev.parent = &pdev->dev;
1786 mtd->name = DRIVER_NAME;
1787
1788 /* 50 us command delay time */
1789 this->chip_delay = 5;
1790
1791 nand_set_controller_data(this, host);
1792 nand_set_flash_node(this, pdev->dev.of_node),
1793 this->dev_ready = mxc_nand_dev_ready;
1794 this->cmdfunc = mxc_nand_command;
1795 this->read_byte = mxc_nand_read_byte;
1796 this->read_word = mxc_nand_read_word;
1797 this->write_buf = mxc_nand_write_buf;
1798 this->read_buf = mxc_nand_read_buf;
1799 this->set_features = mxc_nand_set_features;
1800 this->get_features = mxc_nand_get_features;
1801
1802 host->clk = devm_clk_get(&pdev->dev, NULL);
1803 if (IS_ERR(host->clk))
1804 return PTR_ERR(host->clk);
1805
1806 err = mxcnd_probe_dt(host);
1807 if (err > 0) {
1808 struct mxc_nand_platform_data *pdata =
1809 dev_get_platdata(&pdev->dev);
1810 if (pdata) {
1811 host->pdata = *pdata;
1812 host->devtype_data = (struct mxc_nand_devtype_data *)
1813 pdev->id_entry->driver_data;
1814 } else {
1815 err = -ENODEV;
1816 }
1817 }
1818 if (err < 0)
1819 return err;
1820
1821 this->setup_data_interface = host->devtype_data->setup_data_interface;
1822
1823 if (host->devtype_data->needs_ip) {
1824 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1825 host->regs_ip = devm_ioremap_resource(&pdev->dev, res);
1826 if (IS_ERR(host->regs_ip))
1827 return PTR_ERR(host->regs_ip);
1828
1829 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1830 } else {
1831 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1832 }
1833
1834 host->base = devm_ioremap_resource(&pdev->dev, res);
1835 if (IS_ERR(host->base))
1836 return PTR_ERR(host->base);
1837
1838 host->main_area0 = host->base;
1839
1840 if (host->devtype_data->regs_offset)
1841 host->regs = host->base + host->devtype_data->regs_offset;
1842 host->spare0 = host->base + host->devtype_data->spare0_offset;
1843 if (host->devtype_data->axi_offset)
1844 host->regs_axi = host->base + host->devtype_data->axi_offset;
1845
1846 this->ecc.bytes = host->devtype_data->eccbytes;
1847 host->eccsize = host->devtype_data->eccsize;
1848
1849 this->select_chip = host->devtype_data->select_chip;
1850 this->ecc.size = 512;
1851 mtd_set_ooblayout(mtd, host->devtype_data->ooblayout);
1852
1853 if (host->pdata.hw_ecc) {
1854 this->ecc.mode = NAND_ECC_HW;
1855 } else {
1856 this->ecc.mode = NAND_ECC_SOFT;
1857 this->ecc.algo = NAND_ECC_HAMMING;
1858 }
1859
1860 /* NAND bus width determines access functions used by upper layer */
1861 if (host->pdata.width == 2)
1862 this->options |= NAND_BUSWIDTH_16;
1863
1864 /* update flash based bbt */
1865 if (host->pdata.flash_bbt)
1866 this->bbt_options |= NAND_BBT_USE_FLASH;
1867
1868 init_completion(&host->op_completion);
1869
1870 host->irq = platform_get_irq(pdev, 0);
1871 if (host->irq < 0)
1872 return host->irq;
1873
1874 /*
1875 * Use host->devtype_data->irq_control() here instead of irq_control()
1876 * because we must not disable_irq_nosync without having requested the
1877 * irq.
1878 */
1879 host->devtype_data->irq_control(host, 0);
1880
1881 err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq,
1882 0, DRIVER_NAME, host);
1883 if (err)
1884 return err;
1885
1886 err = clk_prepare_enable(host->clk);
1887 if (err)
1888 return err;
1889 host->clk_act = 1;
1890
1891 /*
1892 * Now that we "own" the interrupt make sure the interrupt mask bit is
1893 * cleared on i.MX21. Otherwise we can't read the interrupt status bit
1894 * on this machine.
1895 */
1896 if (host->devtype_data->irqpending_quirk) {
1897 disable_irq_nosync(host->irq);
1898 host->devtype_data->irq_control(host, 1);
1899 }
1900
1901 /* Scan the NAND device */
1902 this->dummy_controller.ops = &mxcnd_controller_ops;
1903 err = nand_scan(mtd, is_imx25_nfc(host) ? 4 : 1);
1904 if (err)
1905 goto escan;
1906
1907 /* Register the partitions */
1908 err = mtd_device_parse_register(mtd, part_probes, NULL,
1909 host->pdata.parts,
1910 host->pdata.nr_parts);
1911 if (err)
1912 goto cleanup_nand;
1913
1914 platform_set_drvdata(pdev, host);
1915
1916 return 0;
1917
1918 cleanup_nand:
1919 nand_cleanup(this);
1920 escan:
1921 if (host->clk_act)
1922 clk_disable_unprepare(host->clk);
1923
1924 return err;
1925 }
1926
mxcnd_remove(struct platform_device * pdev)1927 static int mxcnd_remove(struct platform_device *pdev)
1928 {
1929 struct mxc_nand_host *host = platform_get_drvdata(pdev);
1930
1931 nand_release(nand_to_mtd(&host->nand));
1932 if (host->clk_act)
1933 clk_disable_unprepare(host->clk);
1934
1935 return 0;
1936 }
1937
1938 static struct platform_driver mxcnd_driver = {
1939 .driver = {
1940 .name = DRIVER_NAME,
1941 .of_match_table = of_match_ptr(mxcnd_dt_ids),
1942 },
1943 .id_table = mxcnd_devtype,
1944 .probe = mxcnd_probe,
1945 .remove = mxcnd_remove,
1946 };
1947 module_platform_driver(mxcnd_driver);
1948
1949 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1950 MODULE_DESCRIPTION("MXC NAND MTD driver");
1951 MODULE_LICENSE("GPL");
1952
