1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
3 * x86_emulate.h
4 *
5 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
6 *
7 * Copyright (c) 2005 Keir Fraser
8 *
9 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
10 */
11
12 #ifndef _ASM_X86_KVM_X86_EMULATE_H
13 #define _ASM_X86_KVM_X86_EMULATE_H
14
15 #include <asm/desc_defs.h>
16 #include "fpu.h"
17
18 struct x86_emulate_ctxt;
19 enum x86_intercept;
20 enum x86_intercept_stage;
21
22 struct x86_exception {
23 u8 vector;
24 bool error_code_valid;
25 u16 error_code;
26 bool nested_page_fault;
27 u64 address; /* cr2 or nested page fault gpa */
28 u8 async_page_fault;
29 };
30
31 /*
32 * This struct is used to carry enough information from the instruction
33 * decoder to main KVM so that a decision can be made whether the
34 * instruction needs to be intercepted or not.
35 */
36 struct x86_instruction_info {
37 u8 intercept; /* which intercept */
38 u8 rep_prefix; /* rep prefix? */
39 u8 modrm_mod; /* mod part of modrm */
40 u8 modrm_reg; /* index of register used */
41 u8 modrm_rm; /* rm part of modrm */
42 u64 src_val; /* value of source operand */
43 u64 dst_val; /* value of destination operand */
44 u8 src_bytes; /* size of source operand */
45 u8 dst_bytes; /* size of destination operand */
46 u8 ad_bytes; /* size of src/dst address */
47 u64 next_rip; /* rip following the instruction */
48 };
49
50 /*
51 * x86_emulate_ops:
52 *
53 * These operations represent the instruction emulator's interface to memory.
54 * There are two categories of operation: those that act on ordinary memory
55 * regions (*_std), and those that act on memory regions known to require
56 * special treatment or emulation (*_emulated).
57 *
58 * The emulator assumes that an instruction accesses only one 'emulated memory'
59 * location, that this location is the given linear faulting address (cr2), and
60 * that this is one of the instruction's data operands. Instruction fetches and
61 * stack operations are assumed never to access emulated memory. The emulator
62 * automatically deduces which operand of a string-move operation is accessing
63 * emulated memory, and assumes that the other operand accesses normal memory.
64 *
65 * NOTES:
66 * 1. The emulator isn't very smart about emulated vs. standard memory.
67 * 'Emulated memory' access addresses should be checked for sanity.
68 * 'Normal memory' accesses may fault, and the caller must arrange to
69 * detect and handle reentrancy into the emulator via recursive faults.
70 * Accesses may be unaligned and may cross page boundaries.
71 * 2. If the access fails (cannot emulate, or a standard access faults) then
72 * it is up to the memop to propagate the fault to the guest VM via
73 * some out-of-band mechanism, unknown to the emulator. The memop signals
74 * failure by returning X86EMUL_PROPAGATE_FAULT to the emulator, which will
75 * then immediately bail.
76 * 3. Valid access sizes are 1, 2, 4 and 8 bytes. On x86/32 systems only
77 * cmpxchg8b_emulated need support 8-byte accesses.
78 * 4. The emulator cannot handle 64-bit mode emulation on an x86/32 system.
79 */
80 /* Access completed successfully: continue emulation as normal. */
81 #define X86EMUL_CONTINUE 0
82 /* Access is unhandleable: bail from emulation and return error to caller. */
83 #define X86EMUL_UNHANDLEABLE 1
84 /* Terminate emulation but return success to the caller. */
85 #define X86EMUL_PROPAGATE_FAULT 2 /* propagate a generated fault to guest */
86 #define X86EMUL_RETRY_INSTR 3 /* retry the instruction for some reason */
87 #define X86EMUL_CMPXCHG_FAILED 4 /* cmpxchg did not see expected value */
88 #define X86EMUL_IO_NEEDED 5 /* IO is needed to complete emulation */
89 #define X86EMUL_INTERCEPTED 6 /* Intercepted by nested VMCB/VMCS */
90
91 struct x86_emulate_ops {
92 /*
93 * read_gpr: read a general purpose register (rax - r15)
94 *
95 * @reg: gpr number.
96 */
97 ulong (*read_gpr)(struct x86_emulate_ctxt *ctxt, unsigned reg);
98 /*
99 * write_gpr: write a general purpose register (rax - r15)
100 *
101 * @reg: gpr number.
102 * @val: value to write.
103 */
104 void (*write_gpr)(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val);
105 /*
106 * read_std: Read bytes of standard (non-emulated/special) memory.
107 * Used for descriptor reading.
108 * @addr: [IN ] Linear address from which to read.
109 * @val: [OUT] Value read from memory, zero-extended to 'u_long'.
110 * @bytes: [IN ] Number of bytes to read from memory.
111 * @system:[IN ] Whether the access is forced to be at CPL0.
112 */
113 int (*read_std)(struct x86_emulate_ctxt *ctxt,
114 unsigned long addr, void *val,
115 unsigned int bytes,
116 struct x86_exception *fault, bool system);
117
118 /*
119 * read_phys: Read bytes of standard (non-emulated/special) memory.
120 * Used for descriptor reading.
121 * @addr: [IN ] Physical address from which to read.
122 * @val: [OUT] Value read from memory.
123 * @bytes: [IN ] Number of bytes to read from memory.
124 */
125 int (*read_phys)(struct x86_emulate_ctxt *ctxt, unsigned long addr,
126 void *val, unsigned int bytes);
127
128 /*
129 * write_std: Write bytes of standard (non-emulated/special) memory.
130 * Used for descriptor writing.
131 * @addr: [IN ] Linear address to which to write.
132 * @val: [OUT] Value write to memory, zero-extended to 'u_long'.
133 * @bytes: [IN ] Number of bytes to write to memory.
134 * @system:[IN ] Whether the access is forced to be at CPL0.
135 */
136 int (*write_std)(struct x86_emulate_ctxt *ctxt,
137 unsigned long addr, void *val, unsigned int bytes,
138 struct x86_exception *fault, bool system);
139 /*
140 * fetch: Read bytes of standard (non-emulated/special) memory.
141 * Used for instruction fetch.
142 * @addr: [IN ] Linear address from which to read.
143 * @val: [OUT] Value read from memory, zero-extended to 'u_long'.
144 * @bytes: [IN ] Number of bytes to read from memory.
145 */
146 int (*fetch)(struct x86_emulate_ctxt *ctxt,
147 unsigned long addr, void *val, unsigned int bytes,
148 struct x86_exception *fault);
149
150 /*
151 * read_emulated: Read bytes from emulated/special memory area.
152 * @addr: [IN ] Linear address from which to read.
153 * @val: [OUT] Value read from memory, zero-extended to 'u_long'.
154 * @bytes: [IN ] Number of bytes to read from memory.
155 */
156 int (*read_emulated)(struct x86_emulate_ctxt *ctxt,
157 unsigned long addr, void *val, unsigned int bytes,
158 struct x86_exception *fault);
159
160 /*
161 * write_emulated: Write bytes to emulated/special memory area.
162 * @addr: [IN ] Linear address to which to write.
163 * @val: [IN ] Value to write to memory (low-order bytes used as
164 * required).
165 * @bytes: [IN ] Number of bytes to write to memory.
166 */
167 int (*write_emulated)(struct x86_emulate_ctxt *ctxt,
168 unsigned long addr, const void *val,
169 unsigned int bytes,
170 struct x86_exception *fault);
171
172 /*
173 * cmpxchg_emulated: Emulate an atomic (LOCKed) CMPXCHG operation on an
174 * emulated/special memory area.
175 * @addr: [IN ] Linear address to access.
176 * @old: [IN ] Value expected to be current at @addr.
177 * @new: [IN ] Value to write to @addr.
178 * @bytes: [IN ] Number of bytes to access using CMPXCHG.
179 */
180 int (*cmpxchg_emulated)(struct x86_emulate_ctxt *ctxt,
181 unsigned long addr,
182 const void *old,
183 const void *new,
184 unsigned int bytes,
185 struct x86_exception *fault);
186 void (*invlpg)(struct x86_emulate_ctxt *ctxt, ulong addr);
187
188 int (*pio_in_emulated)(struct x86_emulate_ctxt *ctxt,
189 int size, unsigned short port, void *val,
190 unsigned int count);
191
192 int (*pio_out_emulated)(struct x86_emulate_ctxt *ctxt,
193 int size, unsigned short port, const void *val,
194 unsigned int count);
195
196 bool (*get_segment)(struct x86_emulate_ctxt *ctxt, u16 *selector,
197 struct desc_struct *desc, u32 *base3, int seg);
198 void (*set_segment)(struct x86_emulate_ctxt *ctxt, u16 selector,
199 struct desc_struct *desc, u32 base3, int seg);
200 unsigned long (*get_cached_segment_base)(struct x86_emulate_ctxt *ctxt,
201 int seg);
202 void (*get_gdt)(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt);
203 void (*get_idt)(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt);
204 void (*set_gdt)(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt);
205 void (*set_idt)(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt);
206 ulong (*get_cr)(struct x86_emulate_ctxt *ctxt, int cr);
207 int (*set_cr)(struct x86_emulate_ctxt *ctxt, int cr, ulong val);
208 int (*cpl)(struct x86_emulate_ctxt *ctxt);
209 void (*get_dr)(struct x86_emulate_ctxt *ctxt, int dr, ulong *dest);
210 int (*set_dr)(struct x86_emulate_ctxt *ctxt, int dr, ulong value);
211 u64 (*get_smbase)(struct x86_emulate_ctxt *ctxt);
212 void (*set_smbase)(struct x86_emulate_ctxt *ctxt, u64 smbase);
213 int (*set_msr)(struct x86_emulate_ctxt *ctxt, u32 msr_index, u64 data);
214 int (*get_msr)(struct x86_emulate_ctxt *ctxt, u32 msr_index, u64 *pdata);
215 int (*check_pmc)(struct x86_emulate_ctxt *ctxt, u32 pmc);
216 int (*read_pmc)(struct x86_emulate_ctxt *ctxt, u32 pmc, u64 *pdata);
217 void (*halt)(struct x86_emulate_ctxt *ctxt);
218 void (*wbinvd)(struct x86_emulate_ctxt *ctxt);
219 int (*fix_hypercall)(struct x86_emulate_ctxt *ctxt);
220 int (*intercept)(struct x86_emulate_ctxt *ctxt,
221 struct x86_instruction_info *info,
222 enum x86_intercept_stage stage);
223
224 bool (*get_cpuid)(struct x86_emulate_ctxt *ctxt, u32 *eax, u32 *ebx,
225 u32 *ecx, u32 *edx, bool exact_only);
226 bool (*guest_has_long_mode)(struct x86_emulate_ctxt *ctxt);
227 bool (*guest_has_movbe)(struct x86_emulate_ctxt *ctxt);
228 bool (*guest_has_fxsr)(struct x86_emulate_ctxt *ctxt);
229
230 void (*set_nmi_mask)(struct x86_emulate_ctxt *ctxt, bool masked);
231
232 unsigned (*get_hflags)(struct x86_emulate_ctxt *ctxt);
233 void (*exiting_smm)(struct x86_emulate_ctxt *ctxt);
234 int (*leave_smm)(struct x86_emulate_ctxt *ctxt, const char *smstate);
235 void (*triple_fault)(struct x86_emulate_ctxt *ctxt);
236 int (*set_xcr)(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr);
237 };
238
239 /* Type, address-of, and value of an instruction's operand. */
240 struct operand {
241 enum { OP_REG, OP_MEM, OP_MEM_STR, OP_IMM, OP_XMM, OP_MM, OP_NONE } type;
242 unsigned int bytes;
243 unsigned int count;
244 union {
245 unsigned long orig_val;
246 u64 orig_val64;
247 };
248 union {
249 unsigned long *reg;
250 struct segmented_address {
251 ulong ea;
252 unsigned seg;
253 } mem;
254 unsigned xmm;
255 unsigned mm;
256 } addr;
257 union {
258 unsigned long val;
259 u64 val64;
260 char valptr[sizeof(sse128_t)];
261 sse128_t vec_val;
262 u64 mm_val;
263 void *data;
264 };
265 };
266
267 struct fetch_cache {
268 u8 data[15];
269 u8 *ptr;
270 u8 *end;
271 };
272
273 struct read_cache {
274 u8 data[1024];
275 unsigned long pos;
276 unsigned long end;
277 };
278
279 /* Execution mode, passed to the emulator. */
280 enum x86emul_mode {
281 X86EMUL_MODE_REAL, /* Real mode. */
282 X86EMUL_MODE_VM86, /* Virtual 8086 mode. */
283 X86EMUL_MODE_PROT16, /* 16-bit protected mode. */
284 X86EMUL_MODE_PROT32, /* 32-bit protected mode. */
285 X86EMUL_MODE_PROT64, /* 64-bit (long) mode. */
286 };
287
288 /* These match some of the HF_* flags defined in kvm_host.h */
289 #define X86EMUL_GUEST_MASK (1 << 5) /* VCPU is in guest-mode */
290 #define X86EMUL_SMM_MASK (1 << 6)
291 #define X86EMUL_SMM_INSIDE_NMI_MASK (1 << 7)
292
293 /*
294 * fastop functions are declared as taking a never-defined fastop parameter,
295 * so they can't be called from C directly.
296 */
297 struct fastop;
298
299 typedef void (*fastop_t)(struct fastop *);
300
301 struct x86_emulate_ctxt {
302 void *vcpu;
303 const struct x86_emulate_ops *ops;
304
305 /* Register state before/after emulation. */
306 unsigned long eflags;
307 unsigned long eip; /* eip before instruction emulation */
308 /* Emulated execution mode, represented by an X86EMUL_MODE value. */
309 enum x86emul_mode mode;
310
311 /* interruptibility state, as a result of execution of STI or MOV SS */
312 int interruptibility;
313
314 bool perm_ok; /* do not check permissions if true */
315 bool tf; /* TF value before instruction (after for syscall/sysret) */
316
317 bool have_exception;
318 struct x86_exception exception;
319
320 /* GPA available */
321 bool gpa_available;
322 gpa_t gpa_val;
323
324 /*
325 * decode cache
326 */
327
328 /* current opcode length in bytes */
329 u8 opcode_len;
330 u8 b;
331 u8 intercept;
332 u8 op_bytes;
333 u8 ad_bytes;
334 union {
335 int (*execute)(struct x86_emulate_ctxt *ctxt);
336 fastop_t fop;
337 };
338 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
339 /*
340 * The following six fields are cleared together,
341 * the rest are initialized unconditionally in x86_decode_insn
342 * or elsewhere
343 */
344 bool rip_relative;
345 u8 rex_prefix;
346 u8 lock_prefix;
347 u8 rep_prefix;
348 /* bitmaps of registers in _regs[] that can be read */
349 u32 regs_valid;
350 /* bitmaps of registers in _regs[] that have been written */
351 u32 regs_dirty;
352 /* modrm */
353 u8 modrm;
354 u8 modrm_mod;
355 u8 modrm_reg;
356 u8 modrm_rm;
357 u8 modrm_seg;
358 u8 seg_override;
359 u64 d;
360 unsigned long _eip;
361
362 /* Here begins the usercopy section. */
363 struct operand src;
364 struct operand src2;
365 struct operand dst;
366 struct operand memop;
367 unsigned long _regs[NR_VCPU_REGS];
368 struct operand *memopp;
369 struct fetch_cache fetch;
370 struct read_cache io_read;
371 struct read_cache mem_read;
372 };
373
374 /* Repeat String Operation Prefix */
375 #define REPE_PREFIX 0xf3
376 #define REPNE_PREFIX 0xf2
377
378 /* CPUID vendors */
379 #define X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx 0x68747541
380 #define X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx 0x444d4163
381 #define X86EMUL_CPUID_VENDOR_AuthenticAMD_edx 0x69746e65
382
383 #define X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx 0x69444d41
384 #define X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx 0x21726574
385 #define X86EMUL_CPUID_VENDOR_AMDisbetterI_edx 0x74656273
386
387 #define X86EMUL_CPUID_VENDOR_HygonGenuine_ebx 0x6f677948
388 #define X86EMUL_CPUID_VENDOR_HygonGenuine_ecx 0x656e6975
389 #define X86EMUL_CPUID_VENDOR_HygonGenuine_edx 0x6e65476e
390
391 #define X86EMUL_CPUID_VENDOR_GenuineIntel_ebx 0x756e6547
392 #define X86EMUL_CPUID_VENDOR_GenuineIntel_ecx 0x6c65746e
393 #define X86EMUL_CPUID_VENDOR_GenuineIntel_edx 0x49656e69
394
395 #define X86EMUL_CPUID_VENDOR_CentaurHauls_ebx 0x746e6543
396 #define X86EMUL_CPUID_VENDOR_CentaurHauls_ecx 0x736c7561
397 #define X86EMUL_CPUID_VENDOR_CentaurHauls_edx 0x48727561
398
is_guest_vendor_intel(u32 ebx,u32 ecx,u32 edx)399 static inline bool is_guest_vendor_intel(u32 ebx, u32 ecx, u32 edx)
400 {
401 return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
402 ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
403 edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
404 }
405
is_guest_vendor_amd(u32 ebx,u32 ecx,u32 edx)406 static inline bool is_guest_vendor_amd(u32 ebx, u32 ecx, u32 edx)
407 {
408 return (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
409 ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
410 edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx) ||
411 (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
412 ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
413 edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx);
414 }
415
is_guest_vendor_hygon(u32 ebx,u32 ecx,u32 edx)416 static inline bool is_guest_vendor_hygon(u32 ebx, u32 ecx, u32 edx)
417 {
418 return ebx == X86EMUL_CPUID_VENDOR_HygonGenuine_ebx &&
419 ecx == X86EMUL_CPUID_VENDOR_HygonGenuine_ecx &&
420 edx == X86EMUL_CPUID_VENDOR_HygonGenuine_edx;
421 }
422
423 enum x86_intercept_stage {
424 X86_ICTP_NONE = 0, /* Allow zero-init to not match anything */
425 X86_ICPT_PRE_EXCEPT,
426 X86_ICPT_POST_EXCEPT,
427 X86_ICPT_POST_MEMACCESS,
428 };
429
430 enum x86_intercept {
431 x86_intercept_none,
432 x86_intercept_cr_read,
433 x86_intercept_cr_write,
434 x86_intercept_clts,
435 x86_intercept_lmsw,
436 x86_intercept_smsw,
437 x86_intercept_dr_read,
438 x86_intercept_dr_write,
439 x86_intercept_lidt,
440 x86_intercept_sidt,
441 x86_intercept_lgdt,
442 x86_intercept_sgdt,
443 x86_intercept_lldt,
444 x86_intercept_sldt,
445 x86_intercept_ltr,
446 x86_intercept_str,
447 x86_intercept_rdtsc,
448 x86_intercept_rdpmc,
449 x86_intercept_pushf,
450 x86_intercept_popf,
451 x86_intercept_cpuid,
452 x86_intercept_rsm,
453 x86_intercept_iret,
454 x86_intercept_intn,
455 x86_intercept_invd,
456 x86_intercept_pause,
457 x86_intercept_hlt,
458 x86_intercept_invlpg,
459 x86_intercept_invlpga,
460 x86_intercept_vmrun,
461 x86_intercept_vmload,
462 x86_intercept_vmsave,
463 x86_intercept_vmmcall,
464 x86_intercept_stgi,
465 x86_intercept_clgi,
466 x86_intercept_skinit,
467 x86_intercept_rdtscp,
468 x86_intercept_rdpid,
469 x86_intercept_icebp,
470 x86_intercept_wbinvd,
471 x86_intercept_monitor,
472 x86_intercept_mwait,
473 x86_intercept_rdmsr,
474 x86_intercept_wrmsr,
475 x86_intercept_in,
476 x86_intercept_ins,
477 x86_intercept_out,
478 x86_intercept_outs,
479 x86_intercept_xsetbv,
480
481 nr_x86_intercepts
482 };
483
484 /* Host execution mode. */
485 #if defined(CONFIG_X86_32)
486 #define X86EMUL_MODE_HOST X86EMUL_MODE_PROT32
487 #elif defined(CONFIG_X86_64)
488 #define X86EMUL_MODE_HOST X86EMUL_MODE_PROT64
489 #endif
490
491 int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len, int emulation_type);
492 bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt);
493 #define EMULATION_FAILED -1
494 #define EMULATION_OK 0
495 #define EMULATION_RESTART 1
496 #define EMULATION_INTERCEPTED 2
497 void init_decode_cache(struct x86_emulate_ctxt *ctxt);
498 int x86_emulate_insn(struct x86_emulate_ctxt *ctxt);
499 int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
500 u16 tss_selector, int idt_index, int reason,
501 bool has_error_code, u32 error_code);
502 int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq);
503 void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt);
504 void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt);
505 bool emulator_can_use_gpa(struct x86_emulate_ctxt *ctxt);
506
507 #endif /* _ASM_X86_KVM_X86_EMULATE_H */
508
